CY74FCT163H952 [TI]
16-Bit Registered Transceivers; 16位寄存收发器
| 型号： | CY74FCT163H952 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Registered Transceivers |
| 文件： | 总6页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY74FCT163952
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163952
CY74FCT163H952
SCCS048 - March 1997 - Revised March 2000
16-Bit Registered Transceivers
Features
Functional Description
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
These 16-bit registered transceivers are high-speed,
low-power devices. 16-bit operation is achieved by connecting
the control lines of the two 8-bit registered transceivers
together. For data flow from bus A-to-B, CEAB must be LOW
to allow data to be stored when CLKAB transitions from
LOW-to-HIGH. The stored data will be present on the output
when OEAB is LOW. Control of data from B-to-A is similar and
is controlled by using the CEBA, CLKBA, and OEBA inputs.
The outputs are 24-mA balanced output drivers with current
limiting resistors to reduce the need for external terminating
resistors and provide for minimal undershoot and reduced
ground bounce.
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.4 ns
• Latch-up performance exceeds JEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
The CY74FCT163H952 has “bus hold” on the data inputs,
which retains the input’s last state whenever the source driving
the input goes to high impedance. This eliminates the need for
pull-up/down resistors and prevents floating inputs.
• TypicalV
olp
(groundbounce)performanceexceedsMil
Std 883D
• VCC = 2.7V to 3.6V
• ESD (HBM) > 2000V
CY74FCT163H952
The CY74FCT163952 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
• Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Pin Configuration
Logic Block Diagrams; CY74FCT163952, CY74FCT163H952
SSOP/TSSOP
Top View
OEAB
1
2
56
55
OEBA
CLKBA
1
1
1
CEBA
CEBA
2
2
1
CLKAB
1
CEAB
1
CEBA
3
4
54
53
1
CLKBA
OEAB
CLKBA
OEAB
1
GND
A
GND
B
1
2
5
6
7
52
51
50
1
1
1
1
CEAB
CEAB
1
2
B
2
A
1
1
2
V
V
CC
CC
A
CLKAB
OEBA
CLKAB
OEBA
2
1
2
B
3
8
9
49
48
1
3
1
A
B
4
1
1
4
1
B
5
A
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
C
C
1
A
A
2 1
CE
D
CE
D
GND
B
1
1
GND
A
B
B
2
1
1
1
1
1
6
1
1
6
C
CE
D
C
CE
D
A
7
B
7
A
B
1 8
1
8
A
B
2 1
2
1
B
A
2
2
2
2
2
B
3
A
2
3
GND
A
GND
B
TO7 OTHERCHANNELS
TO7 OTHERCHANNELS
2
4
2
4
A
5
B
2 5
2
B
A
2
6
2
6
V
CC
V
CC
B
7
A
2
2
2
7
B
8
A
24
25
26
27
28
33
32
31
30
29
2
8
GND
GND
CEBA
2
CEAB
2
CLKAB
CLKBA
OEBA
2
2
2
OEAB
2
Copyright © 2000, Texas Instruments Incorporated
CY74FCT163952
CY74FCT163H952
Maximum Ratings[5, 6]
Pin Description
Name
Description
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
OEAB
OEBA
CEAB
CEBA
CLKAB
CLKBA
A
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
Storage Temperature ..................................–55°C to +125°C
Ambient Temperature with
Power Applied .............................................–55°C to +125°C
Supply Voltage Range......................................0.5V to +4.6V
DC Input Voltage ............................................–0.5V to +7.0V
DC Output Voltage .........................................–0.5V to +7.0V
B-to-A Clock Input
A-to-B Data Inputs or B-to-A Three-State
Outputs[1]
DC Output Current
(Maximum Sink Current/Pin)........................ –60 to +120 mA
B
B-to-A Data Inputs or A-to-B Three-State
Outputs[1]
Power Dissipation.......................................................... 1.0W
Function Table[2, 3]
For A-to-B (Symmetric with B-to-A)
Operating Range
Inputs
Outputs
Ambient
CEAB
CLKAB
OEAB
A
X
X
L
B
B[4]
B[4]
L
Range
Industrial
Temperature
VCC
H
X
L
X
L
L
L
L
L
H
–40°C to +85°C
2.7V to 3.6V
L
H
X
H
X
X
Z
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Input HIGH Voltage
Test Conditions
All Inputs
Min.
Typ.[7] Max.
Unit
V
VIH
VIL
VH
VIK
IIH
2.0
5.5
Input LOW Voltage
Input Hysteresis[8]
0.8
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
VCC=Min., IIN=–18 mA
VCC=Max., VI=5.5
–0.7
–1.2
±1
µA
IIL
Input LOW Current
VCC=Max., VI=GND
±1
±1
µA
µA
IOZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=5.5V
IOZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
IOS
Short Circuit Current[9]
VCC=Max., VOUT=GND
–60
–135
–240
±100
10
mA
µA
µA
IOFF
ICC
Power-Off Disable
VCC=0V, VOUT≤4.5V
Quiescent Power Supply Current
VIN≤0.2V,
VCC=Max.
0.1
2.0
VIN>VCC–0.2V
VIN=VCC–0.6V[10] VCC=Max.
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
30
µA
Notes:
1. On the CY74FCT163H952, these pins have bus hold.
2. A-to-B data flow is shown: B-to-A data flow is similar but uses, CEBA, CLKBA, and OEBA.
3. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition. Z = HIGH Impedance.
4. Level of B before the indicated steady-state input conditions were established.
5. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature.
6. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground,
7. Typical values are at VCC=3.3V, TA = +25˚C ambient.
8. This parameter is specified but not tested.
9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
10. Per TTL driven input; all other inputs at VCC or GND.
2
CY74FCT163952
CY74FCT163H952
Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Input HIGH Voltage
Test Conditions
All Inputs
Min. Typ.[7] Max. Unit
VIH
VIL
VH
VIK
IIH
2.0
VCC
0.8
V
V
Input LOW Voltage
Input Hysteresis[8]
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
VCC=Min., IIN=–18 mA
VCC=Max., VI=VCC
–0.7 – 1.2
±100
µA
IIL
Input LOW Current
±100
µA
µA
µA
µA
IBBH
IBBL
Bus Hold Sustain Current on Bus Hold Input[11] VCC=Min.
VI=2.0V
VI=0.8V
–50
+50
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold Input[11] VCC=Max., VI=1.5V
±500
IOZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=VCC
±1
±1
µA
µA
IOZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
IOS
Short Circuit Current[9]
VCC=Max., VOUT=GND
–60
–135 –240
±100
mA
µA
µA
IOFF
ICC
Power-Off Disable
VCC=0V, VOUT≤4.5V
Quiescent Power Supply Current
VIN≤0.2V VCC
VCC=Max.
+40
VIN>VCC–0.2V
∆
Quiescent Power supply Current
(TTL inputs HIGH)
VIN=VCC–0.6V[10] VCC=Max.
+350
µA
ICC
Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Test Conditions
Min.
Typ.[7] Max.
Unit
IODL
Output LOW Dynamic Current[9]
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
50
90
200
mA
IODH
VOH
Output HIGH Dynamic Current[9]
Output HIGH Voltage
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
–36
–60
–110
mA
VCC=Min., IOH= –0.1 mA VCC–0.2
V
V
V
V
VCC=Min., IOH= –8 mA
VCC=3.0V, IOH= –24 mA
VCC=Min., IOL= 0.1mA
VCC=Min., IOL= 24 mA
2.4[12]
3.0
3.0
2.0
VOL
Output LOW Voltage
0.2
0.3
0.55
Notes:
11. Pins with bus hold are described in Pin Description.
12. OH=VCC–0.6 V at rated current
V
Capacitance[8](TA = +25˚C, f = 1.0 MHz)
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.[7]
Max.
Unit
VIN = 0V
4.5
5.5
6.0
8.0
pF
pF
COUT
VOUT = 0V
3
CY74FCT163952
CY74FCT163H952
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[7]
Max.
Unit
ICCD
Dynamic Power Supply
Current[13]
VCC=Max., One Input Toggling, VIN=VCC or
50
75
µA/MHz
50% Duty Cycle,
VIN=GND
Outputs Open, OE=GND
IC
Total Power Supply
Current[14]
VCC=Max., f1=10 MHz, 50%
Duty Cycle, Outputs Open, One VIN=GND
Bit Toggling, OE=GND
VIN=VCC or
0.5
0.5
2.0
2.0
0.8
0.8
mA
mA
mA
mA
VIN=VCC–0.6V or
VIN=GND
VCC=Max., f1=2.5 MHz, 50%
Duty Cycle, Outputs Open, Six- VIN=GND
teen Bits Toggling, OE=GND
VIN=VCC or
3.0[15]
3.3[15]
VIN=VCC–0.6V or
VIN=GND
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[16,17]
CY74FCT163952C
CY74FCT163952A
CY74FCT163H952C
Parameter
tPLH
tPHL
Description
Min.
Max.
Min.
Max.
Unit
Fig. No.[18]
Propagation Delay Data to
Output
1.5
4.8
1.5
4.4
ns
ns
ns
ns
1, 3
tPZH
tPZL
Output Enable Time
Output Disable Time
Output Skew[19]
1.5
1.5
6.2
5.6
0.5
1.5
1.5
5.8
5.2
0.5
1, 7, 8
1, 7, 8
—
tPHZ
tPLZ
tSK(O)
Notes:
13. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
14. IC
IC
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
f1
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
15. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
16. Minimum limits are specified but not tested on Propagation Delays.
17. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
18. See “Parameter Measurement Information” in the General Information section.
19. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
Ordering Information CY74FCT163952
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (300-Mil) SSOP
4.1
CY74FCT163952CPACT
Z48
O48
O48
Industrial
CY74FCT163952CPVC/PVCT
CY74FCT163952APVC/PVCT
4.8
Industrial
Ordering Information CY74FCT163H952
Speed
(ns)
Package
Operating
Range
Ordering Code
74FCT163H952CPACT
CY74FCT163H952CPVC
74FCT163H952CPVCT
Name
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (300-Mil) SSOP
4.1
Z48
Industrial
O48
O48
4
CY74FCT163952
CY74FCT163H952
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
5
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 2000, Texas Instruments Incorporated
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