CY74FCT16646TSSOP_技术文档

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY74FCT16646T

CY74FCT162646T

SCCS060 - August 1994 - Revised March 2000

16-Bit Registered Transceivers

Features

Functional Description

• FCT-E speed at 3.8 ns

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

• Typical output skew < 250 ps

• ESD > 2000V

• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)

packages

• Industrial temperature range of −40˚C to +85˚C

• V_CC= 5V ± 10%

The CY74FCT16646T and CY74FCT162646T 16-bit

transceivers are three-state, D-type registers, and control

circuitry arranged for multiplexed transmission of data directly

from the input bus or from the internal registers. Data on the A

or B bus will be clocked into the registers as the appropriate

clock pin goes to a HIGH logic level. Output Enable (OE) and

direction pins (DIR) are provided to control the transceiver

function. In the transceiver mode, data present at the high

impedance port may be stored in either the A or B register, or

in both. The select controls can multiplex stored and real-time

(transparent mode) data. The direction control determines

which bus will receive data when the Output Enable (OE) is

Active LOW. In the isolation mode (Output Enable (OE) HIGH),

A data may be stored in the B register and/or B data may be

stored in the A register. The output buffers are designed with

a power-off disable feature that allows live insertion of boards.

CY74FCT16646T Features:

• 64 mA sink current, 32 mA source current

• Typical V_OLP(ground bounce) <1.0V at V_CC= 5V,

T_A= 25˚C

The CY74FCT16646T is ideally suited for driving

high-capacitance loads and low-impedance backplanes.

CY74FCT162646T Features:

• Balanced 24 mA output drivers

• Reduced system switching noise

• Typical V_OLP(ground bounce) <0.6V at V_CC= 5V,

T_A= 25˚C

The CY74FCT162646T has 24-mA balanced output drivers

with current limiting resistors in the outputs. This reduces the

need for external terminating resistors and provides for

minimal undershoot and reduced ground bounce. The

CY74FCT162646T is ideal for driving transmission lines.

Logic Block Diagrams

OE

2

OE

1

DIR

2

DIR

CLKBA

SBA

CLKAB

1

CLKBA

2

1

SBA

CLKAB

2

1

2

1

SAB

2

SAB

1

B REG

D

B REG

D

C

A

2 1

A REG

D

B

2

1

A REG

D

B

1

A

1 1

C

FCT16646-2

TO 7 OTHER CHANNELS

FCT16646-1

TO 7 OTHER CHANNELS

CY74FCT16646T

CY74FCT162646T

Pin Configuration

SSOP/TSSOP

Top View

DIR

OE

1

2

56

55

CLKBA

1

CLKAB

SAB

1

SBA

3

4

54

53

1

GND

B

A

1 1

5

6

7

8

9

52

51

50

49

48

1

2

A

1 2

B

1

V

CC

V

CC

A

1 3

B

1

3

4

5

A

1 4

B

1

A

1 5

B

1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

47

46

45

44

43

42

41

40

39

38

37

36

35

34

GND

B

A

1 6

1

6

7

8

1

2

3

B

1

A

1 7

A

1 8

B

1

B

2

A

2 1

A

2 2

B

2

B

2

A

2 3

GND

B

A

2 4

2

4

5

6

A

2 5

B

2

A

2 6

B

2

V

CC

V

CC

B

A

2 7

2

7

8

A

2 8

B

2

24

25

33

32

GND

SAB

GND

SBA

2

26

27

28

31

30

29

2

CLKAB

CLKBA

2

OE

2

DIR

2

FCT16646-3

Pin Description

Pin Names

Description

A

Data Register A Inputs

Data Register B Outputs

B

Data Register B Inputs

Data Register A Outputs

CLKAB, CLKBA

SAB, SBA

DIR

Clock Pulse Inputs

Output Data Source Select Inputs

Direction

OE

Output Enable (Active LOW)

2

CY74FCT16646T

CY74FCT162646T

Function Table^[1]

Inputs

Data I/O^[2]

Function

OE

DIR

CLKAB

CLKBA

SAB

SBA

A

B

H

X

H or L

X

Input

Input Isolation

Store A and B Data

L

X

L

H

Output Input Real Time B Data to A Bus

Stored B Data to A Bus

H or L

L

H

X

L

H

X

Input Output Real Time A Data to Bus

Stored A Data to B Bus

H or L

BUS A

BUS B

BUS A

BUS B

DIR

L

OE

L

CLKAB

X

CLKBA

X

SAB

X

SBA

L

DIR

H

OE

L

CLKAB

X

CLKBA

X

SAB

L

SBA

X

Real-Time Transfer

BusB to BusA

Real-Time Transfer

BusA to BusB

BUS A

BUS B

BUS A

[3]

DIR

H

L

OE

L

H

SAB

X

SBA

X

DIR

L

H

OE

L

SAB

X

H

SBA

H

X

CLKAB

X

CLKBA

X

CLKAB

X

H or L

CLKBA

H or L

X

Storage from

A and/or B

Transfer Stored Data

to A and/or B

Notes:

1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care

.

= LOW-to-HIGH Transition

2. The data output functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functions are always enabled, i.e., data at the

bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

3. Cannot transfer data to A-bus and B-bus simultaneously.

3

CY74FCT16646T

CY74FCT162646T

Maximum Ratings^[4]

DC Output Current

(Maximum Sink Current/Pin) ...........................−60 to +120 mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Power Dissipation..........................................................1.0W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .....................Com’l −55°C to +125°C

Ambient Temperature with

Power Applied.................................Com’l −55°C to +125°C

Operating Range

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage ..............................................−0.5V to +7.0V

Ambient

Range

Industrial

Temperature

V_CC

−40°C to +85°C

5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

Typ.^[5]

Max.

Unit

V_IH

V_IL

V_H

V_IK

I_IH

Input HIGH Voltage

2.0

V

Input LOW Voltage

Input Hysteresis^[6]

0.8

100

mV

V

Input Clamp Diode Voltage

Input HIGH Current

Input LOW Current

V_CC=Min., I_IN=−18 mA

V_CC=Max., V_I=V_CC

−0.7

−1.2

±1

µA

I_IL

V_CC=Max., V_I=GND

V_CC=Max., V_OUT=2.7V

±1

I_OZH

High Impedance Output Current

(Three-State Output pins)

±1

I_OZL

High Impedance Output Current

(Three-State Output pins)

V_CC=Max., V_OUT=0.5V

±1

µA

I_OS

I_O

Short Circuit Current^[7]

Output Drive Current^[7]

Power-Off Disable

V_CC=Max., V_OUT=GND

V_CC=Max., V_OUT=2.5V

V_CC=0V, V_OUT≤4.5V^[9]

−80

−50

−140

−200

−180

±1

mA

µA

I_OFF

Output Drive Characteristics for CY74FCT16646T

Parameter

Description

Test Conditions

Min.

2.5

Typ.^[5]

3.5

Max.

Unit

V

V_OH

Output HIGH Voltage

V_CC=Min., I_OH=−3 mA

V_CC=Min., I_OH=−15 mA

V_CC=Min., I_OH=−32 mA

V_CC=Min., I_OL=64 mA

2.4

3.5

V

2.0

3.0

V

V_OL

Output LOW Voltage

0.2

0.55

V

Output Drive Characteristics for CY74FCT162646T

Parameter

Description

Output LOW Current^[7]

Output HIGH Current^[7]

Output HIGH Voltage

Output LOW Voltage

Test Conditions

V_CC=5V, V_IN=V_IHor V_IL, V_OUT=1.5V

V_CC=Min., I_OH=−24 mA

Min.

60

Typ.^[5]

115

Max.

150

Unit

mA

V

I_ODL

I_ODH

−60

2.4

−115

3.3

−150

V_OH

V_OL

V_CC=Min., I_OL=24 mA

0.3

0.55

V

Notes:

4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

5. Typical values are at V_CC= 5.0V, T_A= +25˚C ambient.

6. This parameter is speciﬁed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter

tests, I_OStests should be performed last.

8. This parameter is measured at characterization but not tested.

9. Tested at +25˚C.

4

CY74FCT16646T

CY74FCT162646T

Capacitance (T_A= +25˚C, f = 1.0 MHz)

Symbol

Description^[8]

Conditions

V_IN= 0V

Typ.

4.5

Max.

6.0

Unit

pF

C_IN

Input Capacitance

Output Capacitance

C_OUT

V_OUT=0V

5.5

8.0

pF

Power Supply Characteristics

Parameter

Description

Test Conditions^[10]

Min. Typ.^[5]

Max.

Unit

I_CC

Quiescent Power Supply Current V_CC=Max.

V_IN<0.2V

V_IN>V_CC−0.2V

—

5

500

µA

∆I_CC

Quiescent Power Supply Current V_CC= Max.

0.5

75

1.5

mA

TTL Inputs HIGH

V_IN=3.4V^[11]

I_CCD

Dynamic Power Supply

Current^[12]

V_CC=Max.

V_IN=V_CCor

V_IN=GND

120

µA/MHz

Outputs Open

DIR=OE=GND

One-Bit Toggling

50% Duty Cycle

I_C

Total Power Supply Current^[13]

V_CC=Max.

V_IN=V_CCor

V_IN=GND

—

0.8

1.3

1.7

3.2

mA

Outputs Open

f_o=10 MHz (CLKBA)

50% Duty Cycle

DIR=OE=GND

One-Bit Toggling

f₁=5 MHz

V_IN=3.4V or

V_IN=GND

50% Duty Cycle

V_CC=Max.

Outputs Open

V_IN=V_CCor

V_IN=GND

—

3.8

8.3

6.5^[14]

f_o=10 MHz (CLKBA)

50% Duty Cycle

DIR=OE=GND

Sixteen-Bits Toggling

f₁=2.5 MHz

V_IN=3.4V or

V_IN=GND

20.0^[14]

50% Duty Cycle

Notes:

10. For conditions shown as Max. or Min., use appropriate value speciﬁed under Electrical Characteristics for the applicable device type.

11. Per TTL driven input (V_IN=3.4V); all other inputs at V_CCor GND.

12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

13. I_C

I_C

=

I_QUIESCENT+ I_INPUTS+ I_DYNAMIC

I_CC+∆I_CCD_HN_T+I_CCD(f₀/2 + f₁N₁)

Quiescent Current with CMOS input levels

Power Supply Current for a TTL HIGH input (V_IN=3.4V)

Duty Cycle for TTL inputs HIGH

I_CC

∆I_CC

D_H

N_T

I_CCD

f₀

f₁

N₁

Number of TTL inputs at D_H

Dynamic Current caused by an input transition pair (HLH or LHL)

Clock frequency for registered devices, otherwise zero

Input signal frequency

Number of inputs changing at f₁

All currents are in milliamps and all frequencies are in megahertz.

14. Values for these conditions are examples of the ICC formula. These limits are speciﬁed but not tested.

5

CY74FCT16646T

CY74FCT162646T

Switching Characteristics Over the Operating Range^[15]

CY74FCT16646AT

CY74FCT162646AT

CY74FCT16646T

Parameter

t_PLH

t_PHL

Description

Propagation Delay

Bus to Bus

Min.

Max.

Min.

Max.

Unit

Fig. No.^[16]

1.5

9.0

1.5

6.3

ns

1, 2

t_PZH

t_PZL

Output Enable Time

DIR or OE to Bus

1.5

2.0

1.5

5.0

—

14.0

9.0

11.0

—

1.5

2.0

1.5

5.0

—

9.8

6.3

7.7

—

ns

1, 7, 8

1, 5

1,5

4

t_PHZ

t_PLZ

Output Disable Time

DIR or OE to Bus

t_PLH

t_PHL

Propagation Delay

Clock to Bus

t_PLH

t_PHL

Propagation Delay

SBA or SAB to Bus

t_SU

Set-Up Time HIGH or

LOW Bus to Clock

t_H

Hold Time HIGH or

LOW Bus to Clock

—

4

t_W

Clock Pulse Width

HIGH or LOW

Output Skew^[17]

—

6

t_SK(O)

0.5

—

CY74FCT16646CT

CY74FCT16646ET

CY74FCT162646CT CY74FCT162646ET

Parameter

t_PLH

t_PHL

t_PZH

t_PZL

t_PHZ

t_PLZ

t_PLH

t_PHL

t_PLH

t_PHL

t_SU

Description

Min.

Max.

Min.

Max.

Unit

Fig. No.^[16]

Propagation Delay

Bus to Bus

1.5

5.4

1.5

3.8

ns

1, 2

Output Enable Time

DIR or OE to Bus

1.5

2.0

1.5

5.0

—

7.8

6.3

5.7

6.2

—

1.5

2.0

0.0

3.0

—

4.8

4.0

3.8

4.2

—

ns

1, 7, 8

1, 5

1,5

4

Output Disable Time

DIR or OE to Bus

Propagation Delay

Clock to Bus

Propagation Delay

SBA or SAB to Bus

Set-Up Time HIGH or

LOW Bus to Clock

t_H

Hold Time HIGH or

LOW Bus to Clock

—

4

t_W

Clock Pulse Width

HIGH or LOW

Output Skew^[17]

—

6

t_SK(O)

0.5

—

Notes:

15. Minimum limits are speciﬁed but not tested on Propagation Delays.

16. See “Parameter Measurement Information” in the General Information section.

17. Skew any two outputs of the same package switching in the same direction. This parameter is ensured by design.

6

CY74FCT16646T

CY74FCT162646T

Ordering Information CY74FCT16646

Speed

Package

Name

Operating

Range

(ns)

3.8

5.4

6.3

9.0

Ordering Code

Package Type

56-Lead (300-Mil) SSOP

CY74FCT16646ETPVC/PVCT

CY74FCT16646CTPVC/PVCT

CY74FCT16646ATPVC/PVCT

CY74FCT16646TPVC/PVCT

O56

Industrial

56-Lead (300-Mil) SSOP

Ordering Information CY74FCT162646

Speed

Package

Name

Operating

Range

(ns)

Ordering Code

74FCT162646ETPACT

CY74FCT162646ETPVC

74FCT162646ETPVCT

74FCT162646CTPACT

CY74FCT162646CTPVC

74FCT162646CTPVCT

74FCT162646ATPACT

CY74FCT162646ATPVC

74FCT162646ATPVCT

Package Type

3.8

Z56

O56

Z56

O56

Z56

O56

56-Lead (240-Mil) TSSOP

56-Lead (300-Mil) SSOP

56-Lead (240-Mil) TSSOP

56-Lead (300-Mil) SSOP

56-Lead (240-Mil) TSSOP

56-Lead (300-Mil) SSOP

Industrial

5.4

6.3

7

CY74FCT16646T

CY74FCT162646T

Package Diagrams

56-Lead Shrunk Small Outline Package O56

56-Lead Thin Shrunk Small Outline Package Z56

8

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	CY74FCT16646TSSOP
厂家：	TEXAS INSTRUMENTS
描述：	16-Bit Registered Transceivers 16位寄存收发器
文件：	总9页 (文件大小：77K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY74FCT16646TSSOP [TI]

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