CY74FCT2646ATQCT [TI]

8-Bit Registered Transceiver; 8位寄存收发器


型号：	CY74FCT2646ATQCT
厂家：	TEXAS INSTRUMENTS
描述：	8-Bit Registered Transceiver 8位寄存收发器总线驱动器总线收发器逻辑集成电路光电二极管
文件：	总7页 (文件大小：53K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY74FCT2646T

SCCS043 - September 1994 - Revised March 2000

8-Bit Registered Transceiver

Features

Functional Description

• Function and pinout compatible with FCT and F logic

• FCT-C speed at 5.4 ns max.

FCT-A speed at 6.3 ns max.

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

• 25Ω output series resistors to reduce transmission line

reﬂection noise

• Reduced V_OH(typically=3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

The FCT2646T consists of a bus transceiver circuit with

three-state, D-type ﬂip-ﬂops, and control circuitry arranged for

multiplexed transmission of data directly from the input bus or

from the internal registers. Data on the A or B bus will be

clocked into the registers as the appropriate clock pin goes to

a HIGH logic level. Enable Control G and direction pins are

provided to control the transceiver function. On-chip termina-

tion resistors have been added to the outputs to reduce system

noise caused by reﬂections so that the FCT2646T can be used

to replace the FCT646T in an existing design.

In the transceiver mode, data present at the high impedance

port may be stored in either the A or B register, or in both.

Select controls can multiplex stored and real-time (transparent

mode) data. The direction control determines which bus will

receive data when the enable control G is Active LOW. In the

isolation mode (enable control G HIGH), A data may be stored

in the B register and/or B data may be stored in the A register.

• Power-off disable feature permits live insertion

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Sink current

12 mA

Source current 15 mA

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

• Independent register for A and B buses

• Extended commercial temp. range of –40˚C to +85˚C

• Three-state output

Pin Configurations

Functional Block Diagram

QSOP

Top View

DIR

CPBA

SBA

CPAB

SAB

DIR

CPBA

SBA

CPAB

SAB

GND

FCT2646T–3

Logic Block Diagram

CPAB

SAB

DIR

CPBA

SBA

TO 7 OTHERCHANNELS

FCT2646T

–1

FCT2646T–4

CY74FCT2646T

Pin Description

Name

Description

Data Register A Inputs, Data Register B Outputs

Data Register B Inputs, Data Register A Outputs

Clock Pulse Inputs

CPAB, CPBA

SAB, SBA

DIR, G

Output Data Source Select Inputs

Output Enable Inputs

BUS A

BUS B

BUS A

BUS B

DIR

CPAB

CPBA

SAB

SBA

DIR

CPAB

CPBA

SAB

SBA

Real-Time Transfer

Bus B to Bus A

Real-Time Transfer

Bus A to Bus B

BUS A

BUS B

BUS A

[1]

DIR

CPAB

CPBA

SAB

SBA

DIR

CPAB

H or L

CPBA

H or L

SAB

SBA

Storage from

A and/or B

Transfer Stored Data

to A and/or B

Note:

1. Cannot transfer data to A bus and B bus simultaneously.

CY74FCT2646T

Function Table^[2]

Inputs

Data I/O^[3]

Operation or Function

FCT2646T

DIR

CPAB

CPBA

SAB

SBA

A₁thru A₈

B₁thru B₈

H or L

Input

Output

Input

Isolation

Store A and B Data

Input

Real Time B Data to A Bus

Stored B Data to A Bus

H or L

Output

Real Time A Data to B Bus

Stored A Data to B Bus

H or L

Maximum Ratings^{[4, 5]}

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–65°C to +135°C

Operating Range

Ambient

Supply Voltage to Ground Potential ............... –0.5V to +7.0V

DC Input Voltage............................................ –0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

Range

Temperature

V_CC

Commercial

–40°C to +85°C

5V ± 5%

Electrical Characteristics Over the Operating Range

Parameter

V_OH

V_OL

R_OUT

V_IH

Description

Output HIGH Voltage

Output LOW Voltage

Output Resistance

Input HIGH Voltage

Input LOW Voltage

Hysteresis^[7]

Test Conditions

V_CC=Min., I_OH=–15 mA

Min.

Typ^[6]

Max.

Unit

2.4

3.3

0.3

V_CC=Min., I_OL=12 mA

0.55

Ω

2.0

V_IL

0.8

V_H

All inputs

0.2

V_IK

Input Clamp Diode Voltage

Input HIGH Current

Input LOW Current

V_CC=Min., I_IN=–18 mA

V_CC=Max., V_IN=V_CC

V_CC=Max., V_IN=2.7V

V_CC=Max., V_IN=0.5V

–0.7

–1.2

I_IH

µA

I_IH

±1

I_IL

±1

I_OS

Output Short Circuit Current^[8]V_CC=Max., V_OUT=0.0V

–60

–120

–225

±1

I_OFF

Power-Off Disable V_CC=0V, V_OUT=4.5V

Notes:

2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.

3. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled, i.e., data at the bus

pins will be stored on every LOW-to-HIGH transition of the clock inputs.

4. Unless otherwise noted, these limits are over the operating free-air temperature range.

5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V_CCor ground.

6. Typical values are at V_CC=5.0V, T_A=+25˚C ambient.

7. This parameter is speciﬁed but not tested.

8. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, I_OStests should be performed last.

CY74FCT2646T

Capacitance^[7]

Parameter

C_IN

Description

Typ.^[6]

Max.

Unit

Input Capacitance

Output Capacitance

C_OUT

Power Supply Characteristics

Parameter

Description

Test Conditions

V_CC=Max., V_IN≤0.2V,

_IN≥V_CC–0.2V

Typ.^[6]

Max.

Unit

I_CC

Quiescent Power Supply Current

0.1

0.2

∆I_CC

Quiescent Power Supply Current

(TTL inputs HIGH)

V_CC=Max., V_IN=3.4V,^[9]

f₁=0, Outputs Open

0.5

2.0

I_CCD

Dynamic Power Supply Current^[10]V_CC=Max., One Input Toggling,

50% Duty Cycle, Outputs Open,

0.06

0.12

mA/

MHz

G=DIR=GND, GAB=GBA=GND,

V_IN≤0.2V or V_IN≥V_CC–0.2V

I_C

Total Power Supply Current^[11]

V_CC=Max., f₀=10 MHz,

0.7

1.2

2.8

5.1

1.4

3.4

50% Duty Cycle, Outputs Open,

One Bit Toggling at f₁=5 MHz,

G=DIR=GND, GAB=GBA=GND,

V_IN≤0.2V or V_IN≥V_CC–0.2V

V_CC=Max., f₀=10 MHz,

50% Duty Cycle, Outputs Open,

One Bit Toggling at f₁=5 MHz,

G=DIR=GND, GAB=GBA=GND,

V_IN=3.4V or V_IN=GND

V_CC=Max., f₀=10 MHz,

5.6^[12]

50% Duty Cycle, Outputs Open,

Eight Bits Toggling at f₁=5 MHz,

G=DIR=GND, GAB=GBA=GND,

V_IN≤0.2V or V_IN≥V_CC–0.2V

V_CC=Max., f₀=10 MHz,

14.6^[12]

50% Duty Cycle, Outputs Open,

Eight Bits Toggling at f₁=5 MHz,

G=DIR=GND, GAB=GBA=GND,

V_IN=3.4V or V_IN=GND

Notes:

9. Per TTL driven input (V_IN=3.4V); all other inputs at V_CCor GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

11. I_C

I_C

I_QUIESCENT+ I_INPUTS+ I_DYNAMIC

I_CC+∆I_CCD_HN_T+I_CCD(f₀/2 + f₁N₁)

Quiescent Current with CMOS input levels

Power Supply Current for a TTL HIGH input (V_IN=3.4V)

Duty Cycle for TTL inputs HIGH

I_CC

∆I_CC

D_H

N_T

I_CCD

f₀

Number of TTL inputs at D_H

Dynamic Current caused by an input transition pair (HLH or LHL)

Clock frequency for registered devices, otherwise zero

Input signal frequency

f₁

N₁

Number of inputs changing at f₁

All currents are in milliamps and all frequencies are in megahertz.

12. Values for these conditions are examples of the I_CCformula. These limits are speciﬁed but not tested.

CY74FCT2646T

Switching Characteristics Over the Operating Range^[13]

CY74FCT2646AT

CY74FCT2646CT

Parameter

t_PLH

Description

Min.

Max.

Min.

Max.

Unit

Fig. No.^[14]

Propagation Delay Bus to Bus

1.5

6.3

1.5

5.4

1, 3

t_PHL

t_PZH

t_PZL

Output Enable Time Enable to

Bus and DIR to A_nor B_n

1.5

2.0

1.5

5.0

9.8

6.3

7.7

1.5

2.0

1.5

5.0

7.8

6.3

5.7

6.2

1, 7, 8

1, 5

t_PHZ

t_PLZ

Output Disable Time

G to Bus and DIR to Bus

t_PLH

t_PHL

Propagation Delay

Clock to Bus

t_PLH

t_PHL

Propagation Delay

SBA or SAB to A or B

t_S

Set-Up Time HIGH or LOW, Bus

to Clock

t_H

Hold Time HIGH or LOW,

Bus to Clock

Pulse Width,^[7]

HIGH or LOW

t_W

Notes:

13. Minimum limits are speciﬁed but not tested on Propagation Delays.

14. See “Parameter Measurement Information” in the General Information section.

Ordering Information

Speed

(ns)

Package

Name

Operating

Range

Ordering Code

CY74FCT2646CTQCT

CY74FCT2646ATQCT

Package Type

5.4

6.3

Q13

24-Lead (150-Mil) QSOP

Commercial

Document #: 38-00599

CY74FCT2646T

Package Diagrams

24-Lead Quarter Size Outline Q13

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CY74FCT2646ATQCT [TI]

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