CY74FCT2827ATQCTE4 [TI]

FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, QSOP-24;
CY74FCT2827ATQCTE4
型号: CY74FCT2827ATQCTE4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, QSOP-24

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总12页 (文件大小:546K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CY74FCT2827T  
10-BIT BUFFER  
WITH 3-STATE OUTPUTS  
SCCS045A – MAY 1994 – REVISED SEPTEMBER 2001  
Q PACKAGE  
(TOP VIEW)  
Function and Pinout Compatible With FCT,  
F, and AM29827 Logic  
25-Output Series Resistors Reduce  
Transmission-Line Reflection Noise  
OE  
D
D
D
D
D
D
D
D
D
D
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
0
1
2
3
4
5
6
7
8
9
CC  
0
2
Reduced V  
of Equivalent FCT Functions  
(Typically = 3.3 V) Versions  
3
OH  
1
4
2
5
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
3
6
4
7
5
8
6
I
Supports Partial-Power-Down Mode  
off  
9
7
Operation  
10  
11  
12  
8
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
9
GND  
OE  
2
– 1000-V Charged-Device Model (C101)  
Matched Rise and Fall Times  
Fully Compatible With TTL Input and  
Output Logic Levels  
12-mA Output Sink Current  
15-mA Output Source Current  
3-State Outputs  
description  
The CY74FCT2827T 10-bit buffer provides high-performance bus-interface buffering for wide data/address  
paths or buses carrying parity. This 10-bit buffer has NANDed output-enable (OE) inputs for maximum control  
flexibility. The CY74FCT2827T is designed for high-capacitance-load drive capability, while providing  
low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are  
designed for low-capacitance bus loading in the high-impedance state. On-chip termination resistors at the  
outputs reduce system noise caused by reflections. The CY74FCT2827T can replace the CY74FCT827T to  
reduce noise in an existing design.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
SPEED  
(ns)  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QSOP – Q Tape and reel  
QSOP – Q Tape and reel  
4.4  
8
CY74FCT2827CTQCT  
CY74FCT2827ATQCT  
FCT2827C  
FCT2827A  
–40°C to 85°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CY74FCT2827T  
10-BIT BUFFER  
WITH 3-STATE OUTPUTS  
SCCS045A MAY 1994 REVISED SEPTEMBER 2001  
FUNCTION TABLE  
OUTPUT  
INPUTS  
FUNCTION  
Transparent  
3-State  
Y
OE  
L
OE  
L
D
L
1
2
L
H
Z
Z
L
L
H
X
X
H
X
X
H
H = High logic level, L = Low logic level, X = Dont care,  
Z = High-impedance state  
logic diagram (positive logic)  
1
OE  
OE  
1
2
13  
2
23  
D
Y
0
0
To Nine Other Channels  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA  
Package thermal impedance, θ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W  
JA  
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 135°C  
A
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.  
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Note 2)  
MIN NOM  
MAX  
UNIT  
V
V
V
V
Supply voltage  
4.75  
2
5
5.25  
CC  
High-level input voltage  
Low-level input voltage  
High-level output current  
Low-level output current  
Operating free-air temperature  
V
IH  
0.8  
15  
12  
V
IL  
I
mA  
mA  
°C  
OH  
OL  
I
T
A
40  
85  
NOTE 2: All unused inputs of the device must be held at V  
or GND to ensure proper device operation.  
CC  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CY74FCT2827T  
10-BIT BUFFER  
WITH 3-STATE OUTPUTS  
SCCS045A MAY 1994 REVISED SEPTEMBER 2001  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
2.4  
20  
TYP  
MAX  
UNIT  
V
V
V
V
V
CC  
V
CC  
V
CC  
V
CC  
= 4.75,  
= 4.75,  
= 4.75,  
= 4.75,  
I
I
I
I
= 18 mA  
0.7  
3.3  
0.3  
25  
1.2  
IK  
IN  
= 15 mA  
= 12 mA  
= 12 mA  
V
OH  
OL  
OH  
OL  
OL  
0.55  
40  
V
R
out  
V
hys  
All inputs  
0.2  
V
I
I
I
I
I
I
I
I
V
V
V
V
V
V
V
V
V
V
= 5.25 V,  
= 5.25 V,  
= 5.25 V,  
= 5.25 V,  
= 0 V,  
V
V
V
V
V
V
V
V
= V  
CC  
5
±1  
µA  
µA  
µA  
mA  
µA  
µA  
µA  
mA  
mA  
I
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
IN  
= 2.7 V  
= 0.5 V  
IH  
IL  
IN  
±1  
IN  
= 0 V  
60  
120  
225  
±1  
OS  
off  
OUT  
OUT  
OUT  
OUT  
= 4.5 V  
= 2.7 V  
= 0.5 V  
= 5.25 V,  
= 5.25 V,  
= 5.25 V,  
10  
OZH  
OZL  
CC  
10  
0.2  
2
0.2 V,  
V
V  
0.2 V  
0.1  
0.5  
IN  
§
IN CC  
I  
= 5.25 V, V = 3.4 V , f = 0, Outputs open  
IN  
CC  
1
= 5.25 V, One input switching at 50% duty cycle, Outputs open,  
mA/  
MHz  
I
0.06  
0.12  
CCD  
OE or OE = GND, V 0.2 V or V V  
0.2 V,  
1
2
IN  
IN  
CC  
V
V
0.2 V or  
One bit switching  
at f = 10 MHz  
1
at 50% duty cycle  
IN  
IN  
0.7  
1
1.4  
2.4  
V  
0.2 V  
CC  
V
= 5.25 V,  
CC  
V
IN  
= 3.4 V or GND  
#
I
mA  
Outputs open,  
C
V
V
0.2 V or  
Ten bits switching  
at f = 2.5 MHz  
1
at 50% duty cycle  
IN  
IN  
||  
OE or OE = GND  
1.6  
3.2  
1
2
V  
0.2 V  
CC  
||  
13.2  
V
IN  
= 3.4 V or GND  
4.1  
5
C
C
10  
12  
pF  
pF  
i
9
o
Typical values are at V  
CC  
= 5 V, T = 25°C.  
A
Notmorethanoneoutputshouldbeshortedatatime.Durationofshortshouldnotexceedonesecond.Theuseofhigh-speedtestapparatusand/or  
sample-and-holdtechniquesarepreferabletominimizeinternalchipheatingandmoreaccuratelyreflectoperationalvalues.Otherwise,prolonged  
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence  
of parameter tests, I  
Per TTL-driven input (V = 3.4 V); all other inputs at V  
tests should be performed last.  
OS  
§
#
or GND  
IN CC  
This parameter is derived for use in total power-supply calculations.  
= I + I × D × N + I (f /2 + f × N )  
I
C
CC  
CC  
H
T
CCD  
0
1
1
Where:  
I
I
I  
D
N
= Total supply current  
= Power-supply current with CMOS input levels  
C
CC  
CC  
H
T
= Power-supply current for a TTL high input (V = 3.4 V)  
IN  
= Duty cycle for TTL inputs high  
= Number of TTL inputs at D  
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)  
= Clock frequency for registered devices, otherwise zero  
= Input signal frequency  
CCD  
0
1
N
= Number of inputs changing at f  
1
1
All currents are in milliamperes and all frequencies are in megahertz.  
||  
Values for these conditions are examples of the I  
CC  
formula.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CY74FCT2827T  
10-BIT BUFFER  
WITH 3-STATE OUTPUTS  
SCCS045A MAY 1994 REVISED SEPTEMBER 2001  
switching characteristics over operating free-air temperature range (see Figure 1)  
CY74FCT2827AT CY74FCT2827CT  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
TEST LOAD  
UNIT  
ns  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
8
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
4.4  
4.4  
10  
10  
7
t
t
t
t
t
t
t
t
t
t
t
t
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PZH  
PZL  
PHZ  
PLZ  
PHZ  
PLZ  
C
R
= 50 pF,  
= 500 Ω  
L
L
D
Y
Y
Y
Y
Y
Y
8
15  
15  
12  
12  
23  
23  
9
C
R
= 300 pF,  
L
D
ns  
= 500 Ω  
L
C
R
= 50 pF,  
= 500 Ω  
L
L
ns  
OE  
OE  
OE  
OE  
7
14  
14  
5.7  
5.7  
6
C
R
= 300 pF,  
L
ns  
= 500 Ω  
L
C
= 5 pF,  
= 500 Ω  
L
ns  
R
9
L
9
C
R
= 50 pF,  
= 500 Ω  
L
L
ns  
9
6
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CY74FCT2827T  
10-BIT BUFFER  
WITH 3-STATE OUTPUTS  
SCCS045A MAY 1994 REVISED SEPTEMBER 2001  
PARAMETER MEASUREMENT INFORMATION  
7 V  
Open  
GND  
S1  
500 Ω  
From Output  
Under Test  
From Output  
Under Test  
Test  
Point  
TEST  
/t  
S1  
t
Open  
7 V  
PLH PHL  
C
= 50 pF  
C
= 50 pF  
L
L
500 Ω  
500 Ω  
t
/t  
PLZ PZL  
/t  
(see Note A)  
(see Note A)  
t
Open  
PHZ PZH  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
LOAD CIRCUIT FOR  
3-STATE OUTPUTS  
3 V  
0 V  
1.5 V  
Timing Input  
Data Input  
t
w
t
h
t
3 V  
su  
3 V  
0 V  
1.5 V  
Input  
1.5 V  
1.5 V  
1.5 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
t
t
t
t
t
PLH  
PHL  
PLH  
PZL  
PZH  
PLZ  
3.5 V  
V
Output  
Waveform 1  
(see Note B)  
OH  
In-Phase  
Output  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
V
V
+ 0.3 V  
OL  
V
OL  
V
OL  
t
t
PHL  
PHZ  
V
V
V
OH  
OH  
Output  
Waveform 2  
(see Note B)  
Out-of-Phase  
Output  
0.3 V  
OH  
1.5 V  
1.5 V  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
CY74FCT2827ATQCT  
CY74FCT2827ATQCTE4  
CY74FCT2827ATQCTG4  
CY74FCT2827CTQCT  
CY74FCT2827CTQCTE4  
CY74FCT2827CTQCTG4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SSOP  
SSOP  
SSOP  
SSOP  
SSOP  
DBQ  
DBQ  
DBQ  
DBQ  
DBQ  
DBQ  
24  
24  
24  
24  
24  
24  
2500  
2500  
2500  
2500  
2500  
2500  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CY74FCT2827ATQCT  
CY74FCT2827CTQCT  
SSOP  
SSOP  
DBQ  
DBQ  
24  
24  
2500  
2500  
330.0  
330.0  
16.4  
16.4  
6.5  
6.5  
9.0  
9.0  
2.1  
2.1  
8.0  
8.0  
16.0  
16.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CY74FCT2827ATQCT  
CY74FCT2827CTQCT  
SSOP  
SSOP  
DBQ  
DBQ  
24  
24  
2500  
2500  
367.0  
367.0  
367.0  
367.0  
38.0  
38.0  
Pack Materials-Page 2  
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