CY74FCT480BTPCE4 [TI]
Dual 8-Bit Parity Generator/Checker 24-PDIP -40 to 85;
| 型号： | CY74FCT480BTPCE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 8-Bit Parity Generator/Checker 24-PDIP -40 to 85 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
CY74FCT480T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced V
of Equivalent FCT Functions
(Typically = 3.3 V) Versions
OH
A
B
C
D
E
F
G
H
V
A
B
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
1
1
1
1
1
1
1
1
1
CC
2
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
2
C
D
E
2
2
I
Supports Partial-Power-Down Mode
2
2
off
F
Operation
G
H
2
Matched Rise and Fall Times
PAR
2
Fully Compatible With TTL Input and
Output Logic Levels
CHK/GEN 10
ODD
11
GND 12
15 PAR
2
14 ERROR
13 ODD
1
Two 8-Bit Parity Generators/Checkers
Open-Drain Active-Low Parity-Error Output
Expandable for Larger Word Widths
2
CY54FCT480T . . . L PACKAGE
(TOP VIEW)
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
4
3
2
1 28 27 26
25
24
23
22
21
20
19
C
D
E
D
E
F
NC
G
5
1
1
1
2
2
CY54FCT480T
– 32-mA Output Sink Current
– 12-mA Output Source Current
6
7
2
NC
8
CY74FCT480T
– 64-mA Output Sink Current
– 32-mA Output Source Current
F
9
1
2
H
1
PAR
G
2
H
10
11
1
2
12 13 14 15 16 17 18
description
The ’FCT480T devices are high-speed, dual,
8-bit parity generators/checkers. Each parity
generator/checker accepts eight data bits and
one parity bit as inputs, and generates a sum and
parity-error (ERROR) output. These devices can
be used in odd-parity systems. ERROR is an
open-drain output designed for easy expansion of
NC – No internal connection
the word width by a wired-OR connection of several ’FCT480T devices. Because no additional logic is needed,
the parity-generation or parity-checking times remain the same as for an individual ’FCT480T device.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
DIP – P
Tube
6.1
6.1
6.1
6.1
7.5
7.5
7
CY74FCT480BTPC
CY74FCT480BTQCT
CY74FCT480BTSOC
CY74FCT480BTSOCT
CY74FCT480ATPC
CY74FCT480ATQCT
CY54FCT480BTLMB
CY74FCT480BTPC
FCT480B
QSOP – Q
Tape and reel
Tube
–40°C to 85°C SOIC – SO
FCT480B
Tape and reel
Tube
DIP – P
QSOP – Q
CY74FCT480ATPC
FCT480A
Tape and reel
Tube
–55°C to 125°C LCC – L
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
CHK/GEN PAR
OUTPUTS
A –H
A –H
PAR
H
H
L
ODD
L
ODD
L
ERROR
1
1
2
2
1
2
1
2
H
H
H
H
L
H
L
H
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
H
H
H
L
L
Number of
A –H inputs,
high is even
H
L
H
H
H
H
H
L
2
2
L
H
H
L
Number of
A –H inputs,
X
H
L
X
H
H
L
1
1
H
H
H
H
L
high is even
H
L
Number of
H
L
inputs A –H ,
2
2
high is odd
L
H
H
H
L
L
X
H
L
X
H
H
L
L
H
H
H
H
L
L
L
Number of
A –H inputs,
high is even
H
L
H
L
H
H
H
H
H
L
2
2
L
Number of
A –H inputs,
X
H
L
X
H
H
L
L
1
1
H
H
H
H
L
H
L
high is odd
Number of
A –H inputs,
high is odd
H
L
H
L
2
2
L
L
X
X
L
L
H = High logic level, L = Low logic level, X = Don’t care
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
logic diagram
1
A
B
1
1
2
3
4
5
6
7
8
C
D
1
1
11
E
F
ODD
1
1
1
1
1
G
H
9
PAR
1
14
10
ERROR
CHK/GEN
23
22
21
20
19
18
17
16
A
B
2
2
C
D
2
2
13
E
F
ODD
2
2
2
2
2
G
H
15
PAR
2
Pin numbers shown are for the P, Q, and SO packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
(see Note 2): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
(see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
recommended operating conditions (see Note 3)
CY54FCT480T
MIN NOM MAX
CY74FCT480T
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–12
32
0.8
–32
64
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
–40
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CY54FCT480T
CY74FCT480T
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
= 4.5 V,
= 4.75 V,
= 4.5 V,
I
I
I
I
I
I
I
= –18 mA
= –18 mA
–0.7
–1.2
CC
CC
CC
IN
V
V
IK
–0.7
–1.2
IN
= –12 mA
= –15 mA
= –32 mA
= 32 mA
= 64 mA
2.4
3.3
OH
OH
OH
OL
OL
V
OH
2.4
2
3.3
V
V
CC
= 4.75 V
V
V
= 4.5 V,
0.3
0.2
0.55
CC
V
V
V
V
OL
= 4.75 V,
0.3
0.2
0.55
CC
All inputs
hys
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= V
= V
5
±1
±1
IN
IN
IN
IN
IN
IN
CC
CC
I
µA
I
5
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
I
IH
µA
±1
I
I
I
µA
µA
IL
±1
±1
= 4.5 V
= 0 V
±1
off
OS
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
–60
–120
–225
‡
mA
= 0 V
–60
–120
–225
10
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
10
–10
0.2
2
I
I
I
µA
µA
OZH
OZL
CC
–10
0.2
2
≤ 0.2 V,
V
V
≥ V
≥ V
– 0.2 V
– 0.2 V
0.1
0.5
IN
IN
CC
mA
mA
≤ 0.2 V,
0.1
0.5
IN
IN
CC
§
= 5.5 V, V = 3.4 V , f = 0, Outputs open
IN
1
∆I
CC
§
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
1
†
‡
Typical values are at V
= 5 V, T = 25°C.
CC
A
Notmorethanoneoutputshouldbeshortedatatime.Durationofshortshouldnotexceedonesecond.Theuseofhigh-speedtestapparatusand/or
sample-and-holdtechniquesarepreferabletominimizeinternalchipheatingandmoreaccuratelyreflectoperationalvalues.Otherwise,prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, I
Per TTL-driven input (V = 3.4 V); all other inputs at V
tests should be performed last.
OS
§
or GND
IN CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CY54FCT480T
CY74FCT480T
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
= 5.5 V, Outputs open,
CC
One bit switching at 50% duty cycle,
0.06
0.12
V
≤ 0.2 V or V ≥ V
– 0.2 V
IN
IN CC
mA/
MHz
¶
I
CCD
V
CC
= 5.25 V, Outputs open,
One bit switching at 50% duty cycle,
0.06
0.12
V
IN
≤ 0.2 V or V ≥ V – 0.2 V
IN CC
One bit
switching
V
V
≤ 0.2 V or
IN
IN
0.7
1
1.4
2.4
≥ V
– 0.2 V
CC
at f = 2.5 MHz
1
at 50% duty
cycle
V
IN
= 3.4 V or GND
V
= 5.5 V,
= 0 MHz,
CC
f
0
16 bits
switching
Outputs open
V
V
≤ 0.2 V or
IN
IN
||
2.5
6.5
5
≥ V
– 0.2 V
CC
at f = 2.5 MHz
1
at 50% duty
cycle
||
21
V
IN
= 3.4 V or GND
#
I
C
mA
One bit
switching
V
V
≤ 0.2 V or
IN
IN
0.7
1
1.4
2.4
≥ V
– 0.2 V
CC
at f = 2.5 MHz
1
at 50% duty
cycle
V
IN
= 3.4 V or GND
V
= 5.25 V,
CC
= 0 MHz,
f
0
16 bits
switching
Outputs open
V
IN
V
IN
≤ 0.2 V or
||
5
2.5
≥ V
– 0.2 V
CC
at f = 2.5 MHz
1
at 50% duty
cycle
||
21
V
IN
= 3.4 V or GND
6.5
C
C
5
9
10
12
5
9
10
12
pF
pF
i
o
†
¶
#
Typical values are at V
CC
= 5 V, T = 25°C.
A
This parameter is derived for use in total power-supply calculations.
I = I + ∆I × D × N + I (f /2 + f × N )
C
CC
Where:
I = Total supply current
CC
H
T
CCD
0
1
1
C
CC
I
= Power-supply current with CMOS input levels
∆I = Power-supply current for a TTL high input (V = 3.4 V)
CC IN
D = Duty cycle for TTL inputs high
H
N = Number of TTL inputs at D
T
H
I
= Dynamic current caused by an input transition pair (HLH or LHL)
CCD
f = Clock frequency for registered devices, otherwise zero
0
f = Input signal frequency
1
N = Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
CY74FCT480AT CY54FCT480BT
CY74FCT480BT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
MAX
7.5
7
MIN
MAX
7
MIN
MAX
6.1
t
t
t
t
PLH
PHL
PLH
PHL
ODD
(see Figure 1)
A
6.6
6.3
7.4
6.1
6.5
7.5
5.9
ODD
(see Figure 1)
ns
CHK/GEN
A
5.9
†
t
t
t
t
7
8.5
7.5
7
7
8.1
7.1
6.9
6.1
6.5
5.7
5.5
PLH
PHL
PLH
PHL
ERROR
(see Figure 2)
ns
ERROR
(see Figure 2)
ns
CHK/GEN
†
t
is measured up to V
OUT
= V
+ 0.3 V.
OL
PLH
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
/t
S1
t
Open
7 V
PLH PHL
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
t
/t
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
FOR OPEN-DRAIN OUTPUTS
7 V
V
CC
500 Ω
1.5 V
1.5 V
Input
0 V
From Output
Under Test
Test
Point
t
t
PHL
PLH
≈V
C
CC
L
500 Ω
(see Note A)
1.5 V
Output
V
OL
+ 0.3 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR
OPEN-DRAIN OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
PDIP
Drawing
CY54FCT480BTLMB
CY74FCT480ATPC
ACTIVE
ACTIVE
FK
28
24
1
TBD
POST-PLATE N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
NT
15
Pb-Free
(RoHS)
CY74FCT480ATPCE4
CY74FCT480BTPC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
PDIP
NT
NT
24
24
24
24
24
24
24
24
24
15
15
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
Pb-Free
(RoHS)
CY74FCT480BTPCE4
CY74FCT480BTQCT
CY74FCT480BTQCTE4
CY74FCT480BTQCTG4
CY74FCT480BTSOC
CY74FCT480BTSOCE4
CY74FCT480BTSOCG4
NT
Pb-Free
(RoHS)
SSOP/
QSOP
DBQ
DBQ
DBQ
DW
DW
DW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CY74FCT480BTQCT
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP/QSOP DBQ 24
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
CY74FCT480BTQCT
2500
Pack Materials-Page 2
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power.ti.com
microcontroller.ti.com
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