CY74FCT652CTSOC [TI]

8-Bit Registered Transceiver; 8位寄存收发器


型号：	CY74FCT652CTSOC
厂家：	TEXAS INSTRUMENTS
描述：	8-Bit Registered Transceiver 8位寄存收发器触发器逻辑集成电路光电二极管输出元件
文件：	总7页 (文件大小：65K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY74FCT652T

SCCS032 - September 1994 - Revised March 2000

8-Bit Registered Transceiver

Features

Functional Description

• Function, pinout, and drive compatible with FCT and

F logic

• FCT-C speed at 5.4 ns max. (Com’l)

FCT-A speed at 6.3 ns max. (Com’l)

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

The FCT652T consists of bus transceiver circuits, D-type

ﬂip-ﬂops, and control circuitry arranged for multiplexed

transmission of data directly from the input bus or from the

internal storage registers. GAB and GBA control pins are

provided to control the transceiver functions. SAB and SBA

control pins are provided to select either real-time or stored

data transfer. The circuitry used for select control will eliminate

the typical decoding glitch that occurs in a multiplexer during

the transition between stored and real-time data. A LOW input

level selects real-time data and a HIGH selects stored data.

• Power-off disable feature

• Matched rise and fall times

Data on the A or B data bus, or both, can be stored in the

internal D ﬂip-ﬂops by LOW-to-HIGH transitions at the

appropriate clock pins (CPAB or CPBA), regardless of the

select or enable control pins. When SAB and SBA are in the

real-time transfer mode, it is also possible to store data without

using the internal D-type ﬂip-ﬂops by simultaneously enabling

GAB and GBA. In this conﬁguration, each output reinforces its

input. Thus, when all other data sources to the two sets of bus

lines are at high impedance, each set of bus lines will remain

at its last state.

• Fully compatible with TTL input and output logic levels

• Sink Current

Source Current

64mA

32mA

• Independent register for A and B buses

• Multiplexed real-time and stored data transfer

• Extended commercial range of −40˚C to +85˚C

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

Logic Block Diagram

Pin Configurations

CPBA

GAB

LCC

Top View

SBA

SAB

11 10 9

8 7 6 5

GAB

GBA

SAB

CPAB

GND

CPAB

B REG

CPBA

SBA

1 OF 8 CHANNELS

19 20 21 22 2324 25

SOIC/QSOP

Top View

A REG

CPAB

SAB

CPBA

SBA

GAB

GBA

TO 7 OTHERCHANNELS

GND

CY74FCT652T

BUS A

BUS B

BUS A

BUS B

GAB

GBA

CPAB

CPBA

SAB

SBA

GAB

GBA

CPAB

CPBA

SAB

SBA

Real-Time Transfer

Bus B to Bus A

Real-Time Transfer

Bus A to Bus B

BUS A

BUS B

BUS A

BUS B

GAB

GBA

CPAB

CPBA

SAB

SBA

GAB

GBA

CPAB

H or L

CPBA

H or L

SAB

SBA

Transferred Stored Data

to A and/or B

Store Data from A and/or B

Function Table^[1]

Inputs

Data I/O

GAB

GBA

CPAB

CPBA

SAB

SBA

A₁thru A₈

B₁thru B₈

Operation or Function

H or L

Input

Isolation

Store A and B Data

[2]

Unspeciﬁed

Output

H or L

Input

Store A, Hold B

Store A in both registers

X^[1]

[2]

Unspeciﬁed

Output

H or L

Input

Hold A, Store B

Store B in both registers

X^[1]

Output

Input

Output

Real-Time B Data to A Bus

Stored B Data to A Bus

H or L

Input

Real-Time A Data to B Bus

Stored A Data to B Bus

H or L

Output

Stored A Data to B Bus

and Stored B Data to A Bus

Notes:

1. Select control=L: clocks can occur simultaneously. Select control=H: clocks must be staggered in order to load both registers.

H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition.

2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e., data at the

bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

CY74FCT652T

Maximum Ratings^{[3, 4]}

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

(Above which the useful life may be impaired. For user

guidelines, not tested.)

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–65°C to +135°C

Operating Range

Ambient

Supply Voltage to Ground Potential ............... –0.5V to +7.0V

DC Input Voltage............................................ –0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

Range

Temperature

V_CC

Commercial T, AT, CT

–40°C to +85°C

5V ± 5%

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

2.0

Typ.^[5]

Max.

Unit

V_OH

Output HIGH Voltage

V_CC=Min., I_OH=–32 mA

V_CC=Min., I_OH=–15 mA

V_CC=Min., I_OL=64 mA

2.4

3.3

0.3

V_OL

V_IH

V_IL

V_H

V_IK

I_I

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Hysteresis^[6]

0.55

0.8

2.0

All inputs

0.2

Input Clamp Diode Voltage

Input HIGH Current

Input HIGH Current^[6]

Input LOW Current^[6]

V_CC=Min., I_IN=–18 mA

V_CC=Max., V_IN=V_CC

V_CC=Max., V_IN=2.7V

V_CC=Max., V_IN=0.5V

V_CC=Max., V_OUT=2.7V

–0.7

–1.2

µA

I_IH

±1

I_IL

I_OZH

Off State HIGH-Level

Output Current

I_OZL

Off State LOW-Level

Output Current

V_CC=Max., V_OUT=0.5V

–10

µA

I_OS

Output Short Circuit Current^[7]

V_CC=Max., V_OUT=0.0V

V_CC=0V, V_OUT=4.5V

–60

–120

–225

I_OFF

Power-Off Disable

±1

µA

Capacitance^[6]

Parameter

Description

Typ.^[5]

Max.

Unit

C_IN

Input Capacitance

Output Capacitance

C_OUT

Notes:

3. Unless otherwise noted, these limits are over the operating free-air temperature range.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V_CCor ground.

5. Typical values are at V_CC=5.0V, T_A=+25˚C ambient.

6. This parameter is speciﬁed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, I_OStests should be performed last.

CY74FCT652T

Power Supply Characteristics

Parameter

Description

Test Conditions

Typ.^[5]

Max.

Unit

I_CC

Quiescent Power Supply

Current

V_CC=Max., V_IN≤0.2V, V_IN≥V_CC–0.2V

0.1

0.2

∆I_CC

Quiescent Power Supply

Current (TTL inputs HIGH)

V_CC=Max., V_IN=3.4V, f₁=0, Outputs Open^[8]

0.5

2.0

I_CCD

Dynamic Power Supply

Current^[9]

V_CC=Max., One Input Toggling,

50% Duty Cycle, Outputs Open,

GAB=GND, GBA=GND,

0.06

0.12

mA/MHz

V_IN≤0.2V or V_IN≥V_CC–0.2V

I_C

Total Power Supply Current^[10]

V_CC=Max., f₀=10 MHz, 50% Duty Cycle,

Outputs Open, One Bit Toggling at f₁=5 MHz,

GAB=GND, GBA=GND, SAB=CPAB=GND

SBA=V_CC, V_IN≤0.2V or V_IN≥V_CC–0.2V

0.7

1.2

2.8

5.1

1.4

3.4

V_CC=Max., f₀=10 MHz, 50% Duty Cycle,

Outputs Open, One Bit Toggling at f₁=5 MHz,

GAB=GND, GBA=GND, SAB=CPAB=GND

SBA=V_CC, V_IN=3.4V or V_IN=GND

V_CC=Max., f₀=10 MHz, 50% Duty Cycle,

Outputs Open, Eight Bits Toggling at f₁=5 MHz,

GAB=GBA=GND, SAB=CPAB=GND

5.6^[11]

SBA=V_CC, V_IN≤0.2V or V_IN≥V_CC–0.2V

V_CC=Max., f₀=10 MHz, 50% Duty Cycle,

Outputs Open, Eight Bits Toggling at f₁=5 MHz,

GAB=GBA=GND, SAB=CPAB=GND

SBA=V_CC, V_IN=3.4V or V_IN=GND

14.6^[11]

Notes:

8. Per TTL driven input (V_IN=3.4V); all other inputs at V_CCor GND.

9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

10. I_C

I_C

= I_QUIESCENT+ I_INPUTS+ I_DYNAMIC

= I_CC+∆I_CCD_HN_T+I_CCD(f₀/2 + f₁N₁)

I_CC= Quiescent Current with CMOS input levels

∆I_CC= Power Supply Current for a TTL HIGH input (V_IN=3.4V)

D_H

N_T

= Duty Cycle for TTL inputs HIGH

= Number of TTL inputs at D_H

I_CCD= Dynamic Current caused by an input transition pair (HLH or LHL)

f₀

f₁

= Clock frequency for registered devices, otherwise zero

= Input signal frequency

N₁

= Number of inputs changing at f₁

All currents are in milliamps and all frequencies are in megahertz.

11. Values for these conditions are examples of the I_CCformula. These limits are speciﬁed but not tested.

CY74FCT652T

Switching Characteristics Over the Operating Range^[12]

FCT652T

Commercial

FCT652AT

FCT652CT

Commercial

Fig.

Parame-

ter

Description

Propagation Delay

Bus to Bus

Min.

Max.

Min.

Max.

Min.

Max.

Unit

No.^[13]

t_PLH

t_PHL

1.5

9.0

1.5

6.3

1.5

5.4

1, 3

1, 7, 8

1, 5

t_PZH

t_PZL

Output Enable Time Enable to Bus

1.5

4.0

14.0

9.0

1.5

2.0

9.8

6.3

7.7

1.5

2.0

7.8

6.3

5.7

6.2

t_PHZ

t_PLZ

Output Disable Time Enable to Bus

t_PLH

t_PHL

Propagation Delay

Clock to Bus

9.0

t_PLH

t_PHL

Propagation Delay

SBA or SAB to A or B

11.0

1, 5

t_S

Set-Up Time

HIGH or LOW

Bus to Clock

t_H

Hold Time

HIGH or LOW

Bus to Clock

Clock Pulse Width,^[14]

HIGH or LOW

2.0

6.0

1.5

5.0

1.5

5.0

t_W

Ordering Information

Speed

Package

Operating

Range

(ns)

Ordering Code

Name

Q13

S13

Package Type

5.4

CY74FCT652CTQCT

24-Lead (150-Mil) QSOP

Commercial

CY74FCT652CTSOC/SOCT

CY74FCT652ATQCT

24-Lead (300-Mil) Molded SOIC

24-Lead (150-Mil) QSOP

6.3

Q13

S13

CY74FCT652ATSOC/SOCT

CY74FCT652TQCT

24-Lead (300-Mil) Molded SOIC

24-Lead (150-Mil) QSOP

9.0

Q13

Notes:

12. Minimum limits are speciﬁed but not tested on Propagation Delays.

13. See “Parameter Measurement Information” in the General Information section.

14. With one data channel toggling, t_W(L)=t_W(H)=4.0 ns and t_r=t_f=1.0 ns.

Document #: 38-00268-B

CY74FCT652T

Package Diagrams

24-Lead Quarter Size Outline Q13

24-Lead (300-Mil) Molded SOIC S13

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

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CY74FCT652CTSOC [TI]

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