CY74FCT825ATSOC [TI]
具有三态输出的 8 位总线接口触发器 | DW | 24 | -40 to 85;
| 型号： | CY74FCT825ATSOC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的 8 位总线接口触发器 | DW | 24 | -40 to 85 驱动 触发器 总线驱动器 总线收发器 |
| 文件： | 总10页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT821T
CY74FCT823T
CY74FCT825T
SCCS033 - May 1994 - Revised March 2000
8-/9-/10-Bit Bus Interface Registers
Features
Functional Description
• Function, pinout, and drive compatible with FCT, F, and
Am29821/23/25 logic
• FCT-C speed at 6.0 ns max.
FCT-B speed at 7.5 ns max.
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
These bus interface registers are designed to eliminate the
extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses
carrying parity. The FCT821T is a buffered, 10-bit wide version
of the popular FCT374 function. The FCT823T is a 9-bit wide
buffered register with clock enable (EN) and clear (CLR) ideal
for parity bus interfacing in high-performance micropro-
grammed systems. The FCT825T is an 8-bit buffered register
with all the FCT823T controls plus multiple enables (OE1,
OE2, OE3) to allow multiuser control of the interface, e.g., CS,
DMA, and RD/WR. They are ideal for use as an output port
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
requiring high IOL/IOH
.
These devices are designed for high-capacitance load drive
capability, while providing low-capacitance bus loading at both
inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state and are designed with
a power-off disable feature to allow for live insertion of boards.
• Sink current
Source current
64 mA
32 mA
• High-speed parallel registers with positive
edge-triggered D-type flip-flops
• Bufferedcommonclockenable(EN)andasynchronous
clear input (CLR)
• Extended commercial range of −40˚C to +85˚C
Logic Block Diagram
D
0
D
D
4
D
5
D
D
3
D
N- 1
D
N
1
2
[1]
EN
[1]
CLR
CL
CL
CL
CL
CL
CL
CL
CL
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP
CP
CP
CP
CP
CP
CP
CP
Q
CP
OE
Y
0
Y
1
Y
4
Y
5
Y
2
Y
3
Y
n-
Y
n
1
Note:
1. Not on FCT821.
Copyright © 2000, Texas Instruments Incorporated
CY74FCT821T
CY74FCT823T
CY74FCT825T
Logic Diagrams
Pin Configurations
FCT821T (10-Bit Register)
DIP/QSOP/SOIC
Top View
10
D
D
10
1
Q
Y
OE
24
V
CC
2
3
4
D
0
23
22
21
CP
Y
0
D
1
Y
1
CP
OE
D
2
Y
2
D
3
5
6
7
8
9
Y
3
20
19
18
17
16
FCT821T
D
4
Y
4
D
5
Y
5
D
6
Y
6
D
7
Y
7
D
8
Y
10
11
12
8
15
14
13
D
9
Y
9
CP
GND
FCT823T (9-Bit Register)
DIP/QSOP/SOIC
Top View
9
D
D
9
Q
Y
1
OE
24
V
CC
CP EN CLR
2
3
4
5
6
D
0
23
22
21
Y
0
CP
EN
D
1
Y
1
D
2
Y
2
D
3
Y
3
20
19
18
17
16
CLR
OE
D
4
Y
4
FCT823T
D
5
Y
5
7
8
9
D
6
Y
6
D
7
Y
7
D
8
Y
8
10
11
12
15
14
13
CLR
EN
CP
GND
FCT825T (8-Bit Register)
DIP/QSOP/SOIC
Top View
8
D
D
8
Q
Y
1
2
3
4
5
6
24
23
22
21
OE
V
CC
1
CP EN CLR
OE
2
OE
3
CP
EN
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Y
0
Y
1
20
19
18
17
16
Y
2
FCT825T
CLR
Y
3
Y
4
7
OE
1
Y
5
8
OE
2
Y
6
9
OE
3
Y
7
10
11
12
15
14
CLR
EN
CP
GND
13
2
CY74FCT821T
CY74FCT823T
CY74FCT825T
Pin Description
Name
I/O
Description
D
I
I
The D flip-flop data inputs.
CLR
When CLR is LOW and OE is LOW, the Q outputs are LOW. When CLR is HIGH, data can be
entered into the register.
CP
Y
O
O
I
Clock Pulse for the register; enters data into the register on the LOW-to-HIGH transition.
The register three-state outputs.
EN
Clock Enable. When EN is LOW, data on the D input is transferred to the Q output on the
LOW-to-HIGH clock transition. When EN is HIGH, the Q outputs do not change state,
regardless of the data or clock input transitions.
OE
I
Output Control. When OE is HIGH, the Y outputs are in the high-impedance state. When OE
is LOW, the TRUE register data is present at the Y outputs.
Function Table[2]
Inputs
EN
Internal Outputs
OE
CLR
D
CP
Q
Y
Function
H
H
H
H
L
L
L
H
L
H
Z
Z
High Z
H
L
L
L
X
X
X
X
X
X
L
L
Z
L
Clear
Hold
Load
H
L
H
H
H
H
X
X
X
X
NC
NC
Z
NC
H
H
L
H
H
H
H
L
L
L
L
L
H
L
L
H
L
Z
Z
L
L
H
H
H
Maximum Ratings[3,4]
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ............................. −65°C to +150°C
Ambient Temperature with
Power Applied........................................ −65°C to +135°C
Operating Range
Ambient
Supply Voltage to Ground Potential ............. −0.5V to +7.0V
DC Input Voltage ....................................... −0.5V to +7.0V
DC Output Voltage..................................... −0.5V to +7.0V
Range
Range
Temperature
VCC
Commercial All
−40°C to +85°C
5V ± 5%
Notes:
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change,
3. Unless otherwise noted, these limits are over the operating free-air temperature range.
= LOW-to-HIGH Transition, Z = HIGH Impedance.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
3
CY74FCT821T
CY74FCT823T
CY74FCT825T
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOH
VOL
VIH
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Hysteresis[6]
Test Conditions
VCC = Min., IOH = −32 mA
VCC = Min., IOH = −15 mA
VCC = Min., IOL = 64 mA
Min.
2.0
Typ.[5]
Max.
Unit
V
2.4
3.3
0.3
V
0.55
0.8
V
2.0
V
VIL
V
VH
All inputs
0.2
V
VIK
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
VCC = Min., IIN = −18 mA
VCC = Max., VIN = VCC
VCC = Max., VIN = 2.7V
VCC = Max., VIN = 0.5V
VCC = Max., VOUT = 2.7V
−0.7
−1.2
5
V
II
µA
µA
µA
µA
IIH
±1
±1
10
IIL
IOZH
Off State HIGH-Level Output
Current
IOZL
Off State LOW-Level
Output Current
VCC = Max., VOUT = 0.5V
−10
µA
IOS
Output Short Circuit Current[7]
VCC = Max., VOUT = 0.0V
VCC = 0V, VOUT = 4.5V
−60
−120
−225
±1
mA
IOFF
Power-Off Disable
µA
Capacitance[6]
Parameter
Description
Typ.[5]
Max.
Unit
CIN
Input Capacitance
Output Capacitance
5
9
10
12
pF
pF
COUT
Notes:
5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
4
CY74FCT821T
CY74FCT823T
CY74FCT825T
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[5]
Max.
Unit
ICC
Quiescent Power Supply
Current
VCC=Max., VIN≤0.2V, VIN≥VCC−0.2V
0.1
0.2
mA
∆ICC
Quiescent Power Supply
Current (TTL inputs HIGH)
VCC=Max., VIN=3.4V,[8]
f1=0, Outputs Open
0.5
2.0
mA
ICCD
Dynamic Power Supply
Current[9]
VCC=Max., One Bit Toggling, 50% Duty Cycle,
Outputs Open, OE=EN=GND,
0.06
0.12
mA/MHz
VIN≤0.2V or VIN≥VCC−0.2V
IC
Total Power Supply Current[10] VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling
0.7
1.4
mA
at f1=5 MHz, OE=EN=GND,
VIN≤0.2V or VIN≥VCC−0.2V
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f1=5 MHz,
OE=EN=GND, VIN=3.4V or VIN=GND
1.2
1.6
3.4
mA
mA
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f1=2.5 MHz, OE=EN=GND,
3.2[11]
VIN≤0.2V or VIN≥VCC−0.2V
VCC=Max., f0=10 MHz,50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f1=2.5 MHz, OE=EN=GND,
VIN=3.4V or VIN=GND
3.9
12.2[11]
mA
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0 = Clock frequency for registered devices, otherwise zero
f1 = Input signal frequency
N1 = Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
5
CY74FCT821T
CY74FCT823T
CY74FCT825T
Switching Characteristics Over the Operating Range[12]
CY74FCT821AT CY74FCT821BT CY74FCT821CT
CY74FCT823AT CY74FCT823BT CY74FCT823CT
CY74FCT825AT CY74FCT825BT CY74FCT825CT
Commercial
Commercial
Commercial
Param.
Description
Test Load
Min.
Max.
Min.
Max.
Min.
Max. Unit Fig. No.[13]
tPLH
tPHL
Propagation Delay
CP to Y, (OE=LOW)
CL=50 pF
RL=500Ω
10.0
20.0
14.0
12.0
23.0
7.0
7.5
15.0
9.0
6.0
12.5
8.0
ns
ns
ns
ns
ns
ns
ns
1, 5
tPLH
tPHL
Propagation Delay
CL=300 pF
RL=500Ω
1, 5
CP to Y, (OE=LOW)[6]
tPLH
Propagation Delay
CLR to Y
CL=50 pF
RL=500Ω
1, 5
tPZH
tPZL
Output Enable Time
OE to Y
CL=50 pF
RL=500Ω
8.0
7.0
1, 7, 8
1, 7, 8
1, 7, 8
1, 7, 8
tPZH
tPZL
Output Enable Time
OE to Y[6]
CL=300 pF
RL=500Ω
15.0
6.5
12.5
6.0
tPHZ
tPHL
Output Disable Time
OE to Y[6]
CL=5 pF
RL=500Ω
tPHZ
tPHL
Output Disable Time
OE to Y
CL=50 pF
RL=500Ω
8.0
7.5
6.5
tSU
tH
Data to CP, Set-Up Time
Data to CP, Hold Time
4.0
2.0
4.0
3.0
1.5
3.0
3.0
1.5
3.0
ns
ns
ns
4
4
4
tSU
Enable EN to CP,
Set-Up Time
tH
Enable EN to CP,
Hold Time
2.0
6.0
0.0
6.0
0.0
6.0
ns
ns
4
6
CL=50 pF
RL=500Ω
tREM
tW
Clear Recovery Time,
CLR to CP
Clock Pulse Width
7.0
6.0
6.0
6.0
6.0
6.0
ns
ns
5
5
tW
CLR Pulse Width LOW
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information.”
6
CY74FCT821T
CY74FCT823T
CY74FCT825T
Ordering Information—FCT821T
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT821CTQCT
Package Type
24-Lead (150-Mil) QSOP
6.0
Q13
S13
Commercial
Commercial
Commercial
CY74FCT821CTSOC/SOCT
CY74FCT821BTPC
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Molded SOIC
24-Lead (150-Mil) QSOP
7.5
P13/13A
S13
CY74FCT821BTSOC/SOCT
CY74FCT821ATQCT
10.0
Q13
CY74FCT821ATSOC/SOCT
S13
24-Lead (300-Mil) Molded SOIC
Ordering Information—FCT823T
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT823CTQCT
CY74FCT823CTSOC/SOCT
CY74FCT823BTPC
Package Type
24-Lead (150-Mil) QSOP
6.0
Q13
S13
Commercial
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Molded DIP
24-Lead (150-Mil) QSOP
7.5
P13/13A
P13/13A
Q13
Commercial
Commercial
10.0
CY74FCT823ATPC
CY74FCT823ATQCT
CY74FCT823ATSOC/SOCT
S13
24-Lead (300-Mil) Molded SOIC
Ordering Information—FCT825T
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
6.0
CY74FCT825CTQCT
Q13
24-Lead (150-Mil) QSOP
Commercial
Document #: 38−00282−B
7
CY74FCT821T
CY74FCT823T
CY74FCT825T
Package Diagrams
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead Quarter Size Outline Q13
8
CY74FCT821T
CY74FCT823T
CY74FCT825T
Package Diagrams (continued)
24-Lead (300-Mil) Molded SOIC S13
9
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 2000, Texas Instruments Incorporated
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