CY74FCT841CTSOCG4 [TI]
FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, SOIC-24;
| 型号： | CY74FCT841CTSOCG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, SOIC-24 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
CY54FCT841T . . . D PACKAGE
CY74FCT841T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT, F, and AM29841 Logic
Reduced V
Equivalent FCT Functions
(Typically = 3.3 V) Versions of
OH
OE
1
24
23
22
21
20
19
18
17
16
15
14
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
CC
0
D
2
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
0
D
1
3
1
D
4
2
2
D
D
D
D
D
D
D
5
3
4
5
6
7
8
9
3
I
Supports Partial-Power-Down Mode
off
6
4
Operation
7
5
Matched Rise and Fall Times
8
6
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
9
7
10
11
8
9
– 1000-V Charged-Device Model (C101)
GND 12
13 LE
Fully Compatible With TTL Input and
Output Logic Levels
High-Speed Parallel Latches
Buffered Common Latch-Enable Input
3-State Outputs
CY54FCT841T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT841T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing
latches and provide additional data width for wider address/data paths or buses carrying parity. The ’FCT841T
devices are buffered 10-bit-wide versions of the FCT373 function.
The’FCT841Tdevices’high-performanceinterfaceisdesignedforhigh-capacitance-loaddrivecapability, while
providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
I/O
DESCRIPTION
D
I
Latch data inputs
Latch-enable input. The latches are transparent when LE is high.
Input data is latched on the high-to-low transition.
LE
Y
I
O
I
3-state latch outputs
Output-enable control. When OE is low, the outputs are enabled.
When OE is high, the outputs are in the high-impedance (off) state.
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QSOP – Q
SOIC – SO
DIP – P
Tape and reel
Tube
5.5
5.5
5.5
6.5
9
CY74FCT841CTQCT
CY74FCT841CTSOC
CY74FCT841CTSOCT
CY74FCT841BTPC
CY74FCT841ATSOC
CY74FCT841ATSOCT
CY54FCT841ATDMB
FCT841C
FCT841C
Tape and reel
Tube
–40°C to 85°C
–55°C to 125°C
CY74FCT841BTPC
FCT841A
Tube
SOIC – SO
Tape and reel
Tube
9
CDIP – D
10
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INTERNAL
INPUTS
OUTPUTS
FUNCTION
OE
H
H
H
H
L
LE
X
D
X
L
O
X
Y
Z
H
H
L
L
Z
Z
H
X
L
H
Z
NC
L
Z
Latched (Z)
Transparent
Latched
H
H
L
L
L
H
X
H
H
NC
L
NC
H = High logic level, L = Low logic level, X = Don’t care,
NC = No change, Z = High-impedance state
logic diagram (positive logic)
1
OE
13
LE
23
LE
D
Q
Y
0
2
D
0
To Nine Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ
(see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 2): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
(see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
CY54FCT841T
CY74FCT841T
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–12
32
0.8
–32
64
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
–40
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CY54FCT841T
CY74FCT841T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
= 4.75 V,
= 4.5 V,
I
I
I
I
I
I
I
= –18 mA
= –18 mA
–0.7
–1.2
CC
CC
CC
IN
V
V
IK
–0.7
–1.2
IN
= –12 mA
= –32 mA
= –15 mA
= 32 mA
= 64 mA
2.4
3.3
OH
OH
OH
OL
OL
2
V
OH
V
V
CC
= 4.75 V
2.4
3.3
V
V
= 4.5 V,
0.3
0.2
0.55
CC
V
V
V
V
OL
= 4.75 V,
0.3
0.2
0.55
CC
All inputs
hys
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
V
V
V
V
V
= V
= V
5
±1
IN
IN
IN
IN
IN
IN
CC
CC
I
I
I
I
I
µA
I
5
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
µA
µA
µA
µA
IH
±1
IL
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
= 0 V
10
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OZH
OZL
10
–10
–225
–10
–60
–120
‡
mA
µA
I
I
OS
= 0 V
–60
–120
–225
±1
= 4.5 V
±1
off
V
V
V
V
V
= 5.5 V,
V
≤ 0.2 V,
V
V
≥ V
≥ V
– 0.2 V
– 0.2 V
0.1
0.5
0.2
CC
CC
CC
CC
CC
IN
IN
IN
CC
I
mA
CC
= 5.25 V,
V
≤ 0.2 V,
0.1
0.5
0.2
2
IN
CC
§
= 5.5 V, V = 3.4 V , f = 0, Outputs open
IN
2
1
∆I
mA
CC
§
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
1
= 5.5 V, One input switching at 50% duty cycle,
Outputs open, OE = GND, LE = V
,
0.06
0.12
CC
V
IN
≤ 0.2 V or V ≥ V
– 0.2 V
mA/
MHz
IN CC
¶
I
CCD
V
CC
= 5.25 V, One input switching at 50% duty cycle,
Outputs open, OE = GND, LE = V
,
0.06
0.12
CC
V
IN
≤ 0.2 V or V ≥ V
– 0.2 V
IN CC
†
‡
Typical values are at V
= 5 V, T = 25°C.
CC
A
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, I
tests should be performed last.
OS
§
¶
Per TTL-driven input (V = 3.4 V); all other inputs at V
or GND
IN CC
This parameter is derived for use in total power-supply calculations.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CY54FCT841T
CY74FCT841T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
≤ 0.2 V or
≥ V – 0.2 V
CC
One bit switching
IN
IN
0.7
1
1.4
at f = 10 MHz
1
V
CC
= 5.5 V,
at 50% duty cycle
10 bits switching
V
IN
= 3.4 V or GND
2.4
Outputs open,
OE = GND,
V
IN
V
IN
≤ 0.2 V or
||
3.2
1
LE = V
CC
≥ V
CC
– 0.2 V
at f = 2.5 MHz
1
at 50% duty cycle
||
V
IN
= 3.4 V or GND
4.1 13.2
#
I
C
mA
V
V
≤ 0.2 V or
One bit switching
at f = 10 MHz
1
at 50% duty cycle
IN
IN
0.7
1
1.4
2.4
≥ V
CC
– 0.2 V
V
= 5.25 V,
CC
V
IN
= 3.4 V or GND
Outputs open,
OE = GND,
LE = V
CC
V
IN
V
IN
≤ 0.2 V or
10 bits switching
at f = 2.5 MHz
1
at 50% duty cycle
||
||
1
3.2
≥ V
– 0.2 V
CC
V
IN
= 3.4 V or GND
4.1 13.2
C
C
5
9
10
12
5
9
10
12
pF
pF
i
o
†
#
Typical values are at V
= 5 V, T = 25°C.
A
CC
H
I
C
= I
+ ∆I
CC
× D × N + I
(f /2 + f × N )
CC
T
CCD 0 1 1
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
C
CC
CC
H
T
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY54FCT841AT CY74FCT841AT CY74FCT841BT CY74FCT841CT
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↑
Hold time, data after LE↑
5
4
4
4
ns
ns
ns
2.5
3
2.5
2.5
2.5
2.5
2.5
2.5
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
CY54FCT841AT CY74FCT841AT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST LOAD
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
10
10
15
15
13
13
20
20
13
13
25
25
9
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
9
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
C
R
= 50 pF,
= 500 Ω
L
L
D
Y
Y
Y
Y
Y
Y
Y
Y
9
13
13
12
12
16
16
11.5
11.5
23
23
7
C
R
= 300 pF,
L
D
ns
= 500 Ω
L
C
R
= 50 pF,
= 500 Ω
L
L
LE
LE
OE
OE
OE
OE
ns
C
R
= 300 pF,
L
ns
= 500 Ω
L
C
R
= 50 pF,
= 500 Ω
L
L
ns
C
R
= 300 pF,
L
ns
= 500 Ω
L
C
= 5 pF,
= 500 Ω
L
ns
R
9
7
L
10
10
8
C
R
= 50 pF,
= 500 Ω
L
L
ns
8
switching characteristics over operating free-air temperature range (see Figure 1)
CY74FCT841BT CY74FCT841CT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST LOAD
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
6.5
6.5
13
13
8
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
5.5
5.5
13
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
C
R
= 50 pF,
= 500 Ω
L
L
D
Y
Y
Y
Y
Y
Y
Y
Y
C
R
= 50 pF,
= 500 Ω
L
L
D
ns
13
6.4
6.4
15
C
R
= 50 pF,
= 500 Ω
L
L
LE
LE
OE
OE
OE
OE
ns
8
15.5
15.5
8
C
R
= 300 pF,
L
ns
= 500 Ω
15
L
6.5
6.5
12
C
R
= 50 pF,
= 500 Ω
L
L
ns
8
14
14
6
C
R
= 300 pF,
L
ns
= 500 Ω
12
L
5.7
5.7
6
C
= 5 pF,
= 500 Ω
L
ns
R
6
L
7
C
= 50 pF
= 500 Ω,
L
ns
R
L
7
6
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
S1
t
/t
Open
7 V
PLH PHL
t /t
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
LCCC
SOIC
Drawing
5962-88575013A
CY54FCT841ATDMB
CY54FCT841ATLMB
CY74FCT841ATSOC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
28
24
28
24
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 N / A for Pkg Type
POST-PLATE N / A for Pkg Type
JT
FK
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CY74FCT841ATSOCE4
CY74FCT841ATSOCG4
CY74FCT841ATSOCT
CY74FCT841ATSOCTE4
CY74FCT841ATSOCTG4
CY74FCT841BTPC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
DW
NT
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CY74FCT841BTPCE4
CY74FCT841CTQCT
NT
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SSOP/
QSOP
DBQ
DBQ
DBQ
DW
DW
DW
DW
DW
DW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CY74FCT841CTQCTE4
CY74FCT841CTQCTG4
CY74FCT841CTSOC
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CY74FCT841CTSOCE4
CY74FCT841CTSOCG4
CY74FCT841CTSOCT
CY74FCT841CTSOCTE4
CY74FCT841CTSOCTG4
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CY74FCT841ATSOCT
CY74FCT841CTQCT
SOIC
DW
24
24
2000
2500
330.0
330.0
24.4
16.4
10.75
6.5
15.7
9.0
2.7
2.1
12.0
8.0
24.0
16.0
Q1
Q1
SSOP/
QSOP
DBQ
CY74FCT841CTSOCT
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CY74FCT841ATSOCT
CY74FCT841CTQCT
CY74FCT841CTSOCT
SOIC
SSOP/QSOP
SOIC
DW
DBQ
DW
24
24
24
2000
2500
2000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
41.0
Pack Materials-Page 2
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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相关型号：
CY74FCT841CTSOCR
Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOIC-24
CYPRESS
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