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DAC082S085CIMM/NOPB [TI]

具有轨到轨输出的 8 位微功耗双路数模转换器 | DGS | 10 | -40 to 105;
DAC082S085CIMM/NOPB
型号： DAC082S085CIMM/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有轨到轨输出的 8 位微功耗双路数模转换器 | DGS | 10 | -40 to 105

光电二极管 转换器 数模转换器
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DAC082S085  
SNAS365G –MAY 2006–REVISED JUNE 2016  
DAC082S085 8-Bit Micro Power DUAL Digital-to-Analog Converter With Rail-to-Rail Output  
1 Features  
2 Applications  
1
•
•
•
•
•
•
•
•
•
Ensured Monotonicity  
•
•
•
•
Battery-Powered Instruments  
Low Power Operation  
Digital Gain and Offset Adjustment  
Programmable Voltage and Current Sources  
Programmable Attenuators  
Rail-to-Rail Voltage Output  
Power-On Reset to 0 V  
Simultaneous Output Updating  
Wide Power Supply Range: 2.7 V to 5.5 V  
Industry's Smallest Package  
Power-Down Modes  
3 Description  
The DAC082S085 device is a full-featured, general-  
purpose, DUAL, 8-bit, voltage-output, digital-to-analog  
converter (DAC) that can operate from a single 2.7-V  
to 5.5-V supply and consumes 0.6 mW at 3 V and 1.6  
mW at 5 V. The DAC082S085 is packaged in 10-pin  
SON and VSSOP packages. The 10-pin WSON  
package makes the DAC082S085 the smallest DUAL  
DAC in its class. The on-chip output amplifier allows  
rail-to-rail output swing, and the three-wire serial  
interface operates at clock rates up to 40 MHz over  
the entire supply voltage range. Competitive devices  
are limited to 25-MHz clock rates at supply voltages  
in the 2.7 V to 3.6 V range. The serial interface is  
compatible with standard SPI™, QSPI, MICROWIRE,  
and DSP interfaces.  
Key Specifications:  
–
–
–
–
–
–
–
Resolution: 8 Bits  
INL: ±0.5 LSB (Maximum)  
DNL: 0.18 / –0.13 LSB (Maximum)  
Settling Time: 4.5 µs (Maximum)  
Zero Code Error: 15 mV (Maximum)  
Full-Scale Error: –0.75% FS (Maximum)  
Supply Power:  
–
Normal: 0.6 mW (3 V) / 1.6 mW (5 V)  
(Typical)  
Device Information(1)  
–
Power Down: 0.3 µW (3 V) / 0.8 µW (5 V)  
(Typical)  
PART NUMBER  
PACKAGE  
VSSOP (10)  
WSON (10)  
BODY SIZE (NOM)  
3.00 mm × 3.00 mm  
3.00 mm × 3.00 mm  
DAC082S085  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
DNL at VA = 3 V  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
DAC082S085  
SNAS365G –MAY 2006–REVISED JUNE 2016  
www.ti.com  
Table of Contents  
8.4 Programming........................................................... 16  
Application and Implementation ........................ 18  
9.1 Application Information............................................ 18  
9.2 Typical Application ................................................. 18  
1
2
3
4
5
6
7
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Description (continued)......................................... 3  
Pin Configuration and Functions......................... 4  
Specifications......................................................... 5  
7.1 Absolute Maximum Ratings ...................................... 5  
7.2 ESD Ratings.............................................................. 5  
7.3 Recommended Operating Conditions....................... 5  
7.4 Thermal Information.................................................. 6  
7.5 Electrical Characteristics........................................... 6  
7.6 Timing Requirements................................................ 8  
7.7 Typical Characteristics.............................................. 9  
Detailed Description ............................................ 14  
8.1 Overview ................................................................. 14  
8.2 Functional Block Diagram ....................................... 14  
8.3 Device Functional Modes........................................ 15  
9
10 Power Supply Recommendations ..................... 19  
10.1 Using References as Power Supplies................... 19  
11 Layout................................................................... 22  
11.1 Layout Guidelines ................................................. 22  
11.2 Layout Example .................................................... 22  
12 Device and Documentation Support ................. 23  
12.1 Device Support...................................................... 23  
12.2 Receiving Notification of Documentation Updates 24  
12.3 Community Resource............................................ 24  
12.4 Trademarks........................................................... 24  
12.5 Electrostatic Discharge Caution............................ 24  
12.6 Glossary................................................................ 24  
8
13 Mechanical, Packaging, and Orderable  
Information ........................................................... 24  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision F (March 2013) to Revision G  
Page  
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation  
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and  
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1  
•
Changed Thermal Information table ...................................................................................................................................... 6  
Changes from Revision E (March 2013) to Revision F  
Page  
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 22  
2
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DAC082S085  
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SNAS365G –MAY 2006–REVISED JUNE 2016  
5 Description (continued)  
The reference for the DAC082S085 serves both channels and can vary in voltage between 1 V and VA, providing  
the widest possible output dynamic range. The DAC082S085 has a 16-bit input shift register that controls the  
outputs to be updated, the mode of operation, the power-down condition, and the binary input data. Both outputs  
can be updated simultaneously or individually depending on the setting of the two mode of operation bits.  
A power-on reset circuit ensures that the DAC output powers up to 0 V and remains there until there is a valid  
write to the device. A power-down feature reduces power consumption to less than a microWatt with three  
different termination options.  
The low power consumption and small packages of the DAC082S085 make it an excellent choice for use in  
battery-operated equipment.  
The DAC082S085 is one of a family of pin-compatible DACs, including the 10-bit DAC102S085 and the 12-bit  
DAC124S085. The DAC082S085 operates over the extended industrial temperature range of −40°C to 105°C.  
Copyright © 2006–2016, Texas Instruments Incorporated  
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DAC082S085  
SNAS365G –MAY 2006–REVISED JUNE 2016  
www.ti.com  
6 Pin Configuration and Functions  
DSC Package  
10-Pin WSON  
Top View  
DGS Package  
10-Pin VSSOP  
Top View  
V
1
2
SCLK  
SYNC  
10  
9
A
V
1
2
3
4
5
10  
SCLK  
SYNC  
A
V
V
OUTA  
V
V
9
8
7
6
OUTA  
3 Exposed Thermal Pad  
D
8
7
6
OUTB  
NC  
IN  
D
OUTB  
NC  
IN  
4
5
V
REFIN  
V
REFIN  
NC  
GND  
NC  
GND  
Not to scale  
Not to scale  
Pin Functions  
PIN  
TYPE  
DESCRIPTION  
NO.  
1
NAME  
VA  
Supply  
Analog Output  
Analog Output  
—
Power supply input. Must be decoupled to GND.  
Channel A analog output voltage.  
Channel B analog output voltage.  
Not connected  
2
VOUTA  
VOUTB  
NC  
3
4
5
NC  
—
Not connected  
6
GND  
Ground  
Ground reference for all on-chip circuitry.  
Unbuffered reference voltage shared by all channels. Must be decoupled  
to GND.  
7
8
VREFIN  
DIN  
Analog Input  
Digital Input  
Serial data input. Data is clocked into the 16-bit shift register on the falling  
edges of SCLK after the fall of SYNC.  
Frame synchronization input for the data input. When this pin goes low, it  
enables the input shift register and data is transferred on the falling edges  
of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is  
brought high before the 16th clock, in which case the rising edge of  
SYNC acts as an interrupt and the write sequence is ignored by the DAC.  
9
SYNC  
Digital Input  
Serial clock input. Data is clocked into the input shift register on the falling  
edges of this pin.  
10  
SCLK  
PAD  
Digital Input  
Ground  
Exposed die attach pad can be connected to ground or left floating.  
Soldering the pad to the PCB offers optimal thermal performance and  
enhances package self-alignment during reflow.  
PAD  
4
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DAC082S085  
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SNAS365G –MAY 2006–REVISED JUNE 2016  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)  
MIN  
MAX  
6.5  
6.5  
10  
UNIT  
V
Supply voltage, VA  
Voltage on any input pin  
Input current at any pin(4)  
Package input current(4)  
Power consumption at TA = 25°C  
Junction temperature, TJ  
Storage temperature, Tstg  
–0.3  
V
mA  
mA  
20  
See(5)  
150  
150  
°C  
°C  
–65  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.  
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and  
specifications.  
(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin must be limited to 10 mA. The 20-mA  
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10  
mA to two.  
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by  
TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula  
PDMAX = (TJmax − TA) / RθJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault  
condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).  
7.2 ESD Ratings  
VALUE  
±2500  
±250  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)  
Machine model (MM)  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) Human-body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.  
7.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
–40  
2.7  
1
MAX  
105  
UNIT  
°C  
Operating temperature, TA  
Supply voltage, VA  
Reference voltage, VREFIN  
Digital input voltage(2)  
Output load  
5.5  
V
VA  
V
0
5.5  
V
0
1500  
Up to 40  
pF  
MHz  
SCLK frequency  
(1) All voltage are measured with respect to GND = 0 V, unless otherwise specified.  
(2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, does not cause errors in the  
conversation result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.  
L/h  
Çh LbÇ9wb![  
ꢀLwꢀÜLÇwò  
Db5  
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SNAS365G –MAY 2006–REVISED JUNE 2016  
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7.4 Thermal Information  
DAC082S085  
THERMAL METRIC(1)  
DGS (VSSOP)  
DSC (WSON)  
10 PINS  
250  
UNIT  
10 PINS  
240  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
53.3  
78.9  
4.8  
40.7  
23.7  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
0.4  
ψJB  
77.6  
N/A  
23.8  
RθJC(bottom)  
4.7  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
7.5 Electrical Characteristics  
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range  
3 to 252. All limits are at TA = 25°C, unless otherwise specified.(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP(2)  
MAX  
UNIT  
STATIC PERFORMANCE  
Resolution  
T
MIN ≤ TA ≤ TMAX  
MIN ≤ TA ≤ TMAX  
8
8
Bits  
Bits  
Monotonicity  
T
TA = 25°C  
MIN ≤ TA ≤ TMAX  
±0.14  
INL  
Integral non-linearity  
LSB  
T
±0.5  
Max  
Min  
0.04  
TA = 25°C  
DNL  
Differential non-linearity  
VA = 2.7 V to 5.5 V  
−0.02  
LSB  
T
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
TMIN ≤ TA ≤ TMAX  
−0.13  
0.18  
15  
4
ZE  
Zero code error  
Full-scale error  
IOUT = 0  
mV  
T
−0.1  
FSE  
IOUT = 0  
%FSR  
T
−0.75  
−0.2  
−1  
GE  
Gain error  
All ones Loaded to DAC register  
%FSR  
µV/°C  
ZCED  
TC GE  
Zero code error drift  
Gain error tempco  
−20  
−0.7  
–1  
VA = 3 V  
VA = 5 V  
ppm/°C  
OUTPUT CHARACTERISTICS  
Output voltage(3)  
T
MIN ≤ TA ≤ TMAX  
MIN ≤ TA ≤ TMAX  
0
VREFIN  
±1  
V
High-impedance output  
IOZ  
T
µA  
leakage current(3)  
VA = 3 V, IOUT = 200 µA  
VA = 3 V, IOUT = 1 mA  
1.3  
6
ZCO  
Zero code output  
mV  
VA = 5 V, IOUT = 200 µA  
VA = 5 V, IOUT = 1 mA  
7
10  
VA = 3 V, IOUT = 200 µA  
VA = 3 V, IOUT = 1 mA  
2.984  
2.934  
4.989  
4.958  
–56  
–69  
52  
FSO  
Full-scale output  
V
VA = 5 V, IOUT = 200 µA  
VA = 5 V, IOUT = 1 mA  
VA = 3 V, VOUT = 0 V, Input Code = FFh  
VA = 5 V, VOUT = 0 V, Input Code = FFh  
VA = 3 V, VOUT = 3 V, Input Code = 00h  
VA = 5 V, VOUT = 5 V, Input Code = 00h  
Available on each DAC output  
RL = ∞  
Output short-circuit current  
(source)  
mA  
IOS  
Output short-circuit current  
(sink)  
mA  
mA  
pF  
75  
IO  
Continuous output current(3)  
TMIN ≤ TA ≤ TMAX  
11  
1500  
1500  
CL  
Maximum load capacitance  
RL = 2 kΩ  
(1) To ensure accuracy, it is required that VA and VREFIN be well bypassed.  
(2) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing  
Quality Level).  
(3) This parameter is specified by design or characterization and is not tested in production.  
6
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Electrical Characteristics (continued)  
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range  
3 to 252. All limits are at TA = 25°C, unless otherwise specified.(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP(2)  
MAX  
UNIT  
ZOUT  
DC output impedance  
7.5  
Ω
REFERENCE INPUT CHARACTERISTICS  
TA = 25°C  
0.2  
60  
Input range minimum  
T
MIN ≤ TA ≤ TMAX  
MIN ≤ TA ≤ TMAX  
1
V
VREFIN  
Input range maximum  
T
VA  
Input impedance  
kΩ  
µA  
LOGIC INPUT CHARACTERISTICS  
IIN  
Input current(3)  
T
MIN ≤ TA ≤ TMAX  
±1  
0.6  
0.8  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
0.9  
1.5  
1.4  
2.1  
VA = 3 V  
VA = 5 V  
VA = 3 V  
VA = 5 V  
T
VIL  
Input low voltage(3)  
V
T
T
2.1  
2.4  
VIH  
Input high voltage(3)  
Input capacitance(3)  
V
pF  
V
T
CIN  
TMIN ≤ TA ≤ TMAX  
3
POWER REQUIREMENTS  
Supply voltage minimum  
T
MIN ≤ TA ≤ TMAX  
MIN ≤ TA ≤ TMAX  
2.7  
VA  
Supply voltage maximum  
T
5.5  
270  
410  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
210  
320  
VA = 2.7 V to 3.6 V  
VA = 4.5 V to 5.5 V  
T
fSCLK = 30 MHz  
Normal supply current  
(output unloaded)  
IN  
µA  
T
VA = 2.7 V to 3.6 V  
VA = 4.5 V to 5.5 V  
190  
290  
0.1  
fSCLK = 0  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
VA = 2.7 V to 3.6 V  
VA = 4.5 V to 5.5 V  
VA = 2.7 V to 3.6 V  
VA = 4.5 V to 5.5 V  
µA  
µA  
Power down supply current  
(output unloaded, SYNC =  
DIN = 0 V after PD mode  
loaded)  
T
1
1
IPD  
All PD Modes(3)  
0.15  
0.6  
T
T
1
fSCLK = 30 MHz  
1.6  
Normal supply power (output  
unloaded)  
PN  
mW  
T
2.3  
VA = 2.7 V to 3.6 V  
VA = 4.5 V to 5.5 V  
0.6  
1.5  
0.3  
fSCLK = 0  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
VA = 2.7 V to 3.6 V  
VA = 4.5 V to 5.5 V  
Power down supply current  
(output unloaded, SYNC =  
DIN = 0 V after PD mode  
loaded)  
T
3.6  
5.5  
PPD  
All PD Modes(3)  
µW  
0.8  
T
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7.6 Timing Requirements  
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code  
(1)  
range 3 to 252. All other limits are at TA = 25°C, unless otherwise specified.  
MIN  
TYP  
MAX UNIT  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
40  
fSCLK  
SCLK frequency  
MHz  
30  
T
TA = 25°C  
MIN ≤ TA ≤ TMAX  
3
40h to C0h code change  
RL = 2 kΩ, CL = 200 pF  
ts  
Output voltage settling time(2)  
µs  
T
4.5  
SR  
Output slew rate  
1
12  
0.5  
1
V/µs  
nV-sec  
nV-sec  
nV-sec  
nV-sec  
kHz  
Glitch Impulse  
Code change from 80h to 7Fh  
Digital feedthrough  
Digital crosstalk  
DAC-to-DAC crosstalk  
Multiplying bandwidth  
3
VREFIN = 2.5 V ± 0.1 Vpp  
160  
VREFIN = 2.5 V ± 1 Vpp  
input frequency = 10 kHz  
Total harmonic distortion  
Wake-up time  
70  
dB  
µs  
VA = 3 V  
VA = 5 V  
TA = 25°C  
6
39  
25  
tWU  
1/fSCLK  
SCLK cycle time  
SCLK high time  
SCLK low time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
TA = 25°C  
MIN ≤ TA ≤ TMAX  
33  
10  
10  
10  
3.5  
3.5  
3
7
7
tCH  
T
tCL  
T
4
SYNC setup time prior to  
SCLK falling edge  
tSS  
T
1.5  
1.5  
0
Data setup time prior to SCLK  
falling edge  
tDS  
T
Data hold time after SCLK  
falling edge  
tDH  
T
SCLK fall prior to rise of  
SYNC  
tCFSR  
T
6
tSYNC  
SYNC high time  
T
10  
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing  
Quality Level).  
(2) This parameter is specified by design or characterization and is not tested in production.  
1 / f  
SCLK  
14  
SCLK  
1
2
13  
15  
16  
t
t
CL  
t
CH  
SS  
t
SYNC  
t
CFSR  
SYNC  
t
DH  
D
IN  
DB15  
DB0  
t
DS  
Figure 1. Serial Timing Diagram  
8
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7.7 Typical Characteristics  
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated  
FSE  
255 x V  
REFIN  
256  
GE = FSE - ZE  
FSE = GE + ZE  
OUTPUT  
VOLTAGE  
ZE  
0
0
255  
DIGITAL INPUT CODE  
Figure 2. Input and Output Transfer Characteristic  
Figure 3. INL at VA = 3 V  
Figure 4. INL at VA = 5 V  
Figure 5. DNL at VA = 3 V  
Figure 6. DNL at VA = 5 V  
Figure 7. INL/DNL vs VREFIN at VA = 3 V  
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Typical Characteristics (continued)  
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated  
Figure 8. INL/DNL vs VREFIN at VA = 5 V  
Figure 9. INL/DNL vs fSCLK at VA = 2.7 V  
Figure 10. INL/DNL vs VA  
Figure 11. INL/DNL vs Clock Duty Cycle at VA = 3 V  
Figure 12. INL/DNL vs Clock Duty Cycle at VA = 5 V  
Figure 13. INL/DNL vs Temperature at VA = 3 V  
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Typical Characteristics (continued)  
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated  
Figure 14. INL/DNL vs Temperature at VA = 5 V  
Figure 15. Zero Code Error vs VA  
Figure 16. Zero Code Error vs VREFIN  
Figure 17. Zero Code Error vs fSCLK  
Figure 18. Zero Code Error vs Clock Duty Cycle  
Figure 19. Zero Code Error vs Temperature  
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Typical Characteristics (continued)  
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated  
Figure 20. Full-Scale Error vs VA  
Figure 21. Full-Scale Error vs VREFIN  
Figure 22. Full-Scale Error vs fSCLK  
Figure 23. Full-Scale Error vs Clock Duty Cycle  
Figure 24. Full-Scale Error vs Temperature  
Figure 25. Supply Current vs VA  
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Typical Characteristics (continued)  
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated  
Figure 26. Supply Current vs Temperature  
Figure 27. 5-V Glitch Response  
Figure 28. Power-On Reset  
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8 Detailed Description  
8.1 Overview  
The DAC082S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor  
strings that are followed by an output buffer.  
8.2 Functional Block Diagram  
V
REFIN  
DAC082S085  
REF  
REF  
POWER-ON  
RESET  
8 BIT DAC  
BUFFER  
V
OUTA  
8
2.5 kΩ  
100 kΩ  
DAC  
REGISTER  
8 BIT DAC  
BUFFER  
V
OUTB  
8
2.5 kΩ  
100 kΩ  
8
POWER-DOWN  
CONTROL  
LOGIC  
INPUT  
CONTROL  
LOGIC  
SCLK  
SYNC  
D
IN  
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8.2.1 Feature Description  
8.2.1.1 DAC Architecture  
The DAC082S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor  
strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared  
by both DACs.  
For simplicity, a single resistor string is shown in Figure 29. This string consists of 256 equal valued resistors  
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register  
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight  
binary with an ideal output voltage calculated in Equation 1:  
VOUTA,B = VREFIN × (D / 256)  
where  
•
D is the decimal equivalent of the binary code that is loaded into the DAC register. (D can take on any value  
between 0 and 255. This configuration ensures that the DAC is monotonic.)  
(1)  
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Functional Block Diagram (continued)  
V
A
R
R
R
To Output Amplifier  
R
R
Figure 29. DAC Resistor String  
8.2.1.2 Output Amplifiers  
The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to VA when the reference is VA. All  
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA,  
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the  
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the  
amplifier are described in Electrical Characteristics.  
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zero-  
code and full-scale outputs for given load currents are available in the Electrical Characteristics.  
8.2.1.3 Reference Voltage  
The DAC082S085 uses a single external reference that is shared by both channels. The reference pin, VREFIN, is  
not buffered and has an input impedance of 60 kΩ. TI recommends that VREFIN be driven by a voltage source  
with low output impedance. The reference voltage range is 1 V to VA, providing the widest possible output  
dynamic range.  
8.2.1.4 Power-On Reset  
The power-on reset circuit controls the output voltages of both DACs during power-up. Upon application of  
power, the DAC registers are filled with zeros and the output voltages are 0 V. The outputs remain at 0 V until a  
valid write sequence is made to the DAC.  
8.3 Device Functional Modes  
8.3.1 Power-Down Modes  
The DAC082S085 has four power-down modes, two of which are identical. In power-down mode, the supply  
current drops to 20 µA at 3 V and 30 µA at 5 V. The DAC082S085 is set in power-down mode by setting OP1  
and OP0 to 11. Because this mode powers down both DACs, the first two bits of the shift register are used to  
select different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be  
tri-stated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by  
2.5 kΩ or 100 kΩ to ground respectively (see Table 1).  
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Device Functional Modes (continued)  
Table 1. Power-Down Modes  
A1  
0
A0  
0
OP1  
OP0  
OPERATING MODE  
High-Z outputs  
2.5 kΩ to GND  
100 kΩ to GND  
High-Z outputs  
1
1
1
1
1
1
1
1
0
1
1
0
1
1
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the  
power-down modes. However, the contents of the DAC registers are unaffected when in power-down. Each DAC  
register maintains its value prior to the DAC082S085 being powered down unless it is changed during the write  
sequence which instructed it to recover from power down. Minimum power consumption is achieved in the  
power-down mode with SYNC and DIN idled low and SCLK disabled. The time to exit power-down (Wake-Up  
Time) is typically tWU µs as stated in Timing Requirements.  
8.4 Programming  
8.4.1 Serial Interface  
The three-wire interface is compatible with SPI™, QSPI, and MICROWIRE, as well as most DSPs and operates  
at clock rates up to 40 MHz. See Figure 1 for information on a write sequence.  
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked  
into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register,  
it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Figure 1). On the 16th  
falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel  
address, mode of operation or register contents) is executed. At this point the SYNC line may be kept low or  
brought high. Any data and clock pusles after the 16th falling clock edge are ignored. In either case, SYNC must  
be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of  
SYNC.  
Because the SYNC and DIN buffers draw more current when they are high, they must be idled low between write  
sequences to minimize power consumption.  
8.4.2 Input Shift Register  
The input shift register, Figure 30, has sixteen bits. The first bit must be set to 0 and the second bit is an address  
bit. The address bit determines whether the register data is for DAC A or DAC B. This bit is followed by two bits  
that determine the mode of operation (writing to a DAC register without updating the outputs of both DACs,  
writing to a DAC register and updating the outputs of both DACs, writing to the register of both DACs and  
updating their outputs, or powering down both outputs). The final twelve bits of the shift register are the data bits.  
The data format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s  
corresponding to a full-scale output of VREFIN – 1 LSB. The contents of the serial input register are transferred to  
the DAC register on the sixteenth falling edge of SCLK. See Figure 1.  
MSB  
LSB  
A1 A0 OP1 OP0 D7 D6 D5 D4 D3 D2 D1 D0  
X
X
X
X
DATA BITS  
0
0
0
1
DAC A  
DAC B  
0
0
1
1
0
1
0
1
Write to specified register but do not update outputs.  
Write to specified register and update outputs.  
Write to all registers and update outputs.  
Power-down outputs.  
Figure 30. Input Register Contents  
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th  
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift  
register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and  
there is no change in the mode of operation or in the DAC output voltages.  
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Programming (continued)  
8.4.3 DSP and Microprocessor Interfacing  
Interfacing the DAC082S085 to microprocessors and DSPs is quite simple. The following guidelines are offered  
to hasten the design process.  
8.4.3.1 ADSP-2101/ADSP2103 Interfacing  
Figure 31 shows a serial interface between the DAC082S085 and the ADSP-2101/ADSP2103. The DSP must be  
set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control  
register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.  
Transmission is started by writing a word to the TX register after the SPORT mode has been enabled.  
ADSP-2101/  
DAC082S085  
ADSP2103  
SYNC  
TFS  
DT  
DIN  
SCLK  
SCLK  
Figure 31. ADSP-2101/2103 Interface  
8.4.3.2 80C51/80L51 Interface  
A serial interface between the DAC082S085 and the 80C51/80L51 microcontroller is shown in Figure 32. The  
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line  
P3.3. This line is taken low when data is transmitted to the DAC082S085. Because the 80C51/80L51 transmits  
8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line  
must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second  
byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that  
the 80C51/80L51 transmits data with the LSB first while the DAC082S085 requires data with the MSB first.  
80C51/80L51  
P3.3  
DAC082S085  
SYNC  
TXD  
RXD  
SCLK  
DIN  
Figure 32. 80C51/80L51 Interface  
8.4.3.3 68HC11 Interface  
A serial interface between the DAC082S085 and the 68HC11 microcontroller is shown in Figure 33. The SYNC  
line of the DAC082S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.  
The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration  
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the  
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB  
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the  
second byte of data to the DAC, after which PC7 must be raised to end the write sequence.  
68HC11  
PC7  
DAC082S085  
SYNC  
SCK  
SCLK  
MOSI  
DIN  
Figure 33. 68HC11 Interface  
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Programming (continued)  
8.4.3.4 Microwire Interface  
Figure 34 shows an interface between a Microwire-compatible device and the DAC082S085. Data is clocked out  
on the rising edges of the SK signal. As a result, the SK of the Microwire device must be inverted before driving  
the SCLK of the DAC082S085.  
MICROWIRE  
DEVICE  
DAC082S085  
SYNC  
CS  
SK  
SO  
SCLK  
DIN  
Figure 34. Microwire Interface  
9 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
The DAC082S085 is designed for single-supply operation and thus has a unipolar output. However, a bipolar  
output may be obtained with the circuit in Figure 35. This circuit provides an output voltage range of ±5 V. A rail-  
to-rail amplifier must be used if the amplifier supplies are limited to ±5 V.  
9.2 Typical Application  
9.2.1 Bipolar Operation  
10 pF  
R
2
+5V  
+5V  
R
1
+
œ
10 mF  
0.1 mF  
±5V  
+
DAC102S085  
SYNC  
-5V  
V
OUT  
DIN  
SCLK  
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Figure 35. Bipolar Operation  
9.2.1.1 Design Requirements  
•
•
•
The DAC082S085 uses a single supply.  
The output is required to be bipolar with a voltage range of ±5 V.  
Dual supplies are used for the output amplifier.  
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Typical Application (continued)  
9.2.1.2 Detailed Design Procedure  
The output voltage of this circuit for any code is found to be  
VO = (VA × (D / 256) × ((R1 + R2) / R1) – VA × R2 / R1)  
VO = (10 × D / 256) – 5 V  
(2)  
(3)  
where  
•
D is the input code in decimal form (With VA = 5 V and R1 = R2)  
Table 2 lists the rail-to-rail amplifiers suitable for this application.  
Table 2. Some Rail-to-Rail Amplifiers  
AMP  
PKGS  
TYP VOS  
0.9 mV  
TYP ISUPPLY  
25 µA  
LMC7111  
LM7301  
LM8261  
8-pin PDIP, 5-pin SOT-23  
8-pin SO, 5-pin SOT-23  
5-pin SOT-23  
0.03 mV  
0.7 mV  
620 µA  
1 mA  
9.2.1.3 Application Curve  
5V  
hÜÇtÜÇ  
ëh[Ç!D9  
-5V  
0
255  
5LDLÇ![ LbtÜÇ /h59  
Figure 36. Bipolar Input / Output Transfer Characteristic  
10 Power Supply Recommendations  
While the simplicity of the DAC082S085 implies ease of use, it is important to recognize that the path from the  
reference input (VREFIN) to the VOUTs has essentially zero Power Supply Rejection Ratio (PSRR). Therefore, it is  
necessary to provide a noise-free supply voltage to VREFIN. To use the full dynamic range of the DAC082S085,  
the supply pin (VA) and VREFIN can be connected together and share the same supply voltage.  
10.1 Using References as Power Supplies  
Because the DAC082S085 consumes very little power, a reference source may be used as the reference input or  
the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and  
stability. Some low noise regulators can also be used. Listed below are a few reference and power supply  
options for the DAC082S085.  
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Using References as Power Supplies (continued)  
10.1.1 LM4130  
The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the  
DAC082S085. The 4.096-V version is useful if a 0 to 4.095-V output range is desirable or acceptable. Bypassing  
the LM4130 VIN pin with a 0.1-µF capacitor and the VOUT pin with a 2.2-µF capacitor improves stability and  
reduces output noise. The LM4130 comes in a space-saving, 5-pin SOT-23.  
Input  
Voltage  
LM4132-4.1  
C1  
C2  
C3  
0.1 mF  
2.2 mF  
0.1 mF  
VA VREFIN  
DAC082S085  
V
OUT  
= 0V to 4.092V  
SYNC  
DIN  
SCLK  
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Figure 37. The LM4130 as a Power Supply  
10.1.2 LM4050  
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the  
DAC082S085. It is available in 4.096-V and 5-V versions and comes in a space-saving, 3-pin SOT-23.  
Input  
Voltage  
R
I
DAC  
V
Z
I
Z
0.1 mF  
0.47 mF  
V
V
REFIN  
LM4050-4.1  
or  
LM4050-5.0  
A
DAC082S085  
V
OUT  
= 0V to 5V  
SYNC  
DIN  
SCLK  
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Figure 38. The LM4050 as a Power Supply  
The minimum resistor value in the circuit of Figure 38 must be chosen such that the maximum current through  
the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at  
its maximum, the LM4050 voltage at its minimum, and the DAC082S085 drawing zero current. The maximum  
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum  
DAC082S085 current in full operation. The conditions for minimum current include the input voltage at its  
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the  
DAC082S085 draws its maximum current. These conditions can be summarized in Equation 4 and Equation 5:  
R(min) = ( VIN(max) − VZ(min) ) /IZ(max)  
(4)  
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )  
where  
•
VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over  
temperature  
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Using References as Power Supplies (continued)  
•
•
•
IZ(max) is the maximum allowable current through the LM4050  
IZ(min) is the minimum current required by the LM4050 for proper regulation  
IDAC(max) is the maximum DAC082S085 supply current  
(5)  
10.1.3 LP3985  
The LP3985 is a low-noise, ultra-low dropout voltage regulator with a 3% accuracy over temperature. It is a good  
choice for applications that do not require a precision reference for the DAC082S085. It comes in 3-V, 3.3-V, and  
5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because low  
frequency noise is relatively difficult to filter, this specification could be important for some applications. The  
LP3985 comes in a space-saving, 5-pin SOT-23 and 5-bump DSBGA packages.  
Input  
Voltage  
LP3985  
0.1 mF  
0.1 mF  
1 mF  
V
V
REFIN  
0.01 mF  
A
DAC082S085  
V
OUT  
= 0V to 5V  
SYNC  
DIN  
SCLK  
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Figure 39. Using the LP3985 Regulator  
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic  
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and  
understanding of the capacitor specification is required to ensure correct device operation.  
10.1.4 LP2980  
The LP2980 is an ultra-low dropout regulator with a 0.5% or 1% accuracy over temperature, depending upon  
grade. It is available in 3-V, 3.3-V, and 5-V versions, among others.  
V
IN  
Input  
Voltage  
V
OUT  
LP2980  
ON /  
OFF  
1 mF  
0.1 mF  
V
A
V
REFIN  
DAC102S085  
V
OUT  
= 0V to 5V  
SYNC  
DIN  
SCLK  
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Figure 40. Using the LP2980 Regulator  
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor  
must be at least 1-µF over temperature, but values of 2.2 µF or more provide even better performance. The ESR  
of this capacitor must be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum  
capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small  
size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors  
are typically not a good choice due to their large size and have ESR values that may be too high at low  
temperatures.  
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11 Layout  
11.1 Layout Guidelines  
For best accuracy and minimum noise, the printed-circuit board containing the DAC082S085 must have separate  
analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of  
these planes must be placed in the same board layer. There should be a single ground plane. A single ground  
plane is preferred if digital return current does not flow through the analog ground area. Frequently a single  
ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current.  
Separate ground planes must only be used when the fencing technique is inadequate. The separate ground  
planes must be connected in one place, preferably near the DAC082S085. Take special care to ensure that  
digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous  
return path below their traces.  
The DAC082S085 power supply must be bypassed with a 10-µF and a 0.1-µF capacitor as close as possible to  
the device with the 0.1 µF right at the device supply pin. The 10-µF capacitor must be a tantalum type and the  
0.1-µF capacitor must be a low ESL, low ESR type. The power supply for the DAC082S085 must only be used  
for analog circuits.  
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the  
board. The clock and data lines must have controlled impedances.  
11.2 Layout Example  
Figure 41. DAC082S085 Layout Example  
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12 Device and Documentation Support  
12.1 Device Support  
12.1.1 Device Nomenclature  
12.1.1.1 Specification Definitions  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB, which is VREF / 256 = VA / 256.  
DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change  
in the output of another DAC.  
DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale  
change in the input register of another DAC.  
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital  
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.  
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded  
into the DAC and the value of VA × 255 / 256.  
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and  
Full-Scale Errors as GE = FSE – ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.  
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register  
changes. It is specified as the area of the glitch in nanovolt-seconds.  
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line  
through the input to output transfer function. The deviation of any given code from this straight line is measured  
from the center of that code value. The end point method is used. INL for this product is specified over a limited  
range, per the electrical tables.  
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is  
LSB = VREF / 2n  
where  
•
•
VREF is the supply voltage for this product  
n is the DAC resolution in bits, which is 8 for the DAC082S085  
(6)  
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output  
stability maintained.  
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when  
the input code increases.  
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is  
1/2 of VA.  
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3 dB below the input sine wave  
on VREFIN with a full-scale code loaded into the DAC.  
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from  
the power supply. The difference between the supply and output currents is the power consumed by the device  
without a load.  
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is  
updated.  
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs  
with an ideal sine wave applied to VREFIN. THD is measured in dB.  
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the falling edge of the  
16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V.  
Copyright © 2006–2016, Texas Instruments Incorporated  
Submit Documentation Feedback  
23  
Product Folder Links: DAC082S085  
DAC082S085  
SNAS365G –MAY 2006–REVISED JUNE 2016  
www.ti.com  
Device Support (continued)  
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been  
entered.  
12.2 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
12.3 Community Resource  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
12.4 Trademarks  
E2E is a trademark of Texas Instruments.  
SPI is a trademark of Motorola, Inc..  
All other trademarks are the property of their respective owners.  
12.5 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
12.6 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
24  
Submit Documentation Feedback  
Copyright © 2006–2016, Texas Instruments Incorporated  
Product Folder Links: DAC082S085  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
DAC082S085CIMM/NOPB  
DAC082S085CIMMX/NOPB  
DAC082S085CISD/NOPB  
DAC082S085CISDX/NOPB  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
VSSOP  
VSSOP  
WSON  
WSON  
DGS  
DGS  
DSC  
DSC  
10  
10  
10  
10  
1000 RoHS & Green  
3500 RoHS & Green  
1000 RoHS & Green  
4500 RoHS & Green  
SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 105  
X76C  
X76C  
X77C  
X77C  
SN  
SN  
SN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
DAC082S085CIMM/NOPB VSSOP  
DGS  
DGS  
10  
10  
1000  
3500  
178.0  
330.0  
12.4  
12.4  
5.3  
5.3  
3.4  
3.4  
1.4  
1.4  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
DAC082S085CIMMX/  
NOPB  
VSSOP  
DAC082S085CISD/NOPB WSON  
DSC  
DSC  
10  
10  
1000  
4500  
178.0  
330.0  
12.4  
12.4  
3.3  
3.3  
3.3  
3.3  
1.0  
1.0  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
DAC082S085CISDX/  
NOPB  
WSON  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
DAC082S085CIMM/NOPB  
VSSOP  
VSSOP  
DGS  
DGS  
10  
10  
1000  
3500  
210.0  
367.0  
185.0  
367.0  
35.0  
35.0  
DAC082S085CIMMX/  
NOPB  
DAC082S085CISD/NOPB  
WSON  
WSON  
DSC  
DSC  
10  
10  
1000  
4500  
210.0  
367.0  
185.0  
367.0  
35.0  
35.0  
DAC082S085CISDX/  
NOPB  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DGS0010A  
VSSOP - 1.1 mm max height  
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE  
C
SEATING PLANE  
0.1 C  
5.05  
4.75  
TYP  
PIN 1 ID  
AREA  
A
8X 0.5  
10  
1
3.1  
2.9  
NOTE 3  
2X  
2
5
6
0.27  
0.17  
10X  
3.1  
2.9  
1.1 MAX  
0.1  
C A  
B
B
NOTE 4  
0.23  
0.13  
TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.15  
0.05  
0.7  
0.4  
0 - 8  
DETAIL A  
TYPICAL  
4221984/A 05/2015  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.  
5. Reference JEDEC registration MO-187, variation BA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DGS0010A  
VSSOP - 1.1 mm max height  
SMALL OUTLINE PACKAGE  
10X (1.45)  
(R0.05)  
TYP  
SYMM  
10X (0.3)  
1
5
10  
SYMM  
6
8X (0.5)  
(4.4)  
LAND PATTERN EXAMPLE  
SCALE:10X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
0.05 MAX  
ALL AROUND  
0.05 MIN  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
NOT TO SCALE  
4221984/A 05/2015  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DGS0010A  
VSSOP - 1.1 mm max height  
SMALL OUTLINE PACKAGE  
10X (1.45)  
SYMM  
(R0.05) TYP  
10X (0.3)  
8X (0.5)  
1
5
10  
SYMM  
6
(4.4)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:10X  
4221984/A 05/2015  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
MECHANICAL DATA  
DSC0010A  
SDA10A (Rev A)  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
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Copyright © 2022, Texas Instruments Incorporated  

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