DAC11001BPFBR_技术文档

DAC11001B

ZHCSPG5 –DECEMBER 2021

DAC11001B 20 位低噪声、超低谐波失真、

快速稳定、高电压输出数模转换器(DAC)

1 特性

3 说明

• 20 位单调性：1LSB DNL（最大值）

• 积分线性：1LSB INL（最大值）

• 低噪声：7nV/√Hz

• 独立于代码的低干扰：1nV-s

• 出色的THD：

在20kHz f_OUT、1MHz f_DAC下为–118dB

• 快速稳定：1µs

20 位 DAC11001B 是一款高精度、低噪声、电压输

出、单通道数模转换器 (DAC)。DAC11001B 根据设计

具有单调性，并可在所有输出范围内提供出色的线性

度。

非缓冲电压输出可提供低噪声性能 (7nV/√Hz) 和快速

稳定时间 (1µs)，因此这款器件非常适合低噪声、快速

控制环路和波形生成应用。DAC11001B 兼具增强型抗

尖峰脉冲电路以及独立于代码的超低干扰 (1nV-s)，可

实现干净的波形斜坡和超低总谐波失真(THD)。

• 灵活的输出范围：V_REFPF至V_REFNF

• 集成式精密反馈电阻器

• 50MHz、4 线SPI 兼容接口

DAC11001B 器件包含上电复位电路，因此 DAC 上电

时使用寄存器中的已知值。使用外部基准，可以实现

V_REFPF到 V_REFNF的 DAC 输出，包括非对称输出范

围。

– 读回

– 菊花链

• 温度范围：–40°C 至+125°C

• 封装：48 管脚TQFP

DAC11001B 使用一个以高达 50MHz 的时钟速率运行

的多功能4 线制串行接口。

2 应用

• 实验室和现场仪表

• 光谱仪

• 模拟输出模块

• 电池测试

• 半导体测试

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

DAC11001B

TQFP (48)

7.00mm × 7.00mm

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。

• 任意波形发生器(AWG)

• MRI

• X 射线系统

• 专业音频放大器（机架式）

IOVDD DVDD VCC AVDD

REFPS REFPF

Optional Gain

OPA828

C₁

R₂

R₁

+

–

V_REFP

REFPF

REFPS

ROFS

RCM

–

+

SCLK

SDIN

R

V_OUT

DAC11001B

OPA828

REFNS

REFNF

Power On Reset

C₂

–

+

SYNC

SDO

RFB

OUT

V_REFN

OPA828

Buffer

DAC

Register

DAC

LDAC

CLR

Register

任意波形发生电路

Power

Down Logic

ALARM

DGND

VSS AGND

REFNS REFNF

功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASF03

DAC11001B

ZHCSPG5 –DECEMBER 2021

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................28

7.5 Programming............................................................ 29

7.6 Register Map.............................................................31

8 Application and Implementation..................................36

8.1 Application Information............................................. 36

8.2 Typical Application.................................................... 36

8.3 System Examples..................................................... 40

8.4 What to Do and What Not to Do............................... 43

8.5 Initialization Set Up................................................... 43

9 Power Supply Recommendations................................44

9.1 Power-Supply Sequencing........................................46

10 Layout...........................................................................47

10.1 Layout Guidelines................................................... 47

10.2 Layout Example...................................................... 48

11 Device and Documentation Support..........................49

11.1 Device Support........................................................49

11.2 Documentation Support.......................................... 49

11.3 接收文档更新通知................................................... 49

11.4 支持资源..................................................................49

11.5 Trademarks............................................................. 49

11.6 Electrostatic Discharge Caution..............................49

11.7 术语表..................................................................... 49

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................7

6.6 Timing Requirements: Write, 4.5 V ≤DV_DD≤

5.5 V............................................................................10

6.7 Timing Requirements: Write, 2.7 V ≤DV_DD

<

4.5 V............................................................................ 11

6.8 Timing Requirements: Read and Daisy-Chain

Write, 4.5 V ≤DV_DD≤5.5 V..................................... 12

6.9 Timing Requirements: Read and Daisy-Chain

Write, 2.7 V ≤DV_DD< 4.5 V.......................................13

6.10 Timing Diagrams ....................................................14

6.11 Typical Characteristics............................................ 15

7 Detailed Description......................................................25

7.1 Overview...................................................................25

7.2 Functional Block Diagram.........................................25

7.3 Feature Description...................................................25

Information.................................................................... 49

4 Revision History

DATE

REVISION

NOTES

December 2021

*

Initial Release

2

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5 Pin Configuration and Functions

NC

AGND

REFPF

REFPS

REFNF

REFNS

OUT

1

36

35

34

33

32

31

30

29

28

27

26

25

NC

2

AGND

SDO

SYNC

SDIN

SCLK

CLR

3

4

5

6

7

AGND-OUT

RFB

8

NC

9

IOVDD

DVDD

DGND

NC

ROFS

10

11

12

RCM

NC

Not to scale

图5-1. PFB Package, 48-Pin TQFP, Top View

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表5-1. Pin Functions

TYPE

DESCRIPTION

NAME

NO.

2, 35, 38,

40, 42, 43,

46, 47

Analog

ground

AGND

Connect to 0 V.

Analog

ground

AGND-OUT

AGND-TnH

8

Connect to 0 V. Measure DAC output voltage with respect to this node.

Connect to 0 V. Integrated deglitcher clock ground.

Analog

ground

14

ALARM

AVDD

CLR

19

39, 41

30

Output

Power

Input

Alarm output

Positive low voltage analog power supply

DAC registers clear pin, active low

16, 17, 20,

21, 22, 23,

26

Digital

ground

DGND

Connect to 0 V.

DVDD

RFB

27

9

Power

Input

Digital power supply pin

Integrated precision resistor feedback node

Interface power supply pin

IOVDD

LDAC

28

18

Power

Input

Load DAC pin, active low

1, 12, 13,

15, 24, 25,

29, 36, 37,

48

NC

No connection, leave floating

—

OUT

7

11

5

Output

Input

Unbuffered voltage output

RCM

Integrated precision resistor common-mode node

External negative reference input. Connect to 0 V for unipolar DAC output.

External negative reference sense node

External positive reference input

REFNF

REFNS

REFPF

REFPS

ROFS

6

3

4

External positive reference sense node

Integrated precision resistor offset node

10

Serial clock input of serial peripheral interface (SPI). Schmitt-trigger logic input.

Data are transferred at rates of up to 50 MHz.

SCLK

31

Input

Serial data input. Schmitt-trigger logic input.

Data are clocked into the input shift register on the falling edge of the serial clock input.

SDIN

SDO

32

34

33

Input

Output

Input

Serial data output. Data are valid on the falling edge of SCLK.

SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless

SYNC is low. When SYNC is high, the SDO pin is in high-impedance status.

SYNC

VCC

VSS

45

44

Power

Analog positive power supply

Analog negative power supply

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

AV_DDto AGND

7

Positive supply voltage

V_CCto V_SS

40

V

–0.3

V_CCto AGND

40

–0.3

Negative supply voltage

V_SSto AGND

0.3

V

–19

Digital and IO supply voltage

DV_DD,IOV_DDto DGND

V_REFPFto V_REFNF

V_REFPFto V_CC

V_REFPFto AGND

V_REFNFto AGND

V_REFNFto V_SS

7

40

–0.3

Positive reference voltage

V_CC+ 0.3

40

V

–0.3

0.3

–19

Negative reference voltage

Digital input(s) to DGND

V

0.3

V_SS–0.3

DGND –0.3

V_SS

IOV_DD+ 0.3

V_CC

to AGND (V_SS= AGND)

to V_SS

OUT, RFB, RCM, ROFS pin voltage

0

V_CC

Alarm pin voltage, ALARM to DGND

Digital output, SDO to DGND

Current into any pin

DV_DD+ 0.3

10

V

–0.3

mA

°C

–10

T_J

Junction temperature

150

T_stg

Storage temperature

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V

AV_DDto AGND

4.5

5.5

–3

33

V_SSto AGND

V

–18

V_CCto AGND

8

V

V_CCto V_SS

11

2.7

36

V

DV_DDto DGND

5.5

0.3

V

IOV_DDto DGND

AGND to DGND

V_IHdigital input high voltage

V_ILdigital input low voltage

V_REFPFto AGND

V_REFNFto AGND

V_REFPFto V_REFNF

1.7

V

–0.3

0.7 × IOV_DD

V

0.3 × IOV_DD

V

3

–15

3

15

0

V

30

V

T_A

Operating temperature

125

°C

–40

6.4 Thermal Information

DAC11001B

PFB (TQFP)

48 PINS

51.0

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

10.3

16.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

Ψ_JT

16.0

Ψ_JB

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

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6.5 Electrical Characteristics

at T_A= –40°C to +125°C, V_CC= +15 V, V_SS= –15 V, AV_DD= 5.5 V, DV_DD= 3.3 V, IOV_DD= 1.8 V, see note⁽¹⁾for V_REFPFand

V_REFNF, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at T_A=

25°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

STATIC PERFORMANCE

Resolution

20

Bits

T_A= 0°C to 70°C⁽⁴⁾

V_REFPF= 10 V and V_REFNF= 0 V

1

–1

V_REFPF= +5 V and V_REFNF= –5 V

INL

Relative accuracy^{(2) (3)}

LSB

1.25

T_A= 0°C to 70°C⁽⁴⁾

–1.25

–2

2

T_A= –40°C to +125°C

T_A= 25°C, 1000 hrs

T_A= –40°C to +125°C

Relative accuracy drift over time⁽²⁾

Differential nonlinearity^{(2) (3)}

±0.1

LSB

DNL

1

4

LSB

–1

–4

T_A= 0°C to 70°C, code 0d into DAC,

unipolar ranges only

Zero code error⁽⁴⁾

LSB

T_A= –40°C to +125°C, code 0d into DAC,

unipolar ranges only

4

–4

T_A= 25°C, unipolar ranges only

±2

T_A= 0°C to 70°C, code 0d into DAC,

unipolar ranges only

±0.04

ppm

FSR/°C

Zero code error temperature coefficient

T_A= –40°C to +125°C, code 0d into DAC,

unipolar ranges only

±0.04

T_A= 0°C to 70°C

8

–8

ppm of

FSR

Gain error^{(2) (4)}

10

T_A= –40°C to +125°C

T_A= 25°C

–10

±2

±0.04

T_A= 0°C to 70°C

ppm

FSR/°C

Gain error temperature coefficient

T_A= –40°C to +125°C

T_A= 0°C to 70°C, code 1048575d into DAC

8

–8

T_A= –40°C to +125°C, code 1048575d into

DAC

Positive full-scale error⁽⁴⁾

LSB

10

–10

T_A= 25°C, code 1048575d into DAC

T_A= 0°C to 70°C

±2

±0.04

ppm

FSR/°C

Full-scale error temperature coefficient

T_A= –40°C to +125°C

OUTPUT CHARACTERISTICS

Headroom

From V_REFPFto V_CC

From V_REFNFto V_SS

From ROFS to RCM

From RCM to RFB

5

V

Footroom

5

DC impedance

kΩ

Z_O

DC output impedance

2.5

1.5

1

V_CC= 15 V ±20%, V_SS= –15 V

V_CC= 15 V, V_SS= –15 V ±20%

Power supply rejection ratio (dc)

µV/V

ppm of

FSR

Output voltage drift over time

T_A= 25°C, V_OUT= midscale, 1000 hr

1

VOLTAGE REFERENCE INPUT

Reference input impedance (REFPF)

DAC at midscale,

V_REFPF= 10 V, V_REFNF= 0 V

5.5

7

kΩ

DAC at midscale,

V_REFPF= 10 V, V_REFNF= 0 V

Reference input impedance (REFNF)

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6.5 Electrical Characteristics (continued)

at T_A= –40°C to +125°C, V_CC= +15 V, V_SS= –15 V, AV_DD= 5.5 V, DV_DD= 3.3 V, IOV_DD= 1.8 V, see note⁽¹⁾for V_REFPFand

V_REFNF, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at T_A=

25°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC PERFORMANCE

Full-scale settling to 0.1%FSR,

V_REFPF= 10 V, V_REFNF= 0 V

1

3

Full-scale settling to ±1 LSB,

V_REFPF= 10 V, V_REFNF= 0 V

t_s

Output voltage settling time⁽⁵⁾

µs

1-mV step settling to ±1 LSB,

V_REFPF= 10 V, V_REFNF= 0 V

2.5

30

Full-scale step, measured at OUT pin,

V_REFPF= 10 V, V_REFNF= 0 V

SR

Slew rate⁽⁶⁾

V/µs

V

Measured at unbuffered DAC voltage output,

V_REFPF= 10 V, V_REFNF= 0 V

Power-on glitch magnitude

–0.2

0.4

3

0.1-Hz to 10-Hz, DAC at midscale,

V_REFPF= 10 V, V_REFNF= 0 V

µVpp

µVrms

V_n

Output noise

100-kHz bandwidth, DAC at midscale,

V_REFPF= 10 V, V_REFNF= 0 V

Measured at 1 kHz, 10 kHz, 100 kHz,

DAC at mid scale,

V_REFPF= 10 V, V_REFNF= 0 V

nV/√

Hz

Output noise density

7

–120

–114

–92

DAC update rate = 768 kHz, f_OUT= 1 kHz,

V_REFPF= 4.5 V, V_REFNF= –4.5 V,

sixth-order, low-pass, 30-kHz output filter

DAC update rate = 768 kHz, f_OUT= 20 kHz,

V_REFPF= 4.5 V, V_REFNF= –4.5 V,

sixth-order, low-pass, 30-kHz output filter

SFDR Spurious free dynamic range⁽⁶⁾

dB

DAC update rate = 1 MHz, f_OUT= 100 kHz,

V_REFPF= 4.5 V, V_REFNF= –4.5 V,

sixth-order, low-pass, 150-kHz output filter

DAC update rate = 768 kHz, f_OUT= 1 kHz,

V_REFPF= 4.5 V, V_REFNF= –4.5 V,

sixth-order, low-pass, 30-kHz output filter

–118

–96

DAC update rate = 768 kHz, f_OUT= 20 kHz,

V_REFPF= 4.5 V, V_REFNF= –4.5 V,

sixth-order, low-pass, 30-kHz output filter

THD

Total harmonic distortion⁽⁶⁾

dB

DAC update rate = 1 MHz, f_OUT= 100 kHz,

V_REFPF= 4.5 V, V_REFNF= –4.5 V,

sixth-order, low-pass, 150-kHz output filter

200-mV, 50-Hz or 60-Hz sine wave

superimposed on V_SS,V_CC= 15 V

95

Power supply rejection ratio (ac)

200-mV, 50 Hz or 60 Hz sine wave

superimposed on V_CC,V_SS= –15 V

±1 LSB change around mid code (including

feedthrough), V_REFPF= 10 V, V_REFNF= 0 V,

measured at output of buffer op amp

Code change glitch impulse

1

5

nV-s

mV

±1 LSB change around mid code (including

feedthrough), V_REFPF= 10 V, V_REFNF= 0 V,

measured at output of buffer op amp

Code change glitch impulse magnitude

V_REFPF= 10 V ± 10%, V_REFNF= 0 V,

frequency = 100 Hz, DAC at zero scale

–90

1

Reference feedthrough

dB

V_REFNF= –10 V ± 10%, V_REFPF= 10 V,

frequency = 100 Hz, DAC at full scale

SCLK = 1 MHz, DAC static at midscale,

V_REFPF= 10 V, V_REFNF= 0 V

Digital feedthrough

nV-s

8

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6.5 Electrical Characteristics (continued)

at T_A= –40°C to +125°C, V_CC= +15 V, V_SS= –15 V, AV_DD= 5.5 V, DV_DD= 3.3 V, IOV_DD= 1.8 V, see note⁽¹⁾for V_REFPFand

V_REFNF, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at T_A=

25°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DIGITAL INPUTS

Hysteresis voltage

0.4

±5

10

V

Input current

µA

pF

Pin capacitance

Per pin

DIGITAL OUTPUTS

V_OL

Low-level output voltage

Sinking 200 µA

Sourcing 200 µA

0.4

V

IOV_DD

–0.5

V_OH

High-level output voltage

High impedance leakage

±5

10

µA

pF

High impedance output capacitance

POWER

I_AVDD

I_VCC

Current flowing into AV_DD

Current flowing into V_CC

Current flowing into V_SS

Current flowing into DV_DD

V_REFPF= 10 V, V_REFNF= 0 V, midscale code

2.5

15

mA

I_VSS

I_DVDD

0.5

0.1

V_REFPF= 10 V, V_REFNF= 0 V, midscale code,

all digital input pins static at IOV_DD

I_IOVDD

Current flowing into IOV_DD

mA

I_REFPFReference input current (V_REFPF

)

V_REFPF= 10 V, V_REFNF= 0 V, midscale code

7

mA

I_REFNFReference input current (V_REFNF

)

(1) Specified for the following pairs: V_REFPF= 5 V and V_REFNF= 0 V; V_REFPF= 10 V and V_REFNF= 0 V; V_REFPF= 5 V and V_REFNF= –5 V;

V_REFPF= 10 V and V_REFNF= –10 V.

(2) Calculated between code 0d to 1048575d.

(3) With device temperature calibration mode enabled and used.

(4) Specified by design, not production tested.

(5) Adaptive TnH mode. TnH action is disabled for large code steps. For small steps, TnH action happens with a hold time of 1.2 µs.

(6) OUT pin buffered with unity gain OPA828.

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6.6 Timing Requirements: Write, 4.5 V ≤DV_DD≤5.5 V

all input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed from a voltage level of (V_IL+ V_IH) / 2,

SDO loaded with 20 pF, and T_A= –40°C to +125°C (unless otherwise noted)

MIN

NOM

MAX

33

UNIT

SCLK frequency, 1.7 V ≤IOV_DD< 2.7 V

f_SCLK

MHz

50

SCLK frequency, 2.7 V ≤IOV_DD≤5.5 V

15

10

15

10

13

8

SCLK high time, 1.7 V ≤IOV_DD< 2.7 V

t_SCLKHIGH

t_SCLKLOW

t_SDIS

ns

SCLK high time, 2.7 V ≤IOV_DD≤5.5 V

SCLK low time, 1.7 V ≤IOV_DD< 2.7 V

SCLK low time, 2.7 V ≤IOV_DD≤5.5 V

SDI setup, 1.7 V ≤IOV_DD< 2.7 V

SDI setup, 2.7 V ≤IOV_DD≤5.5 V

13

8

SDI hold, 1.7 V ≤IOV_DD< 2.7 V

t_SDIH

SDI hold, 2.7 V ≤IOV_DD≤5.5 V

23

18

15

10

55

50

10

5

SYNC falling edge to SCLK falling edge, 1.7 V ≤IOV_DD< 2.7 V

SYNC falling edge to SCLK falling edge, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC rising edge, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC rising edge, 2.7 V ≤IOV_DD≤5.5 V

SYNC high time, 1.7 V ≤IOV_DD< 2.7 V

t_CSS

t_CSH

t_CSHIGH

SYNC high time, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC ignore, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC ignore, 2.7 V ≤IOV_DD≤5.5 V

t_CSIGNORE

Synchronous update:

SYNC rising edge to LDAC falling edge, 1.7 V ≤IOV_DD< 2.7 V

50

t_LDACSL

ns

Synchronous update:

SYNC rising edge to LDAC falling edge, 2.7 V ≤IOV_DD≤5.5 V

20

LDAC low time, 1.7 V ≤IOV_DD< 2.7 V

LDAC low time, 2.7 V ≤IOV_DD≤5.5 V

CLR low time, 1.7 V ≤IOV_DD< 2.7 V

CLR low time, 2.7 V ≤IOV_DD≤5.5 V

t_LDACW

ns

t_CLRW

10

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6.7 Timing Requirements: Write, 2.7 V ≤DV_DD< 4.5 V

all input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed from a voltage level of (V_IL+ V_IH) / 2,

SDO loaded with 20 pF, and T_A= –40°C to +125°C (unless otherwise noted)

MIN

NOM

MAX

20

UNIT

SCLK frequency, 1.7 V ≤IOV_DD< 2.7 V

f_SCLK

MHz

25

SCLK frequency, 2.7 V ≤IOV_DD≤5.5 V

25

20

25

20

21

16

21

16

41

36

25

20

100

10

5

SCLK high time, 1.7 V ≤IOV_DD< 2.7 V

t_SCLKHIGH

t_SCLKLOW

t_SDIS

ns

SCLK high time, 2.7 V ≤IOV_DD≤5.5 V

SCLK low time, 1.7 V ≤IOV_DD< 2.7 V

SCLK low time, 2.7 V ≤IOV_DD≤5.5 V

SDI setup, 1.7 V ≤IOV_DD< 2.7 V

SDI setup, 2.7 V ≤IOV_DD≤5.5 V

SDI hold, 1.7 V ≤IOV_DD< 2.7 V

t_SDIH

SDI hold, 2.7 V ≤IOV_DD≤5.5 V

SYNC falling edge to SCLK falling edge, 1.7 V ≤IOV_DD< 2.7 V

SYNC falling edge to SCLK falling edge, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC rising edge, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC rising edge, 2.7 V ≤IOV_DD≤5.5 V

SYNC high time, 1.7 V ≤IOV_DD< 2.7 V

t_CSS

t_CSH

t_CSHIGH

SYNC high time, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC ignore, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC ignore, 2.7 V ≤IOV_DD≤5.5 V

t_CSIGNORE

Synchronous update:

SYNC rising edge to LDAC falling edge, 1.7 V ≤IOV_DD< 2.7 V

100

t_LDACSL

ns

Synchronous update:

SYNC rising edge to LDAC falling edge, 2.7 V ≤IOV_DD≤5.5 V

40

LDAC low time, 1.7 V ≤IOV_DD< 2.7 V

LDAC low time, 2.7 V ≤IOV_DD≤5.5 V

CLR low time, 1.7 V ≤IOV_DD< 2.7 V

CLR low time, 2.7 V ≤IOV_DD≤5.5 V

t_LDACW

ns

t_CLRW

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6.8 Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤DV_DD≤5.5 V

all input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed from a voltage level of (V_IL+ V_IH) / 2,

SDO loaded with 20 pF, and T_A= –40°C to +125°C (unless otherwise noted)

MIN

NOM

MAX UNIT

10

1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

20

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

MHz

15

30

50

25

33

16

50

25

33

16

13

8

t_SCLKHIGH

ns

t_SCLKLOW

ns

SDI setup, 1.7 V ≤IOV_DD< 2.7 V

SDI setup, 2.7 V ≤IOV_DD≤5.5 V

SDI hold, 1.7 V ≤IOV_DD< 2.7 V

SDI hold, 2.7 V ≤IOV_DD≤5.5 V

t_SDIS

ns

13

8

t_SDIH

30

20

15

10

55

50

10

5

SYNC falling edge to SCLK falling edge, 1.7 V ≤IOV_DD< 2.7 V

SYNC falling edge to SCLK falling edge, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC rising edge, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC rising edge, 2.7 V ≤IOV_DD≤5.5 V

SYNC high time, 1.7 V ≤IOV_DD< 2.7 V

t_CSS

t_CSH

t_CSHIGH

SYNC high time, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC ignore, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC ignore, 2.7 V ≤IOV_DD≤5.5 V

t_CSIGNORE

Synchronous update:

SYNC rising edge to LDAC falling edge, 1.7 V ≤IOV_DD< 2.7 V

50

t_LDACSL

ns

Synchronous update:

SYNC rising edge to LDAC falling edge, 2.7 V ≤IOV_DD≤5.5 V

20

0

LDAC low time, 1.7 V ≤IOV_DD< 2.7 V

t_LDACW

LDAC low time, 2.7 V ≤IOV_DD≤5.5 V

CLR low time, 1.7 V ≤IOV_DD< 2.7 V

t_CLRW

ns

CLR low time, 2.7 V ≤IOV_DD≤5.5 V

35

SCLK rising edge to SDO valid data, 1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

SCLK rising edge to SDO valid data, 2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

SCLK falling edge to SDO valid data, 1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

SCLK falling edge to SDO valid data, 2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

SYNC rising edge to SDO HiZ, 1.7 V ≤IOV_DD< 2.7 V

SYNC rising edge to SDO HiZ, 2.7 V ≤IOV_DD≤5.5 V

0

25

ns

35

t_SDODLY

0

25

0

20

ns

20

t_SDOZ

0

12

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6.9 Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤DV_DD< 4.5 V

all input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed from a voltage level of (V_IL+ V_IH) / 2,

SDO loaded with 20 pF, and T_A= –40°C to +125°C (unless otherwise noted)

MIN

NOM

MAX UNIT

8

1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

16

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

MHz

10

20

62

31

50

25

62

31

50

25

21

16

21

16

41

36

25

20

100

10

5

t_SCLKHIGH

ns

t_SCLKLOW

ns

SDI setup, 1.7 V ≤IOV_DD< 2.7 V

SDI setup, 2.7 V ≤IOV_DD≤5.5 V

SDI hold, 1.7 V ≤IOV_DD< 2.7 V

SDI hold, 2.7 V ≤IOV_DD≤5.5 V

t_SDIS

ns

t_SDIH

SYNC falling edge to SCLK falling edge, 1.7 V ≤IOV_DD< 2.7 V

SYNC falling edge to SCLK falling edge, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC rising edge, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC rising edge, 2.7 V ≤IOV_DD≤5.5 V

SYNC high time, 1.7 V ≤IOV_DD< 2.7 V

t_CSS

t_CSH

t_CSHIGH

SYNC high time, 2.7 V ≤IOV_DD≤5.5 V

SCLK falling edge to SYNC ignore, 1.7 V ≤IOV_DD< 2.7 V

SCLK falling edge to SYNC ignore, 2.7 V ≤IOV_DD≤5.5 V

t_CSIGNORE

Synchronous update:

SYNC rising edge to LDAC falling edge, 1.7 V ≤IOV_DD< 2.7 V

100

t_LDACSL

ns

Synchronous update:

SYNC rising edge to LDAC falling edge, 2.7 V ≤IOV_DD≤5.5 V

40

0

LDAC low time, 1.7 V ≤IOV_DD< 2.7 V

t_LDACW

LDAC low time, 2.7 V ≤IOV_DD≤5.5 V

CLR low time, 1.7 V ≤IOV_DD< 2.7 V

t_CLRW

ns

CLR low time, 2.7 V ≤IOV_DD≤5.5 V

40

SCLK rising edge to SDO valid data, 1.7 V ≤IOV_DD< 2.7 V, FSDO = 0

SCLK rising edge to SDO valid data, 2.7 V ≤IOV_DD≤5.5 V, FSDO = 0

SCLK rising edge to SDO valid data, 1.7 V ≤IOV_DD< 2.7 V, FSDO = 1

SCLK rising edge to SDO valid data, 2.7 V ≤IOV_DD≤5.5 V, FSDO = 1

SYNC rising edge to SDO HiZ, 1.7 V ≤IOV_DD< 2.7 V

SYNC rising edge to SDO HiZ, 2.7 V ≤IOV_DD≤5.5 V

0

30

ns

40

t_SDODLY

0

30

0

20

ns

20

t_SDOZ

0

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6.10 Timing Diagrams

t_CSS

t_CSH

t_CSHIGH

SYNC

t_CSIGNORE

t_SCLKLOW

SCLK

t_SCLKHIGH

t_SDIH

Bit 31

t_SDIS

SDIN

Bit 1

Bit 0

LDAC¹

t_CLRW

t_LDACSLt_LDACW

CLR

图6-1. Serial Interface Write Timing: Standalone Mode

t_CSHIGH

t_CSS

t_CSH

SYNC

SCLK

t_CSIGNOR

E

t_SCLKLOW

t_SCLKHIGH

FIRST READ COMMAND

Bit 22

ANY COMMAND

Bit 22

SDIN

Bit 31

Bit 0

Bit 31

Bit 0

t_SDIH

t_SDIS

DATA FROM FIRST

READ COMMAND

SDO

Bit 31

Bit 22

Bit 0

t_SDODZ

t_SDODLY

LDAC¹

t_CLRW

t_LDACSLt_LDACW

CLR

图6-2. Serial Interface Read and Write Timing: Daisy-Chain Mode

14

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6.11 Typical Characteristics

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

2

1.5

1

0.8

0.6

0.4

0.2

0

0.5

0

-0.2

-0.4

-0.6

-0.8

-1

-0.5

-1

UP, 5 V

UP, 10 V

BP, ±10 V

UP, 10 V, [gain = 2x]

UP, 5 V

UP, 10 V

BP, 10 V

UP, 10 V, [gain = 2x]

-1.5

-2

0

262144

524288

Code

786432

1048576

0

262144

524288

Code

786432

1048576

图6-4. Differential Linearity Error vs Digital Input Code

图6-3. Integral Linearity Error vs Digital Input Code

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

INL max, UP, 5 V

INL max, UP, 10 V

INL max, BP, ±10 V

INL min, UP, 5 V

INL min, UP, 10 V

INL min, BP, ±10 V

INL max, UP, 10 V, [gain 2x]

INL min, UP, 10 V, [gain 2x]

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Temperature calibration enabled

图6-5. Integral Linearity Error vs Temperature

图6-6. Differential Linearity Error vs Temperature

4

10

8

3

2

6

4

1

2

0

-2

-4

-6

-1

-2

-3

-4

UP, 5 V

BP, 5 V

UP, 10 V

BP, 10 V

UP, 5 V

BP, 5 V

UP, 10 V

BP, 10 V

-8

-10

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Temperature calibration enabled

图6-7. Zero Code Error vs Temperature

图6-8. Positive Full-Scale Error vs Temperature

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

15

12

9

4

3

2

6

1

3

0

-3

-6

-9

-12

-15

-1

-2

-3

-4

UP, 5 V

BP, 5 V

UP, 10 V

BP, 10 V

INL min, UP, 5 V

INL max, UP, 5 V

INL min, BP, ê5 V

INL max, BP, ê5 V

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

11

11.5

12

12.5

13

13.5

14

14.5

15

Supply Voltage, V_CC(V) = -V_SS(V)

Temperature calibration enabled

图6-9. Gain Error vs Temperature

图6-10. Integral Linearity Error vs Supply Voltage

1

0.8

0.6

0.4

0.2

0

10

8

6

4

2

0

-0.2

-0.4

-0.6

-0.8

-1

-2

-4

-6

DNL min, UP, 5 V

DNL max, UP, 5 V

DNL min, BP, ê5 V

DNL max, BP, ê5 V

BP, ê5 V

UP, 5 V

-8

-10

11

11.5

12

12.5

13

13.5

14

14.5

15

11

11.5

12

12.5

13

13.5

14

14.5 15

Supply Voltage, V_CC(V) = -V_SS(V)

图6-11. Differential Linearity Error vs Supply Voltage

图6-12. Zero Code Error vs Supply Voltage

4

BP, 5 V

UP, 5 V

BP, 5 V

UP, 5 V

3.2

2.4

1.6

0.8

0

3.2

2.4

1.6

0.8

0

-0.8

-1.6

-2.4

-3.2

-4

-0.8

-1.6

-2.4

-3.2

-4

11

11.5

12

12.5

13

13.5

14

14.5

15

11

11.5

12

12.5

13

13.5

14

14.5

15

Supply Voltage, V_CC(V) = -V_SS(V)

图6-13. Positive Full-Scale Error vs Supply Voltage

图6-14. Gain Error vs Supply Voltage

16

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

4

3

1

0.8

0.6

0.4

0.2

0

2

1

0

-0.2

-0.4

-0.6

-0.8

-1

-2

-3

-4

INL min

INL max

DNL min

DNL max

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5 10

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5 10

Reference Voltage, V_REFPF(V) = -V_REFNF(V)

图6-15. Integral Linearity Error vs Reference Voltage

图6-16. Differential Linearity Error vs Reference Voltage

4

3.2

2.4

1.6

0.8

0

-0.2

-0.4

-0.6

-0.8

-1

-0.8

-1.6

-2.4

-3.2

-4

-1.2

-1.4

-1.6

-1.8

-2

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5 10

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5 10

Reference Voltage, V_REFPF(V) = -V_REFNF(V)

图6-17. Zero Code Error vs Reference Voltage

图6-18. Gain Error vs Reference Voltage

1.5

20

16

12

8

I_DVDD

I_IOVDD

1.2

0.9

0.6

0.3

0

-0.3

-0.6

-0.9

-1.2

-1.5

4

0

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5 10

0

262144

524288

Code

786432

1048576

Reference Voltage, V_REFPF(V) = -V_REFNF(V)

V_REFPF= 10 V, V_REFNF= 0 V

图6-19. Positive Full-Scale Error vs Reference Voltage

图6-20. Supply Current (DV_DDand IOV_DD) vs Digital Input Code

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

9

7

5

I_REFPF

I_REFNF

3

5

3

1

I_VCC

I_VSS

-1

-3

-5

-7

-9

-1

-3

-5

0

262144

524288

Code

786432

1048576

0

262144

524288

Code

786432

1048576

V_REFPF= 10 V, V_REFNF= 0 V

图6-21. Supply Current (V_CCand V_SS

)

图6-22. Reference Current (V_REFPFand V_REFNF)

vs Digital Input Code

50

40

30

20

10

0

I_DVDD

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (C)

V_REFPF= 10 V, V_REFNF= 0 V, DAC at midcode

V_REFPF= 10 V, V_REFNF= 0 V

图6-24. Supply Current (DV_DD) vs Temperature

图6-23. Supply Current (AV_DD) vs Digital Input Code

12

I_VCC

I_VSS

8

4

0

-4

-8

-12

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (C)

V_REFPF= 10 V, V_REFNF= 0 V, DAC at midcode

图6-25. Supply Current (V_CCand V_SS

)

图6-26. Reference Current (V_REFPFand V_REFNF

)

vs Temperature

18

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

2.4

2.2

2

12

8

I_AVDD

1.8

1.6

1.4

1.2

1

4

0

0.8

0.6

0.4

0.2

0

-4

-8

-12

I_VCC

14

I_VSS

14.5 15

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (C)

11

11.5

12

12.5

13

13.5

Supply Voltage, VCC(V) = -VSS(V)

V_REFPF= 10 V, V_REFNF= 0 V, DAC at midcode

V_REFPF= 5 V, V_REFNF= 0 V, DAC at midcode

图6-28. Supply Current (V_CCand V_SS) vs Supply Voltage

图6-27. Supply Current (AV_DD) vs Temperature

1000

50

IOV_DD= 5V

IOV_DD= 3V

IOV_DD= 1.8 V

800

600

400

200

0

40

30

20

10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Logic Voltage, V_LOGIC(V)

V_REFPF= 10 V, V_REFNF= 0 V, DAC at midcode

图6-29. Supply Current (IOV_DD

)

图6-30. Supply Current (IOV_DD

)

vs Input Pin Logic Level

0.005

0.004

0.003

0.002

0.001

0

15

10

5

0.005

0.004

0.003

0.002

0.001

0

15

V_OUT

LDAC

V_OUT

LDAC

10

5

0

-5

-10

-15

-20

-25

-30

-35

-10

-15

-20

-25

-30

-35

-0.001

-0.002

-0.003

-0.004

-0.005

-0.001

-0.002

-0.003

-0.004

-0.005

DACV glitch (0.4 nV-s)

DAC Glitch (0.75 nV-s)

3E-6 4E-6

0

1E-6

2E-6

Time (s)

5E-6

0

1E-6

2E-6

3E-6

Time (s)

4E-6

5E-6

V_REFPF= 10 V, V_REFNF= –10 V,

DAC transition midcode to midcode –1

图6-32. Glitch Impulse, Falling Edge, 1-LSB Step

DAC transition midcode –1 to midcode

图6-31. Glitch Impulse, Rising Edge, 1-LSB Step

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

1.6

1.4

1.2

1

1.6

1.4

1.2

1

V_OUTglitch, rise

V_OUTglitch, fall

V_OUTglitch, rise

V_OUTglitch, fall

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

Code

V_REFPF= 10 V, V_REFNF= 0 V

V_REFPF= 10 V, V_REFNF= –10 V

图6-34. Segment Glitch Impulse, 1-LSB Step

图6-33. Segment Glitch Impulse, 1-LSB Step

1.6

0.001

10

5

V_OUTglitch, rise

V_OUTglitch, fall

1.4

1.2

1

0.00075

0.0005

0.00025

0

-5

0.8

0.6

0.4

0.2

0

-10

-15

-20

-25

-30

-0.00025

-0.0005

-0.00075

-0.001

V_OUT

SCLK

0

5E-7

1E-6

Time (s)

1.5E-6

2E-6

V_REFPF= 10 V, V_REFNF= 0 V,

Code

DAC at midcode, measured at DAC output pin

图6-36. Clock Feedthrough

0.012

V_REFPF= 5 V, V_REFNF= 0 V

图6-35. Segment Glitch Impulse, 1-LSB Step

45

42

39

36

33

30

27

24

21

18

15

12

9

10.033

10.028

10.023

10.018

10.013

10.008

10.003

9.998

40

30

20

10

0

V_OUT(zoomed)

Settling band (+0.1%)

Settling band (-0.1%)

V_OUT

LDAC

0.01

0.008

0.006

0.004

0.002

0

V_OUT(zoomed)

Settling band (+0.1%)

Settling band (-0.1%)

V_OUT

LDAC

-0.002

-0.004

-0.006

-0.008

-0.01

-0.012

-0.014

-0.016

-0.018

-0.02

-10

-20

-30

-40

-50

6

3

0

-3

9.993

0

1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5

Time(s)

9.988

0

1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5

Time(s)

V_REFPF= 10 V, V_REFNF= 0 V

图6-38. Full-Scale Settling Time, Falling Edge

图6-37. Full-Scale Settling Time, Rising Edge

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

0.0025

0.00245

0.0024

20

0.0013

0.00125

0.0012

0.00115

0.0011

0.00105

0.001

16

10

8

0

0.00235

0.0023

-10

-20

-30

-40

-50

-60

-8

0.00225

0.0022

-16

-24

-32

V_OUT(zoomed)

Settling band (+1 LSB)

Settling band (-1 LSB)

LDAC

V_OUT(zoomed)

Settling band (+1 LSB)

Settling band (-1 LSB)

LDAC

0.00215

0.0021

0

1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5

Time(s)

0

1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5

Time(s)

V_REFPF= 10 V, V_REFNF= 0 V,

DAC transitions 100 codes around midscale

图6-39. 100 Codes Settling Time, Rising Edge

图6-40. 100 Codes Settling Time, Falling Edge

V_OUT(0.1 mV/Div)

10

Zero code

Mid code

Full code

9.25

8.5

7.75

7

6.25

5.5

4.75

4

Time (1 s/Div)

V_REFPF= 10 V, V_REFNF= 0 V,

500

1000 2000

5000 10000 20000

Frequency (Hz)

50000 100000

V_REFPF= 10 V, V_REFNF= 0 V, measured at DAC output

DAC at midcode, measured at DAC output pin

图6-41. DAC Output Noise Spectral Density

图6-42. DAC Output Noise: 0.1 Hz to 10 Hz

0

-40

-80

-40

-80

-120

-160

-120

-160

0

50

100

150

200

250

300

350 384

0

40

80 120 160 200 240 280 320 360384

Frequency (kHz)

DAC update rate = 768 kHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

sixth-order, low-pass, 30-kHz output filter

图6-43. 1-kHz Spectrum vs Frequency

图6-44. 20-kHz Spectrum vs Frequency

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

0

-102

-104

-106

-108

-110

-112

-114

-116

-118

-120

-40

-80

-120

-160

0

50 100 150 200 250 300 350 400 450 500

Frequency (kHz)

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

Output Frequency (kHz)

DAC update rate = 1 MHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

DAC update rate = 768 kHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

sixth-order, low-pass, 150-kHz output filter

sixth-order, low-pass, 30-kHz output filter

图6-45. 100-kHz Spectrum vs Frequency

图6-46. Spurious Free Dynamic Range

vs Output Frequency, f_DAC= 768 kHz

-102

-104

-106

-108

-110

-112

-114

-116

-118

-120

-98

-100

-102

-104

-106

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

Output Frequency (kHz)

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

Output Frequency (kHz)

DAC update rate = 768 kHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

sixth-order, low-pass, 30-kHz output filter

图6-47. Total Harmonic Distortion

图6-48. Total Harmonic Distortion + Noise

vs Output Frequency, f_DAC= 768 kHz

-102

-104

-106

-108

-110

-112

-114

-116

-118

-120

-122

-124

-126

-128

-130

-132

-134

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

Output Frequency (kHz)

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

Output Frequency (kHz)

DAC update rate = 768 kHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

sixth-order, low-pass, 30-kHz output filter

图6-49. Second Harmonic Distortion

图6-50. Third Harmonic Distortion

vs Output Frequency, f_DAC= 768 kHz

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

-88

-92

-96

-100

-104

-108

-112

-116

-120

-100

-104

-108

-112

-116

0

20

40

60

80

100

120

140

0

20

40

60

80

100

120

140

Output Frequency (kHz)

DAC update rate = 1 MHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

sixth-order, low-pass, 150-kHz output filter

图6-51. Spurious Free Dynamic Range

图6-52. Total Harmonic Distortion

vs Output Frequency, f_DAC= 1 MHz

-84

-86

-88

-90

-92

-94

-90

-94

-98

-102

-106

-110

-114

-118

-122

-126

0

20

40

60

80

100

120

140

0

20

40

60

80

100

120

140

Output Frequency (kHz)

DAC update rate = 1 MHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

sixth-order, low-pass, 150-kHz output filter

图6-53. Total Harmonic Distortion + Noise

图6-54. Second Harmonic Distortion

vs Output Frequency, f_DAC= 1 MHz

-102

-106

-110

-114

-118

-122

-126

-130

-134

-104

UP_RATE: 00

UP_RATE: 01

-106

-108

-110

-112

-114

-116

-118

0

200

400

600

800

1000

=

0

20

40

60

80

100

120

140

Update Rate (kHz)

Output Frequency (kHz)

DAC output frequency = 20 kHz, V_REFPF= 4.5 V, V_REFNF

DAC update rate = 1 MHz, V_REFPF= 4.5 V, V_REFNF= −4.5 V,

sixth-order, low-pass, 150-kHz output filter

−4.5 V, sixth-order, low-pass, 30-kHz output filter

图6-56. Spurious Free Dynamic Range vs Update Rate

图6-55. Third Harmonic Distortion

vs Output Frequency, f_DAC= 1 MHz

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6.11 Typical Characteristics (continued)

at T_A= 25°C, V_CC= 15 V, V_SS= –15 V, AV_DD= 5 V, IOV_DD= 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as

reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled

(unless otherwise noted)

-116

-118

-120

-122

-124

-126

-128

-130

-99

-100

-101

-102

-103

-104

-105

UP_RATE: 00

UP_RATE: 01

UP_RATE: 00

UP_RATE: 01

0

200

400

600

800

1000

=

0

200

400

600

800

1000

=

Update Rate (kHz)

DAC output frequency = 20 kHz, V_REFPF= 4.5 V, V_REFNF

−4.5 V, sixth-order, low-pass, 30-kHz output filter

图6-57. Total Harmonic Distortion vs Update Rate

图6-58. Total Harmonic Distortion + Noise vs Update Rate

-116

-131

UP_RATE: 00

UP_RATE: 01

UP_RATE: 00

UP_RATE: 01

-118

-120

-122

-124

-126

-128

-130

-132

-133

-134

-135

0

200

400

600

800

1000

=

0

200

400

600

800

1000

=

Update Rate (kHz)

DAC output frequency = 20 kHz, V_REFPF= 4.5 V, V_REFNF

−4.5 V, sixth-order, low-pass, 30-kHz output filter

图6-59. Second Harmonic Distortion vs Update Rate

图6-60. Third Harmonic Distortion vs Update Rate

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7 Detailed Description

7.1 Overview

The 20-bit DAC11001B is a single-channel DAC. The unbuffered DAC output architecture is based on an R2R

ladder that is designed to provide monotonicity and excellent linearity over wide reference and temperature

ranges. This architecture provides a very low-noise (7 nV/√Hz) and fast-settling (1 µs) output. The DAC11001B

also implements a deglitch circuit that enables low, code-independent glitch at the DAC output. The deglitch

circuit is extremely useful for creating ultra-low, harmonic-distortion waveform generation.

The DAC11001B requires external reference voltages on REFPF and REFNF pins. The output of the DAC

ranges from V_REFNFto V_REFPF. See 节6.3 for V_REFPFand V_REFNFvoltage ranges.

The DAC11001B also includes precision matched gain setting pins (ROFS, RCM, and RFB), Use these pins and

an external op amp to scale the DAC output. The DAC11001B incorporates a power-on reset (POR) circuit to

make sure that the DAC output powers up at zero scale, and remains at zero scale until a valid DAC command

is issued. The DAC11001B uses a 4-wire serial interface that operates at clock rates of up to 50 MHz.

7.2 Functional Block Diagram

IOVDD DVDD VCC AVDD

REFPS REFPF

ROFS

RCM

SCLK

SDIN

R

Power On Reset

SYNC

SDO

RFB

OUT

Buffer

DAC

Register

DAC

LDAC

CLR

Register

Power

Down Logic

ALARM

DGND

VSS AGND

REFNS REFNF

7.3 Feature Description

7.3.1 Digital-to-Analog Converter Architecture

The DAC11001B provides 20-bit monotonic outputs using an R2R ladder architecture. The DAC output ranges

between VREFNF and VREFPF based on the 20-bit DAC data, as described in 方程式1:

CODE

2^N

V_OUT= (V_REFPF- V_REFNF)ì

+ V_REFNF

(1)

where

• CODE is the decimal equivalent of the DAC-DATA loaded to the DAC.

• N is the bits of resolution.

• V_REFPF, V_REFNFis the reference voltage (positive and negative).

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7.3.2 External Reference

The DAC11001B requires external references (REFPF and REFNF) to operate. See 节 6.3 for V_REFPFand

V_REFNFvoltage ranges.

The DAC11001B also contains dedicated sense pins, REFPS for REFPF and REFNS for REFNF. The reference

pins are unbuffered; therefore, use a reference driver circuit for these pins. Set the VREFVAL bits (address 02h)

as per a reference span equal to (V_REFPF– V_REFNF). For example, the VREFVAL bits must be set to 0100 for

V

_REFPF= 5 V and V_REFNF= –5 V.

图 7-1 shows an example reference drive circuit for the DAC11001B. 表 7-1 shows the op-amp options for the

reference driver circuit.

V_REFP

+

Voltage

REFPF

Reference

–

C₁

REFPS

ROFS

RCM

DAC11001B

RFB

C₂

REFNS

REFNF

–

+

–

+

–

+

V_OUT

DAC-OUT

V_REFN

图7-1. Reference Drive Circuit

表7-1. Reference Op Amp Options

SELECTION PARAMETERS

Low voltage and current noise

Low offset and drift

OP AMPS

OPA211, OPA827, OPA828

OPA189

7.3.3 Output Buffers

The DAC11001B outputs are unbuffered. Use an external op amp to buffer the DAC output. The DAC output

voltage ranges from V_REFPFto V_REFNF. Two gain-setting resistors are integrated in the DAC11001B. These

resistors are used to scale the DAC output, minimize the bias current mismatch of the external op amp, and

generate a negative reference for the REFNF pin. See 节 8.3.3 for more information. 表 7-2 shows the op amp

options for the output drive circuit.

表7-2. Output Op Amp Options

SELECTION PARAMETERS

OP AMPS

OPA827, OPA828

OPA211, OPA828

OPA189

Low bias current

Low noise

Low offset and drift

Fast settling and low THD

OPA828

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7.3.4 Internal Power-On Reset (POR)

The DAC11001B incorporates two internal POR circuits for the DV_DD, AV_DD, IOV_DD, V_CC, and V_SSsupplies. The

POR signals are ANDed together, so that all supplies must be at the minimum specified values for the device to

not be in a reset condition. These POR circuits initialize internal registers, as well as set the analog outputs to a

known state, all while the device supplies are ramping. All registers are reset to default values. The DAC11001B

powers on with the DAC registers set to zero scale. The DAC output can be powered down by writing 1 to PDN

(bit 4, address 02h). Typically, the POR function can be ignored as long as the device supplies power up and

maintain the specified minimum voltage levels. However, a supply drop or brownout can trigger an internal POR

reset event. 图 7-2 represents the internal POR threshold levels for the DV_DD, AV_DD, IOV_DD, V_CC, and V_SS

supplies.

Supply (V)

Supply Max

Specified supply

voltage range

No power-on reset

Supply Min

Operation Threshold

Undefined

POR Threshold

Power-on reset

0.00

图7-2. Relevant Voltage Levels for the POR Circuit

For the DV_DDsupply, no internal POR occurs for nominal supply operation from 2.7 V (supply minimum) to 5.5 V

(supply maximum). For a DV_DDsupply region between 2.5 V (undefined operation threshold) and 1.6 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a DV_DD

supply less than 1.6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 1.6 V

for approximately 1 ms.

For the AV_DDsupply, no internal POR occurs for nominal supply operation from 4.5 V (supply minimum) to 5.5 V

(supply maximum). For an AV_DDsupply region between 4.1 V (undefined operation threshold) and 3.3 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an AV_DD

supply less than 3.3 V (POR threshold), the internal POR resets as long as the supply voltage is less than 3.3 V

for approximately 1 ms.

For the V_CCsupply, no internal POR occurs for nominal supply operation from 8 V (supply minimum) to 36 V

(supply maximum). For V_CCsupply voltages between 7.5 V (undefined operation threshold) to 6 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a V_CC

supply less than 6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 6 V for

approximately 1 ms.

For the V_SSsupply, no internal POR occurs for nominal supply operation from –3 V (supply minimum) to –18 V

(supply maximum). For V_SSsupply voltages between –2.7 V (undefined operation threshold) to –1.8 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a V_SS

supply greater than –1.8 V (POR threshold), the internal POR resets as long as the supply voltage is greater

than –1.8 V for approximately 1 ms.

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For the IOV_DDsupply, no internal POR occurs for nominal supply operation from 1.8 V (supply minimum) to

5.5 V (supply maximum). For IOV_DDsupply voltages between 1.5 V (undefined operation threshold) and 0.8 V

(POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an

IOV_DDsupply less than 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is less than

0.8 V for approximately 1 ms.

In case the DV_DD, AV_DD, IOV_DD, V_CC, or V_SSsupply drops to a level where the internal POR signal is

indeterminate, power cycle the device followed by a software reset.

7.3.5 Temperature Drift and Calibration

The DAC11001B includes a calibration circuit that significantly reduces the temperature drift on integrated and

differential nonlinearities. By default, this feature is disabled. Enable the temperature calibration feature by

writing 1 to the EN_TMP_CAL bit (address 02h, B23). After the EN_TMP_CAL bit is set, issue a calibration cycle

by writing 1 to RCLTMP (address 04h, B8). At this point, the device enters a calibration cycle. Do not issue any

DAC update command during this period. The device has the capability to indicate the end of calibration using

two methods:

1. Read the status bit ALM (address 05h, B12) using SPI.

2. Issue an alarm on the ALARM pin by setting logic 0. To enable this feature, write 1 to ENALMP bit (address

02h, B12).

After the calibration cycle completes, update the DAC code to observe the impact at the DAC output. If the

environmental temperature changes after calibration, then recalibrate the device.

7.3.6 DAC Output Deglitch Circuit

The DAC11001B includes a deglitch (track-and-hold) circuit at the output. This circuit is enabled by default. The

deglitch circuit minimizes the code-to-code glitch at the DAC output at the expense of the DAC update rate. This

circuit is disabled by writing 1 to DIS_TNH (bit 7, address 06h). Disable this circuit to enable faster update of the

DAC output, but with higher code-to-code glitches.

7.4 Device Functional Modes

7.4.1 Fast-Settling Mode and THD

The DAC11001B R2R ladder and deglitch circuit reduce the harmonic distortion for waveform generation

applications. The fast settling bit (FSET, bit 10, address 02h) is set to 1 by default, so that the DAC is configured

for enhanced THD performance. The FSET bit can be reset to 0 using an SPI write to enable fast-settling mode.

In this mode, the DAC deglitcher circuit can be configured using TNH_MASK (bits 19:18, address 02h). These

bits disable the deglitch circuit for code changes specified in 表 7-7. These bits are only writable when FSET = 0

(fast settling enabled) and DIS_TNH = 0 (deglitch circuit enabled).

7.4.2 DAC Update Rate Mode

The DAC11001B maximum update rate can be configured up to 1 MHz by using UP_RATE (bits 5:4, address

06h). These bits change the hold time of the deglitch circuit. The bits are set to a 0.8-MHz DAC update rate by

default for enhanced THD performance. Changing the maximum update rate of the DAC impacts THD

performance.

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7.5 Programming

The DAC11001B is controlled through a flexible, four-wire serial interface that is compatible with serial interfaces

used on many microcontrollers and DSP controllers. The interface provides read and write access to all registers

of the DAC11001B. Additionally, the interface can be configured to daisy-chain multiple devices for write

operations.

Each serial interface access cycle is exactly 32 bits long, as shown in 图7-3. A frame is initiated by asserting the

SYNC pin low. The frame ends when the SYNC pin is deasserted high. The first bit is read/write bit B31. A write

is performed when this bit is set to 0, and a read is performed when this bit is set to 1. The next seven bits are

address bits B30 to B24. The next 20 bits are data. For all writes, data are clocked on the falling edge of SCLK.

As 图 7-4 shows, for read access and daisy-chain operation, the data are clocked out on the SDO terminal on

the rising edge of SCLK.

SYNC

1

2

3

4

5

6

7

8

9

31 32

SCLK

SDIN

Write Command

D31 D30 D29 D28 D27 D26 D25 D24 D23

‡‡‡

D1 D0

图7-3. Serial Interface Write Bus Cycle: Standalone Mode

SYNC

SCLK

1

2

3

4

5

6

7

8

9

31 32

1

2

3

4

5

6

7

8

9

10

31 32

Read Command

D31 D30 D29 D28 D27 D26 D25 D24 D23

Any Command

SDIN

SDO

‡‡‡

D1 D0

D31 D30 D29 D28 D27 D26 D25 D24 D23

Read Data

D1 D0

Z-state

D22

D31 D30 D29 D28 D27 D26 D25 D24 D23

图7-4. Serial Interface Read Bus Cycle

7.5.1 Daisy-Chain Operation

For systems that contain several DAC11001B devices, the SDO pin is used to daisy-chain the devices together.

The daisy-chain feature is useful in reducing the number of serial interface lines. The first falling edge on the

SYNC pin starts the operation cycle, as shown in 图 7-5. SCLK is continuously applied to the input shift register

while the SYNC pin is kept low. The DAC is updated with the data on rising edge of SYNC pin.

SYNC

1

2

3

4

5

6

7

8

9

31 32 33

63 64 65

95 96 97

127 128

SCLK

SDIN

SDO

Device A Command

D31 D30 D29 D28 D27 D26 D25 D24

D23 œ D0

Device B Command

Device C Command Device D Command

Device A Command Device B Command Device C Command

图7-5. Serial Interface Daisy-Chain Write Cycle

If more than 32 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line.

These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO

output of the first device to the SDI input of the next device in the chain, a multiple-device interface is

constructed. Each device in the system requires 32 clock pulses.

As a result, the total number of clock cycles must be equal to 32 × N, where N is the total number of devices in

the daisy-chain. When the serial transfer to all devices is complete the SYNC signal is taken high. This action

transfers the data from the SPI shift registers to the internal register of each device in the daisy-chain and

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prevents any further data from being clocked into the input shift register. The DAC11001B implements a bit that

enables higher speeds for clocking out data from the SDO pin. Enable this feature by setting FSDO (bit 13,

address 02h) to 1.

7.5.2 CLR Pin Functionality and Software Clear

The CLR pin is an asynchronous input pin to the DAC. When activated, this level-sensitive pin clears the DAC

buffers and DAC latches to the DAC-CLEAR-DATA bits (address 03h). The device exits clear mode on the

SYNC rising edge of the next valid write to the device. If the CLR pin receives a logic 0 during a write sequence

during normal operation, the clear mode is activated and the buffer and DAC registers are immediately cleared.

The DAC registers can also be cleared using the SCLR bit (address 04h, B5); the contents are cleared at the

rising edge of SYNC.

7.5.3 Output Update (Synchronous and Asynchronous)

The DAC11001B offers both a software and hardware simultaneous update and control function. The DAC

double-buffered architecture has been designed so that new data can be entered for the DAC without disturbing

the analog output. Data updates can be performed either in synchronous or in asynchronous mode, depending

on the status of LDAC-MODE bit (address 02h, B14).

7.5.3.1 Synchronous Update

In synchronous mode (LDACMODE = 1), the LDAC pin is used as an active-low signal for simultaneous DAC

updates. Data buffers must be loaded with the desired data before an LDAC low pulse. After an LDAC low pulse,

the DAC is updated with the last contents of the corresponding data buffers. If the content of a data buffer is not

changed, the DAC output remains unchanged after the LDAC pin is pulsed low.

7.5.3.2 Asynchronous Update

In asynchronous mode (LDACMODE = 0), data are updated with the rising edge of the SYNC (when daisy-chain

mode is enabled, DSDO = 0), or at the 32nd falling edge of SCLK (When daisy-chain mode is disabled,

DSDO = 1). For asynchronous updates, the LDAC pin is not required, and must be connected to 0 V

permanently.

7.5.4 Software Reset Mode

The DAC11001B implements a software reset feature. The software reset function uses the SRST bit (address

04h, B6). When this bit is set to 1, the device resets to the default state.

30

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7.6.1 NOP Register (address = 00h) [reset = 0x000000h for bits [23:0]]

图7-6. NOP Register Format

31

30

29

28

27

26

25

24

23

22

21

20

19

18

2

17

16

0

Read/

Write

Address

NOP

W

11

W-00h

15

14

13

12

10

9

8

7

6

5

4

3

1

NOP

W-000h

RESERVED

W-0h

表7-5. NOP Register Field Descriptions

Bit

31

Field

Type

Reset

Description

Read/Write

Address

W

N/A

Write only register. Must be set to 0.

00h

30-24

23-4

3-0

W

N/A

NOP

W

00000h

0h

No operation; write 00000h

These bits are reserved.

RESERVED

W

7.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h for bits [23:0]]

图7-7. DAC-DATA Register Format

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

16

0

Read/

Write

Address

DAC-DATA (20-bit, left justified)

W

11

R/W-00h

15

14

13

12

10

9

8

7

6

5

4

3

2

DAC-DATA (20-bit, left justified)

R/W-000h

RESERVED

W-0h

表7-6. DAC-DATA Register Field Descriptions

Bit

31

Field

Type

Reset

Description

Read/Write

Address

W

N/A

Read when set to 1 or write when set to 0

01h

30-24

23-4

W

N/A

DAC-DATA[19:0]

R/W

00000h

Stores the 20-bit data to be loaded to the DAC in MSB-aligned,

straight-binary format.

3-0

RESERVED

W

0h

These bits are reserved.

32

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7.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]

图7-8. CONFIG1 Register Format

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Read/

Write

Address

EN_

TMP_

CAL

RESERVED

TNH_MASK

RESERVED

W

11

R/W-0h

7

W-0h

R/W-0h

W-0h

15

14

13

12

10

9

8

6

5

4

3

2

1

0

RSVD

LDAC

MODE

FSDO

ENALMP

R/W-0h

DSDO

FSET

VREFVAL

RSVD

PDN

RESERVED

W-0h

R/W-1h R/W-0h

R/W-1h R/W-1h

R/W-2h

W-0h R/W-0h

W-0h

表7-7. CONFIG1 Register Field Descriptions

Bit

31

Field

Type

Reset

N/A

0h

Description

Read/Write

Address

W

Read when set to 1 or write when set to 0

02h

30-24

23

W

EN_TMP_CAL

R/W

Enables and disables the temperature calibration feature

0: Temperature calibration feature disabled (default)

1: Temperature calibration feature enabled

22-20

19-18

RESERVED

TNH_MASK

W

0h

These bits are reserved.

R/W

Mask track and hold (TNH) circuit. This bit is writable only when FSET = 0

[fast-settling mode] and DIS_TNH = 0 [track-and-hold enabled]

00: TNH masked for code jump > 2¹⁴(default)

01: TNH masked for code jump > 2¹⁵

10: TNH masked for code jump > 2¹³

11: TNH masked for code jump > 2¹²

17-15

14

RESERVED

LDACMODE

W

0h

1h

These bits are reserved.

R/W

Synchronous or asynchronous mode select bit

0: DAC output updated on SYNC rising edge

1: DAC updated on LDAC falling edge (default)

13

12

11

FSDO

R/W

0h

1h

2h

Enable Fast SDO

0: Fast SDO disabled (Default)

1: Fast SDO enabled

ENALMP

DSDO

Enable ALARM pin to be pulled low, end of temperature calibration cycle

0: No alarm on the ALARM pin

1: Indicates end of temperature calibration cycle. ALARM pin pulled low.

Enable SDO (for readback and daisy-chain)

1: SDO enabled (default)

0: SDO disabled

10

9-6

FSET

Fast-settling vs enhanced THD mode

0: Fast settling

1: Enhanced THD (default)

VREFVAL

Reference span value bits

0000: Invalid

0001: Invalid

0010: Reference span = 5 V ± 1.25 V (default)

0011: Reference span = 7.5 V ± 1.25 V

0100: Reference span = 10 V ± 1.25 V

0101: Reference span = 12.5 V ± 1.25 V

0110: Reference span = 15 V ± 1.25 V

0111: Reference span = 17.5 V ± 1.25 V

1000: Reference span = 20 V ± 1.25 V

1001: Reference span = 22.5 V ± 1.25 V

1010: Reference span = 25 V ± 1.25 V

1011: Reference span = 27.5 V± 1.25 V

1100: Reference span = 30 V ± 1.25 V

5

4

RESERVED

PDN

W

0h

This bit is reserved.

R/W

Powers down and power up the DAC

0: DAC power up (default)

1: DAC power down

3-0

RESERVED

W

0h

These bits are reserved.

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7.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]

图7-9. DAC-CLEAR-DATA Register Format

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

Read/

Write

Address

DAC-CLEAR-DATA (8 bits, left justified)

W

11

R/W-00h

15

14

13

12

10

9

8

7

6

5

4

3

2

1

RESERVED

W-000h

RESERVED

W-0h

表7-8. DAC-CLEAR-DATA Register Field Descriptions

Bit

31

Field

Type

Reset

Description

Read/Write

Address

W

N/A

Read when set to 1 or write when set to 0

03h

30-24

23-16

W

N/A

DAC-CLEAR-DATA

R/W

00h

Stores the 8-bit data to be loaded to the DAC in left-justified, straight-

binary format. DAC data registers are updated with this value when the

CLR pin is asserted low

15-4

3-0

RESERVED

W

000h

0h

These bits are reserved.

7.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]

图7-10. TRIGGER Register Format

31

30

29

28

27

26

25

24

23

22

21

20

19

3

18

2

17

1

16

0

Read/

Write

Address

RESERVED

W

11

W-00h

15

14

13

12

10

9

8

7

6

5

4

RESERVED

W-00h

RCLTMP RSVD

R/W-0h W-0h

SRST

R/W-0h

SCLR

RSVD

RESERVED

W-0h

R/W-0h

W-0h

表7-9. TRIGGER Register Field Descriptions

Bit

31

Field

Type

Reset

Description

Read/Write

Address

W

N/A

Read when set to 1 or write when set to 0

30-24

23-9

8

W

N/A

04h

RESERVED

RCLTMP

W

0000h

0h

These bits are reserved.

R/W

Trigger temperature recalibration DAC Codes

0: No temperature recalibration (default)

1: DAC codes recalibrated, ALARM pin pulled low (if ENALMP =

1) and ALM bit (address 05) set to 1 when calibration complete.

Subsequent DAC codes use the latest calibrated coefficients.

7

6

RESERVED

SRST

W

0h

This bit is reserved.

R/W

Software reset

0: No software reset (default)

1: Software reset initiated, device in default state

5

SCLR

R/W

0h

Software clear

0: No software clear (default)

1: Software clear initiated, DAC registers in clear mode, DAC

code set by clear select register (address 03h). DAC output

clears on 32nd SCLK falling (DSDO = 1) or SYNC rising edge

(DSDO = 0)

4

RESERVED

W

0h

This bit is reserved.

3-0

These bits are reserved.

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7.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]

图7-11. STATUS Register Format

31

30

29

28

27

26

25

24

23

22

21

20

19

18

2

17

1

16

0

Read/

Write

Address

RESERVED

R

W

11

W-00h

15

14

13

12

10

9

8

7

6

5

4

3

RESERVED

W-0h

ALM

R-0h

RESERVED

W-00h

RESERVED

W-0h

表7-10. STATUS Register Field Descriptions

Bit

Field

Type

Reset

N/A

000h

0

Description

31

30-24

23-13

12

Read/Write

Address

R

Read only register. Must be set to 1.

05h

W

RESERVED

ALM

W

These bits are reserved.

R

Alarm indicator bit, This bit is not masked by ENALMP bit

0: Temperature recalibration in progress

1: DAC codes recalibrated, ALARM pin is pulled low (if

ENALMP = 1). Subsequent DAC codes will use latest calibrated

coefficients. Reading back this register resets ALARM pin to 1

status.

11-4

3-0

RESERVED

W

00h

0h

These bits are reserved.

7.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]

图7-12. CONFIG2 Register Format

31

30

29

28

27

26

25

24

23

22

21

20

19

18

2

17

1

16

0

Read/

Write

Address

RESERVED

W

11

W-00h

15

14

13

12

10

9

8

7

6

5

4

3

RESERVED

W-00h

DIS_TNH RSVD

R/W-0h W-1h

UP_RATE

R/W-0h

RESERVED

W-0h

表7-11. CONFIG2 Register Field Descriptions

Bit

31

Field

Type

Reset

Description

Read/Write

Address

W

N/A

Read when set to 1 or write when set to 0

30-24

23-8

7

W

N/A

06h

RESERVED

DIS_TNH

W

0000h

0h

These bits are reserved.

R/W

Disable track and hold:

0: Track and hold enabled (default)

1: Track and hold disabled

6

RESERVED

UP_RATE

W

1h

0h

This bit is reserved.

5-4

R/W

DAC output max update rate:

00: 0.8 MHz with 28-MHz SCLK, (default)

01: 1.05 MHz with 38.5-MHz SCLK

10: 0.7 MHz with 25.5-MHz SCLK

11: 0.95 MHz with 34.5-MHz SCLK

3-0

RESERVED

W

0h

These bits are reserved.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DAC11001B is targeted for high-precision applications where ultra-high dc accuracy, ultra-low noise, fast

settling, or high total harmonic distortion (THD) are required. The DAC11001B provides 20-bit monotonic

resolution and excellent linearity. The DAC11001B finds application in high-performance source measure unit

(SMU), arbitrary waveform generation (AWG). The DAC11001B is an also excellent choice for closed-loop

control applications such as microelectromechanical system (MEMS) actuators, linear actuators, precision motor

control, lens autofocus control in precision microscopy, lens control in mass spectrometer, beam control in

electron beam lithography, and so on.

8.2 Typical Application

8.2.1 Source Measure Unit (SMU)

A source measure unit (SMU) is a common building block in memory and semiconductor test equipment and

bench-top source measure units. A DAC is used in an SMU to force a desired voltage or a current to a device-

under-test (DUT). 图8-1 provides a simplified circuit diagram of the force-DAC in an SMU.

R_CABLE

1 M

INA188

G_V

–

+

1

2

R₂

R₁

SW

DUT

OPA828

C₁

INA188

V_REFP

+

–

R_CABLE

G_I

1 M

REFPF

REFPS

–

+

R_SENSE

DAC11001B

OPA828

REFNS

REFNF

C₂

–

+

V_REFN

OPA828

图8-1. Source Measure Unit

8.2.1.1 Design Requirements

• Force voltage range: ±10 V

• Force current range: ±20 mA

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8.2.1.2 Detailed Design Procedure

The DAC11001B is an excellent choice for this application to meet the 20-bit resolution requirement. Switch SW

is used to toggle between force-voltage and force-current modes, as shown in 图 8-1. The OPA828 is a high-

precision amplifier that provides a good balance between dc and ac performance, and can supply ±30-mA output

current. The INA188 is a zero-drift instrumentation amplifier with gain selected with an external resistor. The

external resistor is not shown in the drawing for simplicity. The gain resistor is not required for a gain of 1. 方程式

2 shows the calculation of the voltage gain when switch SW is in position 1.

≈

’

÷

R₁

1

A_V

=

x 1+

∆

G_V

R_{2 ◊}

«

(2)

Precision reference sources are available at 5 V or less. Use a ±5-V reference with a 2x gain configuration to get

an output of ±10 V. The DAC output amplifier sets the gain at 2, assuming G_V= 1, as shown in 方程式 3. R₁and

R₂are 1-kΩeach. 方程式3 shows the calculation for the current gain when the switch is in the position 2.

≈

’

÷

R₁

1

A_V

=

x 1+

∆

R_SENSExG_I

R_{2 ◊}

«

(3)

In order to get ±20-mA output current range with R₁= R₂, R_SENSEx G_Imust be 500. Set G_Ito 50 so that R_SENSE

is 10-Ω. For a ±20-mA output current, the voltage drop across R_SENSEis ±200-mV. In case the design requires a

lower voltage headroom, choose a higher value for G_Iand a smaller resistance value for R_SENSE

.

There is no equation to select C₁and C₂. The values of C₁and C₂depend on the stability criteria of the

reference buffers when driving the reference inputs of DAC11001B. The values are obtained through simulation.

For the OPA828, use C₁= C₂= 100 pF. The 1-MΩresistors in the circuit are used for making sure the amplifiers

are not left in an open-loop state.

8.2.1.3 Application Curves

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0

300000

600000

DAC Code

900000

图8-3. DNL at ±10-V Output

图8-2. INL at ±10-V Output

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8.2.2 High-Precision Control Loop

High-precision control loops are used in precision motion-control applications, such as linear actuator control,

servo motor control, galvanometer control, and more. The key requirements for such applications is resolution,

monotonicity, settling time, and code-to-code glitch. 图8-4 provides a simplified circuit of a linear actuator control

circuit, wherein the DAC11001B commands the set point and an analog loop controls the actuator.

Gain/

Attenuation

THS4011

C₁

Sensor

Output

+

–

V_REFP

REFPF

REFPS

–

+

Linear

Actuator

Power

Amplifier

DAC11001B

THS4011

REFNS

REFNF

C₂

THS4011

–

+

V_REFN

图8-4. High-Precision Control Loop

8.2.2.1 Design Requirements

• DNL: ±1 LSB max at 20-bits

• Settling time: < 2 µs

• Code-to-code glltch: < 2 nV-s

8.2.2.2 Detailed Design Procedure

The DAC11001B provides 20-bit monotonic resolution at < ±1 LSB DNL. The device provides < 2‑µs setting time

and < 2‑nV-s code-to-code glitch for major carry transition. The reference and output buffer used for this design

is the THS4011, a high-speed amplifier with a 90-ns settling time. For the best settling response, use C₁and C₂

between 10 pF to 50 pF.

8.2.2.3 Application Curves

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0

300000

600000

DAC Code

900000

图8-6. DNL at ±5-V Output

图8-5. INL at ±5-V Output

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8.2.3 Arbitrary Waveform Generation (AWG)

Arbitrary waveform generation circuits are common in memory and semiconductor test equipment. These circuits

are used to generate reference ac waveforms to test semiconductor devices. The key performance parameters

of such circuits are THD, SNR, and the update rate. 图 8-7 shows the basic building block example of an AWG

circuit using the DAC11001B.

Optional Gain

OPA828

C₁

R₂

R₁

+

–

V_REFP

REFPF

REFPS

–

+

V_OUT

DAC11001B

OPA828

REFNS

REFNF

C₂

–

+

V_REFN

OPA828

图8-7. Arbitrary Waveform Generation

8.2.3.1 Design Requirements

• THD at 1 kHz: > –105 dB

• Update rate: 768 kHz

8.2.3.2 Detailed Design Procedure

The DAC11001B provides a THD of –115 dB at 1 kHz. The device provides update rates of up to 1 MHz, with

marginal degradation in THD at higher frequencies. The OPA828 amplifier provides the best balance between

the voltage and current noise densities, and is therefore an excellent choice to use as reference buffers. The

OPA828 also offers low-distortion for high-THD applications.

8.2.3.3 Application Curves

0

-40

-80

-120

-160

0

50

100

150

200

250

300

350 384

Frequency (kHz)

图8-8. 1-kHz Spectrum vs Frequency

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8.3 System Examples

This section provides details on the digital interface and the embedded resistor configurations.

8.3.1 Interfacing to a Processor

The DAC11001B works with a 4-wire SPI interface. The digital interface of the device to a processor is shown in

图 8-9. The DAC11001B has an LDAC input option for synchronous output update. In ac-signal-generation

applications, the jitter in the LDAC signal contributes to signal-to-noise ratio (SNR). Therefore, the LDAC signal

must be generated from a low-jitter timer in the processor. The CLR and ALARM pins are static signals, and

therefore can be connected to general-purpose input-output (GPIO) pins on the processor. All active-low signals

(SYNC, LDAC, CLR, and ALARM) must be pulled up to IOVDD using 10-kΩ resistors. ALARM is an output pin

from the DAC; therefore, the corresponding GPIO on the processor must be configured as an input. Either poll

the GPIO, or configure the GPIO as an interrupt to detect any failure alarm from the DAC. When using a high

SCLK frequency, use source termination resistors, as shown in 节 8.3.1. Typically, 33-Ω resistors work on

printed circuit boards (PCBs) with a 50-Ωtrace impedance.

IOVDD

R_S

SCLK

MOSI

MISO

CS

SCLK

SDIN

SDO

R_S

Processor

DAC11001B

SYNC

LDAC

CLR

TIMER

GPIO

ALARM

DGND

R_PULLUP

IOVDD

图8-9. Interfacing to a Processor

8.3.2 Interfacing to a Low-Jitter LDAC Source

When the processor is not able to provide a low-jitter source for the LDAC signal, an external low-jitter LDAC

source can be used, as shown in 图 8-10. The processor can take the LDAC signal as an interrupt and trigger

the SPI frame synchronously.

IOVDD

R_S

SCLK

MOSI

MISO

CS

SCLK

SDIN

SDO

R_S

Processor

DAC11001B

SYNC

LDAC

CLR

INT

GPIO

ALARM

R_PULLUP

IOVDD

DGND

R_S

Low-Jitter

LDAC Source

图8-10. Interfacing to an External LDAC Source

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8.3.3 Embedded Resistor Configurations

The DAC11001B provides two embedded resistors with values that are double the value of the output

impedance of the R2R ladder. These resistors can be used in various configurations, as shown in the following

subsections.

8.3.3.1 Minimizing Bias Current Mismatch

The bias current mismatch in the output amplifier can lead to offset error at the output. To minimize mismatch,

the amplifier must have a matching resistor to that of the R2R output impedance on the feedback path. The

feedback resistors are used in parallel for this purpose, as shown in 图 8-11. Some amplifiers may become

unstable with a feedback resistor in the buffer configuration; therefore, a compensation capacitor (C_COMP) might

be needed, as shown. The typical value of this capacitor is in the range of 22 pF to 100 pF, depending on the

amplifier.

ROFS

DAC11001B

2xR_OUT

C_COMP

RCM

2xR_OUT

RFB

–

R_OUT

V_OUT

DAC-OUT

+

图8-11. Minimizing Bias Current Mismatch

8.3.3.2 2x Gain Configuration

The circuit of 图 8-11 can be configured for 2x gain by connecting one of the resistor ends to ground, as shown

in 图8-12.

ROFS

DAC11001B

2xR_OUT

C_COMP

RCM

2xR_OUT

RFB

–

R_OUT

V_OUT

DAC-OUT

+

图8-12. 2x Gain Configuration

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8.3.3.3 Generating Negative Reference

Generating a negative reference is a challenge because of the fact that the circuit needs an inverting amplifier

involving resistors. The resistor mismatch and temperature drift can lead to inaccuracy. The embedded, matched

resistors in DAC11001B can be used as shown in 图 8-13, the inverting amplifier configuration, to generate an

accurate negative reference voltage.

V_REFP

+

Voltage

REFPF

Reference

–

C₁

REFPS

ROFS

RCM

DAC11001B

RFB

C₂

REFNS

REFNF

–

+

–

+

–

+

V_OUT

DAC-OUT

V_REFN

图8-13. Generating Negative Reference

42

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8.4 What to Do and What Not to Do

8.4.1 What to Do

• Follow recommended grounding, decoupling, and layout schemes for achieving best accuracy.

• Use a low-jitter LDAC source for best ac performance.

• Choose the appropriate amplifiers depending on the application requirements as explained in above sections.

8.4.2 What Not to Do

• Do not apply the reference before the DAC power supplies are powered on.

• Do not use the reference source directly with the DAC reference inputs without using buffers. or else the

accuracy drastically degrades.

8.5 Initialization Set Up

The following text shows the pseudocode to get started with the DAC11001B:

//SPI Settings

//Mode: Mode-1 (CPOL: 0, CPHA: 1)

//CS Type: Active Low, Per Packet

//Frame length: 32

//SYNTAX: WRITE <REGISTER (HEX ADDRESS>, <HEX DATA>

//Select VREF, TnH mode (Good THD), LDAC mode and power-up the DAC

WRITE CONFIG (0x02), 0x004C80

//Write zero code to the DAC

WRITE DACDATA (0x01), 0x000000

//Write mid code to the DAC

WRITE DACDATA (0x01), 0x7FFFF0

//Write full code to the DAC

WRITE DACDATA (0x01), 0xFFFFF0

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9 Power Supply Recommendations

To get the best performance out of the DAC11001B, the power supply, grounding, and decoupling are very

important. Use a PCB with a ground-plane reference, which helps in confining the digital return currents. A low

mutual inductance path is created just beneath the high-frequency digital traces causing the return currents to

follow the respective signal traces, thus minimizing crosstalk. On the other hand, dc signals spread over the

ground plane without being confined below the signal trace. Therefore, in precision dc applications, limiting the

common-impedance coupling is very difficult unless the ground planes are physically separated. 图 9-1 shows a

method to divide the grounds so that there is no common-mode current flow between the grounds, while

maintaining the same dc potential across all grounds. This circuit assumes that the REFGND and LOAD-GND

are provided from isolated power sources, therefore, there is no common-mode current flow through the

reference or the load.

Analog

Power

Inputs

+

–

+

–

IOVDD

DGND

Isolated Reference

Power

Isolated Load

Power

AGND

+

–

+

Load

+

–

VREFP

VOUT

–

REFPF

REFPS

REFNS

REFNF

Circuit

REFGND

C₁

C₂

–

+

Signal

Input

LOAD-GND

Reference

Generation

Circuit

DAC11001B

–

+

VREFN

LOAD-GND

DGND

AGND

AGND-OUT

REFGND

Single-Point Short

图9-1. Power and Signal Grounding

When the load circuit is powered from a source referenced to AGND, and the LOAD-GND is shorted to AGND at

the far end, the AGND-OUT must no longer be shorted to AGND locally near the DAC. The local shorting

creates a ground loop, otherwise. The resulting connection that avoids the ground loop is shown in 图9-2.

Analog

Power

Inputs

+

–

+

–

IOVDD

DGND

Isolated Reference

Power

AGND Shared Between

DAC and Load

AGND

+

–

+

Load

+

–

VREFP

VOUT

–

REFPF

REFPS

REFNS

REFNF

Circuit

REFGND

C₁

C₂

–

+

Signal

Input

AGND

Reference

Generation

Circuit

DAC11001B

–

+

VREFN

AGND

DGND

AGND

AGND-OUT

REFGND

LOAD-GND

REFGND

Single-Point Short

图9-2. Grounding Scheme When AGND is Load Ground

When the reference source is powered from a power source with AGND as the ground, there is a possibility of

common-impedance coupling causing a code-dependent shift in the reference voltage. To avoid undesired

coupling, drive REFGND using a buffer that maintains the reference ground potential equals to that of AGND-

OUT, as shown in 图9-3.

44

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Analog

Power

Inputs

+

–

+

–

IOVDD

DGND

AGND Shared Between

DAC and Reference

AGND Shared Between

DAC and Load

AGND

+

–

Load

Circuit

+

–

VREFP

VOUT

REFPF

REFPS

REFNS

REFNF

AGND

C₁

C₂

–

+

Signal

Input

AGND

Reference

Generation

Circuit

DAC11001B

–

+

VREFN

AGND

DGND

AGND

AGND-OUT

LOAD-GND

Kelvin Connection

Close to the Pin

–

Single-Point Short

+

REFGND

图9-3. Connecting the Reference Ground

Channel-to-channel dc crosstalk is a major concern in multichannel applications, such as battery test equipment.

While the DAC11001B is single-channel, the crosstalk problem can appear at a system level when using multiple

DAC11001B devices. The problem becomes severe when the grounds of the loads are shorted together creating

a possible ground loop. In such cases, avoid the local short between AGND and AGND-OUT. Use a single short

between AGND and DGND for all the DACs. If the PCB layout allows for the digital signal and analog power

supplies to be kept separate, DGND and AGND can be combined to a single ground plane. 图 9-4 shows an

example circuit for minimizing dc crosstalk across DAC channels in a system.

Analog

Power

Inputs

+

–

+

–

IOVDD

DGND

AGND

+

–

+

–

Load

Circuit

+

–

VREFP1

VOUT1

REFPF

REFPS

REFNS

REFNF

AGND

C₁

C₂

–

+

Signal

Input

AGND

Reference

Generation

Circuit

DAC11001B

–

+

I_CROSSTALK= 0

VREFN1

AGND

DGND

AGND

AGND-OUT1

LOAD-GND1

Kelvin Connection

Close to the Pin

–

Single-Point Short

+

REFGND1

Single-Point Short

Common to all DACs

AGND Shared

Across DACs,

Analog

Power

Inputs

+

–

+

–

References, And

Loads

IOVDD

DGND

AGND

DGND Shared

DGND

AGND

Across DACs

+

–

+

–

Load

Circuit

+

–

VREFP2

VOUT2

REFPF

REFPS

REFNS

REFNF

AGND

C₃

C₄

–

+

Signal

AGND

Reference

Generation

Circuit

Input

DAC11001B

–

+

I_CROSSTALK= 0

VREFN2

AGND

DGND

AGND

AGND-OUT2

LOAD-GND2

Kelvin Connection

Close to the Pin

–

+

Single-Point Short

REFGND2

图9-4. Minimizing Multichannel DC Crosstalk

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Power-supply bypassing and decoupling is key to keeping power supply noise, switching transients, and

common-mode currents away from the DAC output. There are three main objective of power-supply bypassing:

• Filtering: Filter out noise and ripple from power supplies

• Bypassing: Supply switching or load transient currents locally by avoiding trace inductances

• Decoupling: Stop local transient currents from impacting other circuits

To achieve these objectives, use the following 3-element scheme. Place a decoupling capacitor close to every

power supply pin to provide the local current path for load and circuit switching transients. This capacitor must be

referenced to the respective load ground for best load transient suppression. Use a 0.1-µF to 1-µF, X7R,

multilayer ceramic capacitor (MLCC) for this purpose. For analog power supplies, a 10-Ω series resistor

provides the best decoupling. For filtering the power-supply noise and ripple, 10-µF capacitors work best when

placed at the power entry point of the board. An example decoupling scheme is shown in 图9-5.

10 ꢀ

10 …F

10 ꢀ

10 …F

VSS

VCC

œ

1 …F

+

15V

+

15V

œ

AGND

Ferrite

bead

10 ꢀ

10 …F

AVDD

DVDD

0.1 …F

1 …F

+

5V

œ

AGND

DGND

Ferrite

bead

IOVDD

0.1 …F

10 …F

+

3.3V

œ

DGND

图9-5. Power-Supply Decoupling

9.1 Power-Supply Sequencing

The DAC11001B does not require any power-supply sequence. However, the power supplies to the AVDD pin

must be capable of providing 30-mA of current if V_SSramps before AV_DD. This current is derived from the AVDD

pin, and flows out of the VSS pin. This condition is transient, and the device stops consuming this current when

the power supplies are ramped up. To avoid this condition, make sure to ramp AV_DDbefore V_SS

.

46

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10 Layout

10.1 Layout Guidelines

PCB layout plays a significant role for achieving desired ac and dc performance from the DAC11001B. The

DAC11001B has a pinout that supports easy splitting of the noisy and quiet grounds. The digital signals are

available on two adjacent sides of the device; whereas, the power and analog signals are available separate

sides. 图 10-4 shows an example layout, where the different ground planes have been clearly demarcated. The

figure also shows the best positions for the single-point shorts between the ground planes. For best power-

supply bypassing, place the bypass capacitors close to the respective power pins as shown. Provide unbroken

ground reference planes for the digital signal traces, especially for the SPI and LDAC signals.

10.1.1 PCB Assembly Effects on Precision

The printed-circuit board (PCB) assembly process, including reflow soldering, imparts thermal stresses on the

device which can degrade the precision of the device and must be considered in the development of very-high-

precision systems. Standard reflow guidelines must be followed to achieve the device specified performance.

For more information please see Texas Instruments, MSL Ratings and Reflow Profiles application report.

Baking the PCBs after the assembly process can restore the precision of the device to pre-assembly values. 图

10-1 to 图10-3 show the effect of reflow soldering on the typical distribution of INL of the device.

图 10-1 shows the INL distribution for a set of DAC11001B devices before the PCB assembly process. Exposing

the devices to a JEDEC-standard thermal profile for reflow soldering produces the histogram shown in 图 10-2

on another set of devices. The standard INL deviation increased due to the thermal stress imparted to the device

from the reflow process. However, baking DAC11001B units for 60 minutes at 125°C after the reflow soldering

process produced the distribution given in 图 10-3. The post-reflow bake restored the INL standard deviation to

pre-assembly levels.

10

9

8

7

6

5

4

3

2

1

0

6.5

6

INL Min

INL Max

INL Min

INL Max

5.5

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

-1.00 -0.75 -0.5 -0.25

0

0.25 0.5 0.75

1

-1.00 -0.75 -0.5 -0.25

0

0.25 0.5 0.75

1

INL (LSB)

图10-2. Typical INL Distribution

图10-1. Typical INL Distribution

After Reflow Soldering

Before Reflow Soldering

9

8

7

6

5

4

3

2

1

0

INL Min

INL Max

-1.00 -0.75 -0.5 -0.25

0

0.25 0.5 0.75

1

INL (LSB)

图10-3. Typical INL Distribution Post-Reflow Units Baked at 125°C for 60 Minutes

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10.2 Layout Example

POWER INPUT

VSS

VCC

AVDD1

AVDD2

AGND

PLANE

REFRENCE

INPUTS

IOVDD

AGND and

DGND short

DIGITAL

SIGNALS

AGND-OUT and

AGND short

DAC_OUT

EMBEDDED

RESISTORS

DAC11001B

IOVDD

DGND

PLANE

DVDD

AGND-OUT

PLANE

IOVDD

DIGITAL

SIGNALS

图10-4. Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

BP-DAC11001 Evaluation Module

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, BP-DAC11001EVM user's guide

• Texas Instruments, Impact of Code-to-Code Glitch in Precision Applications application brief

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC11001BPFBR
厂家：	TEXAS INSTRUMENTS
描述：	High-grade, 20-bit, monotonic DAC with ultra-low noise, low glitch and exceptional THD performance \| PFB \| 48 \| -40 to 125
文件：	总53页 (文件大小：2909K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC11001BPFBR [TI]

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