DAC2932PFBR_技术文档

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SBAS279D − AUGUST 2003 − REVISED JULY 2005

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FEATURES

DESCRIPTION

The DAC2932 is

a

dual 12-bit, current-output

D

Dual, 12-Bit, 40MSPS Current Output DAC

digital-to-analog converter (DAC) designed to combine the

features of high dynamic range and very low power

consumption. The DAC2932 converter supports update

rates of up to 40MSPS. In addition, the DAC2932 features

four 12-bit voltage output DACs, which can be used to

perform system control functions.

Four 12-Bit Voltage Output DACs—for

Transmit Control

D

Single +3V Operation

Very Low Power: 29mW

The advanced segmentation architecture of the DAC2932

is optimized to provide a high spurious-free dynamic range

(SFDR).

High SFDR: 75dB at f

= 5MHz

OUT

Low-Current Standby or Full Power-Down

Modes

The DAC2932 has a high impedance (> 200kΩ) differential

current output with a nominal range of 2mA and a

compliance voltage of up to 0.8V. The differential outputs

allow for either a differential or single-ended analog signal

interface. The close matching of the current outputs

ensures superior dynamic performance in the differential

D

Internal Reference

Optional External Reference

Adjustable Full-Scale Range: 0.5mA to 2mA

configuration, which can be implemented with

a

transformer. Using a small geometry CMOS process, the

monolithic DAC2932 is designed to operate within a

single-supply range of 2.7V to 3.3V. Low power

consumption makes it ideal for portable and

battery-operated systems. Further optimization by

lowering the output current can be realized with the

adjustable full-scale option. The full-scale output current

can be adjusted over a span of 0.5mA to 2mA.

APPLICATIONS

D

Transmit Channels

− I and Q

− PC Card Modems: GPRS, CDMA

− Wireless Network Cards (NICs)

For noncontinuous operation of the DAC2932, a full

power-down mode can reduce the power dissipation to as

little as 25μW.

D

Signal Synthesis (DDS)

Portable Medical Instumentation

Arbitrary Waveform Generation (AWG)

The DAC2932 is designed to operate with a single parallel

data port. While it alternates the loading of the input data

into separate input latches for both current output DACs

(I-DACs), the updating of the analog output signal occurs

simultaneously. The DAC2932 integrates a temperature

compensated 1.22V bandgap reference. The DAC2932

also allows for additional flexibility of using an external ref-

erence.

The DAC2932 is available in a TQFP-48 package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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SBAS279D − AUGUST 2003 − REVISED JULY 2005

ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

(1)

DAC2932PFBT

DAC2932PFBR

Tape and Reel, 250

Tape and Reel, 2000

DAC2932

TQFP-48

PFB

−40°C to +85°C

DAC2932

(1)

For the most current specification and package information, refer to our web site at www.ti.com.

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handledwith appropriate precautions. Failure to observe

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

DAC2932

−0.3 to +4

−0.2 to +0.2

−0.7 to +0.7

UNIT

proper handling and installation procedures can cause damage.

+V to AGND

V

A

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

+V to DGND

D

AGND to DGND

V

+V to +V

V

A

D

CLK, PD, STBY, CS to DGND

−0.3 to V + 0.3

V

D

D0−D11 to DGND

−0.3 to V + 0.3

V

D

I

, I

to AGND

−0.5 to V + 0.3

V

OUT OUT

A

REFV to AGNDV

−0.3 to V + 0.3

V

AV

GSET, REF , FSA to AGND

−0.3 to V + 0.3

V

IN

x to AGNDV

A

V

OUT

−0.3 to V + 0.3

V

AV

DIN to DGNDV

−0.3 to V

DV

+ 0.3

V

Junction temperature

Case temperature

+150

°C

+100

Storage temperature range

−40 to +150

FUNCTIONAL BLOCK DIAGRAM

REF_INGSET

FSA1 FSA2

+V_A

AGND

+V_D

DGND

STBY

DAC2932

+1.22V Reference

Clock

Reference Control Amp

CS

PD

I_OUT1

12−Bit

40MSPS

I−DAC1

Data1

CLK1

DAC

Latch 1

CLK

Parallel Data Input,

[D11:D0]

12−Bit Data,

Interleaved

I_OUT2

12−Bit

40MSPS

I−DAC2

Data2

CLK2

DAC

Latch 2

I−DAC Section

V−DAC Section

12

A0

Dx

12−Bit

String−DAC1

V_OUT1

V_OUT2

V_OUT3

V_OUT4

A

Latch

DIN

12−Bit

String−DAC2

A

A1

A2

A3

SCLK

SYNC

12−Bit

String−DAC3

A

12−Bit

String−DAC4

REFV

PDV +V_DVDGNDV +V_AVAGNDV

2

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SBAS279D − AUGUST 2003 − REVISED JULY 2005

ELECTRICAL CHARACTERISTICS: I-DAC

At T = T

MIN

to T

MAX

(typical values are at T = 25°C), +V = +3V, +V = +3V, Update Rate = 40MSPS, I

= 2mA, R = 250Ω, C ≤ 10pF,

A

D

OUTFS

L

GSET = H, and internal reference, unless otherwise noted.

DAC2932

TYP

PARAMETER

Resolution

TEST CONDITIONS

MIN

MAX

+85

UNITS

12

40

Bits

MSPS

°C

Output update rate (f

)

CLOCK

Specified temperature range, operating

(1)(2)

Ambient, T

−40

A

Static Accuracy

Differential nonlinearity (DNL)

Integral nonlinearity (INL)

−3.5

−8

0.5

1.5

+3.5

+8

LSB

(3)

Dynamic Performance

Spurious-free dynamic range (SFDR)

To Nyquist, 0dBFS

f

= 0.2MHz, f

= 20MSPS

= 40MSPS

(4)

68

71

70

72

75

69

57

dBc

OUT

CLOCK

= 0.55MHz, f

CLOCK

= 1MHz, f

= 25MSPS

= 40MSPS

58

CLOCK

= 2.2MHz, f

CLOCK

= 5MHz, f

CLOCK

= 10MHz, f

= 20MHz, f

= 40MSPS

CLOCK

Spurious-free dynamic range within a

window

f

= 2.2MHz, f

= 10MHz, f

= 40MSPS

1MHz span

2MHz span

76

74

dBc

OUT

CLOCK

Total harmonic distortion (THD)

f

= 0.55MHz, f

= 1MHz, f

CLOCK

= 40MSPS

(4)

−70

−69

−70

dBc

OUT

CLOCK

= 25MSPS

= 40MSPS

−58

= 2.2MHz, f

CLOCK

Signal-to-noise and distortion (SINAD)

(4)

f

= 1MHz, f

= 25MSPS

52

61

20

dBc

ns

OUT

CLOCK

(1)

Output settling time

to 0.1%

(1)

Output rise time

10% to 90%

7.7

7.4

ns

(1)

Output fall time

DC Accuracy

(5)(6)

(7)

Full-scale output range

(FSR)

All bits high, I

, I

0.5

−0.5

−2

2

+0.8

+2

mA

V

OUT1 OUT2

Output compliance range , V

Gain error (Full-Scale)

Gain error drift

+0.5

0.5

70

+0.6

0.001

+0.5

+0.03

200

5

CO

%FSR

ppmFSR/°C

%FSR

%FSR/V

kΩ

Gain matching

Offset error

−2.5

+2.5

Power-supply rejection, +V

+3V, 10%, at 25°C

−0.9

−0.12

+0.9

+0.12

A

Power-supply rejection, +V

Output resistance

D

Output capacitance

I

, I

to Ground

pF

OUT OUT

(1)

At output I

Measured at f = 25MSPS and f

Differential, transformer (n = 4:1) coupled output, R = 400Ω.

Differential outputs with a 250Ω load.

, I

, while driving a 250Ω load, transition from 000h to FFFh.

OUT1 OUT2

(2)

(3)

(4)

= 1.0MHz.

CLOCK

OUT

L

V

Nominal full−scale output current is I_OUTFS+ 32 I_REF+ 32 ^REF; with V_REF+ 1.22V (typ) and R

Ensured by design and characterization; not production tested.

Gain error to remain ≤10% FSR over the full compliance range.

Combined power dissipation of I-DAC and V-DAC.

+ 19.6kW (1%)

(5)

SET

R_SET

(6)

(7)

(8)

3

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SBAS279D − AUGUST 2003 − REVISED JULY 2005

ELECTRICAL CHARACTERISTICS: I-DAC (continued)

At T = T

MIN

to T

MAX

(typical values are at T = 25°C), +V = +3V, +V = +3V, Update Rate = 40MSPS, I

= 2mA, R = 250Ω, C ≤ 10pF,

A

D

OUTFS

L

GSET = H, and internal reference, unless otherwise noted.

DAC2932

TYP

PARAMETER

Reference

TEST CONDITIONS

MIN

MAX

UNITS

Voltage, V

Tolerance

+1.14

+1.22

30

+1.26

V

mV

REF

Voltage drift

Output current

−40

10

ppm/°C

μA

Input resistance

1

MΩ

Input compliance range

Small-signal bandwidth

External V

REF

+1.22

0.1

V

MHz

(6)

Digital Inputs

Logic coding

Straight binary

Logic high voltage, V

IH

+2

+3

0

1

V

μA

pF

Logic low voltage, V

Logic high current

Logic low current

Input capacitance

Power Supply

+0.8

IL

1

5

Analog supply voltage, +V , +V

AV

2.7

3

3.3

V

A

Digital supply voltage, +V , +V

D

DV

Analog supply current, I

f

= 25MSPS, digital inputs at 0

= 40MSPS, f = 2.2MHz

OUT

Standby mode

= 25MSPS, digital inputs at 0

4.7

5.4

0.4

2

4.3

0.02

1.3

20

mA

mW

μW

VA

VD

CLOCK

I

Digital supply current, I

f

CLOCK

f

l

I

= 40MSPS, f

OUT

= 2.2MHz

CLOCK

Standby mode, clock off

Standby mode, CS = 0, f = 25MSPS

CLOCK

= 25MSPS, digital inputs at 0

(8)

Power dissipation, PD

f

25

7

CLOCK

PD

f

= 40MSPS, f

= 2.2MHz

OUT

= 25MSPS

29

5.5

25

CLOCK

Standby mode, f

CLOCK

Power-down mode, clock off, digital inputs at 0

Thermal resistance

TQFP-48

θ

JA

θ

JC

97.5

20

°C/W

(1)

At output I

Measured at f = 25MSPS and f

Differential, transformer (n = 4:1) coupled output, R = 400Ω.

Differential outputs with a 250Ω load.

, I

CLOCK

, while driving a 250Ω load, transition from 000h to FFFh.

= 1.0MHz.

OUT1 OUT2

(2)

(3)

(4)

OUT

L

V

Nominal full−scale output current is I_OUTFS+ 32 I_REF+ 32 ^REF; with V_REF+ 1.22V (typ) and R

Ensured by design and characterization; not production tested.

Gain error to remain ≤10% FSR over the full compliance range.

Combined power dissipation of I-DAC and V-DAC.

+ 19.6kW (1%)

(5)

SET

R_SET

(6)

(7)

(8)

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ELECTRICAL CHARACTERISTICS: V-DAC

At T = T

MIN

to T

MAX

(typical values are at T = 25°C), +V = +3V, +V

= +3V, R = 2kΩ to GND, and C = 40pF, unless otherwise noted.

DV L L

A

AV

DAC2932

TYP

MIN

MAX

PARAMETER

TEST CONDITIONS

UNITS

(1)

Static Performance

Resolution

12

8

Bits

LSB

Relative accuracy

Differential nonlinearity, DNL

At 25°C

−16

−1

+16

+1

Tested; monotonic by design

All 0s loaded to DAC register

All 1s loaded to DAC register

0.2

−3

5

LSB

(2)

Zero code error

+0.8

+2

%FSR

μV/°C

ppmFSR/°C

(2)

Full-scale error

−10

Zero code error drift

Full-scale error drift

Output Characteristics

−15

(3)

Reference voltage setting, REFV

Output voltage settling time

0

+V

AV

V

μs

1/4 scale to 3/4 scale change (400h to C00h)

3

5

C

L

= 470pF

μs

Slew rate

1

V/μs

pF

Capacitive load stability

Code change glitch impulse

Digital feedthrough

DC output impedance

Short-circuit current

Power-up time

R

= 2kΩ

470

11

0.5

4

L

1LSB change around major carry

nV-s

Ω

20

8

mA

μs

Coming out of power-down mode

(3)

Logic Inputs

Input current

1

0

μA

V

Input low voltage, V

IL

0.8

Input high voltage, V

2

3

V

IH

Input capacitance

5

pF

(1)

(2)

(3)

Linearity calculated using a reduced code range of 48 to 3976.

Full-scale range (FSR) based on reference REFV = +V = +3.0V.

AV

Ensured by design and characterization; not production tested.

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SBAS279D − AUGUST 2003 − REVISED JULY 2005

TIMING INFORMATION

t_CP

t_CL

t_CH

CLK

Data In

[D11:D0]

−

DAC1 (n 1)

DAC2 (n 1)

DAC1 (n)

t_H1

DAC2 (n)

t_H2

DAC1 (n +1)

DAC2 (n + 1)

t_S1

t_S2

−

(n 2)

(n 1)

(n)

I−DAC OUT1

I−DAC OUT2

t_DO1

−

(n 1)

(n 2)

t_DO2

Figure 1. Timing Diagram of I-DAC

(1,2)

TIMING REQUIREMENTS

: I-DAC

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

t

Clock cycle time (period)

Clock low time

25

ns

μs

CP

CL

10

Clock high time

CH

S1

Data setup time, I-DAC1

Data setup time, I-DAC2

Data hold time, I-DAC1

Data hold time, I-DAC2

Output delay time, I-DAC1

Output delay time, I-DAC2

CS hold time (pulse width)

1

5

1

S2

3.35

H1

H2

(3)

t

+ t

DO1

DO2

S1 CP

t

+(t

)

S2 CP/2

2.49

CS to clock rising or falling edge setup time

0.52

17

STBY rise time to I

OUT

(I-DAC coming out of power-down mode)

PD fall time to I

OUT

22

(1)

(2)

(3)

Based on design simulation and characterization; not production tested.

All input signals are specified with t = t ≤ 2ns (10% to 90% of +V ) and timed from a voltage level of (V + V )/2.

r

f

DV IL IH

Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.

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SBAS279D − AUGUST 2003 − REVISED JULY 2005

t₁

SCLK

SYNC

t₈

t₂

t₃

t₇

t₄

t₆

t₅

DIN

DB15

DB0

Figure 2. Serial Write Operation of V-DAC

: V-DAC

(1,2)

TIMING REQUIREMENTS

PARAMETER

DESCRIPTION

MIN

50

13

22.5

0

TYP

MAX

UNIT

ns

(3)

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

SCLK cycle time

SCLK high time

SCLK low time

ns

SYNC to SCLK rising edge setup time

Data setup time

ns

5

7.5

2.5

ns

Data hold time

1.5

0

ns

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

−6.0

ns

50

ns

PDV fall time to V

OUT

(V-DAC coming out of power-down mode)

8

μs

(1)

(2)

(3)

All input signals are specified with t = t ≤ 2ns (10% to 90% of +V ) and timed from a voltage level of (V + V )/2.

DV IL IH

r

f

Based on design simulation and characterization; not production tested.

Maximum SCLK frequency is 20MHz at +V = +V = +2.7V to 3.3V.

AV DV

V−DAC: SERIAL DATA INPUT FORMAT

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

D3

DB2

DB1

D1

DB0

A0

A1

A2

A3

D11

D10

D9

D8

D7

D6

D5

D4

D2

D0

DAC1 DAC2 DAC3 DAC4 (MSB)

(LSB)

Address Bits

12-Bit Data Word

NOTE: A logic high in the address bit will select the corresponding V-DAC and write the data word into its register. If more than one address bit

is set high, the selected V-DACs are updated with the same data word simultaneously.

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PIN ASSIGNMENTS

48 47 46 45 44 43 42 41 40 39 38 37

D11 (MSB)

D10

D9

1

2

36 NC

(V−DAC Section)

35 +V_AV

34 I_OUT2

33 I_OUT2

3

D8

4

D7

5

32

31

30

29

28

AGND

+V_A

D6

6

DAC2932

D5

7

D4

+V_A

8

D3

9

AGND

D2

10

11

12

27 I_OUT1

26 I_OUT1

25 REF_IN

D1

D0 (LSB)

13 14 15 16 17 18 19 20 21 22 23 24

Terminal Functions

TERMINAL

NAME

D11:D0

DGND

NO.

1:12

13

I/O

DESCRIPTION

I

Parallel data input port for the dual I-DACs; MSB = D11, LSB = D0; interleaved operation.

Digital ground of I-DAC

+V

D

14

Digital supply of I-DAC; 2.7V to 3.3V

CLK

PD

15

I

Clock input of I-DAC

16

Power-down pin; active high; a logic high initiates power-down mode.

Standby pin of I-DAC; active low; a logic low initiates Standby mode with PD = Low.

STBY

17

A logic high configures the I-DAC for normal operation; pin will resume a high state if left open.

CS

18

19

I

Chip select; active low; enables the parallel data port of the I−DACs; if used as chip select in applications

using multiple DAC2932 devices, the parallel port data must be scrambled for proper functionality. Pin will

resume a low state if left open.

GSET

Gain-setting mode. A logic high enables the use of two separate full-scale adjust resistors on pins FSA1

and FSA2. A logic low allows the use of a common full-scale adjust resistor connected to FSA1. The

function of the FSA2 pin is disabled, and any remaining resistor has no effect. The value for the R

resistor remains the same for a given full-scale range, regardless of the selected GSET mode. Pin will

resume a low state if left open.

SET

DGND

AGND

FSA2

FSA1

20

21

22

23

24

Digital ground of I-DAC

Analog ground of I-DAC

I

Full-scale adjust of I-DAC2; connect external gain setting resistor R

Full-scale adjust of I-DAC1; connect external gain setting resistor R

= 19.6kΩ.

SET2

SET1

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TERMINAL

SBAS279D − AUGUST 2003 − REVISED JULY 2005

Terminal Functions (continued)

NAME

NO.

I/O

DESCRIPTION

REF

25

I

External reference voltage input; internal reference voltage output; bypass with 0.1μF to AGND for internal

reference operation.

IN

I

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

O

Complementary current ouput of I-DAC1

Current output of I-DAC1

OUT1

AGND

+V

Analog ground of I-DAC

Analog supply of I-DAC; 2.7V to 3.3V

Analog ground of I-DAC

A

+V

A

AGND

Analog ground of I-DAC

I

O

Current output of I-DAC2

OUT2

Complementary current ouput of I-DAC2

Analog supply of V-DAC; 2.7V to 3.3V

No internal connection

OUT2

+V

AV

NC

V

O

Voltage output of V-DAC1

OUT1

OUT2

OUT3

OUT4

Voltage output of V-DAC2

Voltage output of V-DAC3

Voltage output of V-DAC4

AGNDV

REFV

Analog ground of V-DAC

I

Reference voltage input for V-DACs; typically connected to supply (+V )

AV

+V

DV

Digital supply of V-DAC; 2.7V to 3.3V

PDV

I

Power-down of V-DACs; active high; a logic high initiates the power-down mode

Serial digital input for V−DAC; see timing and application sections for details

Clock input of V-DAC

DIN

SCLK

SYNC

DGNDV

Frame synchronization signal for the serial data at DIN. Refer to timing section for details.

Digital ground of V-DAC.

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TYPICAL CHARACTERISTICS

T

R

= +25°C, +V = +V = +3V, +V = +V

= +3V, I

= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,

A

L

A

AV

D

DV

OUTFS

L

= 2kΩ on V-DAC, and GSET = H unless otherwise noted.

I−DAC, INL

I−DAC, DNL

2.0

1.0

1.6

1.2

0.8

0.4

0

0.8

0.6

0.4

0.2

0

−

0.4

0.8

1.2

1.6

2.0

0.2

0.4

0.6

0.8

1.0

0

500 1000 1500 2000 2500 3000 3500 4000

Codes

0

500 1000 1500 2000 2500 3000 3500 4000

Codes

Figure 3

Figure 4

SFDR vs f_OUTAT 5MSPS

SFDR vs f_OUTAT 10MSPS

80

78

76

74

72

70

68

66

64

62

60

80

75

70

65

60

55

50

0

0.5

1.0

1.5

2.0

2.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

f_OUT(MHz)

Figure 5

Figure 6

SFDR vs f_OUTAT 20MSPS

SFDR vs f_OUTAT 40MSPS

80

75

70

65

60

55

50

80

75

70

65

60

55

50

0

1

2

3

4

5

6

7

8

9

10

0

2

4

6

8

10

12

14

16 18

20

f_OUT(MHz)

Figure 7

Figure 8

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TYPICAL CHARACTERISTICS (continued)

T

R

= +25°C, +V = +V = +3V, +V = +V

= 2kΩ on V-DAC, and GSET = H unless otherwise noted.

= +3V, I

OUTFS

= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,

A

L

A

AV

D

DV

L

SFDR vs TEMPERATURE

80

SFDR vs I_OUTFS AND f_OUTAT 40MSPS, 0dBFS

80

1mA

75

70

2.2MHz, 40MSPS

70

1.5mA

0.5mA

2mA

1MHz, 20MSPS

65

60

55

50

10MHz, 40MSPS

60

55

19.9MHz, 40MSPS

50

−

40 30 20 10

0

10 20 30 40 50 60 70 80 85

0

2

4

6

8

10

12 14 16

18

20

_

Temperature ( C)

f_OUT(MHz)

Figure 9

Figure 10

TOTAL HARMONIC DISTORTION vs

f_CLKAT f_OUT= 2.2MHZ

TOTAL HARMONIC DISTORTION vs TEMPERATURE

f_OUT= 1MHz at 20MSPS

−

60

65

70

75

80

−

50

55

60

65

70

75

80

85

90

5

10

15

20

25

30

35

40

−

40 30 20 10

0

10 20 30 40 50 60 70 80 85

f

_CLK(MSPS)

_

Temperature ( C)

Figure 11

Figure 12

REFERENCE VOLTAGE vs SUPPLY VOLTAGE

REFERENCE VOLTAGE vs TEMPERATURE

1.2201

1.2200

1.2199

1.223

1.222

1.221

1.220

1.219

1.218

1.217

1.216

1.215

2.7

2.8

2.9

3.0

3.1

3.2

3.3

−

20

40

0

20

40

60

80 85

Supply Voltage (V)

_

Temperature ( C)

Figure 13

Figure 14

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TYPICAL CHARACTERISTICS (continued)

T

R

= +25°C, +V = +V = +3V, +V = +V

= 2kΩ on V-DAC, and GSET = H unless otherwise noted.

= +3V, I

OUTFS

= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,

A

L

A

AV

D

DV

L

I_Avs TEMPERATURE

5.60

I_Dvs TEMPERATURE AT f_OUTAND f_CLK

6.5

19.9MHz, 40MSPS

6.0

5.55

5.50

5.45

5.40

5.35

5.30

5.25

5.20

10MHz, 40MSPS

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

2.2MHz, 40MSPS

1MHz, 20MSPS

−

20

40

0

20

40

60

80 85

−

20

40

0

20

40

60

80 85

_

Temperature ( C)

_

Temperature ( C)

Figure 15

Figure 16

I_Avs SUPPLY VOLTAGE

I

_Dvs SUPPLY VOLTAGE AT f_OUTAND f_CLK

5.43

5.42

5.41

5.40

5.39

5.38

5.37

5.36

5.35

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

19.9MHz, 40MSPS

10MHz, 40MSPS

2.2MHz, 40MSPS

1MHz, 20MSPS

2.7

2.8

2.9

3.0

3.1

3.2

3.3

2.7

2.8

2.9

3.0

3.1

3.2

3.3

Supply Voltage (V)

Figure 17

Figure 18

I−DAC2 OUTPUT SPECTRUM

I−DAC1 OUTPUT SPECTRUM

0

f_OUT= 2.2MHz

f_CLK= 40MSPS

f_OUT= 2.2MHz

f_CLK= 40MSPS

−

10

20

30

40

50

60

70

80

90

10

20

30

40

50

60

70

80

90

−

100

0

2

4

6

8

10

12 14

16

18

20

0

2

4

6

8

10

12 14

16

18

20

Frequency (MHz)

Figure 19

Figure 20

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TYPICAL CHARACTERISTICS (continued)

T

R

= +25°C, +V = +V = +3V, +V = +V

AV DV

= +3V, I

OUTFS

= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,

A

L

A

D

L

= 2kΩ on V-DAC, and GSET = H unless otherwise noted.

DUAL−TONE OUTPUT SPECTRUM

FOUR−TONE OUTPUT SPECTRUM

−

10

20

30

40

50

60

70

80

90

−

10

20

30

40

50

60

70

80

90

f₁= 1.2MHz

f₂= 2.2MHz

f₃= 3.2MHz

f₄= 4.2MHz

f_CLK= 40MSPS

f₁= 1.2MHz

f₂= 2.2MHz

f_CLK= 40MSPS

−

100

110

−

100

−

110

0

2

4

6

8

10

12 14

16

18

20

0

2

4

6

8

10

12 14

16 18 20

Frequency (MHz)

Figure 21

Figure 22

I−DAC CHANNEL ISOLATION vs f_OUTAT 40MSPS

V−DAC, INL

−

60

70

80

90

16

12

8

−

Channel 2

Channel 1

−

4

0

−

4

8

−

100

−

110

−

12

16

−

120

−

0

2

4

6

8

10

12 14

16 18

20

0

500 1000 1500 2000 2500 3000 3500 4000

Codes

Frequency (MHz)

Figure 23

Figure 24

V−DAC, DNL

V_OUTvs CODE

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

1.0

0.8

0.6

0.4

0.2

0

−

0.2

0.4

0.6

0.8

1.0

−

0

500 1000 1500 2000 2500 3000 3500 4000

Codes

0

500 1000 1500 2000 2500 3000 3500 4000

Codes

Figure 25

Figure 26

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The segmented architecture results in a significant

reduction of the glitch energy, and improves the dynamic

performance (SFDR) and DNL. The current outputs

maintain a very high output impedance of greater than

200kΩ.

The full-scale output current is determined by the ratio of

the internal reference voltage (approximately +1.2V) and

an external resistor, R_SET. The resulting I_REFis internally

multiplied by a factor of 32 to produce an effective DAC

output current that can range from 0.5mA to 2mA,

APPLICATION INFORMATION

THEORY OF OPERATION

The architecture of the DAC2932 uses the current steering

technique to enable fast switching and a high update rate.

The core element within the monolithic DAC is an array of

segmented current sources that are designed to deliver a

full-scale output current of up to 2mA, as shown in

Figure 27. An internal decoder addresses the differential

current switches each time the DAC is updated and a

corresponding output current is formed by steering all

currents to either output summing node, I_OUTor I_OUT. The

complementary outputs deliver a differential output signal,

which improves the dynamic performance through

reduction of even-order harmonics and common-mode

signals (noise), and doubles the peak-to-peak output

signal swing by a factor of two, compared to single-ended

operation.

depending on the value of R_SET

.

The DAC2932 is split into a digital and an analog portion,

each of which is powered through its own supply pin. The

digital section includes edge-triggered input latches and

the decoder logic, while the analog section comprises the

current source array with its associated switches, and the

reference circuitry.

REF_INGSET

FSA1

FSA2

+V_A

AGND

+V_D

DGND

STBY

CS

DAC2932

+1.22V Reference

Reference Control Amp

PD

I_OUT1

12−Bit

40MSPS

I−DAC1

Data1

CLK1

Clock

DAC

Latch 1

CLK

Parallel Data Input

[D11:D0]

12−Bit Data,

Interleaved

I_OUT2

12−Bit

40MSPS

I−DAC2

Data2

CLK2

DAC

Latch 2

I−DAC Section

V−DAC Section

12

A0

Dx

12−Bit

String−DAC1

V_OUT1

V_OUT2

V_OUT3

V_OUT4

A

Latch

DIN

12−Bit

String−DAC2

A

A1

A2

A3

SCLK

SYNC

12−Bit

String−DAC3

A

12−Bit

String−DAC4

REFV

PDV +V_DVDGNDV +V_AVAGNDV

Figure 27. Block Diagram of the DAC2932

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The two single-ended output voltages can be combined to

find the total differential output swing:

DAC TRANSFER FUNCTION

Each of the I-DACs in the DAC2932 has a complementary

current output, I_OUT1and I_OUT2. The full-scale output

V_OUTDIFF+ V_OUT* V_OUT

current, I_OUTFS

,

is the summation of the two

(7)

(2 Code * 4095)

complementary output currents:

+

I_OUTFS R_LOAD

4096

I_OUTFS+ I_OUT) I_OUT

The individual output currents depend on the DAC code

and can be expressed as:

(1)

POWER-DOWN MODES

The DAC2932 has several modes of operation. Besides

normal operation, the I-DAC section features a Standby

mode and a full power-down mode, while the V-DAC

section has one power-down mode. All modes are

controlled by appropriate logic levels on the assigned pins

of the DAC2932. Table 1 lists all pins and possible modes.

The pins have internal pull-ups or pull-downs; if left open,

all pins will resume logic levels that place the I-DAC and

V-DAC in a normal operating mode (fully functional).

I_OUT+ I_OUTFS (Codeń4096)

(2)

I_OUT+ I_OUTFS (4095 * Code)ń4096

(3)

where Code is the decimal representation of the DAC data

input word (0 to 4095).

Additionally, I_OUTFSis a function of the reference current

I

_REF, which is determined by the reference voltage and the

external setting resistor, R_SET

.

When in Standby mode the analog functions of the I-DAC

section are powered down. The internal logic is still active

and will consume some power if the clock remains applied.

To further reduce the power in Standby mode the CS pin

may be pulled high, which disables the internal logic from

being clocked, even with the clock signal applied.

V_REF

R_SET

(4)

I_OUTFS+ 32 I_REF+ 32

In most cases, the complementary outputs will drive

resistive loads or a terminated transformer. A signal

voltage will develop at each output according to:

If CS remains low during the Standby mode and a running

clock remains applied, any new data on the parallel data

port will be latched into the DAC. The analog output,

however, will not be updated as long as the I-DACs remain

in Standby mode.

V_OUT+ I_OUT R_LOAD

(5)

(6)

The value of the load resistance is limited by the output

compliance specification of the DAC2932. To maintain

optimum linearity performance, the compliance voltage at

I

_OUTand I_OUTshould be limited to +0.5V or less.

Table 1. Power-Down Modes

PD (16) STBY(17) CS (18) PDV (44)

DAC

MODE

DAC OUTPUTS

0

1

0

1

0

1

X

I-DAC enabled

I-DAC disabled

I-DAC enabled

I-DAC disabled

Standby; data can still be written into the DACs

with running clock applied

High-Z

Standby; writing into DAC disabled—clock input

disabled by CS

High-Z

Normal operation (return from Standby)

Last state prior to

Standby

Data input and clock input disabled; use when

multiple devices on one bus

Last data held

1

0

X

0

1

I-DAC disabled

V-DAC enabled

Full power-down; STBY and CS have no effect

V-DAC normal operation

High-Z

X

V-DAC disabled V-DAC in power-down mode; independent

operation of any I-DAC power-down

configuration

All outputs; High-Z

NOTE: X = don’t care.

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a high condition, ignoring the CLK edges and thus not

latching the bus data. In order to enable data latching, the

CS pin must be returned to a low state. The change of state

in CS is latched into the clock interface on the first rising

CLK edge; this enables the internal clock which causes the

data in channel 2 to be latched on the first falling edge of

CLK. The next rising edge of CLK causes the DAC to

output the old data from channel 1 and the new data just

latched into channel 2 as well as to latch the new data into

channel 1.

CHIP SELECT OPERATION

The I−DAC clock is controlled by PD and CS through a

digital clock interface that generates an internal clock

which controls the data latches. Under normal operation

PD and CS are kept low and the internal clock is just a

delayed version of the clock signal present at the CLK pin.

The data for channel 1 and channel 2 are latched by the

rising and falling edges of CLK, respectively. The rising

edge of CLK also causes the DAC to output the previously

latched data pair.

The operation previously described causes problems in

those situations that have two or more DAC2932 devices

sharing the same data bus with each DAC2932 reading

every nth data pair. The (channel1, channel2) data pairs

appearing at the DAC output correspond to (channel1 from

the previous read cycle, channel2 data from the current

read cycle) pairs. In order for the data bus pairs to be

output correctly it is necessary to scramble the (channel1,

channel2) data pairs so that the bus data corresponds to

. . ., channel1, data for other DACs, channel2, . . . for each

DAC2932.

The CS pin can be used to synchronize the latching of data

from a single data bus connected to multiple DAC2932

devices, however in order for this operation to work

correctly the data pairs on the bus have to be scrambled

so that they are arranged correctly at the DAC outputs. The

reason for this is explained in the following:

Figure 28 shows a timing diagram of the CS operation.

When the CS pin is pulled high, the data in the parallel

input port is not latched. The high condition on the CS pin

is latched into the clock interface on the first rising edge of

CLK following the CS edge; this holds the internal clock in

CLK

CS

Data In

1_0 2_0

1_1

2_1

1_2

2_2 1_3

1_0

2_3

2_1

1_4

2_4

1_5

1_2

[D11:D0]

2_3

I−DAC OUT

Figure 28. Timing Diagram of the CS Pin

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0.5mA may be considered for applications that require low

power consumption, but can tolerate a slightly reduced

performance level.

ANALOG OUTPUTS

The DAC2932 provides two sets of complementary

current outputs, I_OUTand I_OUT. The simplified circuit of the

analog output stage representing the differential topology

is shown in Figure 29. The output impedance of I_OUTand

The current-output DACs of the DAC2932 have a straight

offset binary coding format. With all bits high, the full-scale

output current (for example, 2mA) will be sourced at pins

I

_OUTresults from the parallel combination of the differential

I

_OUT1and I_OUT2, as shown in Table 2.

switches, along with the current sources and associated

parasitic capacitances.

Table 2. Input Coding vs Analog Output Current

+V_A

INPUT CODE

(D11−D0)

I

OUT

(mA)

OUT

DAC2932

(mA)

1111 1111 1111

1000 0000 0000

0000 0000 0000

2

1

0

1

2

OUTPUT CONFIGURATIONS

As mentioned previously, utilizing the differential outputs

of the converter yields the best dynamic performance.

Such a differential output circuit may consist of an RF

transformer or a differential amplifier configuration. The

transformer configuration is ideal for most applications

with ac coupling, while op amps are suitable for a

dc-coupled configuration.

I_OUT

R_L

I_OUT

R_L

Figure 29. Equivalent Analog Output

The signal voltage swing that develops at the two outputs,

I_OUTand I_OUT, is limited by a negative and positive

compliance. The negative limit of –0.5V is given by the

breakdown voltage of the CMOS process, and exceeding

it will compromise the reliability of the DAC2932, or even

cause permanent damage. With the full-scale output set to

2mA, the positive compliance equals 0.8V, operating with

an analog supply of +V_A= 3V. To avoid degradation of the

distortion performance and integral linearity, care must be

taken so that the configuration of the DAC2932 does not

exceed the compliance range.

The single-ended configuration may be considered for ap-

plications requiring a unipolar output voltage. Connecting a

resistor from either one of the outputs to ground converts the

output current into a ground-referenced voltage signal. To im-

prove on the dc linearity by maintaining a virtual ground, an

I-to-V or op-amp configuration may be considered.

DIFFERENTIAL WITH TRANSFORMER

Using an RF transformer provides a convenient way of

converting the differential output signal into a single-ended

signal while achieving excellent dynamic performance

(see Figure 3). The appropriate transformer should be

carefully selected based on the output frequency spectrum

and impedance requirements. The differential transformer

configuration has the benefit of significantly reducing

common-mode signals, thus improving the dynamic

Best distortion performance is typically achieved with the

maximum full-scale output signal limited to approximately

0.5V_PP. This is the case for a 250Ω load and a 2mA

full-scale output current. A variety of loads can be adapted

to the output of the DAC2932 by selecting a suitable

transformer while maintaining optimum voltage levels at

I_OUTand I_OUT. Furthermore, using the differential output

configuration in combination with a transformer is

performance over

a

wide range of frequencies.

Furthermore, by selecting a suitable impedance ratio

(winding ratio), the transformer can be used to provide

optimum impedance matching while controlling the

compliance voltage for the converter outputs. The model

shown, ADT16-6T (by Mini-Circuits), has a 16:1 ratio and

may be used to interface the DAC2932 to a 50Ω load. This

results in a 200Ω load for each of the outputs, I_OUTand

I_OUT. The output signals are ac coupled and inherently

isolated by the transformer.

instrumental

in

achieving

excellent

distortion

performance. Common-mode errors, such as even-order

harmonics or noise, can be substantially reduced. This is

particularly the case with high output frequencies.

For those applications requiring the optimum distortion

and noise performance, it is recommended to select a

full-scale output of 2mA. A lower full-scale range down to

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As shown in Figure 30, the transformer center tap is

connected to ground. This forces the voltage swing on

I_OUTand I_OUTto be centered at 0V. In this case the two

resistors, R_L, may be replaced with one, R_DIFF, or omitted

altogether. Alternatively, if the center tap is not connected,

the signal swing will be centered at R_L× I_OUTFS/2.

However, in this case, the two resistors (R_L) must be used

to enable the necessary dc-current flow for both outputs.

This configuration typically delivers a lower level of ac

performance than the previously discussed transformer

solution because the amplifier introduces another source

of distortion. Suitable amplifiers should be selected based

on their slew-rate, harmonic distortion, and output swing

capabilities. A high-speed amplifier like the OPA690 may

be considered. The ac performance of this circuit can be

improved by adding a small capacitor (C_DIFF) between the

outputs I_OUTand I_OUT, as shown in Figure 31. This will

introduce a real pole to create a low-pass filter in order to

slew-limit the fast output signal steps of the DAC, which

otherwise could drive the amplifier into slew-limitations or

into an overload condition; both would cause excessive

distortion. The difference amplifier can easily be modified

to add a level shift for applications requiring the

single-ended output voltage to be unipolar (that is, swing

between 0V and +2V).

16:1

I_OUT

R_L

Ω

400

DAC2932

R_DIFF

R_S

I_OUT

R_L

Ω

400

DUAL TRANSIMPEDANCE OUTPUT

CONFIGURATION

Figure 30. Differential Output Configuration

Using an RF Transformer

The circuit example of Figure 32 shows the signal output

currents connected into the summing junctions of the

OPA2690 dual voltage-feedback op amp, which is set up as

a transimpedance stage or I-to-V converter. With this circuit,

the DAC output will be kept at a virtual ground, minimizing the

effects of output impedance variations, which results in the

best dc linearity (INL). As mentioned previously, care should

be taken not to drive the amplifier into slew-rate limitations

and produce unwanted distortion.

DIFFERENTIAL CONFIGURATION USING AN OP AMP

If the application requires a dc−coupled output, a difference

amplifier may be considered, as shown in Figure 31. Four

external resistors are needed to configure the OPA690

voltage-feedback op amp as a difference amplifier

performing the differential to single-ended conversion. Under

the configuration shown, the DAC2932 generates a

differential output signal of 0.5V_PPat the load resistors, R_L.

+5V

Ω

50

R₂

1/2

−

•

V_OUT= I_OUTR_F1

Ω

499

OPA2690

R₁

Ω

249

R_F1

C_F1

DAC2932

I_OUT

V_OUT

DAC2932

OPA690

I_OUT

C_D1

R₃

C_OPT

Ω

249

−

5V +5V

R_F2

C_F2

R_L

R₄

Ω

499

Ω

249

Ω

249

C_D2

I_OUT

1/2

Figure 31. Difference Amplifier Provides

−

•

V_OUT= I_OUTR_F2

OPA2690

Differential-to-Single-Ended Conversion and

DC-Coupling

Ω

50

The OPA690 is configured for a gain of two. Therefore,

operating the DAC2932 with a 2mA full-scale output

produces a voltage output of 1V. This requires the

amplifier to operate from a dual power supply ( 5V). The

tolerance of the resistors typically sets the limit for the

achievable common-mode rejection. An improvement can

be obtained by fine tuning resistor R₄.

−

5V

Figure 32. The OPA2690 Dual, Voltage-Feedback

Amplifier Forms a Transimpedance Amplifier

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The DC gain for this circuit is equal to feedback resistor R_F.

At high frequencies, the DAC output impedance (C_D1, C_D2

)

produces a zero in the noise gain for the OPA2690 that can

cause peaking in the closed-loop frequency response. C_Fis

added across R_Fto compensate for this noise gain peaking.

To achieve a flat transimpedance frequency response, the

pole in each feedback network should be set to:

I_OUTFS= 2mA

I_OUT

V_OUT= 0V to +0.5V

DAC2932

Ω

250

I_OUT

Ω

250

Ǹ

GBP

4pR_FC_F

1

(8)

+

2pR_FC_F

where GBP = gain bandwidth product of the op amp, which

gives a corner frequency f_−3dBof approximately:

Figure 33. Differential Output Configuration

Using an RF Transformer

Ǹ

GBP

2pR_FC_D

f

+

*3dB

(9)

Different load resistor values may be selected, as long as

the output compliance range is not exceeded. Additionally,

the output current (I_OUTFS) and the load resistor can be

mutually adjusted to provide the desired output signal

swing and performance.

The full-scale output voltage is simply defined by the

product of I_OUTFS• R_F, and has a negative unipolar

excursion. To improve on the ac performance of this circuit,

adjustment of R_Fand/or I_OUTFSshould be considered.

Further extensions of this application example may

include adding a differential filter at the OPA2690 output

followed by a transformer, in order to convert to a

single-ended signal.

INTERFACING ANALOG QUADRATURE

MODULATORS

One of the main applications for the dual-channel DAC is

baseband I- and Q-channel transmission for digital

communications. In this application, the DAC is followed

by an analog quadrature modulator, modulating an IF

carrier with the baseband data, as shown in Figure 34.

Often, the input stages of these quadrate modulators

consist of npn-type transistors that require a dc bias (base)

voltage of > 0.8V.

SINGLE-ENDED CONFIGURATION

Using a single load resistor connected to one of the DAC

outputs, a simple current-to-voltage conversion can be

accomplished. The circuit in Figure 33 shows a 250Ω

resistor connected to I_OUT. Therefore, with a nominal

output current of 2mA, the DAC produces a total signal

swing of 0V to 0.5V.

V_OUT~ 0V_Pto 0.5V_P

V_IN~ 0.6V_Pto 1.8V_P

I_IN

I_REF

I_IN

DAC2932

I_OUT

1

I_REF

I

_OUT1

Signal

Conditioning

∑

RF

Q_IN

I_OUT

2

Q_REF

I_OUT

Quadrature Modulator

Figure 34. Generic Interface to a Quadrature Modulator. Signal conditioning (level shifting) may be

required to ensure correct dc common-mode levels at the input of the quadrature modulator.

19

ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ

www.ti.com

SBAS279D − AUGUST 2003 − REVISED JULY 2005

Figure 35 shows an example of a dc-coupled interface

with dc level-shifting, using a precision resistor network.

An ac-coupled interface, as shown in Figure 36, has the

advantage in that the common-mode levels at the input of

the modulator can be set independently of those at the

output of the DAC. Furthermore, no voltage loss occurs in

this setup.

The external resistor R_SETconnects to the FSA pin

(full-scale adjust) as shown in Figure 37. The reference

control amplifier operates as a V-to-I converter producing

a reference current, I_REF, which is determined by the ratio

of V_REFand R_SET,as shown in Equation 10. The full-scale

output current, I_OUTFS, results from multiplying I_REFby a

fixed factor of 32.

V_DC

+3V

R₃

+V_A

DAC2932

V_OUT

1

V_REF

R_SET

I_REF

=

FSA

Ref

Control

Amp

Current

Sources

R₄

I_OUT

1

REF_IN

DAC2932

R_SET

I_OUT

1

Ω

19.6k

μ

0.1 F

I_OUT

1

I

_OUT1

+1.22V Ref.

R₅

Figure 35. DC-Coupled Interface to a Quadrature

Modulator Applying Level Shifting

Figure 37. Internal Reference Configuration

Using the internal reference, a 19.6kΩ resistor value

results in a full-scale output of approximately 2mA.

Resistors with a tolerance of 1% or better should be

considered. Selecting higher values, the output current

can be adjusted from 2mA down to 0.5mA. Operating the

DAC2932 at lower than 2mA output currents may be

desirable for reasons of reducing the total power

consumption or observing the output compliance voltage

limitations for a given load condition.

V_DC

R₁

I_OUT1

DAC2932

I_OUT

μ

0.01 F

1

V_OUT

1

V_OUT

I_OUT

1

μ

0.01 F

It is recommended to bypass the REF_INpin with a ceramic

chip capacitor of 0.1μF or more. The control amplifier is

internally compensated, and its small signal bandwidth is

approximately 0.1MHz.

I_OUT1

R_LOAD

R₂

Ω

250

GAIN SETTING OPTIONS

Figure 36. AC-Coupled Interface to a Quadrature

Modulator Applying Level Shifting

The full-scale output current on the DAC2932 can be set

two ways: either for each of the two DAC channels

independently or for both channels simultaneously. For the

independent gain set mode, GSET (pin 19) must be high

(that is, connected to +V_A). In this mode, two external

resistors are required—one R_SETconnected to the FSA1

pin (pin 24) and the other to the FSA2 pin (pin 23). In this

configuration, the user has the flexibility to set and adjust

the full-scale output current for each DAC independently,

allowing for the compensation of possible gain

mismatches elsewhere within the transmit signal path.

INTERNAL REFERENCE OPERATION

The DAC2932 has an on-chip reference circuit that

comprises a 1.22V bandgap reference and two control

amplifiers, one for each DAC. The full-scale output current,

_OUTFS, of the DAC2932 is determined by the reference

voltage, V_REF, and the value of resistor R_SET. I_OUTFScan

I

be calculated by:

V_REF

R_SET

(10)

I_OUTFS+ 32 I_REF+ 32

20

ꢀ ꢒꢕ ꢆꢙ ꢚꢆ

www.ti.com

SBAS279D − AUGUST 2003 − REVISED JULY 2005

Alternatively, bringing GSET low (that is, connected to

AGND), switches the DAC2932 into the simultaneous gain

set mode. Now the full-scale output current of both DAC

channels is determined by only one external R_SETresistor

connected to the FSA1 pin. The resistor at the FSA2 pin

may be removed; however, this is not required since this

pin is not functional in this mode and the resistor has no

effect on the gain equation. The formula for deriving the

correct R_SETremains unchanged. For example,

V−DAC

The architecture consists of a resistor string DAC followed

by an output buffer amplifier. Figure 39 shows a block

diagram of the DAC architecture.

REFV

(+V_DV

)

R

_SET= 19.6kΩ will result in a 2mA output for both DACs.

REF (+)

Resistor

String

The DAC2932 is specified with GSET being high and

operating in inpendent gain mode. It should be noted that

when using the simultaneous gain mode, the gain error

and gain matching error will increase.

V_OUT

DAC Register

−

REF( )

Output

Amplifier

GND

EXTERNAL REFERENCE OPERATION

Figure 39. V-DAC Architecture

The internal reference can be disabled by simply applying

an external reference voltage into the REF_INpin, which in

this case functions as an input, as shown in Figure 38. The

use of an external reference may be considered for

applications that require higher accuracy and drift

performance.

The input coding to the V-DAC is straight binary, so the

ideal output voltage is given by:

D

4096

V_OUT+ REFV

(11)

where D = decimal equivalent of the binary code that is

loaded to the DAC register; it can range from 0 to 4095.

+3V

SERIAL INTERFACE

+V_A

DAC2932

The V−DACs have a three-wire serial interface (SYNC,

SCLK, and DIN), which is compatible with SPI, QSPI, and

Microwire interface standards as well as most Digital

Signal Processors (DSPs).

V_REF

R_SET

I_REF

=

FSA

Ref

Control

Amp

Current

Sources

REF_IN

External

Reference

The write sequence begins by bringing the SYNC line low.

Data from the DIN line is clocked into the 16-bit shift

register on the falling edge of SCLK. The serial clock

frequency can be as high as 20MHz, making the V-DACs

compatible with high-speed DSPs. On the 16th falling

edge of the serial clock, the last data bit is clocked in and

the programmed function is executed (that is, a change in

DAC register contents and/or a change in the mode of

operation).

R_SET

+1.22V Ref.

At this point, the SYNC line may be kept low or brought

high. In either case, it must be brought high for a minimum

of 50ns before the next write sequence so that a falling

edge of SYNC can initiate the next write sequence. Since

the SYNC buffer draws more current when the SYNC

signal is high than it does when it is low, SYNC should be

idled low between write sequences for lowest power

operation of the part. As mentioned above, however, it

must be brought high again just before the next write

sequence.

Figure 38. External Reference Configuration

While a 0.1μF capacitor is recommended for use with the

internal reference, it is optional for the external reference

operation. The reference input, REF_IN, has a high input

impedance and can easily be driven by various sources.

21

ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ

www.ti.com

SBAS279D − AUGUST 2003 − REVISED JULY 2005

each supply pin are adequate to provide a low impedance

decoupling path. Keep in mind that their effectiveness

largely depends on the proximity to the individual supply

and ground pins. Therefore, they should be located as

close as physically possible to those device leads.

Whenever possible, the capacitors should be located

immediately under each pair of supply/ground pins on the

reverse side of the PCB. This layout approach minimizes

the parasitic inductance of component leads and PCB

runs.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide. The first four bits are

the address bits to the four V-DACs. The next 12 bits are

the data bits. These are transferred to the DAC register on

the 16th falling edge of the clock (SCLK).

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for

at least 16 falling edges of SCLK and the DAC is updated

on the 16th falling edge. However, if SYNC is brought high

before the 16th falling edge, this acts as an interrupt to the

write sequence. The shift register is reset and the write

sequence is seen as invalid. Neither an update of the DAC

register contents nor a change in the operating mode

occurs, as shown in Figure 40.

Further supply decoupling with surface-mount tantalum

capacitors (1μF to 4.7μF) can be added as needed in

proximity of the converter.

Low noise is required for all supply and ground

connections to the DAC2932. It is recommended to use a

multilayer PCB with separate power and ground planes.

Mixed signal designs require particular attention to the

routing of the different supply currents and signal traces.

Generally, analog supply and ground planes should only

extend into analog signal areas, such as the DAC output

signal and the reference signal. Digital supply and ground

planes must be confined to areas covering digital circuitry,

including the digital input lines connecting to the converter,

as well as the clock signal. The analog and digital ground

planes should be joined together at one point underneath

the DAC. This can be realized with a short track of

approximately 1/8” (3mm).

POWER-ON RESET

The V-DACs contain a power-on reset circuit that controls

the output voltage during power-up. On power-up, the

DAC register is filled with zeros and the output voltage is

0V; it remains there until a valid write sequence is made to

the DAC. This is useful in applications where it is important

to know the state of the output of the DAC while it is in the

process of powering up.

GROUNDING, DECOUPLING, AND LAYOUT

INFORMATION

The power to the DAC2932 should be provided through

the use of wide PCB runs or planes. Wide runs present a

lower trace impedance, further optimizing the supply

decoupling. The analog and digital supplies for the

converter should only be connected together at the supply

connector of the PCB. In the case of only one supply

voltage being available to power the DAC, ferrite beads

along with bypass capacitors can be used to create an LC

filter. This will generate a low-noise analog supply voltage

that can then be connected to the +V_Asupply pin of the

DAC2932.

Proper grounding and bypassing, short lead length, and

the use of ground planes are particularly important for

high-frequency designs. Multilayer printed circuit boards

(PCBs) are recommended for best performance since they

offer distinct advantages such as minimization of ground

impedance, separation of signal layers by ground layers,

etc.

The DAC2932 uses separate pins for its analog and digital

supply and ground connections. The placement of the

decoupling capacitor should be such that the analog

supply (+V_A) is bypassed to the analog ground (AGND),

and the digital supply bypassed to the digital ground

(DGND). In most cases, 0.1μF ceramic chip capacitors at

While designing the layout, it is important to keep the analog

signal traces separated from any digital line, in order to

prevent noise coupling onto the analog signal path.

CLK

SYNC

DIN

DB15

DB0

DB15

DB0

Invalid Write Sequence:

SYNC high before 16th falling edge

Valid Write Sequence:

Output updates on the 16th falling edge

Figure 40. SYNC Interrupt Facility

22

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www.ti.com

SBAS279D − AUGUST 2003 − REVISED JULY 2005

Revision History

DATE

REV

PAGE

SECTION

DESCRIPTION

Changed tS1, tS2, tH1, tH2 min values, CS hold time (pulse width) min value,

and CS to clock rising or falling edge setup time typ value.

6

Timing Requirements

8

Pin Assignments

Changed pin names for pins 1 − 12

Terminal Functions

Power−Down Modes

Chip Select Operation

Changed CS description.

JUL 05

D

*

15

16

In Table 1, changed column 1 row 7 from X to 0.

Added Chip Select Operation section with figure

Differential With

Transformer

17

—

Changed ratio and load in first paragraph. Changed ratio and load in Figure 30.

Original version

AUG 03

—

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

23

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC2932PFBR

DAC2932PFBT

TQFP

PFB

48

2000

250

330.0

177.8

16.8

16.4

9.6

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC2932PFBR

DAC2932PFBT

TQFP

PFB

48

2000

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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型号：	DAC2932PFBR
厂家：	TEXAS INSTRUMENTS
描述：	Dual, 12-Bit, 40MSPS Digital-to-analog Converter 双通道， 12位， 40MSPS数位类比转换器转换器数模转换器
文件：	总29页 (文件大小：829K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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