DAC3154IRGCR [TI]
具有输入 FIFO 和拉电流的双通道、10 位、500MSPS 数模转换器 (DAC) | RGC | 64 | -40 to 85;
| 型号： | DAC3154IRGCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有输入 FIFO 和拉电流的双通道、10 位、500MSPS 数模转换器 (DAC) | RGC | 64 | -40 to 85 先进先出芯片 转换器 数模转换器 |
| 文件： | 总45页 (文件大小：1417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
双路 12/10 位 500 每秒百万次采样 (MSPS) 数模转换器
查询样品: DAC3154 , DAC3164
1
特性
应用范围
2
•
双通道
分辨率
•
•
•
•
•
多载波、多模式蜂窝基础设施基站
•
雷达
–
–
DAC3154：10 位
DAC3164：12 位
信号智能
软件定义无线电
测试和测量仪器
•
•
最大采样率：500MSPS
与 DAC3174 和 DAC3151/DAC3161/DAC3171 引
脚兼容的系列
说明
DAC3154/DAC3164 是双通道 10/12 位，引脚兼容
500MSPS 数模转换器 (DAC) 系列。
•
输入接口：
–
–
12/10 位宽低压差分信令 (LVDS) 输入
内部先进先出 (FIFO)
DAC3154/DAC3164 使用一个带有输入 FIFO 的 10/12
位宽 LVDS 数字总线。 为了实现精确的信号同
步，FIFO 输入和输出指针可在多个器件上同步。 DAC
输出是电流源型输出，并被端接至依从范围为 -0.5V 至
1V 的接地 (GND)。 DAC3154/DAC3164 与双通
道，14 位，500MSPS 数模转换器 DAC3174，以及单
通道，14/12-10 位，数模转换器
•
•
•
芯片到芯片同步
功率耗散：460mW
20MHz IF 时的频谱性能
–
信噪比 (SNR)：DAC3154 为
62dBFS，DAC3164 为 72dBFS
–
无杂散动态范围 (SFDR)：DAC3154 为
76dBc，DAC3164 为 77dBc
DAC3171/DAC3161/DAC3151 引脚兼容。
•
•
•
电流源型数模转换器 (DAC)
依从范围：-0.5V 至 1.0V
此器件采用 QFN-64 PowerPAD™ 封装，并且可在整
个工业温度范围（-40°C 至 85°C）内工作。
封装：64 引脚四方扁平无引线 (QFN) (9mm x
9mm)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLAS960
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAMS
DACCLKP
DACCLKN
DATACLKP
DATACLKN
DATA9P
EXTIO
BIASJ
LVPECL
LVDS
Clock Distribution
1.2 V
Reference
Programmable
Delay
LVDS
DACA
Gain
QMC
A-offset
DATA9N
IOUTAP
IOUTAN
10-b
DACA
10
IOUTBP
IOUTBN
10-b
DACB
10
LVDS
DATA0P
DATA0N
QMC
B-offset
DACB
Gain
LVDS
SYNCP
SYNCN
ALIGNP
ALIGNN
VDDA33
Optional Input
Used for multi-DAC sync
LVPECL
Control Interface
Figure 1. DAC3154
2
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
DACCLKP
EXTIO
LVPECL
Clock Distribution
1.2 V
Reference
DACCLKN
DATACLKP
DATACLKN
DATA11P
BIASJ
LVDS
LVDS
Programmable
Delay
DACA
Gain
QMC
A-offset
DATA11N
IOUTAP
12-b
DACA
IOUTAN
12
IOUTBP
12-b
DACB
IOUTBN
12
LVDS
DATA0P
DATA0N
QMC
B-offset
DACB
Gain
LVDS
SYNCP
SYNCN
ALIGNP
ALIGNN
VDDA33
Optional Input
Used for multi-DAC sync
LVPECL
Control Interface
Figure 2. DAC3164
Copyright © 2013, Texas Instruments Incorporated
3
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
PINOUT – DAC3154
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DACCLKP
TXENABLE
2
DACCLKN
ALARM
SDO
IOVDD
SDIO
SCLK
SDENB
RESETB
NC
3
CLKVDD18
4
ALIGNP
5
ALIGNN
6
SYNCP
7
SYNCN
8
VFUSE
DAC3154
9
(MSB) D9P
10
D9N
NC
11
D8P
NC
12
D8N
NC
13
D7P
NC
14
D7N
NC
GND PAD (backside)
15
D6P
NC
16
D6N
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN ASSIGNMENT TABLE – DAC3154
PIN
I/O
DESCRIPTION
NAME
NO.
CONTROL/SERIAL
SCLK
43
42
44
I
I
Serial interface clock. Internal pull-down.
Serial interface clock. Internal pull-up.
SDENB
SDIO
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register XYZ), the SDIO pin in
an input only. Internal Pull-down.
SDO
46
41
O
Uni-directional serial interface data in 4 pin mode (register XYZ). The SDO pin is tri-stated in 3-pin
interface mode (default). Internal Pulldown.
RESETB
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
48
O
I
CMOS output for ALARM condition.
TXENABLE
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal
pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
4
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
PIN ASSIGNMENT TABLE – DAC3154 (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
DATA INTERFACE
DATA[9:0]P/N
9/10-
19/20
22/23
26/27-
31/32
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data
transfers per DATACKP/N clock cycle.
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA9P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLKP/N
SYNCP/N
24/25
6/7
I
I
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in
multiplexed output mode.
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge
of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
4/5
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can
be left unconnected.
OUTPUT/CLOCK
DACCLKP/N
IOUTAP/N
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
IOUTBP/N
53/54
O
B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTBP pin.
REFERENCE
EXTIO
58
57
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
POWER SUPPLY
IOVDD
45
3
I
I
I
I
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
1.8V clock supply
CLKVDD18
DIGVDD18
VDDA18
21, 28
50, 64
1.8V digital supply. Also supplies LVDS receivers.
Analog 1.8V supply
VDDA33
55, 56,
59
Analog 3.3V supply
VFUSE
NC
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
33-40,
51, 52,
62, 63
Not used. These pins can be left open or tied to GROUND in actual application use.
Copyright © 2013, Texas Instruments Incorporated
5
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
PINOUT – DAC3164
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DACCLKP
TXENABLE
2
DACCLKN
ALARM
SDO
3
CLKVDD18
4
ALIGNP
IOVDD
SDIO
SCLK
SDENB
RESETB
NC
5
ALIGNN
6
SYNCP
7
SYNCN
8
VFUSE
DAC3164
9
(MSB) D11P
10
D11N
NC
11
D10P
NC
12
D10N
NC
13
D9P
D0N
14
D9N
D0P (LSB)
D1N
GND PAD (backside)
15
D8P
16
D8N
D1P
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN ASSIGNMENT TABLE – DAC3164
PIN
I/O
DESCRIPTION
NAME
NO.
CONTROL/SERIAL
SCLK
43
42
44
I
I
Serial interface clock. Internal pull-down.
Serial interface clock. Internal pull-up.
SDENB
SDIO
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register XYZ), the SDIO pin
in an input only. Internal Pull-down.
SDO
46
41
O
Uni-directional serial interface data in 4 pin mode (register XYZ). The SDO pin is tri-stated in 3-pin
interface mode (default). Internal Pulldown.
RESETB
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
48
O
I
CMOS output for ALARM condition.
TXENABLE
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.
Internal pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
6
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
PIN ASSIGNMENT TABLE – DAC3164 (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
DATA INTERFACE
DATA[11:0]P/N
9/10-
19/20
22/23,
26-27-
35/36
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two
data transfers per DATACKP/N clock cycle.
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA11P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLK[:0]P/N
SYNCP/N
24/25
6/7
I
I
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge
in multiplexed output mode.
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising
edge of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
24/25
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it
can be left unconnected.
OUTPUT/CLOCK
DACCLKP/N
IOUTAP/N
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTA1 pin. The IOUTA2
pin is the complement of IOUTA1.
IOUTBP/N
53/54
O
B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTB1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTB1 pin. The IOUTB2
pin is the complement of IOUTB1.
REFERENCE
EXTIO
58
57
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
POWER SUPPLY
IOVDD
45
3
I
I
I
I
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
1.8V clock supply
CLKVDD18
DIGVDD18
VDDA18
21, 28
50, 64
1.8V digital supply. Also supplies LVDS receivers.
Analog 1.8V supply
VDDA33
55, 56,
59
Analog 3.3V supply
VFUSE
NC
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
37, 38,
39, 40,
51, 52
62, 63
Not used. These pins can be left open or tied to GROUND in actual application use.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
ECO PLAN
QUANTITY
DAC3154IRGCT
DAC3154IRGCR
DAC3164IRGC25
DAC3164IRGCT
DAC3164IRGCR
250
2000
25
DAC3154
GREEN (RoHS
and no Sb/Br)
QFN-64
RGC
–40°C to 85°C
Tape and Reel
DAC3164
250
2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2013, Texas Instruments Incorporated
7
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.5 to 4
UNIT
VDDA33 to GND
VDDA18 to GND
–0.5 to 2.3
–0.5 to 2.3
–0.5 to 4
Supply voltage
CLKVDD18 to GND
V
IOVDD to GND
DIGVDD18 to GND
–0.5 to 2.3
–0.5 to 0.5
–0.5 to 0.5
CLKVDD18 to DIGVDD18
VDDA18 to DIGVDD18
D[11..0]P, D[11..0]N, DATACLKP, DATACLKN, SYNCP, SYNCN to GND
DACCLKP, DACCLKN, ALIGNP, ALIGNN
TXENABLE, ALARM, SDO, SDIO, SCLK, SDENB, RESETB to GND
IOUTAP, IOUTAN, IOUTBP, IOUTBN to GND
EXTIO, BIASJ to GND
–0.5 to DIGVDD18 + 0.5
–0.5 to CLKVDD18 + 0.5
–0.5 to IOVDD + 0.5
–0.7 to 1.4
Terminal voltage
range
V
–0.5 to VDDA33 + 0.5
–65 to 150
Storage temperature range
ESD, Human Body Model
°C
kV
2
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
DAC3174
THERMAL METRIC(1)
UNITS
QFN (64 PIN)
θJA
Junction-to-ambient thermal resistance
23.0
7.6
2.8
0.1
2.8
0.2
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
8
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500MSPS, 50% clock
duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUTFS = 20mA (unless otherwise noted).
DAC3154
TYP
DAC3164
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX MIN
MAX
Resolution
DC ACCURACY
DNL Differential nonlinearity
INL Integral nonlinearity
ANALOG OUTPUTS
10
12
Bits
1 LSB = IOUTFS/210 for
DAC3154; 1 LSB = IOUTFS/212
for DAC3164
±0.04
±0.15
±0.2
±0.5
LSB
Coarse gain linearity
Offset error
±0.4
0.01
±2
±0.4
0.01
±2
LSB
Mid code offset
%FSR
With external reference
With internal reference
With internal reference
Gain error
%FSR
%FSR
mA
±2
±2
Gain mismatch
-2
2
-2
2
1
Minimum full scale output current
Maximum full scale output current
Output compliance range
Output resistance
2
2
Nominal full-scale current,
IOUTFS = 16xIBAIS current
20
20
IOUTFS = 20 mA
-0.5
-0.5
V
300
5
300
5
kΩ
pF
Output capacitance
REFERENCE OUTPUT
VREF
Reference output voltage
Reference output current
1.14
0.1
1.2
1.26 1.14
1.2
1.26
1.25
V
100
100
nA
REFERENCE INPUT
VEXTIO Input voltage range
External reference mode
1.2
1
1.25
0.1
1.2
1
V
Input resistance
Small signal bandwidth
MΩ
kHz
pF
500
100
500
100
Input capacitance
TEMPERATURE COEFFICIENTS
ppm of
FSR/°C
Offset drift
Gain drift
±1
±1
With external reference
With internal reference
±15
±30
±8
±15
±30
±8
Reference voltage drift
ppm /°C
POWER SUPPLY
DIGVDD18, VFUSE, VDDA18,
CLKVDD18
1.71
3.15
1.71
1.8
3.3
1.71
3.15
1.71
1.8
3.3
1.89
3.45
3.45
V
V
V
VDDA33
Sets CMOS IO voltage levels.
Nominal 1.8V, 2.5V or 3.3V
IOVDD
Copyright © 2013, Texas Instruments Incorporated
9
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500MSPS, 50% clock
duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUTFS = 20mA (unless otherwise noted).
DAC3154
TYP
DAC3164
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX MIN
MAX
POWER CONSUMPTION
IVDDA33 3.3V Analog supply current
52
49
59
67
52
49
59
57
mA
mA
ICLKVDD18 1.8V Clock supply current
MODE 1
1.8V Digital supply current
IDIGVDD18
fDAC = 491.52 MSPS,
QMC on,
115
130
115
130
mA
(DIGVDD18 and VFUSE)
IF = 20 MHz
IIOVDD
Pdis
1.8V IO Supply current
Total power dissipation
3.3V Analog supply current
0.002 0.015
0.002 0.015
mA
mW
mA
mA
464
51
530
464
51
530
IVDDA33
ICLKVDD18 1.8V Clock supply current
38
38
MODE 2
1.8V Digital supply current
IDIGVDD18
fDAC = 320 MSPS,
QMC on,
87
87
mA
(DIGVDD18 and VFUSE)
IF = 20 MHz
IIOVDD
Pdis
1.8V IO Supply current
Total power dissipation
3.3V Analog supply current
0.002
396
2.6
0.002
396
2.6
mA
mW
mA
mA
IVDDA33
ICLKVDD18 1.8V Clock supply current
43
43
MODE 3
1.8V Digital supply current
IDIGVDD18
Sleep mode,
fDAC = 491.52 MSPS,
DAC in sleep mode
110
110
mA
(DIGVDD18 and VFUSE)
IIOVDD
Pdis
1.8V IO Supply current
Total power dissipation
3.3V Analog supply current
0.003
284
1.6
0.003
284
1.6
mA
mW
mA
mA
IVDDA33
4
4
4
4
ICLKVDD18 1.8V Clock supply current
1.8
1.8
MODE 4
1.8V Digital supply current
IDIGVDD18
Power-down mode,
no clock,
1.7
3
mA
(DIGVDD18 and VFUSE)
DAC in sleep mode
IIOVDD
Pdis
1.8V IO Supply current
Total power dissipation
Power supply rejection ratio
Operating temperature
0.003 0.015
0.003 0.015
10 26
mA
10
26
mW
PSRR
T
DC tested
–0.4
–40
0.4 -0.4
0.4 %/FSR/V
85 °C
85
-40
10
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
DAC3154
DAC3164
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP MAX MIN TYP MAX
ANALOG OUTPUT
fDAC
Maximum sample rate
500
500
MSPS
ns
Output settling time to
0.1%
ts(DAC)
tPD
Transition: Code 0x0000 to 0x3FFF
11
2
11
2
Output propagation delay Does not include digital latency
ns
Output rise time 10% to
90%
tr(IOUT)
200
200
ps
Output fall time 90% to
10%
tf(IOUT)
200
26
200
26
ps
µs
Length of delay from DAC input pins to DATA at
output pins. In normal operation mode including the
latency of FIFO.
Digital Latency
AC PERFORMANCE
fDAC = 500 MSPS, fout = 10.1 MHz
fDAC = 500 MSPS, fout = 20.1 MHz
fDAC = 500 MSPS, fout = 70.1 MHz
fDAC = 500 MSPS, fout = 10.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 20.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 70.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 150.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 10.1 MHz
fDAC = 500 MSPS, fout = 20.1 MHz
fDAC = 500 MSPS, fout = 70.1 MHz
81
76
82
77
Spurious free dynamic
range
SFDR
dBc
dBc
69
70
82
83
81
82
IMD3 Intermodulation distortion
73.5
61
74
61
147
146
146
158
156
153
NSD
Noise spectral density
dBc/Hz
fDAC = 491.52 MSPS, fout = 30.72 MHz,
WCDMA TM1
69
68
90
77
73
90
Adjacent channel leakage
ratio
ACLR
dBc
dBc
f AC = 491.52 MSPS, fout = 153.6 MHz,
WCDMA TM1
fDAC = 500 MSPS,
fout = 20 MHz
Channel isolation
Copyright © 2013, Texas Instruments Incorporated
11
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
DAC3154
DAC3164
PARAMETERS
TEST CONDITIONS
UNIT
MIN TYP
MAX
MIN TYP
MAX
CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE)
0.6x
IOVDD
0.6x
IOVDD
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
0.25×
IOVDD
0.25×
IOVDD
IOVDD = 3.3 V, 2.5 V
or 1.8 V
IIH
IIL
High-level input current
Low-level input current
–40
–40
40
40
-40
-40
40
40
μA
μA
DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO)
IOVDD = 3.3 V, 2.5 V,
or 1.8 V
0.85×
IOVDD
0.85×
IOVDD
VOH
VOL
High-level output voltage
Low-level output voltage
V
V
0.125×
IOVDD
0.125×
IOVDD
SERIAL PORT TIMING
Setup time, SDENB to rising edge of
SCLK
ts(SENDB)
20
20
ns
ts(SDIO)
th(SDIO)
t(SCLK)
Setup time, SDIO to rising edge of SCLK
Hold time, SDIO from rising edge of SCLK
Period of SCLK
10
5
10
5
ns
ns
ns
ns
ns
100
40
40
100
40
40
t(SCLKH)
t(SCLKL)
High time of SCLK
Low time of SCLK
Data output delay after falling edge of
SCLK
td(DATA)
TRESET
10
10
ns
Minimum RESTB pulsewidth
LVDS INTERFACE (D[x..0]P/N, DA[x..0]P/N , DB[x..0]P/N , DA_CLKP/N, DB_CLKP/N, DATACLKP/N, SYNCP/N, ALIGNP/N)
Logic high differential input voltage
threshold
VA,B+
VA,B–
175
175
mV
Logic low differential input voltage
threshold
-175
–175 mV
VCOM
ZT
Input Common Mode Range
Internal termination
1.0
1.2
2.0
1.0
1.2
2.0
V
Ω
85 110
2
135
85 110
2
135
CL
LVDS input capacitance
pF
12
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
DAC3154
DAC3164
PARAMETERS
TEST CONDITIONS
UNIT
MIN TYP
MAX
MIN TYP
MAX
LVDS INPUT TIMING: SINGLE BUS SINGLE CLOCK MODE
config3 Setting
datadly clkdly
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
-20
-120
-220
-310
-390
-480
-560
-630
70
-20
-120
-220
-310
-390
-480
-560
-630
70
1
2
3
4
5
6
7
0
0
0
0
0
0
0
Setup D[x..0] valid to DATACLK rising or
ts(DATA)
ps
time
falling edge
150
230
330
430
530
620
150
230
330
430
530
620
congfig3 Setting
datadly
clkdly
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
310
390
480
560
650
740
850
930
200
100
20
310
390
480
560
650
740
850
930
200
100
20
Hold
time
D[x..0] valid to DATACLK rising or
falling edge
th(DATA)
ps
-60
-60
-140
-220
-290
-140
-220
-290
Copyright © 2013, Texas Instruments Incorporated
13
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
0.2
0.15
0.1
0.05
0.04
0.03
0.02
0.01
0
0.05
0
−0.01
−0.02
−0.03
−0.04
−0.05
−0.05
−0.1
−0.15
−0.2
0
200
400
600
Code
800
1000
0
200
400
600
Code
800
1000
G003
G004
Figure 3. DAC3154 Integral Nonlinearity
Figure 4. DAC3154 Differential Nonlinearity
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0dBFS
−6dBFS
−12dBFS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (dB)
G005
G006
Figure 5. DAC3154 SFDR vs Output Frequency Over Input
Scale
Figure 6. DAC3154 Second-Order Harmonic Distortion vs
Output Frequency Over Input Scale
100
100
fDAC = 200 MSPS
0dBFS
−6dBFS
−12dBFS
90
90
80
70
60
50
40
30
20
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
80
70
60
50
40
30
20
10
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G007
G008
Figure 7. DAC3154 Third-Order Harmonic Distortion vs
Output Frequency Over Input Scale
Figure 8. DAC3154 SFDR vs Output Frequency Over fDAC
14
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G009
G010
Figure 9. DAC3154 IMD3 vs Output Frequency Over Input
Scale
Figure 10. DAC3154 IMD3 vs Output Frequency Over fDAC
170
170
fDAC = 200 MSPS
0dBFS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
−6dBFS
−12dBFS
160
150
140
130
120
110
100
160
150
140
130
120
110
100
0
50
100
150
200
250
0
100
200
250
Output Frequency (dB)
Output Frequency (MHz)
G011
G012
Figure 11. DAC3154 NSD vs Output Frequency Over Input
Scale
Figure 12. DAC3154 NSD vs Output Frequency Over fDAC
−50
−50
Adjacent channel
Alternate channel
−60
−70
−80
−90
−60
−70
−80
−90
fDAC = 500 MSPS
−100
fDAC = 500 MSPS
−100
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (MHz)
Output Frequency (MHz)
G013
G012
Figure 13. DAC3154 ACLR (Adjacent Channel) vs Output
Frequency
Figure 14. DAC3154 ACLR (Alternate Channel) vs Output
Frequency
Copyright © 2013, Texas Instruments Incorporated
15
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
10
10
fDAC = 491. 52MSPS
fout = 20 MHz
fDAC = 491. 52MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−30
−40
−50
−60
−70
−80
−90
10
50
90
130
170
210
250
10
50
90
130
170
210
250
Frequency (MHz)
Frequency (MHz)
G011
G016
Figure 15. DAC3154 Single-Tone Spectral Plot (IF = 20MHz)
Figure 16. DAC3154 Single-Tone Spectral Plot (IF = 70MHz)
10
10
fDAC = 500 MSPS
fout = 20 MHz
fDAC = 500 MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Tone spacing = 1 MHz
Tone spacing = 1 MHz
15
17
19
21
23
25
65
67
69
71
73
75
Frequency (MHz)
Frequency (MHz)
G017
G018
Figure 17. DAC3154 Two-Tone Spectral Plot (IF = 20MHz)
Figure 18. DAC3154 Two-Tone Spectral Plot (IF = 70MHz)
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 2 0 d B m
*
A t t
5
d B
S W T
2
s
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 1 1 0
A
A
1
R M
*
1
R M
*
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
1 . 5 5 M H z /
S p a n 1 5 . 5 M H z
W - C D M A 3 G P P F W D
C e n t e r 7 0 M H z
4 . 0 8 M H z /
S p a n 4 0 . 8 M H z
T x C h a n n e l
S t a n d a r d : W - C D M A 3 G P P F W D
T x C h a n n e l s
A d j a c e n t C h a n n e l
Lower
B a n d w i d t h
3 . 8 4 M H z
3 . 8 4 M H z
Power
-10.64 dBm
-61.24 dB
-61.34 dB
A d j a c e n t C h a n n e l
B a n d w i d t h
Upper
Lower
Upper
-69.11 dB
-69.15 dB
( R e f )
Ch1
Ch2
Ch3
Ch4
-18.62 dBm
-18.64 dBm
-18.72 dBm
-18.70 dBm
S p a c i n g
5
M H z
A l t e r n a t e C h a n n e l
Lower
Upper
-61.11 dB
-61.39 dB
Total
-12.65 dBm
Figure 19. DAC3154 ACPR Four-Carrier
WCDMA Test Mode 1
Figure 20. DAC3154 ACPR Single-Carrier
WCDMA Test Mode 1
16
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
A
A
1
R M *
1
R M
*
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
5 . 8 5 5 0 3 4 5 3 8 M H z /
S p a n 5 8 . 5 5 0 3 4 5 3 8 M H z
E - U T R A / L T E S q u a r e
C e n t e r 7 0 M H z
2 . 9 2 8 2 7 4 1 9 M H z /
S p a n 2 9 . 2 8 2 7 4 1 9 M H z
E - U T R A / L T E S q u a r e
T x C h a n n e l
T x C h a n n e l
B a n d w i d t h
1 8 . 0 1 5 M H z
B a n d w i d t h
9 . 0 1 5 M H z
Power
-11.14 dBm
Power
-12.33 dBm
A d j a c e n t C h a n n e l
B a n d w i d t h
A d j a c e n t C h a n n e l
B a n d w i d t h
Lower
Upper
-61.93 dB
-62.21 dB
Lower
Upper
-64.00 dB
-64.09 dB
1 8 . 0 1 5 M H z
2 0 M H z
9 . 0 1 5 M H z
1 0 M H z
S p a c i n g
S p a c i n g
Figure 21. DAC3154 ACPR LTE 10-MHz FDD E-TM 1.1
Figure 22. DAC3154 ACPR LTE 20-MHz FDD E-TM 1.1
600
500
400
300
200
100
QMC on
200
300
400
500
G023
fDAC (MSPS)
Figure 23. DAC3154 Power Consumption vs fDAC
0.4
0.3
0.2
0.15
0.1
0.2
0.1
0.05
0
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.05
−0.1
−0.15
−0.2
0
500 1000 1500 2000 2500 3000 3500 4000
Code
0
500 1000 1500 2000 2500 3000 3500 4000
Code
G024
G025
Figure 24. DAC3164 Integral Nonlinearity
Figure 25. DAC3164 Differential Nonlinearity
Copyright © 2013, Texas Instruments Incorporated
17
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0dBFS
−6dBFS
−12dBFS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (dB)
G026
G027
Figure 26. DAC3164 SFDR vs Output Frequency Over Input
Scale
Figure 27. DAC3164 Second-Order Harmonic Distortion vs
Output Frequency Over Input Scale
100
100
fDAC = 200 MSPS
0dBFS
−6dBFS
−12dBFS
90
90
80
70
60
50
40
30
20
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
80
70
60
50
40
30
20
10
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G028
G029
Figure 28. DAC3164 Third-Order Harmonic Distortion vs
Output Frequency Over Input Scale
Figure 29. DAC3164 SFDR vs Output Frequency Over fDAC
100
100
fDAC = 200 MSPS
0dBFS
−6dBFS
−12dBFS
90
90
80
70
60
50
40
30
20
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
80
70
60
50
40
30
20
10
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G030
G031
Figure 30. DAC3164 IMD3 vs Output Frequency Over Input
Scale
Figure 31. DAC3164 IMD3 vs Output Frequency Over fDAC
18
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
180
170
160
150
140
130
120
110
180
170
160
150
140
130
120
110
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
100
200
250
Output Frequency (dB)
Output Frequency (MHz)
G032
G033
Figure 32. DAC3164 NSD vs Output Frequency Over Input
Scale
Figure 33. DAC3164 NSD vs Output Frequency Over fDAC
−50
−50
Adjacent channel
Alternate channel
−60
−70
−80
−90
−60
−70
−80
−90
fDAC = 500 MSPS
−100
fDAC = 500 MSPS
−100
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (MHz)
Output Frequency (MHz)
G034
G035
Figure 34. DAC3164 ACLR (Adjacent Channel) vs Output
Frequency
Figure 35. DAC3164 ACLR (Alternate Channel) vs Output
Frequency
10
10
fDAC = 491. 52MSPS
fout = 20 MHz
fDAC = 491. 52MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−30
−40
−50
−60
−70
−80
−90
10
50
90
130
170
210
250
10
50
90
130
170
210
250
Frequency (MHz)
Frequency (MHz)
G036
G037
Figure 36. DAC3164 Single-Tone Spectral Plot (IF = 20MHz)
Figure 37. DAC3164 Single-Tone Spectral Plot (IF = 70MHz)
Copyright © 2013, Texas Instruments Incorporated
19
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
10
10
fDAC = 500 MSPS
fout = 20 MHz
fDAC = 500 MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Tone spacing = 1 MHz
Tone spacing = 1 MHz
15
17
19
21
23
25
65
67
69
71
73
75
Frequency (MHz)
Frequency (MHz)
G038
G039
Figure 38. DAC3164 Two-Tone Spectral Plot (IF = 20MHz)
Figure 39. DAC3164 Two-Tone Spectral Plot (IF = 70MHz)
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2
s
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
A
A
1
R M
*
1
R M
*
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
4 . 0 8 M H z /
S p a n 4 0 . 8 M H z
C e n t e r 7 0 M H z
1 . 5 5 M H z /
S p a n 1 5 . 5 M H z
W - C D M A 3 G P P F W D
S t a n d a r d : W - C D M A 3 G P P F W D
T x C h a n n e l s
A d j a c e n t C h a n n e l
Lower
T x C h a n n e l
B a n d w i d t h
3 . 8 4 M H z
3 . 8 4 M H z
Power
-10.70 dBm
-70.74 dB
-70.87 dB
A d j a c e n t C h a n n e l
B a n d w i d t h
Upper
Lower
Upper
-77.84 dB
-77.14 dB
( R e f )
Ch1
Ch2
Ch3
Ch4
-18.70 dBm
-18.69 dBm
-18.77 dBm
-18.75 dBm
A l t e r n a t e C h a n n e l
S p a c i n g
5 M H z
Lower
Upper
-70.86 dB
-70.84 dB
Total
-12.71 dBm
Figure 40. DAC3164 ACPR Four-Carrier
WCDMA Test Mode 1
Figure 41. DAC3164 ACPR Single-Carrier
WCDMA Test Mode 1
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 2 0 d B m
*
A t t
5
d B
S W T
2 s
R e f - 2 0 d B m
*
A t t
5
d B
S W T
2 s
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 1 1 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 1 1 0
A
A
1
R M
*
1
R M *
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
5 . 8 5 5 0 3 4 5 3 8 M H z /
S p a n 5 8 . 5 5 0 3 4 5 3 8 M H z
E - U T R A / L T E S q u a r e
C e n t e r 7 0 M H z
2 . 9 2 8 2 7 4 1 9 M H z /
S p a n 2 9 . 2 8 2 7 4 1 9 M H z
E - U T R A / L T E S q u a r e
T x C h a n n e l
T x C h a n n e l
B a n d w i d t h
1 8 . 0 1 5 M H z
B a n d w i d t h
9 . 0 1 5 M H z
Power
-11.20 dBm
Power
-12.37 dBm
A d j a c e n t C h a n n e l
B a n d w i d t h
A d j a c e n t C h a n n e l
B a n d w i d t h
Lower
Upper
-70.91 dB
-70.66 dB
Lower
Upper
-73.67 dB
-73.46 dB
1 8 . 0 1 5 M H z
2 0 M H z
9 . 0 1 5 M H z
1 0 M H z
S p a c i n g
S p a c i n g
Figure 42. DAC3164 ACPR LTE 10-MHz FDD E-TM 1.1
Figure 43. DAC3164 ACPR LTE 20-MHz FDD E-TM 1.1
20
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DAC3164
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ZHCSB11 –MAY 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
600
500
400
300
200
QMC on
500
100
200
300
400
G044
f(MSPS)
Figure 44. DAC3164 Power Consumption vs fDAC
Copyright © 2013, Texas Instruments Incorporated
21
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
DEFINITION OF SPECIFICATIONS
Adjacent Carrier Leakage Ratio (ACLR): Defined as the ratio in decible relative to the carrier (dBc) between
the measured power within the channel and that of its adjacent channel.
Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the
ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB
change in the digital input code.
Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the
value at ambient (25°C) to values over the full operating temperature range.
Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output
current and the ideal full-scale output current.
Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,
determined by a straight line drawn from zero scale to full scale.
Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order
intermodulation distortion product to either fundamental output tone.
Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,
from the value at ambient (25°C) to values over the full operating temperature range.
Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output
current and the ideal mid-scale output current.
Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the
current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting
distortion performance.
Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius
from value at ambient (25°C) to values over the full operating temperature range.
Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the
output signal and the peak spurious signal.
Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the
RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first
six harmonics and dc.
TIMING DIAGRAMS
D[9:0]P/N
A3[9:0]
B3[9:0]
A4[9:0]
B4[9:0]
A5[9:0]
B5[9:0]
A6[9:0]
B6[9:0]
A7[9:0]
B7[9:0]
ts(DATA)
th(DATA)
ts(DATA)
th(DATA)
DATACLKP/N
(DDR)
ts(DATA)
th(DATA)
SYNCP/N
Resets write pointer to position 0
Figure 45. DAC3154 Input Timing Diagram for Dual Channel DDR Mode
22
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D[9:0]P/N
A3[9:0]
A4[9:0]
A5[9:0]
A6[9:0]
A7[9:0]
A8[9:0]
A9[9:0] A10[9:0] A11[9:0]
ts(DATA)
th(DATA)
DATACLKP/N
(SDR)
ts(DATA)
th(DATA)
SYNCP/N
Resets write pointer to position 0
Figure 46. DAC3154 Input Timing Diagram for Single Channel SDR Mode
D[11:0]P/N
A3[11:0] B3[11:0] A4[11:0] B4[11:0] A5[11:0] B5[11:0] A6[11:0] B6[11:0] A7[11:0] B7[11:0]
ts(DATA)
th(DATA)
ts(DATA)
th(DATA)
DATACLKP/N
(DDR)
ts(DATA)
th(DATA)
SYNCP/N
Resets write pointer to position 0
Figure 47. DAC3164 Input Timing Diagram for Dual Channel DDR Mode
D[11:0]P/N
A3[11:0] A4[11:0] A5[11:0] A6[11:0] A7[11:0] A8[11:0] A9[11:0] A10[11:0] A11[11:0]
ts(DATA)
th(DATA)
DATACLKP/N
(SDR)
ts(DATA)
th(DATA)
SYNCP/N
Resets write pointer to position 0
Figure 48. DAC3164 Input Timing Diagram for Single Channel SDR Mode
Copyright © 2013, Texas Instruments Incorporated
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DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
DATA INPUT FORMATS
Table 1. DAC3154 Dual Channel DDR Mode
BITS
DIFFERENTIAL PAIR (P/N)
D9
DATACLK RISING EDGE
DATACLK FALLING EDGE
A9
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
–
D8
D7
A8
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
A0
D0
SYNC
FIFO Write Reset
Table 2. DAC3154 Single Channel SDR Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D9
D8
A9
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
A0
D0
SYNC
FIFO Write Reset
–
Table 3. DAC3164 Dual Channel DDR Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D11
D10
D9
A11
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
–
A10
A9
D8
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
A0
D0
SYNC
FIFO Write Reset
24
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ZHCSB11 –MAY 2013
Table 4. DAC3164 Single Channel DDR Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D11
D10
D9
A11
A10
A9
D8
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
A0
D0
SYNC
FIFO Write Reset
–
Copyright © 2013, Texas Instruments Incorporated
25
DAC3154
DAC3164
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www.ti.com.cn
SERIAL INTERFACE DESCRIPTION
The serial port of the DAC3154/DAC3164 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC3154/DAC3164. It is compatible with most synchronous transfer formats and can be
configured as a 3 or 4 pin interface by sif4_ena in register config0, bit9. In both configurations, SCLK is the serial
interface input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for
both data in and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input
into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte
is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit
address to be accessed. Table 5 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. The data transfer cycle consists of two bytes.
Table 5. Instruction byte of the Serial interface
MSB
7
LSB
0
Bit
6
5
4
3
2
1
Description
R/W
A6
A5
A4
A3
A2
A1
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from DAC3154/DAC3164 and a low indicates a write operation to DAC3154/DAC3164.
[A6 : A0]
Identifies the address of the register to be accessed during the read or write operation.
Figure 49 shows the serial interface timing diagram for a DAC3154/DAC3164 write operation. SCLK is the serial
interface clock input to DAC3154/DAC3164. Serial data enable SDENB is an active low input to
DAC3154/DAC3164. SDIO is serial data in. Input data to DAC3154/DAC3164 is clocked on the rising edges of
SCLK.
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
A6
A5
A4
A3
A2
A1
t
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
(SDENB)
S
SCLK
SDENB
SCLK
SDIO
t
(SDIO)
t
(SDIO)
H
S
Figure 49. Serial Interface Write Timing Diagram
Figure 50 shows the serial interface timing diagram for a DAC3154/DAC3164 read operation. SCLK is the serial
interface clock input to DAC3154/DAC3164. Serial data enable SDENB is an active low input to
DAC3154/DAC3164. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out
from the DAC3154/DAC3164 during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin
configuration, both SDIO and SDO are data out from the DAC3154/DAC3164 during the data transfer cycle. At
the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge
of SDENB when they will 3-state.
26
Copyright © 2013, Texas Instruments Incorporated
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ZHCSB11 –MAY 2013
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
rwb
A6
A5
A4
A3
A2
A1
A0
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SDIO
SDO
SDENB
SCLK
SDIO
SDO
Data n
Data n-1
t
(Data)
d
Figure 50. Serial Interface Read Timing Diagram
REGISTER DESCRIPTIONS
In the SIF interface there are four types of registers:
NORMAL: The NORMAL register type allows data to be written and read from. All 16-bits of the data are
registered at the same time. There is no synchronizing with an internal clock thus all register
writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL:
AUTOSYNC:
A NORMAL register that causes a sync to be generated after the write is
finished. These are most commonly used in things like offsets and phaseadd
where there is a word or block setup that extends across multiple registers
and all of the registers need to be programmed before any take effect on the
circuit. For example, the phaseadd is two registers long. It wouldn’t serve the
user to have the first write 16 of the 32 bits cause a change in the frequency,
so the design allows all the registers to be written and then when that last
one for this block is finished, an autosync is generated for the mixer telling it
to grab all the new SIF values. This will occur on a mixer clock cycle so that
no meta-stability errors occur.
No RESET Value: These are NORMAL registers, but for one reason or another reset value can
not be guaranteed. This could be because the register has some read_only
bits or some internal logic partially controls the bit values. An example is the
SIF_CONFIG6 register. The bits come from the temperature sensor and the
fuses. Depending on which fuses are blown and what the die temp is the
reset value will be different.
FUSE controlled: While this isn’t a type of register, you may see this description in the area
describing the default value for the register. What is means is that fuses will
change the default value and the value shown in the document is for when
no fuses are blown.
READ_ONLY:
Registers that are internal wires ANDed with the address bus then connected to the SIF
output data bus.
WRITE_TO_CLEAR: These registers are just like NORMAL registers with one exception. They can be written
and read, however, when the internal logic asynchronously sets a bit high in one of
these registers, that bit stays high until it is written to ‘0’. This way interrupts will be
captured and stay constant until cleared by the user.
Copyright © 2013, Texas Instruments Incorporated
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DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
(LSB)
Table 6. Register Map
(MSB)
Bit 15
Name
Address
Default
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
config0
0x00
0x44FC
qmc_
offset_ena
dual_ ena
chipwidth (1:0)
reserved
twos
sif4_ena
reserve
d
fifo_ ena
alarm_
out_ena
alarm_
out_pol
alignrx_en syncrx_en lvdsdataclk_
reserved
synconly_en
a
a
a
ena
alarm_1awa alarm_coll
config1
0x01
0x600E
iotest_ena bsideclk_e fullword_i 64cnt_ena dacclkgon dataclkgone collision_ena reserve
daca_
compliment
dacb_
complime
nt
sif_sync
sif_
alarm_
reserved
dual_ena
na
nterface_
ena
e_ ena
_ena
d
sync_ena 2away_en
a
y_ena
ision _ena
config2
config3
config4
config5
0x02
0x03
0x04
0x05
0x3FFF
0x0000
0x0000
0x0000
reserved
datadlya (2:0)
reserved
lvdsdata_ena (13:0)
iotest_results (13:0)
clkdlya (2:0)
datadlyb (2:0)
clkdlyb (2:0)
extref_ena
reserved
alarm_fro
m_
zerochka
alarm_fro
m_
zerochkb
alarms_from_fifoa (2:0)
alarms_from_fifob (2:0)
alarm_dacclk alarm_dat clock_gon alarm_fro
_ gone
alarm_fro
m_ iotesta m_ iotestb
reserved
aclk_
gone
e
config6
0x06
0x0084(D
AC3164)
0x0088(D
AC3154)
tempdata (7:0)
fuse_cntl (5:0)
reserved
config7
config8
config9
config10
0x07
0x08
0x09
0x0A
0xFFFF
0x4000
0x8000
0xF080
alarms_mask (15:0)
reserved
qmc_offseta (12:0)
qmc_offsetb (12:0)
fifo_offset (2:0)
coarse_dac (3:0)
fuse_
sleep
reserved
reserved
reserved
tsense_ clkrecv_ena
sleep
sleepa
sleepb
reserved
config11
config12
config13
config14
config15
config16
config17
config18
config19
config20
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x1111
0x3A7A
0x36B6
0x2AEA
0x0545
0x1A1A
0x1616
0x2AAA
0x06C6
0x0000
reserved
reserved
reserved
reserved
iotest_pattern0 (13:0)
iotest_pattern1 (13:0)
iotest_pattern2 (13:0)
iotest_pattern3 (13:0)
iotest_pattern4 (13:0)
iotest_pattern5 (13:0)
iotest_pattern6 (13:0)
iotest_pattern7 (13:0)
sifdac (13:0)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
sifdac_
ena
reserved
config21
config22
config23
config24
config25
config127
0x15
0x16
0x17
0x18
0x19
0x7F
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0044
sleepcntl (15:0)
fa002_data(15:0)
fa002_data(31:16)
fa002_data(47:32)
fa002_data(63:48)
reserved
reserved
reserved
reserved
reserved
titest_voh
titest_vol
vendorid (1:0)
versionid (2:0)
28
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
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ZHCSB11 –MAY 2013
Register name: config0 – Address: 0x00, Default: 0x44FC
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config0
0x00
15
14
qmc_offset_ena
dual_ena
Enable the offset function when asserted.
Utilizes both DACs when asserted.
0
1
FUSE
controlled
13:12 chipwidth
Programmable bits for setting the input interface width.
00: all 14 bits are used. NOTE: not applicable to
DAC3154/DAC3164.
00
01: upper 12 bits are used 10: upper 10 bits are used
11: upper 10 bits are used
11
10
reserved
twos
reserved
0
1
When asserted, this bit tells the chip to presume 2’s
complement data is arriving at the input. Otherwise offset
binary is presumed.
9
sif4_ena
When asserted the SIF interface becomes a 4 pin interface.
This bit has a lower priority than the dieid_ena bit.
0
0
8
7
reserved
fifo_ena
reserved
When asserted, the FIFO is absorbing the difference between
INPUT clock and DAC clock. If it is not asserted then the
FIFO buffering is bypassed but the reversing of bits and
handling of offset binary input is still available. NOTE: When
the FIFO is bypassed the DACCCLK and DATACLK must
be aligned or there may be timing errors; and, it is not
recommended for actual application use.
1
6
5
4
alarm_out_ena
alarm_out_pol
alignrx_ena
When asserted the pin alarm becomes an output instead of a
tri-stated pin.
1
1
1
This bit changes the polarity of the ALARM signal.
(0=negative logic, 1=positive logic)
When asserted the ALIGN pin receiver is powered up. NOTE:
It is recommended to clear this bit when ALIGNP/N are
not used.
3
syncrx_ena
When asserted the SYNC pin receiver is powered up. NOTE:
It is recommended to clear this bit when SYNCP/N are
not used.
1
2
1
0
lvdsdataclk_ena
reserved
When asserted the DATACLK pin receiver is powered up.
reserved
1
0
0
synconly_ena
When asserted the chip is put into the SYNC ONLY mode
where the SYNC pin is used as the sync input for both the
front and back of the FIFO.
Copyright © 2013, Texas Instruments Incorporated
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Register name: config1 – Address: 0x01, Default: 0x600E
Register Addr
Default
Value
Bit
Name
Function
Name
(Hex)
config1
0x01 15
iotest_ena
Turns on the io-testing circuitry when asserted. This is the circuitry
that will compare a 8 sample input pattern to SIF programmed
registers to make sure the data coming into the chip meets
setup/hold requirements. If this bit is a ‘0’ then the clock to this
circuitry is turned off for power savings. NOTE: Sample 0 should
be aligned with the rising edge of SYNC.
0
14
bsideclk_ena
When asserted the input clock for the B side datapath is enabled.
Otherwise the IO TEST and the FIFO on the B side of the design
will not get a clock.
1
13
12
reserved
reserved.
1
0
64cnt_ena
This enables the resetting of the alarms after 64 good samples with
the goal of removing unnecessary errors. For instance on a lab
board, when checking the setup/hold through IO TEST, there may
initially be errors, but once the test is up and running everything
works. Setting this bit removes the need for a SIF write to clear the
alarm register.
11
10
dacclkgone_ena
dataclkgone_end
This allows the DACCLK gone signal from the clock monitor to be
used to shut the output off.
0
0
This allows the DATACLK gone signal from the clock monitor to be
used to shut the output off.
9
8
7
collision_ena
reserved
This allows the collision alarm from the FIFO to shut the output off
reserved.
0
0
0
daca_compliment
When asserted the output to the DACA is complimented. This
allows the user of the chip to effectively change the + and –
designations of the DAC output pins.
6
5
dacb_compliment
sif_sync
When asserted the output to the DACB is complimented. This
allows the user of the chip to effectively change the + and –
designations of the DAC output pins.
0
0
This is the SIF_SYNC signal. Whatever is programmed into this bit
will be used as the chip sync when SIF_SYNC mode is enabled.
Design is sensitive to rising edges so programming from 0->1 is
when the sync pulse is generated. 1->0 has no effect.
4
3
sif_sync_ena
When asserted enable SIF_SYNC mode.
0
1
alarm_2away_ena
When asserted alarms from the FIFO that represent the pointers
being 2 away are enabled
2
1
0
alarm_1away_ena
alarm_collision_ena
reserved
When asserted alarms from the FIFO that represent the pointers
being 1 away are enabled
1
1
0
When asserted the collision of FIFO pointers causes an alarm to be
generated
reserved
Register name: config2 – Address: 0x02, Default: 0x3FFF
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config2
0x02
15
reserved
reserved
reserved
0
14
reserved
0
13:0
lvdsdata_ena
These 14 bits are individual enables for the 14 input pin receivers.
NOTE: It is recommended to clear bit (1:0) for the 12-bit
DAC3164, and clear bit (3:0) for the 10-bit DAC3154.
0x3FFF
30
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Register name: config3 – Address: 0x03, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config3
0x03
15:13 datadlya
12:10 clkdlya
Controls the delay of the A data inputs through the LVDS receivers. 000
0= no additional delay and each LSB adds a nominal 80ps.
Controls the delay of the A data clock input through the LVDS
receivers. 0= no additional delay and each LSB adds a nominal
80ps.
000
9:7
6:4
datadlyb
clkdlyb
Controls the delay of the B data inputs through the LVDS receivers. 000
0= no additional delay and each LSB adds a nominal 80ps.
Controls the delay of the B data clock input through the LVDS
receivers. 0= no additional delay and each LSB adds a nominal
80ps.
000
3
extref_ena
reserved
Enable external reference for the DAC when set.
reserved
0
2:1
0
00
0
dual_clock_ena
When asserted it tells the LVDS input circuit that there are two
individual data clocks. NOTE: must be in SIF_SYNC mode, and
not applicable to DAC3154/DAC3164.
Register name: config4 – Address: 0x04, Default: 0x0000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config4
0x04
15:14 reserved
13:0 iotest_ results
reserved
00
WRITE TO
CLEAR/
No RESET
value
The values of these bits tell which bit in the input word failed during the 0x0000
io-test pattern comparison. Bit 13 corresponds to the MSB input.
Copyright © 2013, Texas Instruments Incorporated
31
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
Register name: config5 – Address: 0x05, Default: 0x0000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config5
WRITE TO
CLEAR
0x05
15
alarm_from_ zerochka
When this bit is asserted the FIFO A write pointer has an all zeros
pattern in it. Since this pointer is a shift register, all zeros will cause
the input point to be stuck until the next sync. The result could be a
repeated 8T pattern at the output if the mixer is off and no syncs
occur. Check for this error will tell the user that another sync is
necessary to restart the FIFO write pointer.
0
14
alarm_from_ zerochkb
When this bit is asserted the FIFO B write pointer has an all zeros
pattern in it. Since this pointer is a shift register, all zeros will cause
the input point to be stuck until the next sync. The result could be a
repeated 8T pattern at the output if the mixer is off and no syncs
occur. Check for this error will tell the user that another sync is
necessary to restart the FIFO write pointer.
0
13:11 alarms_from_ fifoa
These bits report the FIFO A pointer status.
000: All fine
000
001: Pointers are 2 away
01X: Pointers are 1 away
1XX: FIFO Pointer collision
10:8
alarms_from_ fifob
These bits report the FIFO B pointer status.
000: All fine
0
001: Pointers are 2 away
01X: Pointers are 1 away
1XX: FIFO Pointer collision
7
6
5
alarm_dacclk_ gone
alarm_dataclk_ gone
clock_gone
Bit gets asserted when the DACCLK has been stopped long for
enough cycles to be caught. The number of cycles varies with
interpolation.
0
0
0
Bit gets asserted when the DATACLK has been stopped long for
enough cycles to be caught. The number of cycles varies with
interpolation.
This bit gets set when either alarm_dacclk_gone or
alarm_dataclk_gone are asserted. It controls the output of the
CDRV_SER block. When high, the CDRV_SER block will output
“0x8000” for each output connected to a DAC. The bit must be
written to ‘0’ for CDRV_SER outputs to resume normal operation.
4
3
alarm_from_ iotesta
alarm_from_ iotestb
This is asserted when the input data pattern does not match the
pattern in the iotest_pattern registers.
0
0
This is asserted when the input data pattern does not match the
pattern in the iotest_pattern registers.
2
1
0
reserved
reserved
reserved
reserved
reserved
reserved
0
0
0
32
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
Register name: config6 – Address: 0x06, Default: 0x0084 (DAC3164); 0x0088 (DAC3154)
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config6
0x06
15:8
tempdata
This the output from the chip temperature sensor.
0x00
No RESET
Value
NOTE: when reading these bits the SIF interface must be exteremly
slow, 1MHz range.
7:2
fuse_cntl
These are the values of the blown fuses and are used to determine the
available functionality in the chip.
NOTE: These bits are READ_ONLY and allow the user to check
what features have been disabled in the device.
bit5 = 1: Force full word interface.
0x21 for
DAC3164;
0x22 for
DAC3154
bit4 = 1: reserved
bit3 = 1: reserved
bit2 = 1: Forces Single DAC Mode. Note: This does not force the
channel B in sleep mode. In order to do so, user needs to program
the sleepb SPI bit (config10, bit 5) to "1".
bit1:0 : Forces a different bits size.
“00” 14bit.
“01” 12bit
“10” 10bit
“11” 10bit
1
0
reserved
reserved
reserved
reserved
0
0
Register name: config7 – Address: 0x07, Default: 0xFFFF
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config7
0x07
15:0
alarms_ mask
Each bit is used to mask an alarm. Assertion masks the alarm: bit15 =
alarm_mask_zerochka
0xFFFF
bit14 = alarm_mask_zerochkb
bit13 = alarm_mask_fifoa_collision
bit12 = alarm_mask_fifoa_1away
bit11 = alarm_mask_fifoa_2away
bit10 = alarm_mask_fifob_collision
bit9 = alarm_mask_fifob_1away
bit8 = alarm_mask_fifob_2away
bit7 = alarm_mask_dacclk_gone
bit6 = alarm_mask_dataclk_gone
bit5 = Masks the signal which turns off the DAC output when a clock or
collision occurs. This bit has no effect on the PAD_ALARM output.
bit4 = alarm_mask_iotesta
bit3 = alarm_mask_iotestb
bit2 =
bit1 =
bit0 =
Register name: config8 – Address: 0x08, Default: 0x4000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config8
0x08
15:13 reserved
12:0 qmc_ offseta
reserved
010
The DAC A offset correction. The offset is measured in DAC LSBs.
0x0000
Copyright © 2013, Texas Instruments Incorporated
33
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
Register name: config9 – Address: 0x09, Default: 0x8000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config9
AUTO
SYNC
0x09
15:13 fifo_ offset
This is the starting point for the READ_POINTER in the FIFO block.
The READ_POINTER is set to this location when a sync occurs on the
DACCLK side of the FIFO.
100
12:0
qmc_ offsetb
The DAC B offset correction. The offset is measured in DAC LSBs.
0x0000
NOTE: Writing this register causes an autosync to be generated in
the QMOFFSET block.
Register name: config10 – Address: 0x0A, Default: 0xF080
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
Config10
0x0A 15:12 coarse_ dac
Scales the output current is 16 equal steps.
1111
VrefIO
´ mem_coarse_daca + 1
(
)
Rbias
11
10
9
fuse_ sleep
reserved
Put the fuses to sleep when set high.
0
0
0
0
1
0
0
reserved
reserved
reserved
8
tsense_ sleep
clkrecv_ena
sleepa
When asserted the temperature sensor is put to sleep.
Turn on the DAC CLOCK receiver block when asserted.
When asserted DACA is put to sleep.
7
6
5
sleepb
When asserted DACB is put to sleep. Note: This bit needs to be
programmed to "1" for single DAC mode.
4:0
reserved
reserved
00000
Register name: config11 – Address: 0x0B, Default: 0x1111
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config11
0x0B 15:12 reserved
reserved
reserved
reserved
reserved
0001
0001
0001
0001
11:8
7:4
reserved
reserved
reserved
3:0
Register name: config12 – Address: 0x0C, Default: 0x3A7A
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config12
0x0C 15:14 reserved
13:0 iotest_ pattern0
reserved
00
This is dataword0 in the IO test pattern. It is used with the seven
other words to test the input data. NOTE: This word should be
aligned with the rising edge of SYNC when testing the IO
interface.
0x3A7A
Register name: config13 – Address: 0x0D, Default: 0x36B6
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config13
0x0D 15:14 reserved
13:0 iotest_ pattern1
reserved
00
This is dataword1 in the IO test pattern. It is used with the seven
other words to test the input data.
0x36B6
34
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
Register name: config14 – Address: 0x0E, Default: 0x2AEA
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config14
0x0E 15:14 reserved
13:0 iotest_ pattern2
reserved
00
This is dataword2 in the IO test pattern. It is used with the seven
other words to test the input data.
0x2AEA
Register name: config15 – Address: 0x0F, Default: 0x0545
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config15
0x0F 15:14 reserved
13:0 iotest_ pattern3
reserved
00
This is dataword3 in the IO test pattern. It is used with the seven
other words to test the input data.
0x0545
Register name: config16 – Address: 0x10, Default: 0x1A1A
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config16
0x10
15:14 reserved
13:0 iotest_ pattern4
reserved
00
This is dataword4 in the IO test pattern. It is used with the seven
other words to test the input data.
0x1A1A
Register name: config17 – Address: 0x11, Default: 0x1616
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config17
0x11
15:14 reserved
13:0 iotest_ pattern5
reserved
00
This is dataword5 in the IO test pattern. It is used with the seven
other words to test the input data.
0x1616
Register name: config18 – Address: 0x12, Default: 0x2AAA
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config18
0x12
15:14 reserved
13:0 iotest_ pattern5
reserved
00
This is datawor6 in the IO test pattern. It is used with the seven
other words to test the input data.
0x2AAA
Register name: config19 – Address: 0x13, Default: 0x06C6
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config19
0x13
15:14 reserved
13:0 iotest_ pattern7
reserved
00
This is dataword7 in the IO test pattern. It is used with the seven
other words to test the input data.
0x06C6
Copyright © 2013, Texas Instruments Incorporated
35
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
Register name: config20– Address: 0x14, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config20
0x14
15
sifdac_ ena
When asserted the DAC output is set to the value in sifdac. This
can be used for trim setting and other static tests.
0
14
reserved
sifdac
reserved
0
13:0
This is the value that is sent to the DACs when sifdac_ena is
asserted.
0x0000
Register name: config21– Address: 0x15, Default: 0xFFFF
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config21
0x15
15:0
sleepcntl
This controls what blocks get sent a SLEEP signal when the
PAD_SLEEP pin is asserted. Programming a ‘1’ in a bit will pass
the SLEEP signal to the appropriate block.
0xFFFF
bit15 = DAC A
bit14 = DAC B
bit13 = FUSE Sleep
bit12 = Temperature Sensor
bit11 = Clock Receiver
bit10 = LVDS DATA Receivers
bit9 = LVDS SYNC Receiver
bit8 = PECL ALIGN Receiver
bit7 = LVDS DATACLK Receiver
bit6 =
bit5 =
bit4 =
bit3 =
bit2 =
bit1 =
bit0 =
Register name: config22– Address: 0x16
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
Default Value
Default Value
config22
READ
ONLY
0x16
15:0
fa002_ data(15:0)
Lower 16bits of the DIE ID word
Register name: config23– Address: 0x17
Register
Name
Addr
(Hex)
Bit
Name
Function
config23
READ
ONLY
0x17
15:0
fa002_ data(31:16)
Lower middle 16bits of the DIE ID word
Register name: config24– Address: 0x18, Default
Register
Name
Addr
(Hex)
Bit
Name
Function
config24
READ
0x18
15:0
fa002_ data(47:32)
Upper middle 16bits of the DIE ID word
ONLY
36
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
www.ti.com.cn
ZHCSB11 –MAY 2013
Register name: config25– Address: 0x19
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config25
READ
0x19
15:0
fa002_ data(63:48)
Upper 16bits of the DIE ID word
ONLY
Register name: config127– Address: 0x7F, Default: 0x0045
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config127
READ
ONLY/No
RESET
Value
0x7F 15:14 reserved
13:12 reserved
reserved
reserved
reserved
reserved
reserved
00
00
00
00
0
11:10 reserved
9:8
7
reserved
reserved
titest_voh
titest_vol
vendorid
versionid
6
A fixed ‘1’ that can be used to test the Voh at the SIF output.
A fixed ‘0’ that can be used to test the Vol at the SIF output.
Fixed to "01".
1
5
0
4:3
2:0
01
001
Chip version.
Synchronization Modes
There are three modes of syncing included in the DAC3154/DAC3164.
•
•
•
NORMAL Dual Sync – The SYNC pin is used to align the input side of the FIFO (write pointers) with the A(0)
sample. The ALIGN pin is used to reset the output side of the FIFO (read pointers) to the offset value.
Multiple chip alignment can be accomplished with this kind of syncing.
SYNC ONLY – In this mode only the SYNC pin is used to sync both the read and write pointers of the FIFO.
There is an asynchornized handoff between the DATACLK and DACCLK when using this mode, therefore it is
impossible to accurately align multiple chips closer than 2 or 3T.
SIF_SYNC – When neither SYNC nor ALIGN are used, a programmable SYNC pulse can be used to sync
the design. However, the same issues as SYNC ONLY apply. There is an asynchornized handoff between
the serial clock domain and the two sides of the FIFO. Because of the asynchronous nature of the SIF_SYNC
it is impossible to align the sync up with any sample at the input.
Note: When ALIGNP/N are not used, it is recommended to clear the alignrx_ena register (config1, bit 4),
and tie ALIGNP to DIGVDD18 and ALIGNN to GROUND. When SYNCP/N are not used, it is recommended
to clear register syncrx_ena (config0, bit3), and the unused SYNCP/N pins can be left open or tied to
GROUND.
Copyright © 2013, Texas Instruments Incorporated
37
DAC3154
DAC3164
ZHCSB11 –MAY 2013
www.ti.com.cn
Alarm Monitoring
DAC3154/DAC3164 includes flexible alarm monitoring that can be used to alert a possible malfunction scenario.
All alarm events can be accessed either through the SIP registers and/or through the ALARM pin. Once an alarm
is set, the corresponding alarm bit in register config5 must be reset through the serial interface to allow further
testing. The set of alarms includes the following conditions:
Zero check alarm
•
Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a
shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a
sync to the FIFO block is required.
FIFO alarms
•
•
•
•
alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
alarm_fifo_2away. Pointers are within two addresses of each other.
alarm_fifo_1away. Pointers are within one address of each other.
alarm_fifo_collision. Pointers are equal to each other.
Clock alarms
•
•
•
clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
alarm_dataclk_gone. Occurs when the DATACLK has been stopped.
Pattern checker alarm
alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.
•
To prevent unexpected DAC outputs from propagating into the transmit channel chain, DAC3154, DAC3164
includes a feature that disables the outputs when a catastrophic alarm occurs. The catastrophic alarms include
FIFO pointer collision, the loss DACCLK or the loss of DATACLK. When any of these alarms occur the internal
TXenable signal is driven low, causing a zeroing of the data going to the DAC in <10T. One caveat is if both
clocks stop, the circuit cannot determine clock loss so no alarms are generated; therefore, no zeroing of output
data occurs.
38
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC3154IRGCR
DAC3154IRGCT
DAC3164IRGCR
DAC3164IRGCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
64
64
64
64
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DAC3154I
NIPDAU
NIPDAU
NIPDAU
DAC3154I
DAC3164I
DAC3164I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064H
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
7.4 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219011/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
7.4)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(3.45) TYP
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(
0.2) TYP
VIA
33
16
32
17
(1.16) TYP
(3.45) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219011/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(0.58)
36X ( 0.96)
33
16
17
32
(0.58)
(1.16)
TYP
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219011/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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