DAC3482_14_技术文档

DAC3482

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SLAS748A –MARCH 2011–REVISED JUNE 2011

Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)

Check for Samples: DAC3482

1

FEATURES

DESCRIPTION

The DAC3482 is a very low power, high dynamic

range, dual-channel, 16-bit digital-to-analog converter

(DAC) with a sample rate as high as 1.25 GSPS.

•

Very Low Power: 900 mW at 1.25 GSPS, Full

Operating Conditions

Multi-DAC Synchronization

•

The device includes features that simplify the design

of complex transmit architectures: 2x to 16x digital

interpolation filters with over 90 dB of stop-band

attenuation simplify the data interface and

reconstruction filters. A complex mixer allows flexible

carrier placement. A high-performance low jitter clock

multiplier simplifies clocking of the device without

significant impact on the dynamic range. The digital

Quadrature Modulator Correction (QMC) enables

complete IQ compensation for gain, offset, phase,

and group delay between channels in direct

up-conversion applications.

Selectable 2x, 4x, 8x, 16x Interpolation Filter

–

Stop-Band Attenuation > 90 dBc

•

Flexible On-Chip Complex Mixing

–

Fine Mixer with 32-bit NCO

Power Saving Coarse Mixer: ± n×Fs/8

•

High Performance, Low Jitter Clock

Multiplying PLL

Digital I and Q Correction

–

Gain, Phase, Offset, and Group Delay

Correction

•

Digital Inverse Sinc Filter

Flexible LVDS Input Data Bus

Digital data is input to the device through a flexible

LVDS data bus with on-chip termination. Data can be

input either word-wide or byte-wide. The device

includes a FIFO, data pattern checker and parity test

to ease the input interface. The interface also allows

full synchronization of multiple devices.

–

Word- or Byte-Wide Interface

8 Sample Input FIFO

Data Pattern Checker

Parity Check

The device is characterized for operation over the

entire industrial temperature range of –40°C to 85°C

and is available in a very-small 88-pin 9x9mm WQFN

package.

•

Temperature Sensor

Differential Scalable Output: 10mA to 30mA

Space Saving Package: 88-pin 9x9mm WQFN

(GREEN / Pb-Free)

The DAC3482 very low power, small size, superior

crosstalk, high dynamic range and features are an

ideal fit for today’s communication systems.

APPLICATIONS

•

Cellular Base Stations

Diversity Transmit

Wideband Communications

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC3482

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SLAS748A –MARCH 2011–REVISED JUNE 2011

DEVICE INFORMATION

PINOUT

RKD Package

(Top View)

C1

C4

LPF

PLLAVDD

OSTRP

OSTRN

DACCLKP

DACCLKN

CLKVDD

VFUSE

SYNCP

SYNCN

DIGVDD

IOVDD

D15P

A1

A33

B30

A32

B29

A31

B28

A30

B27

A29

B26

A28

B25

A27

B24

A26

B23

A25

B22

A24

B21

A23

BIASJ

RESETB

TXENABLE

ALARM

SCLK

B1

B2

B3

B4

B5

B6

B7

B8

B9

A2

A3

A4

A5

A6

A7

A8

A9

SDENB

SDIO

SDO

PARITYN

PARITYP

DIGVDD

IOVDD

D0N

DAC3482

88-WQFN 9mm x 9mm

D15N

D0P

D14P

D1N

D14N

D1P

DIGVDD

D13P

DIGVDD

D2N

D13N

A10

B10

A11

D2P

D12P

D3N

D12N

D3P

C2

C3

P0133-01

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NO.

A36, A37,

A38, A40,

A41, A42,

B31

AVDD

I

Analog supply voltage. (3.3 V)

CMOS output for ALARM condition. The ALARM output functionality is defined through the config7

register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol

control bit.

ALARM

B29

O

Full-scale output current bias. For 30mA full-scale output current, connect 1.28kΩ to ground. Change

the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>

BIASJ

A33

A4

O

I

Internal clock buffer supply voltage. (1.2 V)

It is recommended to isolate this supply from DIGVDD and DACVDD.

CLKVDD

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PIN FUNCTIONS (continued)

I/O

DESCRIPTION

NAME

NO.

LVDS positive input data bits 0 through 15. Internal 100 Ω termination resistor. Data format relative to

DATACLKP/N clock is Double Data Rate (DDR) and can be transferred in either byte-wide or

word-wide mode. In byte-wide mode the unused pins can be left unconnected.

A7, A8, B9,

B10, A12,

A13, A14,

A15, B17,

B18, B19,

B20, A23,

A24, B23,

B24

D15P is most significant data bit (MSB) in word-wide mode

D7P is most significant data bit (MSB) in byte-wide mode

D0P is least significant data bit (LSB)

D[15..0]P

I

The order of the bus can be reversed via config2 revbus bit.

B7, B8, A10,

A11, B11,

B12, B13,

B14, A19,

A20, A21,

A22, B21,

B22, A26,

A27

D[15..0]N

LVDS negative input data bits 0 through 15. (See D[15:0]P description above)

DACCLKP

DACCLKN

A3

B3

I

Positive external LVPECL clock input for DAC core with a self-bias.

Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)

A35, A39,

A43

DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and

DIGVDD.

DACVDD

I

LVDS positive input data clock. Internal 100 Ω termination resistor. Input data D[15:0]P/N is latched

on both edges of DATACLKP/N (Double Data Rate).

DATACLKP

DATACLKN

DIGVDD

A16

I

B15

LVDS negative input data clock. (See DATACLKP description)

A6, A9, A25,

A28

Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD.

Used as external reference input when internal reference is disabled through config27 extref_ena =

EXTIO

A34

I/O ‘1’. Used as internal reference output when config27 extref_ena = ‘0’ (default). Requires a 0.1 μF

decoupling capacitor to AGND when used as reference output.

LVDS frame indicator positive input. Internal 100 Ω termination resistor. The main functions of this

input are to reset the FIFO or to be used as a syncing source. These two functions are captured with

the rising edge of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N can be

used as a block parity bit. The FRAMEP/N signal should be edge-aligned with D[15:0]P/N.

FRAMEP

FRAMEN

B16

A18

I

LVDS frame indicator negative input. (See the FRAMEP description)

These pins are ground for all supplies.

C1, C2, C3,

C4, B32,

B33, B38,

B39, Thermal

Pad

GND

IOUTIP

IOUTIN

IOUTQP

IOUTQN

IOVDD

LPF

B36

O

I

I-Channel DAC current output. Connect directly to ground if unused.

I-Channel DAC complementary current output. Connect directly to ground if unused.

Q-Channel DAC current output. Connect directly to ground if unused.

Q-Channel DAC complementary current output. Connect directly to ground if unused.

Supply voltage for all digital I/O. (3.3 V)

B37

B35

B34

B6, A17, B25

A1

I/O PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected.

LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of

OSTRP

A2

I

DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in Dual Sync

Sources Mode. If unused it can be left unconnected.

OSTRN

B2

I

LVPECL output strobe negative input. (See the OSTRP description)

Optional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100 Ω termination

resistor. If unused it can be left unconnected.

PARITYP

B26

PARITYN

PLLAVDD

SCLK

A29

B1

I

Optional LVDS negative input parity bit.

PLL analog supply voltage. (3.3 V)

A31

B28

Serial interface clock. Internal pull-down.

SDENB

Active low serial data enable, always an input to the DAC3482. Internal pull-up.

Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional in 4-pin mode. Internal

pull-down.

SDIO

A30

I/O

4

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PIN FUNCTIONS (continued)

I/O

DESCRIPTION

NAME

SDO

NO.

Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode

(default).

B27

O

I

SLEEP

SYNCP

SYNCN

RESETB

B40

A5

Active high asynchronous hardware power-down input. Internal pull-down.

Optional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100 Ω termination

resistor. If unused it can be left unconnected.

I

B5

I

Optional LVDS SYNC negative input.

Active low input for chip RESET, which resets all the programming registers to their default state.

Internal pull-up.

B30

I

Transmit enable active high input. Internal pull-down.

To enable analog output data transmission, set sif_txenable in register config3 to “1” or pull CMOS

TXENABLE

A32

I

TXENABLE pin to high.

To disable analog output, set sif_txenable to “0” and pull CMOS TXENABLE pin to low. The digital

logic section is forced to all 0, and any input data is ignored.

TESTMODE A44

VFUSE B4

I

This pin is used for factory testing. Internal pull-down. Leave unconnected for normal operation.

Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to

DACVDD for normal operation.

ORDERING INFORMATION⁽¹⁾

T_A

–40°C to 85°C

ORDER CODE

DAC3482IRKDT

DAC3482IRKDR

PACKAGE DRAWING/TYPE⁽²⁾⁽³⁾

TRANSPORT MEDIA

QUANTITY

250

RKD / 88 WQFN Quad Flatpack No-Lead

Tape and Reel

2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

(2) Thermal Pad Size: 6.4 mm x 6.4 mm

(3) MSL Peak Temperature: Level-3-260C-168 HR

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

UNIT

MIN

–0.5

MAX

DACVDD, DIGVDD, CLKVDD

1.5

V

VFUSE

1.5

Supply voltage

range⁽²⁾

IOVDD

4

AVDD, PLLAVDD

4

D[15..0]P/N, DATACLKP/N, FRAMEP/N, PARITYP/N, SYNCP/N

DACCLKP/N, OSTRP/N

IOVDD + 0.5

CLKVDD + 0.5

ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE,

TXENABLE

–0.5

IOVDD + 0.5

V

Pin voltage range⁽²⁾

IOUTIP/N, IOUTQP/N

EXTIO, BIASJ

LPF

–1.0

–0.5

0.5

AVDD + 0.5

V

AVDD + 0.5

PLLAVDD+0.5V

V

Peak input current (any input)

20

–30

85

mA

°C

Peak total input current (all inputs)

Operating free-air temperature range, T_A: DAC3482

Storage temperature range

–40

–65

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND.

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THERMAL INFORMATION

DAC3482

THERMAL METRIC⁽¹⁾

RKD PACKAGE

UNITS

(88) PINS

125

T_J

Maximum junction temperature

°C

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-case (bottom) thermal resistance⁽⁴⁾

Junction-to-board thermal resistance⁽⁵⁾

22.1

7.1

θ_JCtop

θ_JCbot

θ_JB

0.6

°C/W

4.7

ψ_JT

Junction-to-top characterization parameter⁽⁶⁾

Junction-to-board characterization parameter⁽⁷⁾

0.1

ψ_JB

4.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(6) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

6

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SLAS748A –MARCH 2011–REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS⁽¹⁾

over recommended operating free-air temperature range, nominal supplies, IOUT_FS= 20mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Resolution

16

Bits

DC ACCURACY

DNL

INL

Differential nonlinearity

Integral nonlinearity

±2

±4

LSB

1 LSB = IOUT_FS/2¹⁶

ANALOG OUTPUT

Coarse gain linearity

±0.04

±0.001

±2

LSB

%FSR

mA

Offset error

Gain error

Mid code offset

With external reference

With internal reference

±2

Gain mismatch

±2

Full scale output current

Output compliance range

Output resistance

10

20

30

–0.5

0.6

V

300

5

kΩ

Output capacitance

pF

REFERENCE OUTPUT

V_REF

Reference output voltage

Reference output current⁽²⁾

1.2

V

100

nA

REFERENCE INPUT

V_EXTIOInput voltage range

0.6

1.2 1.25

V

External Reference Mode

Input resistance

1

472

100

MΩ

kHz

pF

Small signal bandwidth

Input capacitance

TEMPERATURE COEFFICIENTS

Offset drift

±1

±15

±30

±8

ppm/°C

With external reference

With internal reference

Gain drift

Reference voltage drift

POWER SUPPLY

AVDD, IOVDD, PLLAVDD

CLKVDD, DACVDD, DIGVDD

3.14

1.14

3.3 3.46

1.2 1.26

±0.2

V

PSRR

Power supply rejection ratio

DC tested

%FSR/V

POWER CONSUMPTION

I_(AVDD)

I_(DIGVDD)

I_(DACVDD)

I_(CLKVDD)

P

Analog supply current⁽³⁾

80

390 450

30 50

85

mA

mW

mA

mW

MODE 1

Digital supply current

DAC supply current

Clock supply current

Power dissipation

Analog supply current⁽³⁾

Digital supply current

DAC supply current

Clock supply current

Power dissipation

f_DAC= 1.25GSPS, 2x interpolation, Mixer on,

QMC on, invsinc on,

PLL enabled, 20mA FS output, IF = 200MHz

95 110

882 980

I_(AVDD)

I_(DIGVDD)

I_(DACVDD)

I_(CLKVDD)

P

65

385

30

MODE 2

f_DAC= 1.25GSPS, 2x interpolation, Mixer on,

QMC on, invsinc on,

PLL disabled, 20mA FS output, IF = 200MHz

70

800

(1) Measured differentially across IOUTP/N with 25 Ω each to GND.

(2) Use an external buffer amplifier with high impedance input to drive any external load.

(3) Includes AVDD, PLLAVDD, and IOVDD

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ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS⁽¹⁾(continued)

over recommended operating free-air temperature range, nominal supplies, IOUT_FS= 20mA (unless otherwise noted)

PARAMETER

Analog supply current⁽³⁾

Digital supply current

DAC supply current

Clock supply current

Power dissipation

Analog supply current⁽³⁾

Digital supply current

DAC supply current

Clock supply current

Power dissipation

Analog supply current⁽³⁾

Digital supply current

DAC supply current

Clock supply current

Power dissipation

Analog supply current⁽³⁾

Digital supply current

DAC supply current

Clock supply current

Power dissipation

TEST CONDITIONS

MIN

TYP MAX

65

UNIT

mA

mW

mA

mW

mA

mW

mA

mW

°C

I_(AVDD)

I_(DIGVDD)

I_(DACVDD)

I_(CLKVDD)

P

MODE 3

190

15

f_DAC= 625MSPS, 2x interpolation, Mixer on,

QMC on, invsinc off,

PLL disabled, 20mA FS output, IF = 200MHz

45

515

35

I_(AVDD)

I_(DIGVDD)

I_(DACVDD)

I_(CLKVDD)

P

MODE 4

395

30

f_DAC= 1.25GSPS, 2x interpolation, Mixer on,

QMC on, invsinc on,

PLL enabled, I/Q output sleep, IF = 200MHz,

95

740

20

I_(AVDD)

I_(DIGVDD)

I_(DACVDD)

I_(CLKVDD)

P

Mode 5

10

Power-Down mode: No clock,

DAC on sleep mode (clock receiver sleep),

I/Q output sleep, static data pattern

4

10

95

I_(AVDD)

I_(DIGVDD)

I_(DACVDD)

I_(CLKVDD)

P

80

Mode 6

200

25

f_DAC= 1GSPS, 2x interpolation, Mixer off,

QMC off, invsinc off, PLL enabled, 20mA FS

output, IF = 200MHz

85

636

Operating Range

–40

25

85

8

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SLAS748A –MARCH 2011–REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LVDS INPUTS: D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, PARITYP/N⁽¹⁾

Logic high differential

V_A,B+

200

400

1000

mV

input voltage threshold

Logic low differential

V_A,B–

–200

input voltage threshold

V_COM

Z_T

Input common mode

Internal termination

1.075

1.2

110

2

V

Ω

C_L

LVDS Input capacitance

pF

Interleaved LVDS data

transfer rate

f_INTERL

1250 MSPS

Word-wide interface mode

Byte-wide interface mode

625

MSPS

312.5

f_DATA

Input data rate

CLOCK INPUT (DACCLKP/N)

Duty cycle

40%

0.4

60%

V

Differential voltage⁽²⁾

1.0

DACCLKP/N input

frequency

1250

MHz

OUTPUT STROBE (OSTRP/N)

f_OSTR= f_DACCLK/ (n x 8 x Interp) where n is any positive integer,

f_DACCLKis DACCLK frequency in MHz

f_DACCLK

(8 x interp)

/

f_OSTR

Frequency

MHz

V

Duty cycle

50%

1.0

Differential voltage

0.4

2

CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENABLE

V_IH

V_IL

I_IH

I_IL

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

CMOS input capacitance

V

0.8

40

-40

µA

pF

V

C_I

2

I_load= –100 μA

I_load= –2 mA

I_load= 100 μA

I_load= 2 mA

IOVDD – 0.2

V_OH

ALARM, SDO, SDIO

0.8 x IOVDD

V

0.2

0.5

V

V_OL

V

(1) See LVDS INPUTS section for terminology.

(2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance.

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MAX UNIT

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

DIGITAL INPUT TIMING SPECIFICATIONS

Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching

Config36 Setting

datadly

clkdly

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

150

100

50

0

-50

Setup time, D[15:0]P/N,

FRAMEP/N, SYNCP/N

and PARITYP/N, valid to

either edge of

FRAMEP/N reset and frame indicator latched

on rising edge of DATACLKP/N.

FRAMEP/N parity bit latched on falling edge

of DATACLKP/N.

-100

-150

-200

200

250

300

350

400

450

500

t_s(DATA)

ps

DATACLKP/N

Config36 Setting

datadly

clkdly

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

350

400

450

500

550

600

650

700

300

250

200

150

100

50

Hold time, D[15:0]P/N,

FRAMEP/N, SYNCP/N

and PARITYP/N, valid

after either edge of

DATACLKP/N

FRAMEP/N reset and frame indicator latched

on rising edge of DATACLKP/N.

FRAMEP/N parity bit latched on falling edge

of DATACLKP/N.

t_h(DATA)

ps

0

FRAMEP/N and

SYNCP/N pulse width

t_{(FRAME_SYNC)}

f_DATACLKis DATACLK frequency in MHz

1/2f_DATACLK

ns

10

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SLAS748A –MARCH 2011–REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING⁽³⁾

Setup time, OSTRP/N

t_s(OSTR)

valid to rising edge of

DACCLKP/N

0

ps

Hold time, OSTRP/N

valid after rising edge of

DACCLKP/N

t_h(OSTR)

300

(4)

TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING

Setup time, SYNCP/N

t_{s(SYNC_PLL)}

valid to rising edge of

DACCLKP/N

200

300

ps

Hold time, SYNCP/N

valid after rising edge of

DACCLKP/N

t_{h(SYNC_PLL)}

TIMING SERIAL PORT

Setup time, SDENB to

rising edge of SCLK

t_s(SDENB)

t_s(SDIO)

t_h(SDIO)

20

10

5

ns

Setup time, SDIO valid to

rising edge of SCLK

Hold time, SDIO valid to

rising edge of SCLK

Register config6 read (temperature sensor read)

1

µs

t_(SCLK)

Period of SCLK

All other registers

100

ns

Data output delay after

falling edge of SCLK

t_d(Data)

t_RESET

10

25

ns

Minimum RESETB pulse

width

(3) OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution

device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC3482 devices in the system.

Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.

(4) SYNC is required to synchronize the PLL circuit in multiple devices. The SYNC signal must meet the timing relationship with respect to

the reference clock (DACCLKP/N) of the on-chip PLL circuit.

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ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS

over recommended operating free-air temperature range, nominal supplies, IOUT_FS= 20mA (unless otherwise noted)

PARAMETER

ANALOG OUTPUT⁽¹⁾

TEST CONDITIONS / COMMENTS

MIN

TYP MAX UNIT

f_DAC

Maximum DAC rate

1250

MSPS

t_s(DAC)

Output settling time to 0.1%

Transition: Code 0x0000 to 0xFFFF

10

2

ns

DAC outputs are updated on the falling edge of DAC clock. Does not include

Digital Latency (see below).

t_pd

Output propagation delay

t_r(IOUT)

t_f(IOUT)

Output rise time 10% to 90%

Output fall time 90% to 10%

220

ps

No interpolation, FIFO enabled, Mixer off, QMC off, Inverse

sinc off

250

2x Interpolation

8-bit

212

372

interface

4x Interpolation

8x Interpolation

16x Interpolation

723

1440

No interpolation, FIFO enabled, Mixer off, QMC off, Inverse

sinc off

140

DAC

clock

cycles

Digital latency

2x Interpolation

4x Interpolation

8x Interpolation

16x Interpolation

228

417

817

1630

24

16-bit

interface

Fine mixer

QMC

16

Inverse sinc

20

Power-

up

Time

DAC wake-up time

DAC sleep time

IOUT current settling to 1% of IOUT_FSfrom output sleep

2

μs

IOUT current settling to less than 1% of IOUT_FSin output sleep

2

AC PERFORMANCE⁽²⁾

f_DAC= 1.25 GSPS, f_OUT= 20 MHz

f_DAC= 1.25 GSPS, f_OUT= 50 MHz

f_DAC= 1.25 GSPS, f_OUT= 70 MHz

f_DAC= 1.25 MSPS, f_OUT= 30 ± 0.5 MHz

f_DAC= 1.25 GSPS, f_OUT= 50 ± 0.5 MHz

f_DAC= 1.25 GSPS, f_OUT= 100 ± 0.5 MHz

f_DAC= 1.25 GSPS, f_OUT= 10 MHz

f_DAC= 1.25 GSPS, f_OUT= 80 MHz

f_DAC= 1.2288 GSPS, f_OUT= 30.72 MHz

f_DAC= 1.2288 GSPS, f_OUT= 153.6 MHz

f_DAC= 1.2288 GSPS, f_OUT= 30.72 MHz

f_DAC= 1.2288 GSPS, f_OUT= 153.6 MHz

f_DAC= 1.25 GSPS, f_OUT= 10 MHz

82

77

Spurious free dynamic range

(0 to f_DAC/2) tone at 0 dBFS

SFDR

dBc

72

81

Third-order two-tone

intermodulation distortion

Each tone at –12 dBFS

IMD3

NSD

79

dBc

77.5

160

155

77

Noise spectral density

Tone at 0dBFS

dBc/Hz

Adjacent channel leakage ratio,

single carrier

74

ACLR⁽³⁾

dBc

82

Alternate channel leakage ratio,

single carrier

80

Channel isolation

84

(1) Measured single ended into 50 Ω load.

(2) 4:1 transformer output termination, 50 Ω doubly terminated load

(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms

12

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TYPICAL CHARACTERISTICS

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

5

4

5

4

3

2

1

0

−1

−2

−3

−4

−5

−1

−2

−3

−4

−5

0

10k

20k

30k

Code

40k

50k

60k

0

10k

20k

30k

Code

40k

50k

60k

G001

G002

Figure 1. Integral Nonlinearity

Figure 2. Differential Nonlinearity

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

0 dBFS

−6 dBFS

−12 dBFS

0 dBFS

−6 dBFS

−12 dBFS

0

100

200

300

400

500

600

0

100

200

300

400

500

600

Output Frequency (MHz)

G003

G004

Figure 3. SFDR vs Output Frequency Over Input Scale

Figure 4. Second Harmonic Distortion vs

Output Frequency Over Input Scale

100

90

80

70

60

50

40

30

f_DATA= 312.5 MSPS, 1x Interpolation

f_DATA= 312.5 MSPS, 2x Interpolation

f_DATA= 312.5 MSPS, 4x Interpolation

f_DATA= 156.25MSPS, 8x Interpolation

f_DATA= 78.125MSPS, 16x Interpolation

0 dBFS

−6 dBFS

−12 dBFS

90

80

70

60

50

40

30

0

100

200

300

400

500

600

0

100

200

300

400

500

600

Output Frequency (MHz)

G005

G006

Figure 5. Third Harmonic Distortion vs

Output Frequency Over Input Scale

Figure 6. SFDR vs Output Frequency Over Interpolation

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

f_DAC= 600 MSPS

f_DAC= 800 MSPS

f_DAC= 1000 MSPS

f_DAC= 1250 MSPS

I_OUTFS = 10 mA w/ 4:1 Transformer

I_OUTFS = 20 mA w/ 4:1 Transformer

I_OUTFS = 30 mA w/ 2:1 Transformer

0

100

200

300

400

500

600

0

50

100

150

200

250

300

350

400

Output Frequency (MHz)

G007

G009

G011

G008

G010

G012

Figure 7. SFDR vs Output Frequency Over f_DAC

Figure 8. SFDR vs Output Frequency Over I_OUTFS

10

0

10

NCO Bypassed

QMC Bypassed

f_DAC= 1250 MSPS

f_OUT= 20 MHz

NCO Bypassed

QMC Bypassed

f_DAC= 1250 MSPS

f_OUT= 70 MHz

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−10

−20

−30

−40

−50

−60

−70

−80

−90

0

100

200

300

400

500

600

0

100

200

300

400

500

600

Frequency (MHz)

Figure 9. Single Tone Spectral Plot

Figure 10. Single Tone Spectral Plot

10

0

10

0

f_DAC= 1250 MSPS

f_OUT= 150 MHz

f_DAC= 1250 MSPS

f_OUT= 200 MHz

−10

−20

−30

−40

−50

−60

−70

−80

−90

−10

−20

−30

−40

−50

−60

−70

−80

−90

0

100

200

300

400

500

600

10

110

210

310

410

510

610

Frequency (MHz)

Figure 11. Single Tone Spectral Plot

Figure 12. Single Tone Spectral Plot

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

10

0

100

90

80

70

60

50

40

30

PLL Enabled w/ PFD of 78.125 MHz

f_DAC= 1250 MSPS

f_OUT= 200 MHz

0 dBFS

−6 dBFS

−12 dBFS

−10

−20

−30

−40

−50

−60

−70

−80

−90

10

110

210

310

410

510

610

0

100

200

300

400

500

600

Frequency (MHz)

Output Frequency (MHz)

G013

G014

Figure 13. Single Tone Spectral Plot

Figure 14. IMD3 vs Output Frequency Over Input Scale

100

90

80

70

60

50

40

30

100

f_DAC= 600 MSPS

f_DAC= 800 MSPS

f_DAC= 1000 MSPS

f_DAC= 1250 MSPS

90

80

70

60

50

40

30

f_DATA= 312.5 MSPS, 1x Interpolation

f_DATA= 312.5 MSPS, 2x Interpolation

f_DATA= 312.5 MSPS, 4x Interpolation

f_DATA= 156.25 MSPS, 8x Interpolation

f_DATA= 78.125 MSPS, 16x Interpolation

0

100

200

300

400

500

600

0

100

200

300

400

500

600

Output Frequency (MHz)

G015

G016

Figure 15. IMD3 vs Output Frequency Over Interpolation

Figure 16. IMD3 vs Output Frequency Over f_DAC

100

90

80

70

60

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

NCO Bypassed

QMC Bypassed

f_DAC= 1250 MSPS

f_OUT= 70 MHz

Tone Spacing = 1 MHz

50

I_OUTFS = 10 mA w/ 4:1 Transformer

I_OUTFS = 20 mA w/ 4:1 Transformer

I_OUTFS = 30 mA w/ 2:1 Transformer

40

30

0

50

100

150

200

250

300

350

400

65

66

67

68

69

70

71

72

73

74

75

Output Frequency (MHz)

Frequency (MHz)

G017

G018

Figure 17. IMD3 vs Output Frequency Over I_OUTFS

Figure 18. Two Tone Spectral Plot

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

170

165

160

155

150

145

140

135

130

f_DAC= 1250 MSPS

f_OUT= 200 MHz

Tone Spacing = 1 MHz

0 dBFS

−6 dBFS

−12 dBFS

195 196 197 198 199 200 201 202 203 204 205

Frequency (MHz)

0

100

200

300

400

500

600

Output Frequency (MHz)

G019

G020

Figure 19. Two Tone Spectral Plot

Figure 20. NSD vs Output Frequency Over Input Scale

170

165

160

155

150

145

140

135

130

170

f_DATA= 312.5 MSPS, 1x Interpolation

f_DATA= 312.5 MSPS, 2x Interpolation

f_DATA= 312.5 MSPS, 4x Interpolation

f_DATA= 156.25 MSPS, 8x Interpolation

f_DATA= 78.125 MSPS, 16x Interpolation

f_DAC= 600 MSPS

165

160

155

150

145

140

135

130

f_DAC= 800 MSPS

f_DAC= 1000 MSPS

f_DAC= 1250 MSPS

0

100

200

300

400

500

600

0

100

200

300

400

500

600

Output Frequency (MHz)

G021

G022

Figure 21. NSD vs Output Frequency Over Interpolation

Figure 22. NSD vs Output Frequency Over f_DAC

170

165

160

155

150

145

140

135

130

I_OUTFS = 10 mA w/ 4:1 Transformer

I_OUTFS = 20 mA w/ 4:1 Transformer

I_OUTFS = 30 mA w/ 2:1 Transformer

PLL Bypassed

PLL Enabled w/ PFD of 78.125 MHz

165

160

155

150

145

140

135

130

0

50

100

150

200

250

300

350

400

0

100

200

300

400

500

600

Output Frequency (MHz)

G023

G024

Figure 23. NSD vs Output Frequency Over I_OUTFS

Figure 24. NSD vs Output Frequency Over Clocking

Options

16

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

85

80

75

70

65

60

55

85

80

75

70

65

60

55

PLL Disabled

PLL Enabled

PLL Disabled

PLL Enabled

0

100

200

300

400

500

600

0

100

200

300

400

500

600

Output Frequency (MHz)

G025

G026

Figure 25. Single Carrier WCDMA ACLR (Adjacent) vs

Output Frequency Over Clocking Options

Figure 26. Single Carrier WCDMA ACLR (Alternate) vs

Output Frequency Over Clocking Options

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

f_OUT= 70 MHz

f_OUT= 120 MHz

G027

G028

Figure 27. Single Carrier W-CDMA Test Model 1

Figure 28. Single Carrier W-CDMA Test Model 1

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

f_OUT= 70 MHz

f_OUT= 200 MHz

G029

G030

Figure 29. Single Carrier W-CDMA Test Model 1

Figure 30. Four Carrier W-CDMA Test Model 1

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

f_OUT= 120 MHz

f_OUT= 200 MHz

G031

G032

Figure 31. Four Carrier W-CDMA Test Model 1

Figure 32. Four Carrier W-CDMA Test Model 1

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

f_OUT= 140 MHz

f_OUT= 240 MHz

G033

G034

Figure 33. 10 MHz Single Carrier LTE Test Model 3.1

Figure 34. 10 MHz Single Carrier LTE Test Model 3.1

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

4x Interpolation, 0 dBFS

f_DAC= 1228.8 MSPS

f_OUT= 140 MHz

f_OUT= 240 MHz

G035

G036

Figure 35. 20 MHz Single Carrier LTE Test Model 3.1

Figure 36. 20 MHz Single Carrier LTE Test Model 3.1

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

800

700

600

500

400

300

200

100

0

800

700

600

500

400

300

200

100

0

1x Interpolation

2x Interpolation

4x Interpolation

8x Interpolation

16x Interpolation

1x Interpolation

2x Interpolation

4x Interpolation

8x Interpolation

16x Interpolation

Bandbase Input = 5 MHz

NCO Disabled

QMC Disabled

Bandbase Input = 0 MHz

NCO Enabled w/ 5 MHz Mixing

QMC Enabled

CMIX Disabled

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

f_DAC(MSPS)

G037

G038

f_DAC(MSPS)

Figure 37. Power Consumption vs f_DACOver Interpolation

Figure 38. Power Consumption vs f_DACOver Interpolation

80

500

NCO Enabled

QMC Enabled

1x Interpolation

2x Interpolation

4x Interpolation

8x Interpolation

16x Interpolation

Bandbase Input = 5 MHz

NCO Disabled

QMC Disabled

450

400

350

300

250

200

150

100

50

70

60

50

40

30

20

10

0

CMIX Disabled

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

f_DAC(MSPS)

G039

G040

Figure 39. Power Consumption vs f_DACOver Digital

Processing Functions

Figure 40. DIGVDD Current vs f_DACOver Interpolation

400

80

1x Interpolation

2x Interpolation

4x Interpolation

8x Interpolation

16x Interpolation

NCO Enabled

QMC Enabled

350

300

250

200

150

100

50

70

60

50

40

30

20

10

0

Bandbase Input = 0 MHz

NCO Enabled w/ 5 MHz Mixing

QMC Enabled

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

f_DAC(MSPS)

G041

G042

Figure 41. DIGVDD Current vs f_DACOver Interpolation

Figure 42. DIGVDD Current vs f_DACOver Digital

Processing Functions

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC

enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer

(unless otherwise noted)

40

35

30

25

20

15

10

5

100

90

80

70

60

50

40

30

20

10

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

f_DAC(MSPS)

G043

G044

Figure 43. DACVDD Current vs f_DAC

Figure 44. CLKVDD Current vs f_DAC

100

90

80

70

60

50

40

30

20

10

0

120

110

100

90

80

70

60

50

40

30

0

200

400

600

800

1000

1200

0

50

100

150

200

250

Output Frequency (MHz)

f_DAC(MSPS)

G045

G046

Figure 45. AVDD Current vs f_DAC

Figure 46. Isolation Level vs Output Frequency

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DEFINITION OF SPECIFICATIONS

Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a

3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio.

Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the

ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.

Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB

change in the digital input code.

Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the

value at ambient (25°C) to values over the full operating temperature range.

Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output

current and the ideal full-scale output current.

Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,

determined by a straight line drawn from zero scale to full scale.

Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order

intermodulation distortion product to either fundamental output tone.

Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,

from the value at ambient (25°C) to values over the full operating temperature range.

Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output

current and the ideal mid-scale output current.

Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the

current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting

distortion performance.

Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius

from value at ambient (25°C) to values over the full operating temperature range.

Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the

output signal and the peak spurious signal within the first Nyquist zone.

Noise Spectral Density (NSD): Defined as the difference of power (in dBc) between the output tone signal

power and the noise floor of 1Hz bandwidth within the first Nyquist zone.

SERIAL INTERFACE

The serial port of the DAC3482 is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of DAC3482. It is compatible with most synchronous transfer formats and can be configured as

a 3 or 4 pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial interface input

clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in

and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device

with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte

is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit

address to be accessed. Table 1 below indicates the function of each bit in the instruction cycle and is followed

by a detailed description of each bit. The data transfer cycle consists of two bytes.

Table 1. Instruction Byte of the Serial Interface

MSB

7

LSB

0

Bit

6

5

4

3

2

1

Description

R/W

A6

A5

A4

A3

A2

A1

A0

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R/W

Identifies the following data transfer cycle as a read or write operation. A high indicates a read

operation from DAC3482 and a low indicates a write operation to DAC3482.

[A6 : A0]

Identifies the address of the register to be accessed during the read or write operation.

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REGISTER DESCRIPTIONS

Register name: config0 – Address: 0x00, Default: 0x049C

Register

Name

Default

Value

Address

Bit

Name

Function

config0

0x00

15

qmc_offset_ena

When set, the digital Quadrature Modulator Correction (QMC) offset

correction is enabled.

0

14

13

12

Reserved

Reserved for factory use.

0

qmc_corr_ena

Reserved

When set, the QMC phase and gain correction circuitry is enabled.

Reserved for factory use.

0

11:8 interp(3:0)

These bits define the interpolation factor

0100

interp

0000

0001

0010

0100

1000

Interpolation Factor

1x

2x

4x

8x

16x

7

fifo_ena

When set, the FIFO is enabled. When the FIFO is disabled

DACCCLKP/N and DATACLKP/N must be aligned (not

recommended).

1

6

5

4

Reserved

Reserved for factory use.

0

1

Reserved

alarm_out_ena

When set, the ALARM pin becomes an output. When cleared, the

ALARM pin is 3-stated.

3

2

alarm_out_pol

This bit changes the polarity of the ALARM signal.

MM 0: Negative logic

MM 1: Positive logic

1

clkdiv_sync_ena

When set, enables the syncing of the clock divider using the sync

source selected by register config32. The internal divided-down

clocks will be phase aligned after syncing. See the Power-Up

Sequence section for more detail.

1

0

invsinc_ena

Reserved

When set, the inverse sinc filter is enabled.

Reserved for factory use.

0

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Register name: config1 – Address: 0x01, Default: 0x050E

Register

www.ti.com

Default

Value

Address

Bit

Name

Function

Name

config1

0x01

15

iotest_ena

When set, enables the data pattern checker test. The outputs are

deactivated regardless of the state of TXENABLE and

sif_txenable.

0

14

13

12

Reserved

64cnt_ena

Reserved for factory use.

0

When set, enables resetting of the alarms after 64 good samples

with the goal of removing unnecessary errors. For instance, when

checking setup/hold through the pattern checker test, there may

initially be errors. Setting this bit removes the need for a SIF write to

clear the alarm register.

11

10

oddeven_parity

word_parity_ena

Selects between odd and even parity check

MM 0: Even parity

MM 1: Odd parity

0

1

When set, enables parity checking of each input word using the

PARITYP/N parity input. It should match the oddeven_parity

register setting.

9

8

frame_parity_ena

Reserved

When set, enables parity checking using the FRAME signal to

source the parity bit.

0

1

Reserved for factory use.

Note: Default value is ‘1’. Must be set to ‘0’ for proper operation

7

6

Reserved

Reserved for factory use.

0

dacI_complement

When set, the DACI output is complemented. This allows to

effectively change the + and – designations of the LVDS data lines.

5

dacQ_complement

When set, the DACQ output is complemented. This allows to

0

effectively change the + and – designations of the LVDS data lines.

4

3

Reserved

Reserved for factory use.

0

1

alarm_2away_ena

When set, the alarm from the FIFO indicating the write and read

pointers being 2 away is enabled.

2

1

0

alarm_1away_ena

alarm_collision_ena

Reserved

When set, the alarm from the FIFO indicating the write and read

pointers being 1 away is enabled.

1

0

When set, the alarm from the FIFO indicating a collision between the

write and read pointers is enabled.

Reserved for factory use.

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Register name: config2 – Address: 0x02, Default: 0x7000

Register

Name

Default

Value

Address

Bit

Name

Function

config2

0x02

15

16bit_in

When set, the input interface is set to word-wide mode.

When cleared, the input interface is set to byte-wide mode.

0

14

13

12

dacclkgone_ena

dataclkgone_ena

collisiongone_ena

When set, the DACCLK-gone signal from the clock monitor circuit can

be used to shut off the DAC outputs. The corresponding alarms,

alarm_dacclk_gone and alarm_output_gone, must not be masked

(i.e.Config7, bit <10> and bit <8> must set to "0").

1

When set, the DATACLK-gone signal from the clock monitor circuit

can be used to shut off the DAC outputs. The corresponding alarms,

alarm_dataclk_gone and alarm_output_gone, must not be masked

(i.e.Config7, bit <9> and bit <8> must set to "0").

When set, the FIFO collision alarms can be used to shut off the DAC

outputs. The corresponding alarms, alarm_fifo_collision and

alarm_output_gone, must not be masked (i.e.Config7, bit <13> and

bit <8> must set to "0").

11

10

9

Reserved

sif4_ena

Reserved for factory use.

0

8

7

When set, the serial interface (SIF) is a 4 bit interface, otherwise it is

a 3 bit interface.

6

5

4

3

mixer_ena

mixer_gain

nco_ena

revbus

When set, the mixer block is enabled.

0

When set, a 6dB gain is added to the mixer output.

When set, the NCO is enabled. This is not required for coarse mixing.

When set, the input bits for the data bus are reversed. MSB becomes

LSB.

2

1

Reserved

twos

Reserved for factory use.

0

When set, the input data format is expected to be 2’s complement.

When cleared, the input is expected to be offset-binary.

0

Reserved

Reserved for factory use.

0

Register name: config3 – Address: 0x03, Default: 0xF000

Register

Name

Default

Value

Address

Bit

Name

Function

config3

0x03

15:12 coarse_dac(3:0)

Scales the output current in 16 equal steps.

1111

V_EXTIO

I_FS

=

´ 2´ coarse _ dac +1

(

)

R_BIAS

11:8

7:1

0

Reserved

sif_txenable

Reserved for factory use.

0000

0000000

0

Reserved for factory use.

When set, the internal value of TXENABLE is set to “1”.

To enable analog output data transmission, set sif_txenable to “1” or

pull CMOS TXENABLE pin (A32) to high. To disable analog output,

set sif_txenable to “0” and pull CMOS TXENABLE pin (A32) to low.

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Register name: config4 – Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)

Register

Name

Default

Value

Address

Bit

Name

Function

config4

0x04

15:0

iotest_results(15:0)

This register is used with pattern checker test enabled (iotest_ena in config1,

bit<15> set to “1”). It does not have a default RESET value.

No RESET

Value

The values of these bits tell which bit in the word failed during the pattern

checker test. iotest_results(15:8) correspond to the data bits on D[15:8] and

iotest_results(7:0) correspond to the data bits on D[7:0].

Register name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO

CLEAR)

Register Address

Name

Default

Value

Bit

Name

Function

config5

0x05

15

alarm_from_zerochk

This alarm indicates the 8-bit FIFO write pointer address has an all

zeros patterns. Due to pointer address being a shift register, this is

not a valid address and will cause the write pointer to be stuck until

the next sync. This error is typically caused by timing error or

improper power start-up sequence. If this alarm is asserted,

resynchronization of FIFO is necessary. Refer to the Power-Up

Sequence section for more detail.

NA

14

Reserved

Reserved for factory use.

NA

13:11 alarms_from_fifo(2:0)

Alarm indicating FIFO pointer collisions and nearness:

MM 000: All fine

MM 001: Pointers are 2 away

MM 01x: Pointers are 1 away

MM 1xx: FIFO pointer collision

If the FIFO pointer collision alarm is set when collisiongone_ena is

enabled, the FIFO must be re-synchronized and the bits must be

cleared to resume normal operation.

10

9

alarm_dacclk_gone

alarm_dataclk_gone

Alarm indicating the DACCLK has been stopped. If the bit is set

when dacclkgone_ena is enabled, the DACCLK must resume and

the bit must be cleared to resume normal operation.

NA

Alarm indicating the DATACLK has been stopped.

If the bit is set when dataclkgone_ena is enabled, the DATACLK

must resume and the bit must be cleared to resume normal

operation.

8

7

alarm_output_gone

alarm_from_iotest

Alarm indicating either alarm_dacclk_gone, alarm_dataclk_gone, or

alarm_fifo_collision are asserted. It controls the output. When high it

will output "0x8000" for each output connected to the DAC. If the bit

is set when dacclkgone_ena, dataclkgone_ena, or

collisiongone_ena are enabled, then the corresponding errors must

be fixed and the bits must be cleared to resume normal operation.

NA

Alarm indicating the input data pattern does not match the pattern in

the iotest_pattern registers. When data pattern checker mode is

enabled, this alarm in register config5, bit7 is the only valid alarm.

Other alarms in register config5 are not valid and can be

disregarded.

6

5

Reserved

Reserved for factory use.

NA

alarm_from_pll

Alarm indicating the PLL has lost lock. For version ID "100" or

earlier, alarm_from_PLL may not indicate the correct status of the

PLL. Refer to pll_lfvolt(2:0) in register config24 for proper PLL lock

indication.

4

3

alarm_rparity

alarm_fparity

Alarm indicating a parity error on data captured on the rising edge

of DATACLKP/N.

NA

Alarm indicating a parity error on data captured on the falling edge

of DATACLKP/N.

2

1

0

alarm_frame_parity

Reserved

Alarm indicating a parity error when using the FRAME as parity bit.

Reserved for factory use.

NA

Reserved

Reserved for factory use.

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Register name: config6 – Address: 0x06, Default: No RESET Value (READ ONLY)

Register

Name

Default

Value

Address

Bit

Name

tempdata(7:0)

Function

config6

0x06

15:8

This is the output from the chip temperature sensor. The value of this register in

two’s complement format represents the temperature in degrees Celsius. This

register must be read with a minimum SCLK period of 1μs.

No

RESET

Value

7:2

1

Reserved

Reserved for factory use.

000000

0

Register name: config7 – Address: 0x07, Default: 0xFFFF

Register

Name

Default

Value

Address

Bit

Name

Function

config7

0x07

15:0 alarms_mask(15:0)

These bits control the masking of the alarms. (0=not masked, 1= masked)

0xFFFF

alarm_mask

Alarm that is Masked

alarm_from_zerochk

not used

15

14

13

12

11

10

9

alarm_fifo_collision

alarm_fifo_1away

alarm_fifo_2away

alarm_dacclk_gone

alarm_dataclk_gone

alarm_output_gone

alarm_from_iotest

not used

8

7

6

5

alarm_from_pll

alarm_rparity

4

3

alarm_lparity

2

alarm_frame_parity

not used

1

0

not used

Register name: config8 – Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config8

0x08

15

14

13

Reserved for factory use.

0

Reserved

0

12:0 qmc_offsetI(12:0)

DACI offset correction. The offset is measured in DAC LSBs. If enabled in config30

writing to this register causes an auto-sync to be generated. This loads the values of

the QMC offset registers (config8-config9) into the offset block at the same time.

When updating the offset values config8 should be written last. Programming

config9 will not affect the offset setting.

All zeros

Register name: config9 – Address: 0x09, Default: 0x8000

Register

Name

Default

Value

Address

Bit

Name

Function

config9

0x09

15:13 fifo_offset(2:0)

When the sync to the FIFO occurs, this is the value loaded into the FIFO read pointer. With

this value the initial difference between write and read pointers can be controlled. This may

be helpful in syncing multiple chips or controlling the delay through the device.

100

12:0 qmc_offsetQ(12:0)

DACQ offset correction. The offset is measured in DAC LSBs.

All zeros

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Register name: config10 – Address: 0x0A, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config10

0x0A

15

14

Reserved for factory use.

0

Reserved

0

13

12:0

All zeros

Register name: config11 – Address: 0x0B, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Reserved

config10

0x0A

15

14

Reserved for factory use.

0

Reserved

0

13

12:0

All zeros

Register name: config12 – Address: 0x0C, Default: 0x0400

Register

Name

Default

Value

Address

Bit

Name

Reserved

config12

0x0C

15

14

Reserved for factory use.

0

Reserved

13

Reserved

12

Reserved

11

Reserved

10:0

qmc_gainI(10:0)

QMC gain for DACI. The full 11-bit qmc_gainI(10:0) word is formatted as UNSIGNED

with a range of 0 to 1.9990. The implied decimal point for the multiplication is between bit

9 and bit 10.

10000000

000

Register name: config13 – Address: 0x0D, Default: 0x0400

Register

Name

Default

Value

Address

Bit

Name

Function

Sets the mixing function of the coarse mixer.

config13

0x0D

15

cmix_mode(3:0)

0000

MM Bit 15: Fs/8 mixer

MM Bit 14: Fs/4 mixer

MM Bit 13: Fs/2 mixer

MM Bit 12: -Fs/4 mixer

The various mixers can be combined together to obtain a ±n×Fs/8 total mixing factor.

11

Reserved

Reserved for factory use.

0

10:0

qmc_gainQ(10:0)

QMC gain for DACQ. The full 11-bit qmc_gainb(10:0) word is formatted as UNSIGNED

with a range of 0 to 1.9990. The implied decimal point for the multiplication is between

bit 9 and bit 10.

10000000

000

Register name: config14 – Address: 0x0E, Default: 0x0400

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config14

0x0E

15

14

Reserved for factory use.

0

Reserved

13

12

11

10:0

10000000

000

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Register name: config15 – Address: 0x0F, Default: 0x0400

Register

Name

Default

Value

Address

Bit

Name

Function

config15

0x0F

15:14 output_ delay(1:0)

13:12 Reserved

Delays the DAC outputs from 0 to 3 DAC clock cycles.

Reserved for factory use.

00

0

11

Reserved

Reserved for factory use.

10:0

Reserved for factory use.

10000000

000

Register name: config16 – Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config16

0x10

15

14

13

Reserved for factory use.

0

Reserved

Reserved for factory use. Note: Default value is ‘0’. Must be set to ‘1’ for proper

operation

12

Reserved

Reserved for factory use. Note: Default value is ‘0’. Must be set to ‘1’ for proper

0

operation

11:0

qmc_phase(11:0)

QMC correction phase. The 12-bit qmc_phase(11:0) word is formatted as two’s

complement and scaled to occupy a range of -0.5 to 0.49975 and a default phase

correction of 0.00. To accomplish QMC phase correction, this value is multiplied by

the current B sample, then summed into the A sample. If enabled in config30

writing to this register causes an auto-sync to be generated. This loads the

values of the QMC offset registers (config12, config13, and config16) into the

QMC block at the same time. When updating the QMC values config16 should

be written last. Programming config12 and config13 will not affect the QMC

settings.

All zeros

Register name: config17 – Address: 0x11, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config17

0x11

15

14

Reserved for factory use.

0

Reserved

0

13

0

12

11:0

All zeros

Register name: config18 – Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)

Register

Name

Default

Value

Address

Bit

Name

Function

config18

0x12

15:0

phase_offset(15:0)

Phase offset added to the NCO accumulator before the generation of the SIN and

COS values. The phase offset is added to the upper 16 bits of the NCO accumulator

results and these 16 bits are used in the sin/cos lookup tables. If enabled in

config31 writing to this register causes an auto-sync to be generated. This

loads the values of the Qfine mixer block registers (config18, config20, and

config21) at the same time. When updating the mixer values the config18

should be written last. Programming config20 and config21 will not affect the

mixer settings.

0x0000

Register name: config19 – Address: 0x13, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config19

0x13

15:0

Reserved for factory use.

0x0000

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Register name: config20 – Address: 0x14, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Function

config20

0x14

15:0

phase_ add(15:0)

The phase_add(15:0) value is used to determine the NCO frequency. The two’s

complement formatted value can be positive or negative. Each LSB represents

Fs/(2^32) frequency step.

0x0000

Register name: config21 – Address: 0x15, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Function

config21

0x15

15:0

phase_ add(31:16)

See config20 above.

0x0000

Register name: config22 – Address: 0x16, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Reserved

config22

0x16

15:0

Reserved for factory use.

0x0000

Register name: config23 – Address: 0x17, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Reserved

config23

0x17

15:0

Reserved for factory use.

0x0000

Register name: config24 – Address: 0x18, Default: NA

Register

Name

Default

Value

Address

Bit

Name

config24

0x18

15:13

12

Reserved

pll_reset

Reserved for factory use.

001

0

When set, the PLL loop filter (LPF) is pulled down to 0V. Toggle from ‘1’ to ‘0’ to

restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the

process is fast, the supplies are higher than nominal, etc. resulting in the feedback

dividers missing a clock.

11

10

pll_ndivsync_ena

pll_ena

When set, the LVDS SYNC input is used to sync the PLL N dividers.

When set, the PLL is enabled. When cleared, the PLL is bypassed.

Reserved for factory use.

1

0

9:8

7:6

Reserved

00

pll_cp(1:0)

PLL pump charge select

MM 00: No charge pump

MM 01: Single pump charge

MM 10: Not used

MM 11: Dual pump charge

5:3

pll_p(2:0)

PLL pre-scaler dividing module control.

001

MM 010: 2

MM 011: 3

MM 100: 4

MM 101: 5

MM 110: 6

MM 111: 7

MM 000: 8

2:0

pll_lfvolt(2:0)

PLL loop filter voltage. This three bit read-only indicator has step size of 0.4125V.

The entire range covers from 0V to 3.3V. The optimal lock range of the PLL will be

from 010 to 101 (i.e. 0.825V to 2.063V). Adjust pll_vco(5:0) for optimal lock range.

NA

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Register name: config25 – Address: 0x19, Default: 0x0440

Register

Name

Default

Value

Address

Bit

Name

pll_m(7:0)

Function

M portion of the M/N divider of the PLL.

config25

0x19

15:8

00000100

If pll_m<7> = 0, the M divider value has the range of pll_m<6:0>, spanning from

4 to 127. (i.e. 0, 1, 2, and 3 are not valid.)

If pll_m<7> = 1, the M divider value has the range of 2 × pll_m<6:0>, spanning

from 8 to 254. (i.e. 0, 2, 4, and 6 are not valid. M divider has even values only.)

7:4

pll_n(3:0)

N portion of the M/N divider of the PLL.

MM 0000: 1

0100

MM 0001: 2

MM 0010: 3

MM 0011: 4

MM 0100: 5

MM 0101: 6

MM 0110: 7

MM 0111: 8

MM 1000: 9

MM 1001: 10

MM 1010: 11

MM 1011: 12

MM 1100: 13

MM 1101: 14

MM 1110: 15

MM 1111: 16

3:2

1:0

pll_vcoitune(1:0)

Reserved

PLL VCO bias tuning bits. Set to "01" for normal PLL operation.

Reserved for factory use.

00

Register name: config26 – Address: 0x1A, Default: 0x0020

Register

Name

Default

Value

Address

Bit

Name

pll_vco(6:0)

Function

config26

0x1A

15:10

VCO frequency coarse tuning bits.

Reserved for factory use.

000000

9

8

7

6

5

4

Reserved

0

1

0

Reserved

Reserved for factory use.

bias_sleep

tsense_sleep

pll_sleep

When set, the bias amplifier is put into sleep mode.

Turns off the temperature sensor when asserted.

When set, the PLL is put into sleep mode.

clkrecv_sleep

When asserted the clock input receiver gets put into sleep mode. This affects the

OSTR receiver as well.

3

2

1

0

Reserved

Reserved for factory use.

0

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Register name: config27 – Address: 0x1B, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

extref_ena

Function

config27

0x1B

15

Allows the device to use an external reference or the internal reference.

MM 0: Internal reference

0

MM 1: External reference

14

13

12

11

Reserved

fuse_sleep

Reserved for factory use.

0

Puts the fuses to sleep when set high.

Note: Default value is ‘0’. Must be set to ‘1’ for proper operation

10

9

Reserved

Reserved for factory use.

0

8

0

7

0

6

5:0

000000

Register name: config28 – Address: 0x1C, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Function

config28

0x1C

15:8

7:0

Reserved

Reserved for factory use.

0x00

Register name: config29 – Address: 0x1D, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

config29

0x1D

15:8

7:0

Reserved

Reserved for factory use.

0x00

Register name: config30 – Address: 0x1E, Default: 0x1111

Register

Name

Default

Value

Address

Bit

Name

config30

0x1E

15:12 syncsel_qmoffset(3:0)

Selects the syncing source(s) of the double buffered QMC offset registers. A ‘1’ in

the bit enables the signal as a sync source. More than one sync source is

permitted.

0001

MM Bit 15: sif_sync (via config31)

MM Bit 14: SYNC

MM Bit 13: OSTR

MM Bit 12: Auto-sync from register write

11:8

7:4

Reserved

Reserved for factory use.

0001

syncsel_qmcorr(3:0)

Selects the syncing source(s) of the double buffered QMC correction registers. A ‘1’

in the bit enables the signal as a sync source. More than one sync source is

permitted.

MM Bit 7: sif_sync (via config31)

MM Bit 6: SYNC

0001

MM Bit 5: OSTR

MM Bit 4: Auto-sync from register write

3:0

Reserved

Reserved for factory use.

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Register name: config31 – Address: 0x1F, Default: 0x1140

Register

Name

Default

Value

Address

Bit

Name

Function

config31

0x1F

15:12 syncsel_mixer(3:0)

Selects the syncing source(s) of the double buffered mixer registers. A ‘1’ in the

0001

bit enables the signal as a sync source. More than one sync source is permitted.

MM Bit 15: sif_sync (via config31)

MM Bit 14: SYNC

MM Bit 13: OSTR

MM Bit 12: Auto-sync from register write

11:8

7:4

Reserved

Reserved for factory use.

0001

0100

syncsel_nco(3:0)

Selects the syncing source(s) of the two NCO accumulators. A ‘1’ in the bit

enables the signal as a sync source. More than one sync source is permitted.

MM Bit 7: sif_sync (via config31)

MM Bit 6: SYNC

MM Bit 5: OSTR

MM Bit 4: FRAME

3:2

syncsel_dataformatter

Selects the syncing source of the data formatter. Unlike the other syncs only

one sync source is allowed.

00

MM 00: FRAME

MM 01: SYNC

MM 10: No sync

MM 11: No sync

1

0

sif_sync

SIF created sync signal. Set to ‘1’ to cause a sync and then clear to ‘0’ to

remove it.

0

Reserved

Reserved for factory use.

Register name: config32 – Address: 0x20, Default: 0x2400

Register

Name

Default

Value

Address

Bit

Name

Function

config32

0x20

15:12

syncsel_fifoin(3:0)

Selects the syncing source(s) of the FIFO input side. A ‘1’ in the bit enables the

0010

signal as a sync source. More than one sync source is permitted.

MM Bit 15: sif_sync (via config31)

MM Bit 14: Always zero

MM Bit 13: FRAME

MM Bit 12: SYNC

11:8

syncsel_fifoout(3:0)

Selects the syncing source(s) of the FIFO output side. A ‘1’ in the bit enables the

0100

signal as a sync source. More than one sync source is permitted.

MM Bit 11: sif_sync (via config31)

MM Bit 10: OSTR – Dual Sync Sources Mode

MM Bit 9: FRAME – Single Sync Source mode

MM Bit 8: SYNC – Single Sync Source mode

7:1

0

Reserved

Reserved for factory use.

0000

0

clkdiv_sync_sel

Selects the signal source for clock divider synchronization.

clkdiv_sync_sel

Sync Source

0

1

OSTR

FRAME or SYNC, based on syncsel_fifoin source

selection (config32, bit<15:12>)

Register name: config33 – Address: 0x21, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config33

0x21

15:0

Reserved for factory use.

0x0000

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Register name: config34 – Address: 0x22, Default: 0x1B1B

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config34

0x22

15:14

13:12

11:10

9:8

Reserved for factory use.

00

01

10

11

00

01

10

11

Reserved

7:6

5:4

3:2

1:0

Register name: config35 – Address: 0x23, Default: 0xFFFF

Register

Name

Default

Value

Address

Bit

Name

Function

config35

0x23

15:0

sleep_cntl(15:0)

Controls the routing of the CMOS SLEEP signal (pin B40) to different blocks. When a

bit is set, the SLEEP signal will be sent to the corresponding block. These bits do not

override the SIF bits in register config26.

0xFFFF

sleep_cntl(bit)

Function

reserved

15

14

DACI sleep

13

DACQ sleep

reserved

12

11

Clock receiver sleep

PLL sleep

10

9

LVDS data sleep

LVDS control sleep

Temp sensor sleep

reserved

8

7

6

5

Bias amplifier sleep

not used

All others

Register name: config36 – Address: 0x24, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Function

config36

0x24

15:13 datadly(2:0)

Controls the delay of the data inputs through the LVDS receivers. Each LSB adds

approximately 40 ps

000

MM 0: Minimum

12:10 clkdly(2:0)

Controls the delay of the data clock through the LVDS receivers. Each LSB adds

approximately 40 ps

000

MM 0: Minimum

9:0

Reserved

Reserved for factory use.

0x000

Register name: config37 – Address: 0x25, Default: 0x7A7A

Register

Name

Default

Value

Address

Bit

Name

Function

config37

0x25

15:0

iotest_pattern0

Dataword0 in the IO test pattern. It is used with the seven other words to test the input data.

0x7A7A

At the start of the IO test pattern, this word should be aligned with rising edge of FRAME or

SYNC signal to indicate sample 0.

Register name: config38 – Address: 0x26, Default: 0xB6B6

Register

Name

Default

Value

Address

Bit

Name

Function

config38

0x26

15:0

iotest_pattern1

Dataword1 in the IO test pattern. It is used with the seven other words to test the input data.

0xB6B6

38

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Register name: config39 – Address: 0x27, Default: 0xEAEA

Register

Name

Default

Value

Address

Bit

Name

Function

config39

0x27

15:0

iotest_pattern2

Dataword2 in the IO test pattern. It is used with the seven other words to test the input

data.

0xEAEA

Register name: config40 – Address: 0x28, Default: 0x4545

Register

Name

Default

Value

Address

Bit

Name

Function

config40

0x28

15:0

iotest_pattern3

Dataword3 in the IO test pattern. It is used with the seven other words to test the input data.

0x4545

Register name: config41 – Address: 0x29, Default: 0x1A1A

Register

Name

Default

Value

Address

Bit

Name

Function

config41

0x29

15:0

iotest_pattern4 Dataword4 in the IO test pattern. It is used with the seven other words to test the input data.

0x1A1A

Register name: config42 – Address: 0x2A, Default: 0x1616

Register

Name

Default

Value

Address

Bit

Name

Function

config42

0x2A

15:0

iotest_pattern5

Dataword5 in the IO test pattern. It is used with the seven other words to test the input

data.

0x1616

Register name: config43 – Address: 0x2B, Default: 0xAAAA

Register

Name

Default

Value

Address

Bit

Name

Function

config43

0x2B

15:0

iotest_pattern6

Dataword6 in the IO test pattern. It is used with the seven other words to test the input

data.

0xAAAA

Register name: config44 – Address: 0x2C, Default: 0xC6C6

Register

Name

Default

Value

Address

Bit

Name

Function

config44

0x2C

15:0

iotest_pattern7

Dataword7 in the IO test pattern. It is used with the seven other words to test the input

data.

0xC6C6

Register name: config45 – Address: 0x2D, Default: 0x0004

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

config45

0x2D

15

14

Reserved for factory use.

0

ostrtodig_sel

When set, the OSTR signal is passed directly to the digital block. This is the signal that

is used to clock the dividers.

13

ramp_ena

Reserved

When set, a ramp signal is inserted in the input data at the FIFO input.

Reserved for factory use.

0

12:1

0000

0100

0

sifdac_ena

When set, the DAC output is set to the value in sifdac(15:0) in register config48.

0

Register name: config46 – Address: 0x2E, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Function

config46

0x2E

15:8

7:0

Reserved

grp_delayI(7:0)

Reserved for factory use.

0x00

Sets the group delay function for DACI. The maximum delay ranges from 30ps to

100ps and is dependent on DAC sample clock. Contact TI for specific application

information.

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Register name: config47 – Address: 0x2F, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

Function

config47

0x2F

15:8

grp_delayQ(7:0)

Sets the group delay function for DACQ. The maximum delay ranges from 30ps to

100ps and is dependent on DAC sample clock. Contact TI for specific application

information.

0x00

7:0

Reserved

Reserved for factory use.

0x00

Register name: config48 – Address: 0x30, Default: 0x0000

Register

Name

Default

Value

Address

Bit

Name

sifdac(15:0)

Function

config48

0x30

15:0

Value sent to the DACs when sifdac_ena is asserted. DATACLK must be running to

0x0000

latch this value into the DACs. The format would be based on twos in register config2.

Register name: version– Address: 0x7F, Default: 0x5409 (READ ONLY)

Register

Name

Default

Value

Address

Bit

Name

Function

version

0x7F

15:10

9

Reserved

Reserved for factory use.

Returns ‘01’ for DAC3482.

010101

0

8:7

6:5

4:3

2:0

00

deviceid(1:0)

versionid(2:0)

01

A hardwired register that contains the version of the chip.

100

40

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DATA INTERFACE

The DAC3482 has a 16-bit LVDS bus that accepts 16-bit I and Q data in either word-wide or byte-wide formats.

In word-wide mode data is sent through a 16-bit bus while in byte-wide mode an 8-bit bus is used. The selection

between the two modes is done through 16bit_in in the config2 register. The LVDS bus inputs in each mode are

shown in Table 3.

Table 3. LVDS Bus Input Assignment

Input Mode

Word-wide

Byte-wide⁽¹⁾

Pins

D[15..0]

D[7..0]

(1) The unused pins can be left floating. For word-by-word parity and IO

pattern checker functionality, the pins need to have known logic

values for valid functionality.

Data is sampled by the LVDS double data rate (DDR) clock DATACLK. Setup and hold requirements must be

met for proper sampling.

For both input bus modes, a sync signal, either FRAME or SYNC, can sync the FIFO read and/or write pointers.

In byte-wide mode the sync source is needed to establish the correct sample boundaries.

The sync signal, either FRAME or SYNC, can be either a pulse or a periodic signal where the sync period

corresponds to multiples of 8 samples. FRAME or SYNC is sampled by a rising edge in DATACLK. The

pulse-width (t_{(FRAME_SYNC)}) needs to be at least equal to ½ of the DATACLK period.

For both input bus mode, the value in FRAME sampled by the next falling edge in DATACLK can be used as a

block parity value. This feature is enabled by setting frame_parity_ena in register config1 to “1”. Refer to “Parity

Check Test” section for more detail

WORD-WIDE FORMAT

The word-wide format is selected by setting 16bit_in to “1” in the config2 register. In this mode the 16-bit data for

channels I and Q is word-wide interleaved in the form I₀, Q₀, I₁, Q₁… into the D[15:0] 16-bit bus. Data into the

DAC3482 is formatted according to the diagram shown in Figure 49 where index 0 is the data LSB and index 15

is the data MSB.

SAMPLE 0

SAMPLE 1

SAMPLE 2

SAMPLE 3

I₀

Q₀

[15:0]

I₁

Q₁

[15:0]

I₂

Q₂

[15:0]

I₃

Q₃

[15:0]

D[15:0]P/N

[15:0]

DATACLKP/N (DDR)

t_{(FRAME_SYNC)}

Sync

FRAMEP/N

Option #1

Optional

Parity Bit

t_{(FRAME_SYNC)}

Sync

SYNCP/N

Option #2

T0523-01

Figure 49. Word-Wide Data Transmission Format

For word-wide format only. The FIFO read and write pointers can also be synced by SIF SYNC as the third

option if multi-device synchronization is not needed. In this sync mode, syncsel_data_formatter(1:0) in register

config32 can be set to "10" or "11". The syncsel_fifoin(3:0) and syncsel_fifoout(3:0) in register config32 need to

be both set to "1000" for the SIF SYNC option.

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BYTE-WIDE FORMAT

The byte-wide format is selected by setting 16bit_in to “0” in the config2 register. In this mode the 16-bit data for

channels I and Q is byte-wide interleaved in the form I₀[15:8], I₀[7:0], Q₀[15:8], Q₀[7:0], I₁[15:8]… into the D[7:0]

8-bit bus. Data into the DAC3482 is formatted according to the diagram shown in Figure 50 where index 0 is the

data LSB and index 15 is the data MSB. A rising edge transition of the sync signal, either FRAME or SYNC, is

used to establish the correct sample boundaries.

SAMPLE 0

SAMPLE 1

I₀

Q₀

[15:8]

Q₀

I₁

Q₁

[15:8]

Q₁

D[7:0]P/N

DATACLKP/N (DDR)

FRAMEP/N

[15:8]

[7:0]

[15:8]

[7:0]

t_{(FRAME_SYNC)}

Sync

Option #1

Optional

Parity Bit

t_{(FRAME_SYNC)}

Sync

Option #2

SYNCP/N

T0524-01

Figure 50. Byte-Wide Data Transmission Format

INPUT FIFO

The DAC3482 includes a 2-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic buffer.

The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data

rate clock such as the ones resulting from clock-to-data variations from the data source.

Figure 51 shows a simplified block diagram of the FIFO.

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Clock Handoff

Input Side

Clocked by DATACLK

Output Side

Clocked by FIFO Out Clock

Word Wide Mode: DACCLK/2/Interpolation Factor

Byte Wide Mode: DACCLK/Interpolation Factor

FIFO:

2 x 16-Bits Wide

8-Samples deep

Initial

Position

Sample 0

I₀[15:0], Q₀[15:0]

0

1

2

3

4

5

6

7

0

16-Bit

I-Data, 16-Bit

DATA

FIFO I Output

Sample 1

I₁[15:0], Q₁[15:0]

1

32-Bit

Frame Align

Sample 2

I₂[15:0], Q₂[15:0]

16-Bit

2

Q-Data, 16-Bit

FIFO Q Output

Sample 3

I₃[15:0], Q₃[15:0]

3

Initial

Position

4

Sample 4

I₄[15:0], Q₄[15:0]

FRAME/

SYNC

Sample 5

I₅[15:0], Q₅[15:0]

5

Write Pointer Reset

Sample 6

I₆[15:0], Q₆[15:0]

Read Pointer Reset

6

7

Sample 7

I₇[15:0], Q₇[15:0]

FIFO Reset

fifo_offset(2:0)

syncsel_fifoout

S

M

OSTR

syncsel_fifoin

S (Single Sync Source Mode): Reset handoff from

input side to output side

M (Dual Sync Source Mode): OSTR resets read

pointer. Allows Multi-DAC synchronization

B0451-01

Figure 51. DAC3482 FIFO Block Diagram

Data is written to the device on the rising and falling edges of DATACLK. Each 32-bit wide sample (16-bit I-data

and 16-bit Q-data) is written into the FIFO at the address indicated by the write pointer. Similarly, data from the

FIFO is read by the FIFO Out Clock 32-bits at a time from the address indicated by the read pointer. The FIFO

Out Clock is generated internally from the DACCLK signal. Its rate is equal to DACCLK/2/Interpolation for

word-wide data transmission, or DACCLK/Interpolation for byte-wide data transmission. Each time a FIFO write

or FIFO read is done the corresponding pointer moves to the next address.

The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in

Figure 51. This offset gives optimal margin within the FIFO. The default read pointer location can be set to

another value using fifo_offset(2:0) in register config3 (address 4 by default). Under normal conditions data is

written-to and read-from the FIFO at the same rate and consequently the write and read pointer gap remains

constant. If the FIFO write and read rates are different, the corresponding pointers will be cycling at different

speeds which could result in pointer collision. Under this condition the FIFO attempts to read and write data from

the same address at the same time which will result in errors and thus must be avoided.

The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either

FRAME or SYNC is used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising

edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.

Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be

set to reset the read pointer as well. In this case, the FIFO Out clock will recapture the write pointer sync signal

to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of

the reset signal. This limits the precise control of the output timing and makes full synchronization of multiple

devices difficult.

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To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write

pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing

requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock

distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the

DAC3482 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones

establishes proper phase relationship.

The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers

automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, the

signals to sync the FIFO read and write pointer can repeat at multiples of 8 FIFO samples when the data

interface is byte-wide format. When the data interface is word-wide format, the signal to sync the FIFO read and

write pointer can repeat at multiples of 16 FIFO samples.

The frequency limitation for FRAME and SYNC signals are the following:

f_sync= f_DATACLK/(n x 16) where n = 1, 2, … can repeat multiples of 8 FIFO samples for Byte-Wide Mode

f_sync= f_DATACLK/(n x 16) where n = 1, 2, … can repeat multiples of 16 FIFO samples for Word-Wide Mode

The frequency limitation for the OSTR signal is the following:

f_OSTR= f_DAC/(n x interpolation x 8) where n = 1, 2, … can repeat multiples of 8 FIFO samples for Byte-Wide

Mode

f_OSTR= f_DAC/(n x interpolation x 16) where n = 1, 2, … can repeat multiples of 16 FIFO samples for

World-Wide Mode

The frequencies above are at maximum when n = 1. This is when the FRAME, SYNC, or OSTR have a rising

edge transition every 8 or 16 FIFO samples. The occurrence can be made less frequent by setting n > 1, for

example, every n × 8 or n × 16 FIFO samples.

D[15:0]P/N

t_S(DATA)

t_H(DATA)

t_S(DATA)

t_H(DATA)

DATACLKP/N

(DDR)

t_H(DATA)

t_S(DATA)

FRAMEP/N

SYNCP/N

Resets Write Pointer to Position 0

DACCLKP/N

1x Interpolation

t_S(OSTR)

t_H(OSTR)

OSTRP/N

(optionally internal

sync from Write Reset)

Resets Read Pointer to Position

Set by fifo_offset (4 by Default)

T0525-01

Figure 52. FIFO Write and Read Descriptions (Example shown with Word-Wide Mode)

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FIFO MODES OF OPERATION

The DAC3482 input FIFO can be completely bypassed through registers config0 and config32. The register

configuration for each mode is described in Table 4.

Register

config0

Control Bits

fifo_ena

config32

syncsel_fifoout(3:0)

Table 4. FIFO Operation Modes

config0 and config32 FIFO Bits

syncsel_fifoout

FIFO Mode

fifo_ena

Bit 3: sif_sync

Bit 2: OSTR

Bit 1: FRAME

Bit 0: SYNC

Dual Sync Sources

1

0

X

1

0

Single Sync

Source

1 or 0 Depends on the sync

source

1 or 0 Depends on the

sync source

0

Bypass

X

DUAL SYNC SOURCES MODE

This is the recommended mode of operation for those applications that require precise control of the output

timing. In Dual Sync Sources mode, the FIFO write and read pointers are reset independently. The FIFO write

pointer is reset using the LVDS FRAME or SYNC signal, and the FIFO read pointer is reset using the LVPECL

OSTR signal. This allows LVPECL OSTR signal to control the phase of the output for either a single chip or

multiple chips. Multiple devices can be fully synchronized in this mode.

SINGLE SYNC SOURCE MODE

In Single Sync Source mode, the FIFO write and read pointers are reset from the same source, either LVDS

FRAME or LVDS SYNC signal. This mode has a possibility of up to 2 DAC clocks offset between the multiple

DAC outputs. Applications requiring exact output timing control will need Dual Sync Sources mode instead of

Single Sync Source Mode. A single rising edge for FIFO and clock divider sync is recommended. Periodic sync

signal is not recommended due to non-deterministic latency of the sync signal through the clock domain transfer.

BYPASS MODE

In FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK to

the DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK

is critical and used as a synchronizing mechanism for the internal logic. Due to this constraint this mode is not

recommended. In bypass mode the pointers have no effect on the data path or handoff.

CLOCKING MODES

The DAC3482 has a dual clock setup in which a DAC clock signal is used to clock the DAC cores and internal

digital logic and a separate DATA clock is used to clock the input LVDS receivers and FIFO input. The DAC3482

DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL).

In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC

clock directly from a high-quality external clock to the DACCLK input. In most applications system clocking can

be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance

requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.

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16-Bit

DACI

PLL

DACCLK

Clock Distribution

to Digital

16-Bit

DACQ

VCO/

Dividers

pll_ena

B0452-01

Figure 53. Top Level Clock Diagram

PLL BYPASS MODE

In PLL bypass mode a very high quality clock is sourced to the DACCLK inputs. This clock is used to directly

clock the DAC3482 DAC sample rate clock. This mode gives the device best performance and is recommended

for extremely demanding applications.

The bypass mode is selected by setting the following:

1. pll_ena bit in register config24 to “0” to bypass the PLL circuitry.

2. pll_sleep bit in register config26 to “1” to put the PLL and VCO into sleep mode.

PLL MODE

In this mode the clock at the DACCLK input functions as a reference clock source to the on-chip PLL. The

on-chip PLL will then multiply this reference clock to supply a higher frequency DAC sample rate clock. Figure 54

shows the block diagram of the PLL circuit.

OSTR (Internally Generated)

External Loop

Filter

DACCLKP

REFCLK

DACCLKN

PFD

and

CP

N

Divider

Prescaler

DACCLK

SYNCP

SYNCN

SYNC_PLL

VCO

Internal Loop

Filter

Note:

The PLL generates internal OSTR signal. In this mode

external LVPECL OSTR signal is not required.

M

Divider

If the DAC is configured with PLL enabled with Dual Sync

Sources mode, then the PFD frequency has to be the pre-

defined OSTR frequency.

B0453-01

Figure 54. PLL Block Diagram

The DAC3482 PLL mode is selected by setting the following:

1. pll_ena bit in register config24 to “1” to route to the PLL clock path.

2. pll_sleep bit in register config26 to “0” to enable the PLL and VCO.

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The output frequency of the VCO is designed to be the in the range from 3.3GHz to 4.0GHz. The prescaler

value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC

sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse tune bits, pll_vco(5:0) in

register config26, can adjust the center frequency of the VCO towards the product of the prescaler value and

DAC sample rate clock. Figure 55 shows a typical relationship between coarse tune bits and VCO center

frequency.

4000

VCO Frequency MHz - 3253

)

(

Coarse Tune Bits @

3900

3800

3700

3600

3500

3400

3300

11.6

0

8

16

32

40

48

56

64

24

Coarse Tuning Bits

G047

Figure 55. Typical PLL/VCO Lock Range vs Coarse Tuning Bits

Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 1.2288GHz, etc.) are generated from this

VCO frequency in conjunction with the pre-scaler setting as shown in Table 5.

Table 5. VCO Operation

VCO Frequency (MHz)

3440.64

Pre-Scale Divider

Desired DACCLK (MHz)

pll_p(2:0)

111

7

6

5

3

491.52

614.4

3686.4

110

3686.4

737.28

1228.8

101

3686.4

011

The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.

Table 6. PFD and CP Operation

DACCLK Frequency

M Divider

PDF Update Rate (MHz)

pll_m(7:0)

(MHz)

491.52

4

8

122.88

61.44

30.72

15.36

00000100

00001000

00010000

00100000

16

32

The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N

dividers can keep the PFD frequency below 155 MHz for peak operation.

The overall divide ratio inside the loop is the product of the Pre-Scale and M dividers (P * M) and the following

guidelines should be followed:

•

The overall divide ratio range is from 24 to 480

When the overall divide ratio is less than 120, the internal loop filter can guarantee a stable loop

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•

When the overall divide ratio is greater than 120, an external loop filter is required to ensure loop stability

The single charge pump current option is selected by setting pll_cp in register config24 to “01”.

If an external filter is required, the following filter should be connected to the LPF pin (A1):

LPF

R = 1 kΩ

C2 = 1 nF

C1 = 100 nF

S0514-01

Figure 56. Recommended External Loop Filter

The PLL will generate an internal OSTR signal and does not require the external LVPECL OSTR signal. The

OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same

as the PFD frequency. Therefore, using PLL with Dual Sync Sources mode requires the PFD frequency to be the

pre-defined OSTR frequency listed in Input FIFO section. This will allow the FIFO to be synced correctly by the

internal OSTR.

MULTI-DEVICE SYNCHRONIZATION

In various applications, such as multi antenna systems where the various transmit channels information is

correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase

aligned. The DAC3482 architecture supports this mode of operation.

MULTI-DEVICE SYNCHRONIZATION: PLL BYPASSED WITH DUAL SYNC SOURCES MODE

For single or multi-device synchronization it is important that delay differences in the data are absorbed by the

device so that latency through the device remains the same. Furthermore, to guarantee that the outputs from

each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In

the DAC3482 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode

the additional OSTR signal is required by each DAC3482 to be synchronized.

Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into the

multiple DAC devices can experience different delays due to variations in the digital source output paths or board

level wiring. These different delays can be effectively absorbed by the DAC3482 FIFO so that all outputs are

phase aligned correctly.

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DACCLKP/N

OSTRP/N

D[15:0]P/N

FPGA

DAC3482 DAC1

FRAMEP/N

Delay 1

LVPECL Outputs

DATACLKP/N

Outputs are

Phase Aligned

Variable delays due to variations in the FPGA(s) output

paths or board level wiring or temperature/voltage deltas

PLL/

DLL

Clock Generator

LVPECL Outputs

D[15:0]P/N

FRAMEP/N

DATACLKP/N

OSTRP/N

Delay 2

DAC3482 DAC2

DACCLKP/N

B0454-01

Figure 57. Synchronization System in Dual Sync Sources Mode with PLL Bypassed

For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR

signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock

generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of

the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the

DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.

Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from

device to device with the lowest skew possible as this will affect the synchronization process. In order to

minimize the skew across devices it is recommended to use the same clock distribution device to provide the

DACCLK and OSTR signals to all the DAC devices in the system.

DACCLKP/N(1)

t_S(OSTR)

t_H(OSTR)

t_{SKEW ~ 0}

OSTRP/N(1)

DACCLKP/N(2)

OSTRP/N(2)

t_S(OSTR)

t_H(OSTR)

•

T0526-01

Figure 58. Timing Diagram for LVPECL Synchronization Signals

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The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the

DAC3482 devices have a DACCLK and OSTR signal and must be carried out on each device.

1. Start-up the device as described in the power-up sequence. Set the DAC3482 in Dual Sync Sources mode

and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).

2. Sync the clock divider and FIFO pointers.

3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.

4. Disable clock divider sync by setting clkdiv_sync_ena to “0” in register config0.

After these steps all the DAC3482 outputs will be synchronized.

MULTI-DEVICE SYNCHRONIZATION: PLL ENABLED WITH DUAL SYNC SOURCES MODE

The DAC3482 allows exact phase alignment between multiple devices even when operating with the internal PLL

clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the

reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal.

For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state

by setting pll_ndivsync_ena in register config24 to “1”. The SYNC signal resets the PLL N dividers with a rising

edge, and the timing relationship t_{s(SYNC_PLL)}and t_{h(SYNC_PLL)}are relative to the reference clock presented on the

DACCLK pin.

Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be

just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the

pll_ndivsync_ena bit after resetting the PLL dividers). Besides the t_{(SYNC_PLL)}requirement between SYNC and

DACCLK, there is no additional required timing relationship between the SYNC and FRAME signals or between

DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK and SYNC signals

are distributed from device to device with the lowest skew possible.

DACCLKP/N

SYNCP/N

D[15:0]P/N

FPGA

DAC3482 DAC1

FRAMEP/N

Delay 1

Outputs

DATACLKP/N

Outputs are

Phase Aligned

Variable delays due to variations in the FPGA(s) output

paths or board level wiring or temperature/voltage deltas

PLL/

DLL

Clock Generator

Outputs

D[15:0]P/N

FRAMEP/N

DATACLKP/N

SYNCP/N

Delay 2

DAC3482 DAC2

DACCLKP/N

B0455-01

Figure 59. Synchronization System in Dual Sync Sources Mode with PLL Enabled

The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the

DAC3482 devices have a DACCLK and OSTR signal and must be carried out on each device.

1. Start-up the device as described in the power-up sequence. Set the DAC3482 in Dual Sync Sources mode

and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to "1").

2. Reset the PLL dividers with a rising edge on SYNC.

3. Disable PLL dividers resetting.

4. Sync the clock divider and FIFO pointers.

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5. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.

6. Disable clock divider sync by setting clkdiv_sync_ena to “0” in register config0.

After these steps all the DAC3482 outputs will be synchronized.

MULTI-DEVICE OPERATION: SINGLE SYNC SOURCE MODE

In Single Sync Source mode, the FIFO write and read pointers are reset from the same sync source, either

FRAME or SYNC. Although the FIFO in this mode can still absorb the data delay differences due to variations in

the digital source output paths or board level wiring it is impossible to guarantee data will be read from the FIFO

of different devices simultaneously thus preventing exact phase alignment.

In Single Sync Source mode the FIFO read pointer reset is handoff between the two clock domains (DATACLK

and FIFO OUT CLOCK) by simply re-sampling the write pointer reset. Since the two clocks are asynchronous

there is a small but distinct possibility of a meta-stable situation during the pointer handoff. This meta-stable

situation can cause the outputs of the multiple devices to slip by up to 2 DAC clock cycles.

When the PLL is enabled with Single Sync Source mode, the FIFO read pointer is not synchronized by the

OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section.

DACCLKP/N

D[15:0]P/N

FPGA

DAC3482 DAC1

FRAMEP/N

Delay 1

LVPECL Outputs

DATACLKP/N

Variable delays due to variations in the FPGA(s) output

paths or board level wiring or temperature/voltage deltas

PLL/

DLL

Clock Generator

LVPECL Outputs

0 to 2 DAC Clock Cycles

D[15:0]P/N

FRAMEP/N

Delay 2

DATACLKP/N

DAC3482 DAC2

DACCLKP/N

B0456-01

Figure 60. Multi-Device Operation in Single Sync Source Mode

FIR FILTERS

Figure 61 through Figure 64 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3

interpolating filters where f_INis the input data rate to the FIR filter. Figure 65 to Figure 68 show the composite

filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to

0.6 x f_DATA(the input data rate to the device) with < 0.001dB of pass-band ripple and > 90 dB stop-band

attenuation.

The DAC3482 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (f_DAC) that can be used

to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the

output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known

sin(x)/x or sinc(x) frequency response (Figure 15, red line). The inverse sinc filter response (Figure 62, blue line)

has the opposite frequency response from 0 to 0.4 x Fdac, resulting in the combined response (Figure 62, green

line). Between 0 to 0.4 x f_DAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03

dB error.

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The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from

full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and

is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0

dB). For example, if the signal input to FIR4 is at 0.25 x f_DAC, the response of FIR4 is 0.9 dB, and the signal must

be backed off from full scale by 0.9 dB to avoid saturation. The gain function in the QMC blocks can be used to

reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that

the user is then able to optimize the back-off of the signal based on its frequency.

The filter taps for all digital filters are listed in Table 4. Note that the loss of signal amplitude may result in lower

SNR due to decrease in signal amplitude.

SPACER

20

0

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

f/f_IN

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

f/f_IN

1

G048

G049

Figure 61. Magnitude Spectrum for FIR0

SPACER

Figure 62. Magnitude Spectrum for FIR1

SPACER

20

0

–20

–40

–60

–80

–20

–40

–60

–80

–100

–120

–140

–160

–120

–140

–160

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

f/f_IN

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

f/f_IN

1

G050

G051

Figure 63. Magnitude Spectrum for FIR2

SPACER

Figure 64. Magnitude Spectrum for FIR3

SPACER

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20

0

20

0

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

f/f_DATA

1

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

f/f_DATA

G052

G053

Figure 65. 2x Interpolation Composite Response

SPACER

Figure 66. 4x Interpolation Composite Response

SPACER

20

0

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

0

0.5

1

1.5

2

2.5

3

3.5

4

0

1

2

3

4

5

6

7

8

f/f_DATA

G054

G055

Figure 67. 8x Interpolation Composite Response

Figure 68. 16x Interpolation Composite Response

SPACER

4

3

2

FIR4

1

Corrected

0

–1

–2

–3

–4

sin(x)/x

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

f/f_DAC

G056

Figure 69. Magnitude Spectrum for Inverse Sinc Filter

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Table 7. FIR Filter Coefficients

Non-Interpolating

Inverse-SINC Filter

2x Interpolating Half-band Filters

FIR0

FIR1

FIR2

FIR3

FIR4

59 Taps

23 Taps

11 Taps

9 Taps

6

0

6

0

-12

0

-12

0

29

0

29

0

3

0

3

0

1

-4

1

-4

-19

0

-19

0

84

-214

0

-214

0

-25

0

-25

0

13

-50

0

-50

592⁽¹⁾

47

-336

0

-336

0

1209

2048⁽¹⁾

1209

150

256⁽¹⁾

150

0

-100

0

-100

0

1006

0

1006

0

192

0

192

0

-2691

0

-2691

0

-342

0

-342

0

10141

16384⁽¹⁾

10141

572

0

572

0

-914

0

-914

0

1409

0

1409

0

-2119

0

-2119

0

3152

0

3152

0

-4729

0

-4729

0

7420

0

7420

0

-13334

0

-13334

0

41527

65536⁽¹⁾

41527

(1) Center taps are highlighted in BOLD

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COMPLEX SIGNAL MIXER

The DAC3482 has two paths of complex signal mixer blocks that contain two full complex mixer (FMIX) blocks

and power saving coarse mixer (CMIX) blocks. The signal path is shown in Figure 70.

16

I Data In

I Data Out

Complex

Signal

Multiplier

Fs/2

Mixer

Fs/4

Mixer

16

Q Data In

Q Data Out

sine

16

cosine

16

CMIX<1>

CMIX<2> CMIX<0>

CMIX<3>

sine

16

cosine sine

16 16

cosine

16

Numerically

Controlled

Oscillator

Fixed Fs/8

Oscillator

NCO_ENA

B0471-01

Figure 70. Path of Complex Signal Mixer

FULL COMPLEX MIXER

The DAC3482 has a full complex mixer (FMIX) block with a Numerically Controlled Oscillators (NCO) that

enables flexible frequency placement without imposing additional limitations in the signal bandwidth. The NCO

has a 32-bit frequency registers (phaseadd(31:0)) and a 16-bit phase register (phaseoffset(15:0)) that generate

the sine and cosine terms for the complex mixing. The NCO block diagram is shown below in Figure 71.

32

16

sin

Accumulator

32

16

32

16

Look-Up

Table

Frequency

Register

Σ

16

cos

CLK

RESET

16

f_DAC

Phase

Register

NCO SYNC

via

syncsel_NCO[3:0]

B0026-03

Figure 71. NCO Block Diagram

Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is

selected by syncsel_NCO(3:0) in config31. The frequency word in the phaseadd(31:0) register is added to the

accumulators every clock cycle, f_DAC. The output frequency of the NCO is:

freq´ f_{NCO _ CLK}

f_NCO

=

2³²

(1)

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With the complex mixer enabled, the two channels in the mixer path are treated as complex vectors of the form

I_IN(t) + j Q_IN(t). The complex signal multiplier (shown in Figure 72) will multiply the complex channels with the sine

and cosine terms generated by the NCO. The resulting output, I_OUT(t) + j Q_OUT(t), of the complex signal multiplier

is:

I_OUT(t) = (I_IN(t)cos(2πf_NCOt + δ) – Q_IN(t)sin(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

Q_OUT(t) = (I_IN(t)sin(2πf_NCOt + δ) + Q_IN(t)cos(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

16

I_OUT(t)

I_IN(t)

16

Q_IN(t)

16

Q_OUT(t)

16

cosine

16

sine

B0472-01

Figure 72. Complex Signal Multiplier

where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value and mixer_gain is

either 0 or 1. δ is given by:

δ = 2π × phase_offset(15:0)/2¹⁶

The mixer_gain option allows the output signals of the multiplier to reduce by half (6dB). See Mixer Gain Section

for detail.

COARSE COMPLEX MIXER

In addition to the full complex mixer, the DAC3482 also has a coarse mixer block capable of shifting the input

signal spectrum by the fixed mixing frequencies ±n×f_S/8. Using the coarse mixer instead of the full mixer lowers

power consumption.

The output of the fs/2, fs/4, and –fs/4 mixer block is:

I_OUT(t) = I(t)cos(2πf_CMIXt) – Q(t)sin(2πf_CMIXt)

Q_OUT(t) = I(t)sin(2πf_CMIXt) + Q(t)cos(2πf_CMIXt)

Since the sine and the cosine terms are a function of fs/2, fs/4, or –fs/4 mixing frequencies, the possible resulting

value of the terms will only be 1, -1, or 0. The simplified mathematics allows the complex signal multiplier to be

bypassed in any one of the modes, thus mixer gain is not available. The fs/2, fs/4, and –fs/4 mixer blocks

performs mixing through negating and swapping of I/Q channel on certain sequence of samples. Table 8 shows

the algorithm used for those mixer blocks.

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Table 8. Fs/2, Fs/4, and –Fs/4 Mixing Sequence

MODE

MIXING SEQUENCE

Iout = {+I1, +I2, +I3, +I4…}

Qout = {+Q1, +Q2, +Q3, +Q4…}

Iout = {+I1, -I2, +I3, -I4…}

Normal (mixer bypassed)

fs/2

fs/4

Qout = {+Q1, -Q2, +Q3, -Q4…}

Iout = {+I1, -Q2, -I3, +Q4…}

Qout = {+Q1, +I2, -Q3, -I4…}

Iout = {+I1, +Q2, -I3, -Q4…}

Qout = {+Q1, -I2, -Q3, +I4…}

-fs/4

The fs/8 mixer can be enabled along with various combinations of fs/2, fs/4, and –fs/4 mixer. Since the fs/8 mixer

uses the complex signal multiplier block with fixed fs/8 sine and cosine term, the output of the multiplier is:

I_OUT(t) = (I_IN(t)cos(2πf_NCOt + δ) – Q_IN(t)sin(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

Q_OUT(t) = (I_IN(t)sin(2πf_NCOt + δ) + Q_IN(t)cos(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

where f_CMIXis the fixed mixing frequency selected by cmix(3:0). The mixing combinations are described in

Table 9. The mixer_gain option allows the output signals of the multiplier to reduce by half (6dB). See Mixer Gain

section for detail.

Table 9. Coarse Mixer Combinations

Fs/8 Mixer

cmix(3)

Fs/4 Mixer

cmix(2)

Fs/2 Mixer

cmix(1)

–Fs/4 Mixer

cmix(0)

cmix(3:0)

Mixing Mode

0000

0001

Disabled

Enabled

–

Disabled

Enabled

Disabled

Enabled

–

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

–

Disabled

Enabled

Disabled

–

No mixing

–Fs/4

0010

Fs/2

0100

+Fs/4

1000

+Fs/8

1010

–3Fs/8

1100

+3Fs/8

1110

–Fs/8

All others

Not recommended

MIXER GAIN

The maximum output amplitude out of the complex signal multiplier (i.e., FMIX mode or CMIX mode with fs/8

mixer enabled) occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and the sine and cosine

arguments are equal to 2π x f_MIXt + δ (2N-1) x π/4, where N = 1, 2, 3, etc....

sine

cosine

Max output occurs when both

sine and cosine are 0.707

M0221-01

Figure 73. Maximum Output of the Complex Signal Multiplier

With mixer_gain = 1 and both I_IN(t) and Q_IN(t) are simultaneously full scale amplitude, the maximum output

possible out of the complex signal multiplier is 0.707 + 0.707 = 1.414 (or 3dB). This configuration can cause

clipping of the signal and should therefore be used with caution.

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With mixer_gain = 0 in config2, the maximum output possible out of the complex signal multiplier is 0.5 x (0.707

+ 0.707) = 0.707 (or -3dB). This loss in signal power is in most cases undesirable, and it is recommended that

the gain function of the QMC block be used to increase the signal by 3 dB to compensate.

REAL CHANNEL UPCONVERSION

The mixer in the DAC3482 treats the I and Q inputs are complex input data and produces a complex output for

most mixing frequencies. The real input data for each channel can be isolated only when the mixing frequency is

set to normal mode or fs/2 mode. Refer to Table 8 for details.

QUADRATURE MODULATION CORRECTION (QMC)

GAIN AND PHASE CORRECTION

The DAC3482 includes a Quadrature Modulator Correction (QMC) block. The QMC blocks provide a mean for

changing the gain and phase of the complex signals to compensate for any I and Q imbalances present in an

analog quadrature modulator. The block diagram for the QMC block is shown in Figure 74. The QMC block

contains 3 programmable parameters.

Register qmc_gain(10:0) controls the I and Q path gains and is an 11-bit unsigned value with a range of 0 to

1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication is between bit 9 and bit 10.

Register qmc_phase(11:0) control the phase imbalance between I and Q and is a 12-bit values with a range

of –0.5 to approximately 0.49975. The QMC phase term is not a direct phase rotation but a constant that is

multiplied by each "Q" sample then summed into the "I" sample path. This is an approximation of a true phase

rotation in order to keep the implementation simple. The corresponding phase rotation corresponds to

approximately +3.75 to –3.75 degrees in 1024 steps.

LO feed-through can be minimized by adjusting the DAC offset feature described below.

qmc_gain[10:0]

11

16

I Data In

I Data Out

Σ

12

qmc_phase[11:0]

Q Data Out

16

Q Data In

11

qmc_gain[10:0]

B0164-02

Figure 74. QMC Block Diagram

OFFSET CORRECTION

Registers qmc_offsetI(12:0) and qmc_offsetQ(12:0) can be used to independently adjust the DC offsets of each

channel. The offset values are in represented in 2s-complement format with a range from –4096 to 4095.

The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is

added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset

values are LSB aligned.

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qmc_offsetI

{–4096, –4095, ..., 4095}

13

16

I Data In

I Data Out

Σ

Q Data In

Q Data Out

13

qmc_offsetQ

{–4096, –4095, ..., 4095}

B0165-02

Figure 75. Digital Offset Block Diagram

GROUP DELAY CORRECTION

A complex transmitter system typically is consisted of a DAC, reconstruction filter network, and I/Q modulator.

Besides the gain and phase mismatch contribution, there could also be timing mismatch contribution from each

components. For instance, the timing mismatch could come from the PCB trace length variation between the I

and Q channels and the group delay variation from the reconstruction filter.

This timing mismatch in the complex transmitter system creates phase mismatch that varies linearly with respect

to frequency. To compensate for the I/Q imbalances due to this mismatch, the DAC3482 has group delay

correction block for each DAC channel. Each DAC channel can adjust its delay through grp_delayI(7:0) and

grp_delayq(7:0) in register config46 and config47, respectively. The maximum delay ranges from 30ps to 100ps

and is dependent on DAC sample clock. Contact TI for specific application information. The group delay

correction, along with gain/phase correction, can be useful for correcting imbalances in wide-band transmitter

system.

TEMPERATURE SENSOR

The DAC3482 incorporates a temperature sensor block which monitors the temperature by measuring the

voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation

(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement

value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled

(tsense_sleep = 0 in register config26) a conversion takes place each time the serial port is written or read. The

data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in

config6. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the

data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth

SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the

temperature sensor is enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from config6 must be done with

an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

DATA PATTERN CHECKER

The DAC3482 incorporates a simple pattern checker test in order to determine errors in the data interface. The

main cause of failures is setup/hold timing issues. The test mode is enabled by asserting iotest_ena in register

config1. In test mode the analog outputs are deactivated regardless of the state of TXENABLE or sif_texnable in

register config3.

The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in

registers config37 through config44. The data pattern key can be modified by changing the contents of these

registers.

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The first word in the test frame is determined by a rising edge transition in FRAME or SYNC, depending on the

syncsel_fifoin(3:0) setting in config32. At this transition, the pattern0 word should be input to the data pins.

Patterns 1 through 7 should follow sequentially on each edge of DATACLK (rising and falling). The sequence

should be repeated until the pattern checker test is disabled by setting iotest_ena back to 0. It is not necessary to

have a rising FRAME or SYNC edge aligned with every pattern0 word, just the first one to mark the beginning of

the series.

Start cycle again with optional rising edge of FRAME or SYNC

Pattern 0 Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5 Pattern 6 Pattern 7

D[15:0]P/N

[15:0]

DATACLKP/N (DDR)

Sync

Option #1

FRAMEP/N

Sync

Option #2

SYNCP/N

T0528-01

Figure 76. IO Pattern Checker Data Transmission Format

The test mode determines if the 16-bit LVDS data D[15:0]P/N of all the patterns were received correctly by

comparing the received data against the data pattern key. If any of the 16-bit data D[15:0]P/N were received

incorrectly, the corresponding bits in iotest_results(15:0) in register config4 will be set to “1” to indicate bit error

location. Furthermore, the error condition will trigger the alarm_from_iotest bit in register config5 to indicate a

general error in the data interface. When data pattern checker mode is enabled, this alarm in register config5, bit

7 is the only valid alarm. Other alarms in register config5 are not valid and can be disregarded.

For instance, pattern0 is programmed to the default of 0x7A7A. If the received Pattern 0 is 0x7A7B, then bit 0 in

iotest_results(15:0) will be set to “1” to indicate an error in bit 0 location. The alarm_from_iotest will also be set to

“1” to report the data transfer error. The user can then narrow down the error from the alarm_from_iotest bit

location information and implement the fix accordingly.

The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and “0” to alarm_from_iotest through the

serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The

corresponding alarm bit will remain a “1” if the errors remain.

Note that unless the unused data pins in byte-wide input format are forced to a known value the data pattern

checker is only available for the word-wide input data format. In byte-wide input format, the first 8-bits of the

iotest_pattern[0:7] in registers config37 through config44 will either need to be 0s or 1s for valid data pattern

checking.

It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete

cycles before clearing the iotest_results(15:0) and alarm_from_iotest. This will eliminate the possibility of false

alarms generated during the setup sequence.

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PARITY CHECK TEST

The DAC3482 has a parity check test that enables continuous validity monitoring of the data received by the

DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting

board assembly issues due to missing pad connections.

For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits

(bits with logic value of “1”) is even or odd. This simple scheme is used to detect data transfer errors. Parity

testing is implemented in the DAC3482 in two ways: word-by-word parity and block parity.

WORD-BY-WORD PARITY

Word-by-word parity is the easiest mode to implement. In this mode the additional parity bit is sourced to the

parity input (PARITYP/N) for each data word transfer into the D[15:0]P/N inputs. This mode is enabled by setting

the word_parity_ena bit. The input parity value is defined to be the total number of logic 1s on the 17-bit data

bus, the D[15:0]P/N inputs and the PARITYP/N input. This value, the total number of logic 1s, must match the

parity test selected in the oddeven_parity bit in register config1.

For example, if the oddeven_parity bit is set to “1” for odd parity, then the number of 1s on the 17-bit data bus

should be odd. The DAC will check the data transfer through the parity input. If the data received has odd

number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect.

The corresponding alarm for parity error will be set accordingly.

Note that unless the unused data pins in byte-wide input format are forced to a known value the word-by-word

parity is only available for the word-wide input data format.

Figure 78 shows the simple XOR structure used to check word parity. Parity is tested independently for data

captured on both rising and falling edges of DATACLK (alarm_rparity and alarm_fparity, respectively). Testing on

both edges helps in determining a possible setup/hold issue. Both alarms are captured individually in register

config5.

alarm_rparity

PARITY

oddeven_parity

D[15:0]

alarm_fparity

Parity Block

DATACLK

B0458-01

Figure 78. DAC3482 Word-by-Word Parity Check

BLOCK PARITY

The block parity method uses the FRAME signal to determine the boundaries of the data block to compute parity.

This mode is enabled by setting the frame_parity_ena bit in register config1.

A low-to-high transition of FRAME captured with the DATACLK rising edge determines the end point of the parity

block and the beginning of the next one. In this method the parity bit of the completed block corresponds to the

FRAME value captured on the DATACLK falling edge right after the STOP/START point.

The input parity value is defined to be the total number of logic 1s in the data block. A logic HIGH captured on

the falling edge of DATACLK indicates odd parity or odd number of logic 1s, while a logic LOW indicates even

parity or even number of logic 1s. If the expected parity does not match the number of logic 1s in the received

data, then alarm_frame_parity in register config5 will be set to “1”. The main advantage of the block parity mode

is that there is no need for an additional parity LVDS input.

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Since the FRAME signal is used for parity testing in addition to FIFO syncing and frame boundary assignment, it

is mandatory to take some extra steps to avoid device malfunction. If FRAME is used to reset the FIFO pointers

continuously, the block size must be a multiple of 8 samples (each sample corresponding to 16-bits I and 16-bits

Q). In addition since FRAME is used in byte-wide input data mode to establish the frame boundary, the parity

block must be aligned with the data frame boundaries.

I₀

Q₀

I₁

Q₁

I_x

Q_x

I_y

Q_y

D[15:0]P/N

[15:0]

DATACLKP/N

(DDR)

DATACLKP/N

(DDR)

• • •

High = Odd Parity

Low = Even Parity

High = Odd Parity

Low = Even Parity

FRAMEP/N

Parity Bit for

Data Block N – 1

Parity Bit for

Data Block N

Stop Point for

Data Block N – 1

Start Point for

Data Block N

Stop Point for

Data Block N

Start Point for

Data Block N + 1

T0527-01

Notes: Rising edge of FRAMEP/N indicates the beginning of data block.

Parity bit for the current data block is latched on falling edge of DATACLK after the start point for next data block.

Figure 79. DAC3482 Block Parity Check (Example shown with Word-Wide Mode)

DAC3482 ALARM MONITORING

The DAC3482 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction

scenario. All the alarm events can be accessed either through the config5 register or through the ALARM pin.

Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to

allow further testing. The set of alarms includes the following conditions

Zero check alarm

•

Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a

shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a

sync to the FIFO block is required.

FIFO alarms

alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.

•

–

alarm_fifo_2away. Pointers are within two addresses of each other.

alarm_fifo_1away. Pointers are within one address of each other.

alarm_fifo_collision. Pointers are equal to each other.

Clock alarms

clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.

•

–

alarm_dacclk_gone. Occurs when the DACCLK has been stopped.

alarm_dataclk_gone. Occurs when the DATACLK has been stopped.

Pattern checker alarm

alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.

PLL alarm

•

alarm_from_pll. Occurs when the PLL is out of lock.

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Parity alarms

•

alarm_rparity. Occurs when there is a parity error in the data captured by the rising edge of DATACLKP/N.

The PARITYP/N input is the parity bit (word-by-word parity test).

alarm_fparity. Occurs when there is a parity error in the data captured by the falling edge of DATACLKP/N.

The PARITYP/N input is the parity bit (word-by-word parity test).

alarm_frame_parity_err. Occurs when there is a frame parity error when using the FRAME as the parity bit

(block parity test).

To prevent unexpected DAC outputs from propagating into the transmit channel chain, the clock and alarm_

fifo_collision alarms can be set in config2 to shut-off the DAC output automatically regardless of the state of

TXENABLE or sif_txenable.

Alarm monitoring is implemented as follows:

•

Power up the device using the recommended power-up sequence.

Clear all the alarms in config5 by setting them to 0.

Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7.

Enable automatic DAC shut-off in register config2 if required.

In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the

DAC outputs will be disabled.

•

Read registers config5 to determine which alarm triggered the ALARM pin.

Correct the error condition and re-synchronize the FIFO.

Clear the alarms in config5.

Re-read config5 to ensure the alarm event has been corrected.

Keep clearing and reading config5 until no error is reported.

POWER-UP SEQUENCE

The following startup sequence is recommended to power-up the DAC3482:

1. Set TXENABLE low

2. Supply all 1.2V voltages (DACVDD, DIGVDD, CLKVDD and VFUSE) and all 3.3V voltages (AVDD, IOVDD,

and PLLAVDD). The 1.2V and 3.3V supplies can be powered up simultaneously or in any order. There are

no specific requirements on the ramp rate for the supplies.

3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after

the SIF register programming.

4. Toggle the RESETB pin for a minimum 25 ns active low pulse width.

5. Program the SIF registers.

6. Program config1, bit <8> = "0" and config16, bit <13:12> = "11".

7. Program fuse_sleep (config 27, Bit <11> ) to put internal fuses to sleep.

8. FIFO configuration needed for synchronization:

(a) Program syncsel_fifoin(3:0) (config32, bit<15:12>) to select the FIFO input pointer sync source.

(b) Program syncsel_fifoout(3:0) (config32, bit<11:8>) to select the FIFO output pointer sync source.

(c) Program syncsel_dataformatter(1:0) (config32, bit<3:2>) to select the FIFO Data Formatter sync source.

9. Clock divider configuration needed for synchronization:

(a) Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source.

(b) Program clkdiv_sync_ena (config0, bit<2>) to "1" to enable clock divider sync.

(c) For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit<11>) to “1” to

synchronize the PLL N-divider.

10. Provide all LVDS inputs (D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N)

simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.

(a) For Single Sync Source Mode where either FRAMEP/N or SYNCP/N is used to sync the FIFO, a single

rising edge for FIFO, FIFO data formatter, and clock divider sync is recommended. Periodic sync signal

is not recommended due to the non-deterministic latency of the sync signal through the clock domain

transfer.

(b) For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.

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(c) For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL

N-divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as

long as the t_{(SYNC_PLL)}setup and hold timing requirement is met with respect to the reference clock

source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point.

11. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed

for synchronization:

(a) For Single Sync Source Mode where the clock divider sync source is either FRAMEP/N or SYNCP/N,

clock divider syncing may be disabled after DAC3482 initialization and before the data transmission by

setting clkdiv_sync_ena (config0, bit 2) to “0”. This is to prevent accidental syncing of the clock divider or

when sending FRAMEP/N or SYNCP/N pulse to other digital blocks.

(b) For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from

external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time.

(c) Optionally, to prevent accidental syncing of the FIFO and FIFO data formatter when sending the

FRAMEP/N or SYNCP/N pulse to other digital blocks such as NCO, QMC, etc, disable FIFO syncing by

setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to “0000” after the FIFO input and output pointers are

initialized. Also Disable the FIFO data formatter by setting syncsel_dataformatter(1:0) to “10” or “11”. If

the FIFO and FIFO data formatter sync remain enabled after initialization, the FRAMEP/N or SYNCP/N

pulse must occur in ways to not disturb the FIFO operation. Refer to the INPUT FIFO section for detail.

(d) Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit<11>) to "0".

12. Enable transmit of data by asserting the TXENABLE pin or set sif_txenable to “1”.

13. At any time, if any of the clocks (i.e DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a

complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 8 through 12.

Program the FIFO configuration and clock divider configuration per steps 8 and 9 appropriately to accept the

new sync pulse or pulses for the synchronization.

EXAMPLE START-UP ROUTINE

DEVICE CONFIGURATION

f_DATA= 614.4MSPS, 16-bit word wide interface

Interpolation = 2x

Input data = baseband data

f_OUT= 122.88MHz

PLL = Enabled

Full Mixer = Enabled

Dual Sync Sources Mode

PLL CONFIGURATION

f_REFCLK= 614.4MHz at the DACCLKP/N LVPECL pins

f_DACCLK= f_DATAx Interpolation = 1228.8MHz

f_VCO= 3 x f_DACCLK= 3686.4MHz (keep f_VCObetween 3.3GHz to 4GHz)

PFD = f_OSTR= 38.4MHz

N = 16, M = 32, P = 3, single charge pump

pll_vco(5:0) = “100100” (36)

NCO CONFIGURATION

f_NCO= 122.88MHz

f_{NCO_CLK}= 1228.8MHz

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freq = f_CNOx 2^32 / 1228.8 = 429496730 = 0x1999999A

phaseaddAB(31:0) or phaseaddCD(31:0) = 0x1999999A

NCO SYNC = sif_sync

EXAMPLE START-UP SEQUENCE

Table 10. Example Start-Up Sequence Description

STEP

READ/WRITE

ADDRESS

N/A

VALUE

N/A

DESCRIPTION

1

2

3

4

N/A

Set TXENABLE Low

Power-up the device

N/A

Apply LVPECL DACCLKP/N for PLL reference clock

Toggle RESETB pin

QMC offset and correction enabled, 2x int, FIFO enabled, Alarm enabled,

clock divider sync enabled, inverse sinc filter enabled.

5

6

Write

0x00

0x01

0x02

0x03

0x07

0x08

0xA19E

0x040E

0xF052

0xA000

0xD8FF

N/A

Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision).

Note: bit8 = ‘0’

Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision.

Mixer block with NCO enabled, twos complement. Word wide interface.

7

Output current set to 20mAFS with internal reference and 1.28kohm R_BIAS

resistor.

8

Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the

Alarm output.

9

Program the desired channel I QMC offset value. (Causes Auto-Sync for

QMC Offset Block)

10

11

12

Write

0x09

0x0C

N/A

Program the desired FIFO offset value and channel Q QMC offset value.

Program the desired channel I QMC gain value.

Coarse mixer mode not used. Program the desired channel Q QMC gain

value.

13

14

15

Write

0x0D

0x10

0x12

N/A

Program the desired channel IQ QMC phase value. (Causes Auto-Sync

QMC Correction Block) Note : bit13 and bit12 = ‘1’

Program the desired channel IQ NCO phase offset value. (Causes

Auto-Sync for Channel IQ NCO Mixer)

16

17

Write

0x14

0x15

0x999A

0x1999

Program the desired channel IQ NCO frequency value

PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler =

3.

18

Write

0x18

0x2C58

19

20

21

Write

0x19

0x1A

0x1B

0x20F4

0x9000

0x0800

M = 32, N = 16, PLL VCO bias tune = “01”

PLL VCO coarse tune = 36

Internal reference

QMC offset IQ and QMC correction IQ can be synced by sif_sync or

auto-sync from register write

22

23

Write

0x1E

0x1F

0x9191

0x4140

Mixer IQ values synced by SYNCP/N. NCO accumulator synced by

SYNCP/N. FIFO data formatter synced by FRAMEP/N.

FIFO Input Pointer Sync Source = FRAME

24

25

Write

N/A

0x20

N/A

0x2400

N/A

FIFO Output Pointer Sync Source = OSTR (from PLL N-divider output)

Clock Divider Sync Source = OSTR

Provide all the LVDS DATA and DATACLK

Provide rising edge FRAMEP/N and rising edge SYNCP/N to sync the FIFO

input pointer and PLL N-dividers.

Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in

0x1A.

26

27

Read

Write

0x18

0x05

N/A

0x0000

Clear all alarms in 0x05.

Read back all alarms in 0x05. Check for PLL lock, FIFO collision,

DACCLK-gone, DATACLK-gone, etc. Fix the error appropriately. Repeat

step 26 and 27 as necessary.

28

Read

0x05

N/A

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Table 10. Example Start-Up Sequence Description (continued)

STEP

29

READ/WRITE

Write

ADDRESS

VALUE

0x4142

0xA19A

0x4148

DESCRIPTION

Sync all the QMC blocks using sif_sync. These blocks can also be synced

via auto-sync through appropriate register writes.

0x1F

30

Write

0x00

Disable clock divider sync.

Disable FIFO data formatter sync. Set sif_sync to “0” for the next sif_sync

31

Write

0x1F

event.

32

33

34

Write

N/A

0x20

0x18

N/A

0x0000

0x2458

N/A

Disable FIFO input and output pointer sync.

Disable PLL N-dividers sync.

Set TXENABLE high. Enable data transmission.

LVPECL INPUTS

Figure 80 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the output strobe clock

(OSTRP/N).

CLKVDD

250 Ω

2 kΩ

DACCLKP

OSTRP

DACCLKN

OSTRN

Internal

Digital In

250 Ω

SLEEP

GND

S0515-01

Figure 80. DACCLKP/N and OSTRP/N Equivalent Input Circuit

Figure 81 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential

ECL/PECL source.

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C_AC

0.1 μF

+

CLKIN

Differential

ECL

or

C_AC

100 Ω

0.1 μF

(LV)PECL

Source

–

CLKINC

R_T

150 Ω

S0029-02

Figure 81. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source

LVDS INPUTS

The D[15:0]P/N, DATACLKP/N, SYNCP/N, PARITYP/N and FRAMEP/N LVDS pairs have the input configuration

shown in Figure 82. Figure 83 shows the typical input levels and common-move voltage used to drive these

inputs.

IOVDD

LVDS

Receiver

Internal Digital In

100 Ω

GND

S0516-01

Figure 82. D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N LVDS Input Configuration

Example

V_A

V_B

1.4 V

1 V

DAC3482

LVDS

Receiver

V_{A, B}

100 Ω

400 mV

0 V

V_{A, B}

V_A

V_COM= (V_A+ V_B)/2

–400 mV

V_B

GND

1

0

Logical Bit

Equivalent

B0459-01

Figure 83. LVDS Data Input Levels

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Table 11. Example LVDS Data Input Levels

Resulting Differential

Voltage

Resulting Common-Mode

Applied Voltages

Logical Bit Binary

Equivalent

Voltage

V_A

V_B

V_A,B

V_COM

1.4 V

1.0 V

1.2 V

0.8 V

1.0 V

1.4 V

0.8 V

1.2 V

400 mV

-400 mV

400 mV

-400 mV

1.2 V

1

0

1

0

1.0 V

CMOS DIGITAL INPUTS

Figure 84 shows a schematic of the equivalent CMOS digital inputs of the DAC3482. SDIO, SCLK, SLEEP and

TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3482.

See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to

100kΩ.

IOVDD

100 kΩ

SDIO

SCLK

SLEEP

400 Ω

Internal

Digital In

Internal

Digital In

SDENB

RESETB

TXENABLE

100 kΩ

GND

S0027-03

Figure 84. CMOS Digital Equivalent Input

REFERENCE OPERATION

The DAC3482 uses a bandgap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor R_BIASto pin BIASJ. The bias current I_BIASthrough

resistor R_BIASis defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale

output current equals 64 times this bias current and can thus be expressed as:

IOUT_FS= 64 x I_BIAS= 64 x (V_EXTIO/ R_BIAS) / 2

The DAC3482 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the

IOUT_FScan be expressed as:

IOUT_FS= (coarse_dac + 1)/16 x IBIAS x 64 = (coarse_dac + 1)/16 x (VEXTIO / RBIAS) / 2 x 64

where V_EXTIOis the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of

1.2V. This reference is active when extref_ena = ‘0’ in config27. An external decoupling capacitor C_EXTof 0.1 µF

should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be

used for external reference operation. In that case, an external buffer with high impedance input should be

applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be

disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor C_EXTmay hence

be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor R_BIAS, programming

coarse_dac(3:0), or changing the externally applied reference voltage.

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SLAS748A –MARCH 2011–REVISED JUNE 2011

www.ti.com

NOTE

With internal reference, the minimum Rbias resistor value is 1.28kΩ. Resistor value below

1.28kΩ is not recommended since it will program the full-scale current to go above 30mA

and potentially damages the device.

DAC TRANSFER FUNCTION

The CMOS DAC’s consist of a segmented array of PMOS current sources, capable of sourcing a full-scale

output current up to 30 mA. Differential current switches direct the current to either one of the complementary

output nodes IOUTP or IOUTN. Complementary output currents enable differential operation, thus canceling out

common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion

components, and increasing signal output power by a factor of two.

The full-scale output current is set using external resistor R_BIASin combination with an on-chip bandgap voltage

reference source (+1.2 V) and control amplifier. Current I_BIASthrough resistor R_BIASis mirrored internally to

provide a maximum full-scale output current equal to 64 times I_BIAS

The relation between IOUTP and IOUTN can be expressed as:

IOUT_FS= IOUTP + IOUTN

.

We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the

output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in

each pin driving a resistive load can be expressed as:

IOUTP = IOUT_FSx CODE / 65536

IOUTN = IOUT_FSx (65535 – CODE) / 65536

where CODE is the decimal representation of the DAC data input word

For the case where IOUTP and IOUTN drive resistor loads R_Ldirectly, this translates into single ended voltages

at IOUTP and IOUTN:

VOUTP = IOUT1 x R_L

VOUTN = IOUT2 x R_L

Assuming that the data is full scale (65535 in offset binary notation) and the R_Lis 25 Ω, the differential voltage

between pins IOUTP and IOUTN can be expressed as:

VOUTP = 20mA x 25 Ω = 0.5 V

VOUTN = 0mA x 25 Ω = 0 V

VDIFF = VOUTP – VOUTN = 0.5V

Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would

lead to increased signal distortion.

ANALOG CURRENT OUTPUTS

The DAC3482 can be easily configured to drive a doubly terminated 50 Ω cable using a properly selected RF

transformer. Figure 85 and Figure 86 show the 50 Ω doubly terminated transformer configuration with 1:1 and 4:1

impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded

to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.5 Vpp for a 1:1

transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the

transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer

results in an output between –0.5 V and +0.5 V.

70

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Product Folder Link(s): DAC3482

DAC3482

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SLAS748A –MARCH 2011–REVISED JUNE 2011

50 Ω

1:1

IOUTP

IOUTN

R_LOAD

50 Ω

100 Ω

AGND

50 Ω

S0517-01

Figure 85. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer

100 Ω

4:1

IOUTP

R_LOAD

AGND

50 Ω

IOUTN

100 Ω

S0518-01

Figure 86. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer

Submit Documentation Feedback

71

Product Folder Link(s): DAC3482

DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011

www.ti.com

REVISION HISTORY

Changes from Original (March 2011) to Revision A

Page

•

Changed from PRODUCT PREVIEW to PRODUCTION DATA ........................................................................................... 1

72

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Product Folder Link(s): DAC3482

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jun-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC3482IRKDR

DAC3482IRKDT

WQFN

RKD

88

2000

250

330.0

16.4

9.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jun-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC3482IRKDR

DAC3482IRKDT

WQFN

RKD

88

2000

250

333.2

345.9

28.6

Pack Materials-Page 2

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型号：	DAC3482_14
厂家：	TEXAS INSTRUMENTS
描述：	Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)
文件：	总79页 (文件大小：1507K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC3482_14 [TI]

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