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DAC38RF82, DAC38RF89

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

具有 JESD204B 接口、片上 PLL 和宽带插值的 DAC38RF8x 双通道、差

分输出、14 位、9GSPS、射频采样 DAC

1 特性

在双通道运行状态下，无插值时输入接口的数据速率高

1

达 3.33GSPS（12 位分辨率）和 2.5GSPS（16 位分

辨率）。当用作具有 2x 至 24x 插值模式的复合基带发

送器时，DAC38RF82 或 DAC38RF89 可以合成具有

16 位输入分辨率的高达 2GHz 带宽的宽带信号和具有

12 位输入分辨率的 2.66GHz 带宽的宽带信号。

•

具有多模式运行方式的 14 位分辨率、9GSPS DAC

–

16 位、双通道数据模式

–

最大输入速率：2.5GSPS

宽带数字上变频器

–

插值：1、2、4、6、8、10、12、16、

18、20、24x

8 位模式允许以 9GSPS 的最大 DAC 采样率进行输

入，并可合成 0 至 4.5GHz 的宽带信号。

–

12 位、双通道数据模式

–

最大输入速率：3.33GSPS

可选的低抖动 PLL/VCO 通过允许使用频率较低的参考

时钟来简化 DAC 时钟的生成。DAC38RF82 和

DAC38RF89 支持不同的 VCO 频率范围，如器件比较

表所示。

宽带数字上变频器

–

插值：1、2、24x

8 位、单通道数据模式

最大输入速率：9GSPS

JESD204B 接口

–

器件信息⁽¹⁾

•

–

子类 1 支持多芯片同步

器件型号

DAC38RF82

DAC38RF89

封装

封装尺寸（标称值）

最大通道速率：12.5Gbps

FCBGA (144)

10.0mm x 10.0mm

差分输出

–

支持直流耦合

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

射频满量程输出功率（采用 2:1 平衡-非平衡变

压器）：

2.14GHz 时为 3dBm

32x6MHz 256QAM 载波

•

具有旁路功能的内部 PLL 和 VCO

–

DAC38RF82：f_C(VCO)= 5.9 或 8.9GHz

DAC38RF89：f_C(VCO)= 5 或 7.5GHz

•

电源：-1.8V、1.0V、1.8V

封装：10mm x 10mm BGA，间距为 0.8mm，

144 个焊球

2 应用

•

任意波形发生器

雷达和电子战

通信测试设备

符合 DOCSIS 3.0/3.1 要求的直接射频合成

微波回程

3 说明

DAC38RF82 和 DAC38RF89 是高性能的宽带宽型射

频采样数模转换器 (DAC)，能够实现高达 3.33GSPS

的双通道输入数据速率或高达 9GSPS 的 8 位单通道

运行状态。这些器件具有一个多达 8 通道的低功耗

JESD204B 接口，最大比特率为 12.5Gbps。

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEA6

DAC38RF82, DAC38RF89

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

www.ti.com.cn

8.3 Feature Description................................................. 25

8.4 Device Functional Modes........................................ 62

8.5 Register Maps ........................................................ 66

Application and Implementation ...................... 128

9.1 Application Information.......................................... 128

9.2 Typical Application ............................................... 129

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics - DC Specifications........... 8

7.6 Electrical Characteristics - Digital Specifications .... 10

7.7 Electrical Characteristics - AC Specifications ......... 13

7.8 PLL/VCO Electrical Characteristics ........................ 16

7.9 Timing Requirements.............................................. 17

7.10 Typical Characteristics.......................................... 18

Detailed Description ............................................ 23

8.1 Overview ................................................................. 23

8.2 Functional Block Diagrams ..................................... 23

9

10 Power Supply Recommendations ................... 133

10.1 Power Supply Sequencing.................................. 134

11 Layout................................................................. 134

11.1 Layout Guidelines ............................................... 134

11.2 Layout Example .................................................. 136

12 器件和文档支持 ................................................... 137

12.1 相关链接.............................................................. 137

12.2 接收文档更新通知 ............................................... 137

12.3 支持资源.............................................................. 137

12.4 商标..................................................................... 137

12.5 静电放电警告....................................................... 137

12.6 Glossary.............................................................. 137

13 机械、封装和可订购信息..................................... 137

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (August 2017) to Revision C

Page

•

Changed the t_rNOM value from 50 ns To 50 ps in the Anaolog Output of the Timing Requirements table ....................... 17

Changed the t_fNOM value from 50 ns To 50 ps in the Anaolog Output of the Timing Requirements table ....................... 17

Changed the MPY values in Table 4.................................................................................................................................... 27

Changed The title From: SerDes PLL Modes Selection To: SerDes PLL Multiplier (MPY) Values in in Table 4................ 27

Added section: Digital Quadrature Modulator....................................................................................................................... 53

Added section: Low Power Coarse Resolution Mixing Modes............................................................................................. 54

Added cross reference to MPY values in Table 132 ......................................................................................................... 124

Changed the enable/disable description for bit [15:13] of Table 134 ................................................................................ 126

Changes from Revision A (April 2017) to Revision B

Page

•

已删除将特性中的“插值：1、2、4、24x”更改为“插值：1、2、24x” .................................................................................... 1

Changed the ALARM pin From: alarm_out_pol To: alm_out_pol in the Pin Functions table................................................. 5

Changed the Description of pins A3, A4, A7, A6, A9, A10, A12, E12, F11, F7, G6, H5, H7, J6, J11 in the Pin

Functions table ....................................................................................................................................................................... 5

•

Changed description of TXENABLE pin in the PIN Functions table ...................................................................................... 6

Changed the MAX value of VEE18N rail From: 0.5 V To 0.3 V in the Absolute Maximum Ratings table............................. 7

Added "Supply Voltage Range" to the Recommended Operating Conditions table .............................................................. 7

Changed DNL typical value From: ±0.5 to ±3 LSB in Electrical Characteristics - DC Specifications table ........................... 8

Changed INL typical value From: ±1 To: ±4 LSB in Electrical Characteristics - DC Specifications table.............................. 8

Added "Reference voltage drift" to the Electrical Characteristics - DC Specifications table.................................................. 8

Changed Power Dissipation Test Condition From: MODE 5: dual channel, 8-bit input mode, 2x Interpolation To:

MODE 5: dual channel, 8-bit input mode, 1x Interpolation in the Electrical Characteristics - DC Specifications .................. 9

•

Changed the ILOAD values to negative for CMOS interface parameter, low-level output voltage, in the Electrical

2

DAC38RF82, DAC38RF89

www.ti.com.cn

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

Characteristics - Digital Specifications table......................................................................................................................... 10

Added 0 dBFS to the condition statement for the Electrical Characteristics - AC Specifications table ............................... 13

•

Added MIN and TYP value to maximum DAC sample rate for DAC38RF89 only in the Electrical Characteristics - AC

Specifications table............................................................................................................................................................... 13

•

Added NSD values for DAC38RF82 with on-chip PLL enabled to Electrical Characteristics - AC Specifications table...... 15

Changed the Isolation values in the TEST CONDITIONS, TYP value From: 74 dBc To: 82 dBc and 56 dBc To 73

dBc in the Electrical Characteristics - AC Specifications table............................................................................................. 15

•

Added Figure 16 ................................................................................................................................................................... 19

Added MPY value for 16.5x in the Table 4........................................................................................................................... 27

Changed input rate max and fdac max for 6x interpolation mode in Table 9 ..................................................................... 30

Changed input data rate From: 6666 MSPS To: 3333 MSPS for LMFSHd=41380, 2x interpolation in Table 9 ................ 31

Changed Table 12, JESD204B frame format for LMFSHd=84111 ..................................................................................... 31

Changed Table 14, JESD204B frame format for LMFSHd=44210 ...................................................................................... 32

Changed Table 16, JESD204B frame format for LMFSHd = 24410.................................................................................... 32

Changed Table 17, JESD204B frame format for LMFSHd = 44210.................................................................................... 32

Changed Table 18, JESD204B frame format for LMFSHd = 88210.................................................................................... 33

Changed Table 19, JESD204B frame format for LMFSHd = 24410.................................................................................... 33

Changed Table 20, JESD204B frame format for LMFSHd=48410 ...................................................................................... 33

Changed Table 21, JESD204B frame format for LMFSHd = 24310.................................................................................... 33

Changed Table 22, JESD204B frame format for LMFSHd = 48310.................................................................................... 33

Changed Table 23, JESD204B frame format for LMFSHd = 81180.................................................................................... 34

Changed Table 24, JESD204B frame format for LMFSHd = 41380.................................................................................... 34

Changed Table 26, JESD204B frame format for LMFSHd = 41121.................................................................................... 35

Added Table 27, JESD204B frame format for LMFSHd = 41121 ........................................................................................ 36

Changed Table 38 ................................................................................................................................................................ 47

Changed register field programming values for LMFSHd=24410, 41380, 41121 and 24310 in the Register

Programming for JESD and Interpolation Mode table.......................................................................................................... 52

•

Changed the bit positions of N_M1 register field From: 12-8 To: 4-0 in the Table 42 table ................................................ 53

Changed the bit positions of N_M1’ (NPRIME_M1) register field From: 4-0 To: 12-0 in the Table 42 table....................... 53

Changed the description of DAC PLL alarm in Alarm Monitoring ........................................................................................ 58

Changed from BIST_ENA to Reserved in Table 61 ............................................................................................................ 78

Changed from BIST_ZERO to Reserved in Table 61 ......................................................................................................... 78

Changed the description of OUTSUM_SEL field in Table 69 ............................................................................................. 84

Changed the Description of Bit 11 From "dummy data generation" to "distortion enhancement" in Table 116 ............... 114

已更改 the junction temp and loop filter voltage range for PLL tuning in 图 142 ............................................................... 128

Changes from Original (February 2017) to Revision A

Page

•

Corrected the NSD values for -9dBFS in Electrical Characteristics - AC Specifications table ........................................... 15

Added PLL/VCO characteristics table to PLL/VCO Electrical Characteristics ..................................................................... 16

Added JESD204B clock phase register setting to Table 41 ................................................................................................ 52

Removed descriptions for CLKJESD_DIV register from Table 41 ...................................................................................... 52

Added JESD204B clock phase register setting to Table 42 ................................................................................................ 52

Added information about the DAC output total current for various full scale current settings in DAC Fullscale Output

Current ................................................................................................................................................................................. 60

•

Changed Bit 0 of Table 128 From: Enables the GSM PLL To: Reserved.......................................................................... 121

Changed Table 130 ........................................................................................................................................................... 123

Changed description of SERDES_REFCLK_DIV register field in Table 131 .................................................................... 124

3

DAC38RF82, DAC38RF89

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

www.ti.com.cn

•

Changed Bit 12:11, 6:5 and 4:2 of Table 134 ................................................................................................................... 126

4

DAC38RF82, DAC38RF89

www.ti.com.cn

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

5 Device Comparison Table

PART NUMBER

DAC38RF82

DAC38RF89

ANALOG OUTPUT TYPE

VCO0 CENTER FREQUENCY

VCO1 CENTER FREQUENCY

Differential

5.9 GHz

5 GHz

8.9 GHz

7.5 GHz

6 Pin Configuration and Functions

AAV Package

144-Pin (FCBGA)

Top View

A

B

C

D

E

F

G

H

J

K

L

M

12

11

10

9

DACCLKSE VSSCLK

AGND

VOUT2+

VOUT2-

AGND

VDDOUT18 VDDOUT18

AGND

VOUT1-

VOUT1+

AGND

VSSCLK

AGND

EXTIO

AGND

VDDA1

VDDA18

VDDA1

VSSCLK

DGND

AGND

VEE18N

RESET

ALARM

GPI0

AGND

VEE18N

SCLK

AGND

SDIO

SDO

DACCLK+ VDDAPLL18

DACCLK- VDDAPLL18

VEE18N

VSSCLK

VDDL2_1

RBIAS VDDAVCO18VDDAVCO18 VSSCLK

VDDCLK1 VDDCLK1

8

VSSCLK

CLKTX+

CLKTX-

VDDDIG1

SYSREF-

SYSREF+

DGND

VSSCLK

VDDTX18

VDDTX1

VDDDIG1

VDDS18

DGND

ATEST

SYNC1+

SYNC1-

VDDDIG1

SYNC0+

SYNC0-

DGND

VDDPLL1 VDDPLL1

VSSCLK

VDDE1

DGND

VDDL1_1

DGND

VDDL1_1

VDDE1

DGND

SLEEP

GPO0

GPO1

DGND

RX1-

SDEN

GPI1

7

VDDDIG1

DGND

VDDDIG1

DGND

6

VDDE1

VDDDIG1

AMUX0

DGND

VDDE1

TRST

TXENABLE

DGND

RX3+

RX3-

5

VDDDIG1

VSENSE

IFORCE

DGND

VDDDIG1

AMUX1

DGND

VDDIO18

TMS

4

TDI

TDO

TCLK

3

VDDT1

VDDR18

RX4+

VDDT1

VDDR18

RX0+

TESTMODE

DGND

RX2-

2

RX2+

1

RX7+

RX7-

RX6-

RX6+

RX5+

RX5-

RX4-

RX0-

RX1+

Not to scale

5

DAC38RF82, DAC38RF89

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NO.

NAME

C11, C12, D11, E11,

F12, J12, K11, L11,

M11, M12

AGND

–

Analog ground.

CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high via

RESET_CONFIG alm_out_pol control bit..

K8

ALARM

O

G3

F3

AMUX0

O

I

Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating.

AMUX1

Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating.

C8

A7

ATEST

Analog test pin for DAC, references and PLL. Can be left floating.

CLKTX+

CLKTX-

Divided output clock, internal 100 Ω differential termination, self-biased, positive terminal.

Divided output clock, internal 100 Ω differential termination, self-biased, negative terminal.

Device clock, internal 100 Ω differential termination, self-biased, positive terminal.

Device clock, internal 100 Ω differential termination, self-biased, negative terminal.

Single ended device clock optional input. Can be left floating if not used, internal 50 Ω termination.

A6

A10

A9

DACCLK+

DACCLK-

DACCLKSE

I

A12

I

A2, B2, C2, D2, D6, E2,

E7, F2, F6, G2, G7, H6,

J7, K2, L2, L3, L4, L5,

M6

DGND

-

Digital ground.

C10

K7

M7

L7

EXTIO

GPI0

I/O

-

Requires a 0.1 μF decoupling capacitor to AGND.

Factory use only. User should GND.

Used for CMOS SYNC0\ signal.

GPI1

-

GPO0

GPO1

IFORCE

O

L6

Used for CMOS SYNC1\ signal.

D3

Test pin for on chip parametrics. Can be left floating.

Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS

(8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output.

C9

K9

RBIAS

O

I

Active low input for chip RESET, which resets all the programming registers to their default state. Internal

pull-up.

RESET

J1

K1

M1

L1

RX0+

RX0-

RX1+

RX1-

RX2+

RX2-

RX3+

RX3-

RX4+

RX4-

RX5+

RX5-

RX6+

RX6-

RX7+

RX7-

SCLK

SDEN

I

CML SerDes interface lane 0 input, positive

CML SerDes interface lane 0 input, negative

CML SerDes interface lane 1 input, positive

CML SerDes interface lane 1 input, negative

CML SerDes interface lane 2 input, positive

CML SerDes interface lane 2 input, negative

CML SerDes interface lane 3 input, positive

CML SerDes interface lane 3 input, negative

CML SerDes interface lane 4 input, positive

CML SerDes interface lane 4 input, negative

CML SerDes interface lane 5 input, positive

CML SerDes interface lane 5 input, negative

CML SerDes interface lane 6 input, positive

CML SerDes interface lane 6 input, negative

CML SerDes interface lane 7 input, positive

CML SerDes interface lane 7 input, negative

Serial interface clock. Internal pull-down.

M2

M3

M5

M4

H1

G1

E1

F1

D1

C1

A1

B1

L9

M8

Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up.

Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal

pull-down.

M10

M9

SDIO

SDO

I/O

O

Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface

mode (default).

L8

C4

C3

C7

C6

SLEEP

I

Active high asynchronous hardware power-down input. Internal pull-down.

Synchronization request to transmitter for JESD204B link 0, LVDS positive output.

Synchronization request to transmitter for JESD204B link 0, LVDS negative output.

Synchronization request to transmitter for JESD204B link 1, LVDS positive output.

Synchronization request to transmitter for JESD204B link 1, LVDS negative output.

SYNC0+

SYNC0-

SYNC1+

SYNC1-

O

6

DAC38RF82, DAC38RF89

www.ti.com.cn

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This

positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC

synchronization.

A3

SYSREF+

I

LVPECL SYSREF negative input, self biased, internal 100 Ω differential termination. (See the SYSREF+

description)

A4

SYSREF-

K4

H4

J4

TCLK

TDI

I

JTAG test clock. Internal pull-down

JTAG test data in. Internal pull-up

JTAG test data out. Internal pull-up

TDO

O

This pin is used for factory testing.

Recommended to connect to ground for normal operation.

K3

TESTMODE

-

K5

J5

TMS

I

JTAG test mode select. Internal pull-up

TRST

JTAG test reset. Internal pull-up. Must be connected to ground if not used

Transmit enable active high input. Internal pull-down.

This pin is ORed with spi_txenable bit in JESD_FIFO register to enable analog output data transmission.

To enable analog output data transmission, pull CMOS TXENABLE pin to high.

To disable analog output, pull CMOS TXENABLE pin to low. The DAC output is forced to midscale.

K6

TXENABLE

I

F11, J11

G11, H11

D8, E8

VDDA1

I

Analog 1 V supply voltage. Must be separated from VDDDIG1 supply for best performance.

Analog 1.8 V supply voltage. (1.8 V)

VDDA18

VDDPLL1

VDDAPLL18

VDDAVCO18

Analog 1 V supply for PLL.

B9, B10

D9, E9

PLL analog supply voltage. (1.8 V)

Analog supply voltage for VCO (1.8 V)

Internal clock buffer supply voltage (1 V).

It is recommended to isolate this supply from VDDDIG1 and VDDA1.

G9, H9

VDDCLK1

I

G8, H8

VDDL1_1

VDDL2_1

I

DAC core supply voltage. (1 V)

G10, H10

A5, B5, C5, D5, D7, E3,

E4, E5, E6, F4, F5, G4, VDDDIG1

G5

Digital supply voltage. (1 V).

It is recommended to isolate this supply from VDDCLK1 and VDDA1.

I

Digital Encoder supply voltage (1 V).

Must be separated from VDDDIG1 supply

F7, H7, G6, J6

VDDE1

H5

VDDIO18

VDDOUT18

VDDR18

VDDS18

VDDT1

I

Supply voltage for all digital I/O and CMOS I/O. (1.8 V)

DAC output supply. (1.8 V)

G12, H12

H2, J2

I

Supply voltage for SerDes. (1.8 V)

B3, B4

I

Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8 V)

Supply voltage for SerDes termination. (1 V)

Supply voltage for divided clock output. (1 V)

Supply voltage for divided clock output . (1.8 V)

Analog supply voltage. (-1.8 V)

H3, J3

I

B6

VDDTX1

VDDTX18

VEE18N

VOUT1+

VOUT1-

VOUT2+

VOUT2-

VSENSE

I

B7

I

D10, E10, K10, L10

I

L12

K12

D12

E12

D4

O

DAC channel 1 output.

DAC channel 1 complementary output.

DAC channel 2 output.

DAC channel 2 complementary output.

Test pin for on chip parametrics. Can be left floating.

A8, A11, B8, B11, B12,

F8, F9, F10, J8, J9, J10

VSSCLK

-

Clock ground.

7

DAC38RF82, DAC38RF89

ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

VDDDAC1, VDDDIG1, VDDL1_1, VDDL2_1,

VDDCLK1, VDDT1, VDDCLK1, VDDTX1, VDDE1

–0.3

1.3

V

VDDR18, VDDIO18, VDDS18, VDDAPLL18,

VDDAREF18, VDDAOUT18, VDDA18,

VDDAVCO18, VDDTX18

Supply Voltage Range⁽²⁾

–0.3

2.45

V

VEE18N

–2

0.3

V

Voltage between AGND and DGND

–0.3

–0.5

RX[0..7]+/-

VDDDIG1 + 0.5 V

SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM,

RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST,

TESTMODE, GPI0, GPI1, GPO0, GPO1

–0.5

VDDIO + 0.5 V

V

CLKOUT+/-

–0.5

VDDTX18 + 0.5 V

VDDCLK1 + 0.5 V

VDDS18 + 0.5 V

V

DACCLK+/-, SYSREF+/-, DACCLKSE

SYNC0+/-, SYNC1+/-

IOUT1+/-, IOUT2+/-

RBIAS, EXTIO, ATEST

IFORCE, VSENSE

Pin Voltage Range⁽²⁾

VDDAOUT18 + 0.5 V

VDDDIG1 + 0.5 V

VDDT1 + 0.5 V

20

V

AMUX1, AMUX0

V

Peak input current (any input)

Peak total input current (all inputs)

Junction temperature T_J

mA

°C

–30

150

85

Operating free-air temperature, T_A

Storage temperature, T_stg

–40

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to AGND or DGND.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

°C

Recommended operating temperature

Maximum rated operating junction temperature⁽¹⁾

Recommended free-air temperature

105

T_J

125

–40

°C

T_A

85

°C

VDDA18, VDDAPLL18, VDDS18,

VDDIO18, VDDR18, VDDAPLL18,

VDDOUT18, VDDAVCO18

1.71

1.8

1.89

Supply Voltage Range

VDDDIG1 VDDA1, VDDT1, VDDAPLL1,

VDDCLK1, VDDL1_1, VDDL2_1,

VDDTX1, VDDE1

V

0.95

1

1.05

VEE18N

–1.89

–1.8

–1.71

(1) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate

8

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ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

7.4 Thermal Information

DAC38RF82

DAC38RF89

THERMAL METRIC⁽¹⁾

UNIT

AAV (FCBGA)

144 PINS

R_θJA

Junction-to-ambient thermal resistance

25

1.0

7.7

0.1

7.7

N/A

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics - DC Specifications

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, nominal supplies, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC ACCURACY

8-bit Input Mode

8

12

16

14

Digital Input Resolution

12-bit Input Mode

16-bit Input Mode

bits

DAC Core Resolution

bits

LSB

DNL Differential nonlinearity

INL Integral nonlinearity

±3

±4

Analog Output

Gain Error

±2

30

%FSR

mA

Full scale output current

10

40

2:1 transformer coupled into 50 Ω- load.

Transformer (TCM2-452X-2+) loss not de-

embedded

P_(OUTFS)

Full scale output power

3

dBm

2.1 GHz output frequency

Output Compliance Range

Output capacitance

Output resistance

1.3

2.3

V

Single ended to ground

Differential

1.5

pF

100

ohms

Reference Output: EXTIO

V_REFReference output voltage

0.9

100

±8

V

nA

Reference output current

Reference voltage drift

ppm/°C

Power Supply Current and consumption

1 V Digital supplies: VDDDIG1

815

1300

1250

mA

1 V Analog supplies: VDDA1 VDDACLK1

VDDTX1 VDDAPLL1 VDDT1 VDDE1

1144

MODE 1: dual channel, 12-bit input mode, 2x

Interpolation, Sin(x)/x enabled, f_DAC= 6 GHz,

CLKTX Disabled

1.8 V Supplies: VDDA18 VDDOUT18

VDDAVCO18 VDDAPLL18 VDDR18

VDDIO18 VDDS18 VDDTX18

218

270

mA

-1.8 V Supply: VEE18N

Power Dissipation

159

2638

798

180

mA

mW

mA

P_DIS

3360

1 V Digital supplies: VDDDIG1

1 V Analog supplies: VDDA1 VDDACLK1

VDDTX1 VDDAPLL1 VDDT1 VDDE1

1026

222

mA

MODE 2: dual channel, 16-bit input mode, 2x

Interpolation, Sin(x)/x enabled, f_DAC= 5 GHz,

CLKTX Disabled

1.8 V Supplies: VDDA18 VDDOUT18

VDDAVCO18 VDDAPLL18 VDDR18

VDDIO18 VDDS18 VDDTX18

-1.8 V Supply: VEE18N

Power Dissipation

159

mA

P_DIS

2510

mW

9

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Electrical Characteristics - DC Specifications (continued)

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, nominal supplies, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1V Digital supplies: VDDDIG1

500

mA

1 V Analog supplies: VDDA1 VDDACLK1

VDDTX1 VDDAPLL1 VDDT1 VDDE1

751

218

mA

MODE 3: dual channel, 12-bit input mode, 2x

Interpolation, Sin(x)/x enabled, f_DAC= 3 GHz,

CLKTX Disabled

1.8 V Supplies: VDDA18 VDDOUT18

VDDAVCO18 VDDAPLL18 VDDR18

VDDIO18 VDDS18 VDDTX18

-1.8V Supply: VEE18N

Power Dissipation

159

1930

517

mA

mW

mA

P_DIS

1 V Digital supplies: VDDDIG1

1 V Analog supplies: VDDA1 VDDACLK1

VDDTX1 VDDAPLL1 VDDT1 VDDE1

708

222

mA

MODE 4: dual channel, 16-bit input mode, 2x

Interpolation, Sin(x)/x enabled, f_DAC= 2.5

GHz, CLKTX Disabled

1.8 V Supplies: VDDA18 VDDOUT18

VDDAVCO18 VDDAPLL18 VDDR18

VDDIO18 VDDS18 VDDTX18

-1.8 V Supply: VEE18N

Power Dissipation

159

1911

624

mA

mW

mA

1 V Digital supplies: VDDDIG1

1 V Analog supplies: VDDA1 VDDACLK1

VDDTX1 VDDAPLL1 VDDT1 VDDE1

1469

218

mA

MODE 5: dual channel, 8-bit input mode, 1x

Interpolation, Sin(x)/x enabled, f_DAC= 9 GHz,

CLKTX Disabled

1.8 V Supplies: VDDA18 VDDOUT18

VDDAVCO18 VDDAPLL18 VDDR18

VDDIO18 VDDS18 VDDTX18

-1.8 V Supply: VEE18N

Power Dissipation

159

2772

63

mA

mW

mA

1 V Digital supplies: VDDDIG1

568

105

1 V Analog supplies: VDDA1 VDDACLK1

VDDTX1 VDDAPLL1 VDDT1 VDDE1

18

47

mA

1.8 V Supplies: VDDA18 VDDOUT18

VDDAVCO18 VDDAPLL18 VDDR18

VDDIO18 VDDS18 VDDTX18

MODE 6: Power down mode, no clock, DAC

in sleep, SerDes in sleep, CLKTX Disabled

51

-1.8 V Supply: VEE18N

Power Dissipation

23

208

25

28

mA

mW

mA

815

f_DAC= 8847 MSPS, Clock Out Divider Enabled

f_DAC= 5898 MSPS, Clock Out Divider Enabled

Clock Out Enabled

VDDTX1

19

VDDTX18

16

10

DAC38RF82, DAC38RF89

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ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

7.6 Electrical Characteristics - Digital Specifications

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, external differential clock mode at 9

GSPS, 12x Interpolation, f_OUT= 2.14 GHz, I_(OUTFS)= 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CML SerDes Inputs: RX[7:0]+/-

V_DIFF

Receiver input amplitude

50

1200

mV

TERM = 111

TERM = 001

TERM = 100

TERM = 101

600

700

0

V_COM

Input Common Mode Voltage

mV

250

100

Z_DDIFF

f_SerDes

Internal differential termination

SerDes bit rate

85

115

Ω

0.78125

12.5

Gbps

Differential Clock Inputs: SYSREF±, DACCLK±

f_DACCLK

V_COM

V_I(DPP)

Z_T

DACCLK input frequency

Input common mode voltage

Differential input peak-to-peak voltage

Internal termination

0.1

9

GHz

V

0.5

800

100

2

2000

mV

Ω

C_L

Input capacitance

pF

Duty cycle (DACCLK only

40%

60%

LVDS Output: SYNC0±, SYNC1±

V_COM

Z_T

Output common mode voltage

1.2

100

500

V

Ω

Internal termination

V_OD

Differential output voltage swing

mV

CML Output: DIVCLKOUT±

V_ODCML OUTPUT: CLKTX+/-

1300

mV

CMOS Interface: SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM, RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST, TESTMODE, SYNCSE1,

SYNCSE2

0.7 x

VDDIO

V_IH

V_IL

High-level input voltage

Low-level input voltage

V

0.3 x

VDDIO

I_IH

I_IL

C_I

High-level input current

Low-level input current

CMOS input capacitance

–40

40

µA

pF

2

VDDIO –

0.2

I_LOAD= –100 µA

I_LOAD= –2 mA

V_OH

High-level output voltage

Low-level output voltage

V

0.8 x

VDDIO

I_LOAD= 100 µA

I_LOAD= 2 mA

0.2

0.5

V_OL

Latency

full rate, RATE = “00”

half rate, RATE = “01”

quarter rate, RATE = “10”

eighth rate, RATE = “11”

34

29

RX SerDes Digital Delay

UI

26.5

26.25

JESD

clock

cycles

SerDes output to JED204B elastic buffer

input latency

21 -39

11

DAC38RF82, DAC38RF89

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Electrical Characteristics - Digital Specifications (continued)

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, external differential clock mode at 9

GSPS, 12x Interpolation, f_OUT= 2.14 GHz, I_(OUTFS)= 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LMFSHD = 41121 or 82121, 1x Interpolation

LMFSHD = 41121 or 82121, 2x Interpolation

LMFSHD = 41121 or 82121, 4x Interpolation

LMFSHD = 41380 or 82380, 1x Interpolation

LMFSHD = 41380 or 82380, 2x Interpolation

LMFSHD = 81180, 1x Interpolation

269

417

717

293

465

289

LMFSHD = 82121, 6x Interpolation

269

LMFSHD = 82121, 8x Interpolation

1120

1602

2091

817

LMFSHD = 82121, 12x Interpolation

LMFSHD = 82121, 16x Interpolation

LMFSHD = 42111 or 84111, 6x Interpolation

LMFSHD = 42111 or 84111, 8x Interpolation

1057

LMFSHD = 42111 or 84111, 10x

Interpolation

1184

1532

1997

2142

LMFSHD = 42111 or 84111, 12x

Interpolation

LMFSHD = 42111 or 84111, 16x

Interpolation

LMFSHD = 42111 or 84111, 18x

Interpolation

LMFSHD = 42111 or 84111, 24x

Interpolation

2941

1020

1473

DAC clock

cycles

LMFSHD = 22210 or 44210, 8x Interpolation

Digital Latency: JESD Buffer to DAC Output

LMFSHD = 22210 or 44210, 12x

Interpolation

LMFSHD = 22210 or 44210, 16x

Interpolation

1917

2050

2275

2821

1912

LMFSHD = 22210 or 44210, 18x

Interpolation

LMFSHD = 22210 or 44210, 20x

Interpolation

LMFSHD = 22210 or 44210, 24x

Interpolation

LMFSHD = 12410 or 24410, 16x

Interpolation

LMFSHD = 12410 or 24410, 24x

Interpolation

2786

916

LMFSHD = 44210 or 88210, 8x Interpolation

LMFSHD = 44210 or 88210, 12x

Interpolation

1317

LMFSHD = 44210 or 88210, 16x

Interpolation

1709

2509

1672

1593

LMFSHD = 44210 or 88210, 24x

Interpolation

LMFSHD = 24410 or 48410, 16x

Interpolation

LMFSHD = 24410 or 48410, 24x

Interpolation

12

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Electrical Characteristics - Digital Specifications (continued)

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, external differential clock mode at 9

GSPS, 12x Interpolation, f_OUT= 2.14 GHz, I_(OUTFS)= 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

13

9

MAX

UNIT

LMFSHD = 41121 or 82121, 1x Interpolation

LMFSHD = 41121 or 82121, 2x Interpolation

LMFSHD = 41121 or 82121, 4x Interpolation

LMFSHD = 41380 or 82380, 1x Interpolation

LMFSHD = 41380 or 82380, 2x Interpolation

LMFSHD = 81180, 1x Interpolation

6

15

10

6

LMFSHD = 82121, 6x Interpolation

5

LMFSHD = 82121, 8x Interpolation

5

LMFSHD = 82121, 12x Interpolation

5

LMFSHD = 82121, 16x Interpolation

5

LMFSHD = 42111 or 84111, 6x Interpolation

LMFSHD = 42111 or 84111, 8x Interpolation

16

LMFSHD = 42111 or 84111, 10x

Interpolation

15

13

15

LMFSHD = 42111 or 84111, 12x

Interpolation

LMFSHD = 42111 or 84111, 16x

Interpolation

LMFSHD = 42111 or 84111, 18x

Interpolation

LMFSHD = 42111 or 84111, 24x

Interpolation

15

8

JESD

clock

LMFSHD = 22210 or 44210, 8x Interpolation

SYSREF TO JESD LMFC RESET

cycles

LMFSHD = 22210 or 44210, 12x

Interpolation

7

LMFSHD = 22210 or 44210, 16x

Interpolation

6

7

5

4

9

LMFSHD = 22210 or 44210, 18x

Interpolation

LMFSHD = 22210 or 44210, 20x

Interpolation

LMFSHD = 22210 or 44210, 24x

Interpolation

LMFSHD = 12410 or 24410, 16x

Interpolation

LMFSHD = 12410 or 24410, 24x

Interpolation

7

29

27

LMFSHD = 44210 or 88210, 8x Interpolation

LMFSHD = 44210 or 88210, 12x

Interpolation

LMFSHD = 44210 or 88210, 16x

Interpolation

26

25

8

LMFSHD = 44210 or 88210, 24x

Interpolation

LMFSHD = 24410 or 48410, 16x

Interpolation

LMFSHD = 24410 or 48410, 24x

Interpolation

6

13

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www.ti.com.cn

7.7 Electrical Characteristics - AC Specifications

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, external differential clock mode at 9

GSPS, 12x Interpolation, 0 dBFS, f_OUT= 2.14 GHz, I_(OUTFS)= 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Output

f_DACMaximum DAC sample rate

AC Performance - CW

DAC38RF82 only

DAC38RF89 only

9

GSPS

8.4

9

f_CLK= 6 GHz , f_OUT= 501 MHz

f_CLK= 6 GHz , f_OUT= 951 MHz

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

f_CLK= 6 GHz , f_OUT= 501 MHz

f_CLK= 6 GHz , f_OUT= 951 MHz

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

f_CLK= 6 GHz , f_OUT= 501 MHz

f_CLK= 6 GHz , f_OUT= 951 MHz

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

f_CLK= 6 GHz , f_OUT= 501 MHz

f_CLK= 6 GHz , f_OUT= 951 MHz

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

63

62

58

57

62

61

54

51

97

93

88

77

94

90

85

82

79

72

71

74

71

69

72

71

67

72

65

57

71

65

62

54

51

Spurious Free Dynamic Range 0 –

f_DAC/2

SFDR

HD2

dBc

Spurious Free Dynamic Range within

500 MHz f_OUT± 250 MHz

Spurious Free Dynamic Range

excluding HD2, HD3 and CMP2 0 –

f_DAC/2

2nd Order Harmonic

14

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ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

Electrical Characteristics - AC Specifications (continued)

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, external differential clock mode at 9

GSPS, 12x Interpolation, 0 dBFS, f_OUT= 2.14 GHz, I_(OUTFS)= 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_CLK= 6 GHz , f_OUT= 501 MHz

63

62

71

69

62

61

66

65

67

85

82

79

78

76

73

74

68

92

87

81

78

95

89

84

79

74

80

76

f_CLK= 6 GHz , f_OUT= 951 MHz

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

f_CLK= 6 GHz , f_OUT= 501 MHz

f_CLK= 6 GHz , f_OUT= 951 MHz

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

f_CLK= 6 GHz , f_OUT= 501 MHz

f_CLK= 6 GHz , f_OUT= 951 MHz

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

f_CLK= 6 GHz , f_OUT= 501 ± 5 MHz, –6 dBFS each tone

f_CLK= 6 GHz , f_OUT= 951 ± 5 MHz, –6 dBFS each tone

HD3

3rd Order Harmonic

dBc

CMP2

Fs/2 clock mixing product (Fs/2 – f_OUT

)

dBc

Fs/N (N = 4, 8, 16) clock mixing product

(f_OUT± Fs/N)

CMP4+

dBc

f_CLK= 6 GHz , f_OUT= 1851 ± 5 MHz, –6 dBFS each

tone

73

72

f_CLK= 6 GHz , f_OUT= 2651 ± 5 MHz, –6 dBFS each

tone

Third-order two-tone intermodulation

distortion

f_CLK= 9 GHz , f_OUT= 501 ± 5 MHz, –6 dBFS each tone

f_CLK= 9 GHz , f_OUT= 951 ± 5 MHz, –6 dBFS each tone

80

75

IMD3

dBc

f_CLK= 9 GHz , f_OUT= 1851 ± 5 MHz, –6 dBFS each

tone

70

68

f_CLK= 9 GHz , f_OUT= 2651 ± 5 MHz, –6 dBFS each

tone

f_CLK= 9 GHz , f_OUT= 3651 ± 5 MHz, –6 dBFS each

tone

15

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www.ti.com.cn

Electrical Characteristics - AC Specifications (continued)

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, external differential clock mode at 9

GSPS, 12x Interpolation, 0 dBFS, f_OUT= 2.14 GHz, I_(OUTFS)= 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_CLK= 6 GHz , f_OUT= 501 MHz

–170

f_CLK= 6 GHz , f_OUT= 951 MHz

–163

–157

–155

–172

–166

–157

–156

–153

–172

–164

–162

–159

–172

–166

–157

–173

–167

–159

–155

–151

–169

–167

–162

–157

82

f_CLK= 6 GHz , f_OUT= 1851 MHz

f_CLK= 6 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 501 MHz

f_CLK= 9 GHz , f_OUT= 951 MHz

f_CLK= 9 GHz , f_OUT= 1851 MHz

f_CLK= 9 GHz , f_OUT= 2651 MHz

f_CLK= 9 GHz , f_OUT= 3651 MHz

f_CLK= 6 GHz , f_OUT= 501 MHz, –9 dBFS

f_CLK= 6 GHz , f_OUT= 951 MHz, –9 dBFS

f_CLK= 6 GHz , f_OUT= 1851 MHz, –9 dBFS

f_CLK= 9 GHz , f_OUT= 2651 MHz, –9 dBFS

f_CLK= 9 GHz , f_OUT= 3651 MHz, –9 dBFS

f_CLK= 5 GHz , f_OUT= 501 MHz

Noise Spectral Density > 50 MHz

offset⁽¹⁾

NSD

dBFS/Hz

f_CLK= 5 GHz , f_OUT= 951 MHz

f_CLK= 5 GHz , f_OUT= 1851 MHz

f_CLK= 7.5 GHz , f_OUT= 501 MHz

f_CLK= 7.5 GHz , f_OUT= 951 MHz

f_CLK= 7.5 GHz , f_OUT= 1851 MHz

f_CLK= 7.5 GHz , f_OUT= 2651 MHz

f_CLK= 7.5 GHz , f_OUT= 3651 MHz

f_CLK= 5 GHz , f_OUT= 501 MHz, –9 dBFS

f_CLK= 5 GHz , f_OUT= 951 MHz, –9 dBFS

f_CLK= 5 GHz , f_OUT= 1851 MHz, –9 dBFS

f_CLK= 7.5 GHz , f_OUT= 2651 MHz, –9 dBFS

f_CLK= 7.5 GHz , f_OUT= 3651 MHz, –9 dBFS

f_OUT= 1856 MHz

NSD

(on-chip

PLL)

Noise Spectral Density > 50 MHz offset

On-chip PLL enabled

dBFS/Hz

Isolation between DAC A and DAC B

analog output

Isolation

dBc

f_OUT= 3105 MHz

73

(1) Also valid for on-chip PLL enabled in DAC38RF82

16

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ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

7.8 PLL/VCO Electrical Characteristics

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, internal PLL/VCO clock mode, 12x

Interpolation, f_OUT= 1.8 GHz, I_(OUTFS)= 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.

PARAMETER

TEST CONDITIONS

DAC38RF82

MIN TYP

DAC38RF89

UNIT

MAX

MIN

TYP

MAX

PLL/VCO

f_ref

Reference clock

frequency

100

f_VCO

/4

100

f_VCO

/4

MHz

KHz

f_PFD

f_vcoL

f_vcoH

f_BW

Frequency of phase &

frequency detector

500

6720

9000

500

5600

8400

Low VCO operating

frequency

5240

7960

500

4500

6600

High VCO operating

frequency

Loop filter bandwidth

500

Low VCO Phase Noise

600 KHz

-123

-132

-135

-146

Frequ

ency

1.2 MHz

f_vco= 6 GHz,CP=5, f_PFD= 500 MHz,

measured at output frequency = 1.8 GHz

1.8 MHz

Offset

6.0 MHz

dBc/Hz

600 KHz

-123

-132

-136

-147

Frequ

ency

1.2 MHz

f_vco= 5 GHz,CP=5, f_PFD= 312.5 MHz,

measured at output frequency = 1.8 GHz

1.8 MHz

Offset

6.0 MHz

High VCO Phase Noise

600 kHz

-123

-131

-135

-148

Frequ

ency

1.2 MHz

f_vco= 9 GHz, CP=5, f_PFD= 500 MHz,

measured at output frequency = 1.8 GHz

1.8 MHz

Offset

6.0 MHz

dBc/Hz

600 kHz

-124

-132

-136

-148

Frequ

ency

1.2 MHz

f_vco= 7.5 GHz, CP=5, f_PFD= 468.75 MHz,

measured at output frequency = 1.8 GHz

1.8 MHz

Offset

6.0 MHz

17

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7.9 Timing Requirements

MIN

NOM

MAX

UNIT

Digital Input Timing Specifications

Timing: SYSREF+/-

Setup time, SYSREF+/- valid to rising

edge of DACCLK+/-

t_s(SYSREF)

SYSREF Capture assist disabled

50

ps

Hold time, SYSREF+/- valid after rising

edge of DACCLK+/-

t_h(SYSREF)

Timing: Serial Port

t_s(/SDEN)

t_s(SDIO)

t_h(SDIO)

Setup time, SDEN to rising edge of SCLK

20

10

5

ns

µs

ns

Setup time, SDIO valid to rising edge of SCLK

Hold time, SDIO valid after rising edge of SCLK

temperature sensor read

All other registers

1

t_(SCLK)

Period of SCLK

100

25

t_d(Data)

t_RESET

Analog Output

Data output delay after falling edge of SCLK

Minimum RESET pulse width

t_s(DAC)

Output settling time to 0.1%

1

50

ns

ps

t_r

Output rise time 10% to 90%

Output fall time 90% to 10%

t_f

Latency

RX SerDes AnalogDelay

DAC wake-up time

250

90

ps

µs

I_OUTcurrent settling to 1% of I_OUTFS

from deep sleep

I_OUTcurrent settling to less than 1% of

I_OUTFSin deep sleep

DAC sleep time

90

µs

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7.10 Typical Characteristics

Unless otherwise noted, all plots are at T_A= 25°C, nominal supply voltages, f_DAC= 8847.36MSPS, 12x interpolation, 0dBFS

digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.

180

174

168

162

156

150

144

138

132

126

120

180

174

168

162

156

150

144

138

132

126

120

-12dBFS

-9dBFS

-6dBFS

0dBFS

Iout=40mA

Iout=30mA

Iout=20mA

Iout=10mA

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D005

D011

Figure 1. NSD vs Output Frequency Over Input Scale

Figure 2. NSD vs Output Frequency Over Output Current

I_outFS

180

80

-12dBFS

-6dBFS

0dBFS

174

168

162

156

150

144

138

132

126

120

75

70

65

60

55

50

45

40

35

5 GHz VCO (DAC38RF89)

7.5GHz VCO (DAC38RF89)

6 GHz VCO (DAC38RF82)

9 GHz VCO (DAC38RF82)

9 GHz External clock

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D012

D002

Figure 3. NSD vs Output Frequency Over Clocking Option

Figure 4. HD2 vs Output Frequency Over Input Scale

80

90

85

80

75

70

65

60

55

50

45

40

35

Iout=10mA

5 GHz VCO (DAC38RF89)

7.5GHz VCO (DAC38RF89)

6 GHz VCO (DAC38RF82)

9 GHz VCO (DAC38RF82)

9 GHz External clock

75

70

65

60

55

50

45

40

35

Iout=20mA

Iout=30mA

Iout=40mA

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D010

D012

Figure 5. HD2 vs Output Frequency Over Output Current

I_outFS

Figure 6. HD2 vs Output Frequency Over Clocking Option

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Typical Characteristics (continued)

Unless otherwise noted, all plots are at T_A= 25°C, nominal supply voltages, f_DAC= 8847.36MSPS, 12x interpolation, 0dBFS

digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.

80

75

70

65

60

55

50

45

40

35

105

100

95

90

85

80

75

70

65

60

55

50

45

40

35

Iout=10mA

Iout=20mA

Iout=30mA

Iout=40mA

-12dBFS

-6dBFS

0dBFS

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D004

D024

Figure 7. HD3 vs Output Frequency Over Input Scale

Figure 8. HD3 vs Output Frequency Over Output Current

I_outFS

80

-12dBFS

-6dBFS

0dBFS

75

70

65

60

55

50

45

40

35

75

70

65

60

55

50

45

40

35

5 GHz VCO (DAC38RF89)

7.5GHz VCO (DAC38RF89)

6 GHz VCO (DAC38RF82)

9 GHz VCO (DAC38RF82)

9 GHz External clock

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D012

D001

Figure 9. HD3 vs Output Frequency Over Clocking Option

Figure 10. SFDR vs Output Frequency Over Input Scale

80

90

Iout=10mA

5 GHz VCO (DAC38RF89)

7.5GHz VCO (DAC38RF89)

6 GHz VCO (DAC38RF82)

9 GHz VCO (DAC38RF82)

9 GHz External clock

85

80

75

70

65

60

55

50

45

40

35

75

70

65

60

55

50

45

40

35

Iout=20mA

Iout=30mA

Iout=40mA

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D008

D012

Figure 11. SFDR vs Output Frequency Over Output Current

I_outFS

Figure 12. SFDR vs Output Frequency Over Clocking Option

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Typical Characteristics (continued)

Unless otherwise noted, all plots are at T_A= 25°C, nominal supply voltages, f_DAC= 8847.36MSPS, 12x interpolation, 0dBFS

digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.

80

75

70

65

60

55

50

45

40

35

80

75

70

65

60

55

50

45

40

35

5 GHz VCO (DAC38RF89)

7.5GHz VCO (DAC38RF89)

6 GHz VCO (DAC38RF82)

9 GHz VCO (DAC38RF82)

9 GHz External clock

-18dBFS

-12dBFS

-6dBFS

0dBFS

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D006

D012

-18 dBFS digital backoff

Figure 13. IMD3 vs Output Frequency Over Input Scale

Figure 14. IMD3 vs Output Frequency Over Clocking Option

6

5

4

90

DAC A to B

DAC B to A

86

82

3

2

78

74

70

66

62

58

54

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

50

0

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

500 1000 1500 2000 2500 3000 3500 4000 4500

Output Frequency (MHz)

D000

D002

Figure 15. Power vs Output Frequency

Figure 16. Isolation vs Output Frequency

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Typical Characteristics (continued)

Unless otherwise noted, all plots are at T_A= 25°C, nominal supply voltages, f_DAC= 8847.36MSPS, 12x interpolation, 0dBFS

digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.

-60

-80

-100

-120

-140

-160

CP=1

CP=2

CP=3

CP=4

CP=5

CP=6

CP=7

CP=8

CP=9

CP=10

CP=11

CP=12

CP=13

CP=14

CP=15

CP=2

CP=3

CP=4

CP=5

CP=6

CP=7

CP=8

CP=9

CP=10

CP=11

CP=12

CP=13

CP=14

CP=15

-80

-100

-120

-140

-160

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

D027

D003

VCO frequency = 8.85 GHz

Measured at 1.8 GHz

VCO frequency = 7.5 GHz

Measured at 1.8 GHz

Figure 17. DAC38RF82 VCO1 Phase Noise vs Offset

Frequency Over Charge pump current

Figure 18. DAC38RF89 VCO1 Phase Noise vs Offset

Frequency Over Charge pump current

-90

div4

div3

div2

div4

div3

div2

-100

-110

-120

-130

-140

-150

-160

-100

-110

-120

-130

-140

-150

-160

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

D028

D004

VCO frequency = 8.85 GHz

VCO frequency = 7.5 GHz

Figure 19. DAC38RF82 VCO1 Output Clock Phase Noise vs

Offset frequency Over Divider Ratio

Figure 20. DAC38RF89 VCO1 Output Clock Phase Noise vs

Offset frequency Over Divider Ratio

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Typical Characteristics (continued)

Unless otherwise noted, all plots are at T_A= 25°C, nominal supply voltages, f_DAC= 8847.36MSPS, 12x interpolation, 0dBFS

digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.

-80

-100

-120

-140

-160

-80

-100

-120

-140

-160

CP=1

CP=2

CP=3

CP=4

CP=5

CP=6

CP=7

CP=8

CP=9

CP=10

CP=11

CP=12

CP=13

CP=14

CP=15

CP=1

CP=2

CP=3

CP=4

CP=5

CP=6

CP=7

CP=8

CP=9

CP=10

CP=11

CP=12

CP=13

CP=14

CP=15

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

D029

D001

VCO frequency = 5.9 GHz

Measured at 1.8 GHz

VCO frequency = 5.0 GHz

Measured at 1.8 GHz

Figure 21. DAC38RF82 VCO0 Phase Noise vs Offset

Frequency Over Charge Pump Current

Figure 22. DAC38RF89 VCO0 Phase Noise vs Offset

Frequency Over Charge Pump Current

-100

div4

div3

div2

div4

div3

div2

-110

-120

-130

-140

-150

-160

-110

-120

-130

-140

-150

-160

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

1000

10000

100000 1000000

Freq offset (Hz)

1E+7

5E+7

D030

VCO frequency = 5.9 GHz

VCO frequency = 5.0 GHz

Figure 23. DAC38RF82 VCO0 Output clock Phase Noise vs

Offset Frequency Over Divider Ratio

Figure 24. DAC38RF89 VCO0 Output clock Phase Noise vs

Offset Frequency Over Divider Ratio

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8 Detailed Description

8.1 Overview

The DAC38RF82 and DAC38RF89 are high performance, wide bandwidth RF-sampling digital-to-analog (DACs)

that are capable of dual channel input data rate up to 3.33 GSPS or single-channel operation with 8-bits up to 9-

GSPS. The devices have a low power JESD204B Interface with up to 8 lanes, with a maximum bit rate of 12.5

Gbps. In dual channel operation, the input interface is capable of data rates up to 3.33 GSPS at 12-bits and 2.5

GSPS at 16-bits resolution without interpolation. When used as a complex baseband transmitter with

interpolation modes from 2x to 24x, the DAC38RF82 (or DAC38RF89) is capable of synthesizing wideband

signals up to 2 GHz bandwidth with 16-bit input resolution and 2.66 GHz bandwidth with 12-bit input resolution.

The 8-bit mode allows an input at the full 9 GSPS maximum DAC sample rate and can synthesize wideband

signals from 0 to 4.5 GHz. An optional low jitter PLL/VCO simplifies the DAC clock generation by allowing use of

a lower frequency reference clock. DAC38RF82 and DAC38RF89 support different VCO frequency ranges,

summarized in Device Comparison Table.

8.2 Functional Block Diagrams

DACCLK+

CLKTX+

Divider

/2, /3, /4

Low Jitter

PLL

Clock

Distribution

CLKTXœ

DACCLKœ

VDDTX1

DACCLKSE

Multi-band DUC Channel 2 (multi-DUC2)

NCO 3

VDDTX18

DACB

Gain

SYSREF+

I

SYSREFœ

Q

I

VOUT2+

14-b

DAC

x

sin(x)

RX[4..7]+

100 W

VOUT2œ

RX[4..7]œ

Q

SYNC2\+

SYNC2\œ

VDDT1

NCO 4

NCO 1

0.9 V

Ref

EXTIO

RBIAS

TESTMODE

VDDR18

I

RX[0..3]+

Q

I

VOUT1+

14-b

DAC

x

sin(x)

100 W

RX[0..3]œ

VOUT1œ

SYNC1\+

Q

VEE18N

VDDA18

ATEST

DACA

Gain

NCO 2

SYNC1\œ

VDDS18

Multi-band DUC Channel 1 (multi-DUC1)

AMUX0/1

IFORCE

Temp

Sensor

JTAG

Control Interface

VSENSE

Figure 25. 12-, 16-Bit Input Mode Block Diagram

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Functional Block Diagrams (continued)

DACCLK+

CLKTX+

Divider

/2, /3, /4

Low Jitter

PLL

Clock

Distribution

CLKTX-

DACCLK-

VDDTX1

DACCLKSE

VDDTX18

SYSREF+

SYSREF-

RX[4..7]+

RX[4..7]-

DACA

Gain

SYNC2\+

SYNC2\-

VOUT1+

VOUT1-

14-b

DAC

x

100W

sin(x)

8

VDDT1

VDDR18

RX[0..3]+

RX[0..3]-

0.9 V

Ref

EXTIO

RBIAS

TESTMODE

SYNC1\+

VEE18N

SYNC1\-

VDDS18

VDDA18

ATEST

AMUX0/1

IFORCE

Temp

Sensor

JTAG

Control Interface

VSENSE

Figure 26. 8-Bit Input Mode Block Diagram

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8.3 Feature Description

8.3.1 SerDes Inputs

The DAC38RF82 (or DAC38RF89) RX [0..7]+/- differential inputs are each internally terminated to a common

point via 50 Ω, as shown in Figure 27.

RXP

0.7V

50O

To

TERM

Equalizer

&

Samplers

=001

Level

Shift

TERM

=100

50pF

TERM

=101

50O

0.25V

RXN

Figure 27. Serial Lane Input Termination

Common mode termination is via a 50 pF capacitor to GND. The common mode voltage and termination of the

differential signal can be controlled in a number of ways to suit a variety of applications via field TERM in register

SRDS_CFG2 (8.5.87), as described in Table 1.

NOTE

AC coupling is recommended for JESD204B compliance.

Table 1. Receiver Termination Selection

TERM

EFFECT

000

Reserved

Common point set to 0.7 V. This configuration is for AC coupled systems. The transmitter has no effect on the

receiver common mode, which is set to optimize the input sensitivity of the receiver. Note: this mode is not

compatible with JESD204B.

001

01x

100

101

110

Reserved

Common point set to GND. This configuration is for applications that require a 0 V common mode.

Common point set to 0.25 V. This configuration is for applications that require a low common mode.

Reserved

Common point floating. This configuration is for DC coupled systems in which the common mode voltage is set by

the attached transmit link partner to 0 and 0.6 V. Note: this mode is not compatible with JESD204B

111

Input data is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm.

The polarity of RX+ and RX- can be inverted by setting the bit of the corresponding lane in field INVPAIR in

register SRDS_POL (8.5.88) to “1”. This can potentially simplify PCB layout and improve signal integrity by

avoiding the need to swap over the differential signal traces.

Due to processing effects, the devices in the RX+ and RX- differential sense amplifiers will not be perfectly

matched and there will be some offset in switching threshold. The DAC38RF82 (or DAC38RF89) contains

circuitry to detect and correct for this offset. This feature can be enabled by setting ENOC in register

SRDS_CFG1 (8.5.86) to “1”. It is anticipated that most users will enable this feature.

8.3.2 SerDes Rate

The DAC38RF82 (or DAC38RF89) has eight configurable JESD204B serial lanes. The highest speed of each

SerDes lane is 12.5 Gbps. Because the primary operating frequency of the SerDes is determined by its reference

clock and PLL multiplication factor, there is a limit on the lowest SerDes rate supported. To support lower speed

application, each receiver should be configured to operate at half, quarter or eighth of the full rate via field RATE

in register SRDS_CFG2 (8.5.87). Refer to Table 2 for details.

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Table 2. Lane Rate Selection

RATE

00

EFFECT

Full rate. Four data samples taken per SerDes PLL output clock cycle.

Half rate. Two data samples taken per SerDes PLL output clock cycle.

Quarter rate. One data samples taken per SerDes PLL output clock cycle.

Eighth rate. One data samples taken every two SerDes PLL output clock cycles.

01

10

11

8.3.3 SerDes PLL

The DAC38RF82 (or DAC38RF89) has two integrated PLLs, one PLL is to provide the clocking of DAC, refer to

the DAC PLL section; the other PLL is to provide the clocking for the high speed SerDes. The reference

frequency of the SerDes PLL can be in the range of 100-800 MHz nominal, and 300-800 MHz optimal. The

reference frequency is derived from DACCLK divided down by the value in field SerDes_REFCLK_DIV in register

SRDS_CLK_CFG (8.5.84), as shown in Figure 28. Field SerDes_CLK_SEL in register SRDS_CLK_CFG (8.5.84)

determines if the DACCLK input or DAC PLL output is used as the source of the SerDes PLL reference. If the

DACCLK input is used, a pre-divider set by field SerDes_REFCLK_PREDIV in register SRDS_CLK_CFG

(8.5.84) should be used to reduce the frequency of the DACCLK.

SERDES_REFCLK_PREDIV

Predivider

DAC PLL

0

1

SERDES

PLL

REFCLK

DACCLK+

DACCLK-

divider

0

1

DACCLKSE

SERDES_REFCLK_DIV

SERDES_REFCLK_SEL

SEL_EXTCLK_DIFFSE

Figure 28. Reference Clock of SerDes PLL

During normal operation, the clock generated by PLL is 4-25 times the reference frequency, according to the

multiply factor selected via the field MPY] in register SRDS_PLL_CFG (8.5.85). In order to select the appropriate

multiply factor and reference clock frequency, it is first necessary to determine the required PLL output clock

frequency. The relationship between the PLL output clock frequency and the lane rate is determined by field

RATE in register SRDS_CFG2 (8.5.87) is shown in Table 3. Having computed the PLL output frequency, the

reference frequency can be obtained by dividing this by the multiply factor specified via MPY.

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Table 3. Relationship Between Lane Rate and SerDes PLL Output Frequency

RATE

00

LINE RATE

x Gbps

PLL OUTPUT FREQUENCY

0.25x GHz

01

x Gbps

0.5x GHz

10

x Gbps

1x GHz

11

x Gbps

2x GHz

Table 4. SerDes PLL Multiplier (MPY) Values

MPY

0x10

EFFECT

4x

0x14

5x

0x18

6x

0x20

8x

0x21

8.25x

10x

0x28

0x30

12x

0x32

12.5x

15x

0x3C

0x40

16x

0x42

16.5x

20x

0x50

0x58

22x

0x64

25x

Other codes

Reserved

The wide range of multiply factors combined with the different rate modes means it is often possible to achieve a

given line rate from multiple different reference frequencies. The configuration which utilizes the highest

reference frequency achievable is always preferable.

The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop

filter depending on the operating frequency of the VCO. If the PLL output frequency is below 2.17 GHz, VRANGE

in register SRDS_PLL_CFG (8.5.84) should be set high.

Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock

by setting the appropriate loop bandwidth via field LB in register SRDS_PLL_CFG (8.5.84). The loop bandwidth

is obtained by dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and

PLL output frequency as shown in Table 5.

Table 5. SerDes PLL Loop Bandwidth Selection

LB

EFFECT

BWSCALE vs PLL OUTPUT FREQUENCY

3.125 GHz

2.17 GHz

1.5625 GHz

00

01

10

11

Medium loop bandwidth

Ultra high loop bandwidth

Low loop bandwidth

13

7

14

8

16

8

21

10

23

11

30

14

High loop bandwidth

An approximate loop bandwidth of 8 – 30 MHz is suitable and recommended for most systems where the

reference clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input

cell, but of low quality, an approximate loop bandwidth of less than 8 MHz may offer better performance. For

systems where the reference clock is cleaned via an ultra-low jitter LC-based cleaner PLL, a high loop bandwidth

up to 60 MHz is more appropriate. Note that the use of ultra-high loop bandwidth setting is not recommended for

PLL multiply factor of less than 8.

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A free running clock output is available when field ENDIVCLK in register SRDS_PLL_CFG (8.5.85) is set high. It

runs at a fixed divided-by-80 of the PLL output frequency and can be output on the ALARM pin by setting field

DTEST to “0001” (lanes 0 – 3) or “0010” (lanes 4 – 7) in register DTEST (8.5.76).

8.3.4 SerDes Equalizer

All channels of the DAC38RF82 (or DAC38RF89) incorporate an adaptive equalizer, which can compensate for

channel insertion loss by attenuating the low frequency components with respect to the high frequency

components of the signal, thereby reducing inter-symbol interference. Figure 29 shows the response of the

equalizer, which can be expressed in terms of the amount of low frequency gain and the frequency up to which

this gain is applied (i.e., the frequency of the ’zero’). Above the zero frequency, the gain increases at 6 dB/octave

until it reaches the high frequency gain.

dB

6

-6.3

Log₁₀MHz

108

414

Frequency

Figure 29. Equalizer Frequency Response

The equalizer can be configured via fields EQ and EQHLD in register SRDS_CFG1 (8.5.86). Table 6 and Table 7

summarize the options. When enabled, the receiver equalization logic analyzes data patterns and transition times

to determine whether the low frequency gain should be increased or decreased. The decision logic is

implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results

reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable

response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not possible to

specify a generally applicable absolute limit. However, assuming random data, the maximum lock time will be

6x106 divided by the CDR activity level. For field CDR in register SRDS_CFG1 (8.5.86) = 110, the activity level

is 1.5 x 10⁶UI.

When EQ[2] = 0, finer control of gain boost is available using the EQBOOST IEEE1500 tuning chain field, as

shown in Table 6.

Table 6. Receiver Equalization Configuration

EQ

EFFECT

No equalization. The equalizer provides a flat response at the maximum gain. This setting may be

appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than

frequency dependent loss.

00

01

10

11

Fully adaptive equalization. The zero position is determined by the selected operating rate, and the

low frequency gain of the equalizer is determined algorithmically by analyzing the data patterns and

transition positions in the received data. This setting should be used for most applications.

[1-0]

Precursor equalization analysis. The data patterns and transition positions in the received data are

analyzed to determine whether the transmit link partner is applying more or less precursor

equalization than necessary.

Postcursor equalization analysis. The data patterns and transition positions in the received data are

analyzed to determine whether the transmit link partner is applying more or less post-cursor

equalization than necessary.

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Table 6. Receiver Equalization Configuration (continued)

EQ

EFFECT

0

1

Default

[2]

Boost. Equalizer gain boosted by 6 dB, with a 20% reduction in bandwidth, and an increase of

5mW power consumption. May improve performance over long links.

Table 7. Receiver Equalizer Hold

EQHOLD

EFFECT

Equalizer adaption enabled. The equalizer adaption and analysis algorithm is enabled. This should be the default

state.

0

Equalizer adaption held. The equalizer is held in its current state. Additionally, the adaption and analysis algorithm

is reset.

1

Table 8. Relationship Between Lane Rate and SerDes PLL Output Frequency

EQBOOST

GAIN BOOST (dB)

BANDWIDTH CHANGE (%)

POWER INCREASE (mW)

00

01

11

0

2

4

6

0

5

-30

10

-20

When EQ is set to 010 or 011, the equalizer is reconfigured to provide analytical data about the amount of pre

and post cursor equalization respectively present in the received signal. This can in turn be used to adjust the

equalization settings of the transmitting link partner, where a suitable mechanism for communicating this data

back to the transmitter exists. Status information is provided by setting field DTEST in register DTEST (8.5.76) to

“0111” for EQOVER and “0110” for EQUNDER. The procedure is as follows:

1. Enable the equalizer by setting fields EQHLD low and EQ to “001” (register SRDS_CFG1 8.5.86). Allow

sufficient time for the equalizer to adapt;

2. Set EQHLD to 1 to lock the equalizer and reset the adaption algorithm. This also causes both EQOVER and

EQUNDER to become low;

3. Wait at least 48 UI, and proportionately longer if the CDR activity is less than 100%, to ensure the 1 on

EQHLD is sampled and acted upon;

4. Set EQ to “010” or “011”, and EQHLD to 0. The equalization characteristics of the received signal are

analysed (the equalizer response will continue to be locked);

5. Wait at least 150×103 UI to allow time for the analysis to occur, proportionately longer if the CDR activity is

less than 100%;

6. Examine EQOVER and EQUNDER for results of analysis

–

If EQOVER is high, it indicates the signal is over equalized;

If EQUNDER is high, it indicates the signal is under equalized;

7. Set EQHLD to 1;

8. Repeat items 3–7 if required;

9. Set EQ to “001”, and EQHLD to 0 to exit analysis mode and return to normal adaptive equalization.

NOTE

When changing EQ from one non-zero value to another, EQHLD must already be 1. If this

is not the case, there is a chance the equalizer could be reset by a transitory input state

(i.e., if EQ is momentarily 000). EQHLD can be set to 0 at the same time as EQ is

changed.

As the equalizer adaption algorithm is designed to equalize the post cursor, EQOVER or

EQUNDER will only be set during post cursor analysis if the amount of post cursor

equalization required is more or less than the adaptive equalizer can provide.

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8.3.5 JESD204B Descrambler

The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x14 + x15. From

the JESD204B specification, the scrambling/descrambling process only occurs on the user data, not on the code

group synchronization or the ILA sequence. Each multi-DUC has a separate descrambler that can be enabled

independently. The descrambler is enabled by field SCR in the multi-DUC paged register JESD_N_HD_SCR

(8.5.49).

8.3.6 JESD204B Frame Assembly

The DAC38RF82 (or DAC38RF89) may be programmed as a single or dual DAC device, with one JESD RX

block designated for each DAC. The two JESD RX blocks can be programmed to operate as two separate links

or as a single link.

The JESD204B defines the following parameters:

•

L is the number of lanes

M is the number of I or Q streams per device (2 = 1 IQ pair, 4 = 2 IQ pairs, 8 = 4 IQ pairs)

F is the number of octets per frame clock period

S is the number of samples per frame

HD is the High-Density bit which controls whether a sample may be divided over more lanes

N = NPRIME is the number of bits per sample (12 or 16 - bits)

Fields K and L are found in multi-DUC paged register JESD_K_L (8.5.46), M and S in multi-DUC paged register

JESD_M_S (8.5.48), and N, NPRIME and HD in multi-DUC paged register JESD_N_HD_SCR (8.5.49).

Table 9 lists the available JESD204B formats, interpolation rates and sample rate limits for the DAC38RF82 (or

DAC38RF89). The ranges are limited by the SerDes PLL VCO frequency range, the SerDes PLL reference clock

range, the maximum SerDes line rate, and the maximum DAC sample frequency. Table 10 through Table 27 lists

the frame formats for each mode. In the frame format tables, i CH (N) [x:y] and q CH (N) [x:y] are bits x through y

of the I and Q samples at time N of DUC channel CH. If [x..y] is not listed, the full sample is assumed. For

example, i0(0)[15:8] are bits 15 – 8 of the I sample at time 0, and q(1) is the full Q sample at time 1.

Table 9. JESD204B Formats for DAC38RF82 and DAC38RF89

L-M-F-S-Hd

1 TX

L-M-F-S-Hd

2 TX

Input

Resolution

IQ pairs per

DAC

Input rate

max (MSPS)

f_DACMax

(MSPS)

Frame Format

Interp

16

1

6

1500

1125

750

9000

7500

9000

5000

7500

9000

5000

7500

8

82121

42111

NA

1 TX: Table 10

12

16

6

562.5

1250

1125

900

8

10

12

16

18

24

8

1 TX: Table 11

2 TX: Table 12

84111

750

562.5

500

375

625

12

16

18

20

24

16

24

625

562.5

500

1 TX: Table 13

2 TX: Table 14

22210

12410

44210

24410

450

375

312.5

1 TX: Table 15

2 TX: Table 16

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Table 9. JESD204B Formats for DAC38RF82 and DAC38RF89 (continued)

L-M-F-S-Hd

1 TX

L-M-F-S-Hd

2 TX

Input

Resolution

IQ pairs per

DAC

Input rate

max (MSPS)

f_DACMax

(MSPS)

Frame Format

Interp

16

2

8

625

5000

7500

9000

5000

7500

12

16

24

16

24

1 TX: Table 17

2 TX: Table 18

44210

24410

88210

48410

562.5

375

312.5

1 TX: Table 19

2 TX: Table 20

1 TX: Table 21

2 TX: Table 22

24310

81180

48310

NA

12

8

2

24

375

9000

1 TX: Table 23

real input

1

2

1

2

4

9000

3333

2500

2250

9000

3333

6666

2500

5000

9000

1 TX: Table 24

2 TX: Table 25

41380

82380

12

real input⁽¹⁾

1 TX: Table 26

2 TX: Table 27

41121

82121

16

real input⁽¹⁾

(1) Can also be used as I-Q pair per 2 DACs. See description in Wideband DUC (wide-DUC)

Table 10. JESD204B Frame Format for LMFSHd = 82121

# un bits

# en bits

Nibble

4

5

1

8

10

2

lane RX0

lane RX1

lane RX2

lane RX3

lane RX4

lane RX5

lane RX6

lane RX7

i0[15:8]

i0[7:0]

i1[15:8]

i1[7:0]

q0[15:8]

q0[7:0]

q1[15:8]

q1[7:0]

Table 11. JESD204B Frame Format for LMFSHd = 42111

# un bits

# en bits

Nibble

4

5

1

8

10

2

lane RX0

lane RX1

lane RX2

lane RX3

i0[15:8]

i0[7:0]

q0[15:8]

q0[7:0]

Table 12. JESD204B Frame Format for LMFSHd = 84111

# un bits

# en bits

Nibble

4

5

1

8

10

2

lane RX0

lane RX1

A-i0[15:8]⁽¹⁾

A-i0[7:0]⁽²⁾

(1) DAC A, I sample 0, MSB byte

(2) DAC A, I sample 0, LSB byte

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Table 12. JESD204B Frame Format for LMFSHd = 84111 (continued)

lane RX2

lane RX3

lane RX4

lane RX5

lane RX6

lane RX7

A-q0[15:8]

A-q0[7:0]

B-i0[15:8]

B-i0[7:0]

B-q0[15:8]

B-q0[7:0]

Table 13. JESD204B Frame Format for LMFSHd = 22210

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

lane RX0

lane RX1

i0

q0

Table 14. JESD204B Frame Format for LMFSHd = 44210

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

lane RX0

lane RX1

lane RX2

lane RX3

A-i0⁽¹⁾

A-q0

B-i0

B-q0

(1) DAC A, I sample 0

Table 15. JESD204B Frame Format for LMFSHd = 12410

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

20

25

5

24

30

6

28

35

7

32

40

8

lane RX0

i0

q0

Table 16. JESD204B Frame Format for LMFSHd = 24410

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

20

25

5

24

30

6

28

35

7

32

40

8

lane RX0

lane RX1

A-i0⁽¹⁾

B-i0

A-q0

B-q0

(1) DAC A, I sample 0

Table 17. JESD204B Frame Format for LMFSHd = 44210

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

lane RX0

lane RX1

lane RX2

A1-i0⁽¹⁾

A1-q0⁽²⁾

A2-i0

(1) DAC A, MultiDUC 1, I sample 0

(2) DAC A, MultiDUC 2, I sample 0

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Table 17. JESD204B Frame Format for LMFSHd = 44210 (continued)

lane RX3

A2-q0

Table 18. JESD204B Frame Format for LMFSHd = 88210

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

lane RX0

lane RX1

lane RX2

lane RX3

lane RX4

lane RX5

lane RX6

lane RX7

A1-i0⁽¹⁾

A1-q0

A2-i0

A2-q0

B1-i0

B1-q0

B2-i0

B1-q0

(1) DAC A, MultiDUC 1, I sample 0

Table 19. JESD204B Frame Format for LMFSHd = 24410

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

20

25

5

24

30

6

28

35

7

32

40

8

lane RX0

lane RX1

A1-i0⁽¹⁾

A2-i0

A1-q0

A2-q0

(1) DAC A, MultiDUC 1, I sample 0

Table 20. JESD204B Frame Format for LMFSHd = 48410

# un bits

# en bits

Nibble

4

5

1

8

10

2

12

15

3

16

20

4

20

25

5

24

30

6

28

35

7

32

40

8

lane RX0

lane RX1

lane RX2

lane RX3

A1-i0⁽¹⁾

A2-i0

A1-q0

A2-q0

B1-q0

B2-q0

B1-i0

B2-i0

(1) DAC A, MultiDUC 1, I sample 0

Table 21. JESD204B Frame Format for LMFSHd = 24310

# un bits

# en bits

Nibble

4

5

1

8

10

12

15

3

16

20

4

20

25

5

24

30

6

2

lane RX0

lane RX1

A1-i0⁽¹⁾

A1-q0

A2-q0

A2-i0

(1) DAC A, MultiDUC 1, I sample 0

Table 22. JESD204B Frame Format for LMFSHd = 48310

# un bits

# en bits

4

5

8

12

15

16

20

25

24

30

10

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Table 22. JESD204B Frame Format for LMFSHd = 48310 (continued)

Nibble

1

2

3

4

5

6

lane RX0

lane RX1

lane RX2

lane RX3

A1-i0⁽¹⁾

A2-i0

B1-i0

B2-i0

A1-q0

A2-q0

B1-q0

B2-q0

(1) DAC A, MultiDUC 1, I sample 0

Table 23. JESD204B Frame Format for LMFSHd = 81180

# un bits

# en bits

Nibble

4

5

1

8

10

2

lane RX0

lane RX1

lane RX2

lane RX3

lane RX4

lane RX5

lane RX6

lane RX7

A0⁽¹⁾

A1

A2

A3

A4

A5

A6

A7

(1) DAC A, sample 0

Table 24. JESD204B Frame Format for LMFSHd = 41380

# un bits

# en bits

Nibble

lane 0

4

5

1

8

10

12

15

3

16

20

4

20

25

24

30

6

2

5

A-0⁽¹⁾

A-2

A-4

A-6

A-1

A-3

A-5

A-7

lane 1

lane 2

lane 3

(1) DAC A, sample 0

Table 25. JESD204B Frame Format for LMFSHd = 82380

# un bits

# en bits

Nibble

lane 0

lane 1

lane 2

lane 3

lane 4

lane 5

lane 6

lane 7

4

5

1

8

12

15

3

16

20

4

20

25

24

30

6

10

2

5

i(0)

i(2)

i(4)

i(6)

q(0)

q(2)

q(4)

q(6)

i(1)

i(3)

i(5)

i(7)

q(1)

q(3)

q(5)

q(7)

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Table 26. JESD204B Frame Format for LMFSHd = 41121

# un bits

# en bits

Nibble

lane 0

4

5

1

8

10

2

A-0[15:8]⁽¹⁾

A-0[7:0]⁽²⁾

A-1[15:8]

A-1[7:0]

lane 1

lane 2

lane 3

(1) DAC A, sample 0, MSB byte

(2) DAC A, sample 0, LSB byte

Table 27. JESD204B Frame Format for LMFSHd = 82121

# un bits

# en bits

Nibble

4

5

1

8

10

2

lane RX0

lane RX1

lane RX2

lane RX3

lane RX4

lane RX5

lane RX6

lane RX7

A-0[15:8]⁽¹⁾

A-0[7:0]⁽²⁾

A-1[15:8]

A-1[7:0]

B-0[15:8]

B-0[7:0]

B-1[15:8]

B-1[7:0]

(1) DAC A, sample 0, MSB byte

(2) DAC A, sample 0, LSB byte

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8.3.7 SYNC Interface

The DAC38RF82 (or DAC38RF89) JESD204B interface has two differential SYNC outputs called SYNC0 and

SYNC1 to support one or two links. Alternatively, GPO0 and GPO1 can be used to output SYNC as a single-

ended CMOS level. Each of the differential or CMOS outputs is enabled by a 2-bit register (fields GPO0_SEL,

GPO1_SEL, SYNC0B_SEL, SYNC1B_SEL in register IO_CONFIG 8.5.2), with bit 0 enabling multi-DUC1 SYNC

and bit 1 enabling multi-DUC2 SYNC. If both are enabled, the SYNC\ signals are OR’ed.

The SYNC signal can be asserted low by the receiver either to make a synchronization request to

initialize/reinitialize the link or to report an error to the transmitter. Synchronization requests must have a

minimum duration of five frames plus nine octets rounded up to the nearest whole number of frames. To report

an error, the SYNC signal is asserted for exactly two frames. The transmitter interprets any negative edge of its

SYNC input as an error and any SYNC assertion lasting four frames or longer as a synchronization request. See

the following sections in the standard for more details.

•

7.6.3 Errors requiring re-initialization

7.6.4 Error reporting via SYNC interface

8.4 SYNC signal decoding

8.3.8 Single or Dual Link Configuration

The DAC38RF82 (or DAC38RF89) JESD204B interface can be configures with one or two links. The advantage

of using two links, one for each DAC, is that one link can be re-established without affecting the other link and

DAC.

The configuration for each mode of operation are:

1. Dual DAC, dual link

a. Program fields OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers

JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data off

of the appropriate SerDes lane.

b. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for

each multi-DUC enable the lanes used.

c. Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) should be ‘0’ (default).

2. Dual DAC, single link

a. Program OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers JESD_CROSSBAR1

(8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data off the appropriate

SerDes lane.

b. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for

each multi-DUC enable the lanes used.

c. Set field ONE_LINK_ONLY to ‘1’ to configure TXENABLE output.

3. Single DAC, single link

a. Set Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) to ‘1’ to gate clocks to unused multi-

DUC2 for power savings.

b. ONE_LINK_ONLY bit does not matter in this case.

8.3.9 Multi-Device Synchronization

In many applications, such as multi antenna systems where the various transmit channels information is

correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely

synchronized such that their outputs are phase aligned. The DAC38RF82 (or DAC38RF89) achieves the

deterministic latency using SYSREF (JESD204B Subclass 1).

SYSREF is generated from the same clock domain as DACCLK. After having resynchronized its local multiframe

clock (LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the

signal on the SYSREF input can be enabled and disabled via the SPI interface.

The SYSREF capture circuit and the timing requirements relative to device clock are described in SYSREF

Capture Circuit.

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8.3.10 SYSREF Capture Circuit

The JESD204B standard for Device Subclass 1 introduces a SYSREF signal that can be used as a global timing

reference to align the phase of the internal local multiframe clock (LMFC) and frame clock across multiple

devices. This allows the system to achieve deterministic latency and align data samples across several data

converters. The SYSREF signal accomplishes this goal by identifying a device clock edge for each chip that can

be used as an alignment reference. In particular, the LMFC and frame clock align to the device clock edge upon

which the SYSREF transition from “0” to “1” is sampled. SYSREF may be periodic, one-shot, or “gapped”

periodic and its period must be a multiple of the LMFC period.

Figure 30. SYSREF Signal Timing

With high-speed device clocks, the phase of the SYSREF signals relative to the device clock must meet the

setup/hold time requirements of each individual device clock. Historically, this has been done by controlling the

board-level routing delay and/or employing commercial clock distribution capable of generating device clocks and

SYSREF signals with programmable delays and with the option of splitting SYSREF into multiple SYSREFS,

each with its own fine-tuned delay. Since the DAC38RF82 (or DAC38RF89) supports device clock frequencies

up to 9 GHz, a SYSREF capture circuit is includes in the DAC38RF82 (or DAC38RF89) that allows a relaxation

in meeting the device clock setup and hold.

The SYSREF capture circuit provides:

•

tolerance to manufacturing and environmental variations in SYSREF phase

immunity to sampling errors due to setup/hold/meta-stability

information about phase of SYSREF relative to DAC clock inside the data converter

software compensation for phase misalignment due to PCB design errors

The concepts behind the SYSREF capture scheme are illustrated in Figure 31.

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Figure 31. SYSREF Capture Strategy and Phase Tolerance Windows

To understand Figure 31, to begin with we’ll ignore the SYSREF phase tolerance windows in the lower portion of

the figure and focus on the blue clock waveform at the top of the figure. This waveform represents the device

clock input to a particular DAC chip. The green arrows, labeled “R” and “F”, correspond to the rising and falling

edges of this clock (ignoring for the moment the additional arrows labeled “ER” and "EF”). While previous

devices with lower device clocks captured SYSREF only on the rising edge of the device clock, the new scheme

samples SYSREF on the falling edge as well, which provides more flexibility when optimizing the setup and hold

time of the SYSREF capture path. Moreover, each time a rising SYSREF edge is captured, the chip remembers

the clock phase during which the event occurred, and the system designer can later read back the phase

information to observe the SYSREF timing relative to the device clock at the internal capture point. If SYSREF

transitions close to the rising or falling clock edge sampling points the capture flop setup and hold time may not

be met and the observed phase may be unreliable and subject to meta-stability phenomenon.

To reduce the sensitivity to setup/hold/meta-stability concerns an “early” version of the device clock is generated

within the DAC and additional SYSREF samples are taken at the “early falling” and “early rising” edges of the

clock (labeled “EF” and “ER”, respectively, in Figure 31). The resulting set of four samples is used to narrow

down the timing of the rising SYSREF edge to one of four possible clock phases. If the rising SYSREF transition

takes place between the “EF” and “F” samples, then SYSREF is said to occur in phase θ1. Similarly, if it takes

place between the “F” and “ER” samples, then it is said to occur in phase θ2. If SYSREF transitions between the

“ER” and “R” samples, then it is said to occur in phase θ3. And, finally, if the SYSREF rising edge event happens

between the “R” and “EF” samples, then it is said to occur in phase θ4. As mentioned before, the chip

remembers all observed SYSREF phases and the user can later read them back. Since the delay between

“early” and “on time” versions of the clock is intentionally chosen to be larger than the setup/hold/meta-stability

window, at most one of the four samples can be affected even when the SYSREF transitions right at one of the

four sampling points. Thus, the uncertainty in the observed SYSREF timing is limited to adjacent phases, and

with twice as many sampling phases the resolution of the timing information is improved by a factor of two.

Referring to the lower portion of Figure 31, the user can now see how this information regarding the observed

SYSREF phases is used to devise a reliable SYSREF capture methodology with a high degree of tolerance to

manufacturing and environmental variations in SYSREF phase. Based on the SYSREF phases observed for a

particular DAC chip during system characterization, the system designer can select one of four so-called “phase

tolerance window” options (denoted “’00”, “01”, “10”, and “11”) to maximize immunity to manufacturing and

environmental variations. For example, consider the default phase tolerance window labeled “window=00” in the

figure. If, during characterization, the system designer observes (by reading back the recorded phase

observations) that the rising SYSREF edge nominally occurs in either θ1 or θ2 or both (i.e. θ12) then he would

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program that particular DAC chip to use phase tolerance window “00”. This mapping is indicated in the figure

with the label “θ1|θ12|θ2: window=00”. Having programmed the device to use window “00”, all future SYSREF

events that occur in θ1 or θ2 would trigger the LMFC and frame clock to be aligned using the following rising

clock edge as the alignment reference (as indicated by the red arrow pointing to rising clock edge “R” and

labeled “Window=00/01 alignment edge”).

The full extent of each phase tolerance window is indicated in the figure using “box and whisker” plots. For the

“window=00” example, the “box” portion of the plot indicates that the phase tolerance window is centered on θ12

(to be precise on the boundary between θ1 and θ2) and the “whisker” portion indicates that even if the rising

edge of SYSREF occurs as early as the preceding θ4 or as late as the following θ3 it still results in LMFC and

frame clock alignment to the same rising clock edge indicated by the red arrow labeled “Window=00/01

alignment edge”. When programmed for phase tolerance window “00”, the DAC chip is tolerant to variations in

the SYSREF timing ranging from a rising SYSREF edge that occurs just after one rising edge of clock to just

before the next rising edge of the clock. The qualifying phrases “just after” and “just before” are used here to

indicate that the SYSREF transition must occur far enough away from the rising edges of the clock to avoid

setup/hold violations and prevent the device from concluding that the SYSREF transition has crossed out off the

phase tolerance window when in fact it has not. The tolerance range for window “00” is from rising clock edge to

rising clock edge and is indicated in the figure by the green text labeled “tolerance = R↔R”.

Following the above example, if characterization reveals SYSREF timing centered on θ23 then phase tolerance

window “01” (with tolerance for SYSREF rising edge events from EF to EF) should be chosen. Notice that this

option is tolerant even to rising SYSREF edges that occur after the rising device clock edge (i.e. in θ4) and will

treat them just as if they had occurred in one of the earlier three phases, aligning to the same rising device clock

edge indicated by the red arrow labeled “Window=00/01 Alignment Edge”. This allows the system designer to

tolerate PCB design errors and/or environmental and manufacturing variations – achieving his intended

alignment without having to make physical changes to the board to adjust the SYSREF timing.

Similarly, if characterization indicates that SYSREF timing is centered on θ34 or θ41 then phase tolerance

window “10” or “11” can be selected, resulting in tolerance for “F↔F” or “ER↔ER” SYSREF timing, respectively.

Note, however, that in these two cases the alignment reference edge is by default taken to be the subsequent

rising edge of the device clock. Since this may not be the desired behavior, the DAC38RF82 (or DAC38RF89)

allows the user to program in an optional alignment offset of θ1 if the default offset of 0 does not achieve the

desired alignment. This feature is illustrated in Figure 32 where the user can see that by setting the alignment

offset to -1, phase tolerance windows “10” and “11” can be made to trigger alignment to the earlier rising device

clock edge used by windows “00” and “01”. Alternatively, the window “00” and “01” alignment edge can be

pushed one cycle later by setting their alignment offset to +1.

Figure 32. Optional SYSREF Alignment Offset

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Several important controls related to SYSREF alignment and capture timing are contained in register

SYSR_CAPTURE (8.5.78). For example, as mentioned before, the device is capable of monitoring the observed

phases of the rising SYSREF edge events; however, in order to avoid unwanted noise coupling from the

SYSREF circuits into the DAC output, the SYSREF monitoring circuits are disabled by default. Field

SYSR_STATUS_ENA enables SYSREF status monitoring. Field SYSR_PHASE_WDW contains the the phase

tolerance window selected for normal operation, which is optimized during characterization. Field

SYSR_ALIGN_DLY contains the control that allows the system designer to optionally offset the SYSREF

alignment event by ±1 device clock cycles. Field SYSR_STATUS_ENA enables the SYSREF capture alignment

accumulation and will generate alarms when enabled. Writing a “1” to field SYSR_ALIGN_SYNC clears the

accumulated SYSREF alignment statistics. The SYSREF alignment block can be bypassed completely by field

SYSREF_BYPASS_ALIGN, in which case SYSREF is latched by the rising edge of DACCLK.

When field SYSR_STATUS_ENA is high the device records the phase associated with each SYSREF event for

use in characterizing the SYSREF capture timing and selecting an appropriate phase tolerance window. The

phase data is available in two forms. First, each of the four phases has a corresponding “sticky” alarm flag

indicating which phases have been observed since the last time the register was cleared. In addition, the device

also accumulates statistics on the relative number of occurrences of each phase spanning multiple SYSREF

events using saturating 8-bit counters. These accumulated real-time SYSREF statistics allow us to account for

time-varying effects during characterization such as potential timing differences between the 1st and Nth edges

in a “gapped” SYSREF pulse train. The counters are fields PHASE1_CNT and PHASE2_CNT in register

SYSREF12_CNT (8.5.10), PHASE3_CNT and PHASE4_CNT in register SYSREF34_CNT (8.5.11), and

ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT in register SYSREF_ALIGN_R (8.5.9).

The accumulated SYSREF statistics can be cleared by writing ‘1’ to SYSR_ALIGN_SYNC. This sync signal

affects only the SYSREF statistics monitors and does not cause a sync of any other portions of the design.

Before collecting phase statistics, the user must first enable the SYSREF status monitoring logic by setting the

SYSR_STATUS_ENA bit. The user must then generate

a repeating SYSREF input before using

SYSR_ALIGN_SYNC to clear the statistic counters. This is necessary to flush invalid data out of the status

pipeline.

The “sticky” alarm flags indicating which of the four phases have been observed since the last

SYSR_ALIGN_SYNC write of ‘1’ are fields ALM_SYSRPHASE1 to ALM_SYSRPHASE4 and are contained in the

ALM_SYSREF_DET register (8.5.6).

8.3.11 JESD204B Subclass 0 Support

Some functionality has been implemented to support Subclass 0 operation. Note that programming the

SUBCLASSV configuration parameter has no functional impact on the logic. The value programmed for

SUBCLASSV is only used in the initial lane alignment (ILA) sequence. The following configuration parameters

are used to support Subclass 0 operation:

•

Field SYSREF_MODE in register JESD_SYSR_MODE (8.5.56) = 0

Field DISABLE_ERR_RPT in register JESD_ERR_OUT (8.5.53) = 1

Field MIN_LATENCY_ENA in register JESD_MATCH (8.5.50) = 1

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8.3.12 SerDes Test Modes through Serial Programming

The DAC38RF82 (or DAC38RF89) supports a number of basic pattern generation and verification of SerDes via

the serial interface. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating

0/1 pattern and a 20-bit user-defined sequence. The 2⁷- 1, 2³¹- 1 or 2²³– 1 sequences implemented can often

be found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation

and verification selection is via field TESTPATT in register SRDS_CFG1 (8.5.86), as shown in Table 28.

Table 28. SerDes Test Pattern Selection

TESTPATT

000

EFFECT

Test mode disabled.

001

Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2 UI.

010

Verify 2⁷- 1 PRBS. Uses a 7-bit LFSR with feedback polynomial x⁷+ x⁶+ 1.

011

Verify 2²³- 1 PRBS. Uses an ITU O.150 conformant 23-bit LFSR with feedback polynomial x²³+ x¹⁸+ 1.

Verify 2³¹- 1 PRBS. Uses an ITU O.150 conformant 31-bit LFSR with feedback polynomial x³¹+ x²⁸+ 1.

100

User-defined 20-bit pattern. Uses the USR PATT IEEE1500 Tuning instruction field to specify the pattern. The default

value is 0x66666.

101

11x

Reserved.

Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there

is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM terminal by

setting field DTEST in register DTEST (8.5.76) to “0011”.

8.3.13 SerDes Test Modes through IEEE 1500 Programming

DAC38RF82 (or DAC38RF89) also provide a number of advanced diagnostic capabilities controlled by the IEEE

1500 interface. These are:

•

Accumulation of pattern verification errors;

The ability to map out the width and height of the receive eye, known as Eye Scan;

Rreal-time monitoring of internal voltages and currents;

The SerDes blocks support the following IEEE1500 instructions:

Table 29. IEEE1500 Instruction for SerDes Receivers

INSTRUCTION

OPCODE

DESCRIPTION

Bypass. Selects a 1-bit bypass data register. Use when accessing other macros on the same

IEEE1500 scan chain.

ws_bypass

0x00

ws_cfg

ws_core

0x35

0x30

0x31

0x32

0x34

0x33

Configuration. Write protection options for other instructions.

Core. Fields also accessible via dedicated core-side ports.

Tuning. Fields for fine tuning macro performance.

ws_tuning

ws_debug

ws_unshadowed

ws_char

Debug. Fields for advanced control, manufacturing test, silicon characterization and debug.

Unshadowed. Fields for silicon characterization.

Char. Fields used for eye scan.

The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver

or transmitter) and tail. DAC38RF82 (or DAC38RF89) uses two SerDes receiver blocks R0 and R1, each of

which contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head,

receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for

each instruction is given as follows:

NOTE

All multi-bit signals in each chain are packed with bits reversed e.g. mpy[7:0] in ws_core

head subchain is packed as {retime, enpll, mpy[0:7], vrange, lb[0:1]}. All DATA REGISTER

READS from SerDes Block R0 should read 1 bit more than the desired number of bits and

discard the first bit received on TDO e.g., to read 40-bit data from R0 block, 41 bits should

be read off from TDO and the first bit received should be discarded. Similarly, any data

written to SerDes Block R0 Data Registers should be prefixed with an extra 0.

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Table 30. ws_cfg Chain

FIELD

DESCRIPTION

HEAD (STARTING FROM THE MSB OF CHAIN)

RETIME

No function.

CORE_WE

Core chain write enable.

RECEIVER (FOR EACH LANE 0, 1, 2, 3)

CORE_WE

TUNING_WE

Core chain write enable.

Tuning chain write enable.

Reserved.

DEBUG_WE

CHAR_WE

Char chain write enable.

Reserved.

UNSHADOWED_WE

TAIL (ENDING WITH THE LSB OF CHAIN)

CORE_WE

TUNING_WE

DEBUG_WE

RETIME

Core chain write enable.

Tuning chain write enable.

Reserved.

No function.

CHAIN LENGTH = 26 BITS

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Table 31. ws_core Chain

FIELD

DESCRIPTION

HEAD (STARTING FROM THE MSB OF CHAIN)

RETIME

No function.

PLL enable.

ENPLL

MPY[7:0]

VRANGE

ENDIVCLK

LB[1:0]

PLL multiply.

VCO range.

Enable DIVCLK output

Loop bandwidth

RECEIVER (FOR EACH LANE 0,1,2,3)

ENRX

SLEEPRX

BUSWIDTH[2:0]

RATE[1:0]

INVPAIR

Receiver enable.

Receiver sleep mode.

Bus width.

Operating rate.

Invert polarity.

TERM[2:0]

ALIGN[1:0]

LOS[2:0]

Termination.

Symbol alignment.

Loss of signal enable.

Clock/data recovery.

Equalizer.

CDR[2:0]

EQ[2:0]

EQHLD

Equalizer hold.

ENOC

Offset compensation.

Loopback.

LOOPBACK[1:0]

BSINRXP

BSINRXN

RESERVED

Testpatt[2:0]

TESTFAIL

LOSTDTCT

BSRXP

Boundary scan initialization.

Reserved.

Test pattern selection.

Test failure (real time).

Loss of signal detected (real time).

Boundary scan data.

Offset compensation in progress.

Receiver signal over equalized.

Receiver signal under equalized.

Loss of signal detected (sticky).

BSRXN

OCIP

EQOVER

EQUNDER

LOSTDTCT

Re-alignment done, or aligned comma output

(sticky).

SYNC

RETIME

No function.

TAIL (ENDING WITH THE LSB CHAIN)

CLKBYP[1:0]

SLEEPPLL

RESERVED

LOCK

Clock bypass.

PLL sleep mode.

Reserved.

PLL lock (real time).

Boundary scan initialization clock.

Enable TX boundary scan.

Enable RX boundary scan.

RX pulse boundary scan.

Reserved.

BSINITCLK

ENBSTX

ENBSRX

ENBSPT

RESERVED

NEARLOCK

UNLOCK

PLL near to lock.

PLL lock (sticky).

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Table 31. ws_core Chain (continued)

FIELD

CFG OVR

RETIME

DESCRIPTION

Configuration over-ride.

No function.

CHAIN LENGTH = 196 BITS

Table 32. ws_tuning Chain

FIELD

DESCRIPTION

HEAD (STARTING FROM THE MSB OF CHAIN)

RETIME No function.

RECEIVER (FOR EACH LANE 0,1,2,3)

PATTERRTHR[2:0]

Resync error threshold.

PRBS timer.

PATT TIMER

RXDSEL[3:0]

ENCOR

Status select.

Enable clear-on-read for error counter.

EQZ OVRi Equalizer zero.

Equalizer zero over-ride.

EQ OVRi Equalizer gain observe or set.

Equalizer over-ride.

EQZERO[4:0]

EQZ OVR

EQLEVEL[15:0]

EQ OVR

EQBOOST[1:0]

RXASEL[2:0]

Equalizer gain boost.

Selects amux output.

TAIL (ENDING WITH THE LSB CHAIN)

ASEL[3:0]

USR PATT[19:0]

RETIME

Selects amux output.

User-defined test pattern.

No function.

CHAIN LENGTH = 174 BITS

Table 33. ws_char Chain

FIELD

DESCRIPTION

HEAD (STARTING FROM THE MSB OF CHAIN)

RETIME No function.

RECEIVER (FOR EACH LANE 0,1,2,3)

Test failure (sticky).

TESTFAIL

ECOUNT[11:0]

ESWORD[7:0]

ES[3:0]

Error counter.

Eye scan word masking.

Eye scan.

ESPO[6:0]

Eye scan phase offset.

Eye scan compare bit select.

Eye scan voltage offset.

Eye scan voltage offset override.

Eye scan run length.

Eye scan run.

ES BIT SELECT[4:0]

ESVO[5:0]

ESVO OVR

ESLEN[1:0]

ESRUN

ESDONE

Eye scan done.

TAIL (ENDING WITH THE LSB CHAIN)

RETIME

No function.

CHAIN LENGTH = 194 BITS

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8.3.14 Error Counter

All receive channels include a 12-bit counter for accumulating pattern verification errors. This counter is

accessible via the ECOUNT IEEE1500 Char field. It is an essential part of the eye scan capability (see the Eye

Scan section).

The counter increments once for every cycle that the TESTFAIL bit is detected. The counter does not increment

when at its maximum value (i.e., all 1s). When an IEEE1500 capture is performed, the count value is loaded into

the ECOUNT scan elements (so that it can be scanned out), and the counter is then reset, provided NCOR is set

high.

ECOUNT can be used to get a measure of the bit error rate. However, as the error rate increases, it becomes

less accurate due to limitations of the pattern verification capabilities. Specifically, the pattern verifier checks

multiple bits in parallel (as determined by the Rx bus width), and it is not possible to distinguish between 1 or

more errors.

8.3.15 Eye Scan

All receive channels provide features which facilitate mapping the received data eye or extracting a symbol

response. A number of fields accessible via the IEEE1500 Char scan chain allow the required low level data to

be gathered. The process of transforming this data into a map of the eye or a symbol response must then be

performed externally, typically in software.

The basic principle used is as follows:

•

Enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the

normal data sample;

•

Apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity;

Apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken;

Reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset

adjustments;

•

Run in this state for a period of time, periodically checking to see if any errors have occurred;

Change voltage and/or phase offset, and repeat.

Alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a

specified time interval.

Eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. The

IEEE1500 Char fields used to directly control eye scan and symbol response extraction are ES, ESWORD, ES

BIT SELECT, ESLEN, ESPO, ESVO, ESVO OVR, ESRUN and ESDONE. Eye scan errors are accumulated in

ECOUNT.

The required eyescan mode is selected via the ES field, as shown in Table 34. When enabled, only data from

the bit position within the 20-bit word specified via ES BIT SELECT is analyzed. In other words, only eye scan

errors associated with data output at this bit position will accumulate in ECOUNT. The maximum legal ES BIT

SELECT is 10011.

Table 34. Eye Scan Mode Selection

ES[3:0]

EFFECT

0000

Disabled. Eye scan is disabled.

Compare. Counts mismatches between the normal sample and the eye scan sample if ES[2] = 0, and matches

otherwise.

0x01

0x10

0x11

0100

Compare zeros. As ES = 0x01, but only analyses zeros, and ignores ones.

Compare ones. As ES = 0x01, but only analyses ones, and ignores zeroes.

Count ones. Increments ECOUNT when the eye scan sample is a 1.

Average. Adjusts ESVO to the average eye opening over the time interval specified by ESLEN. Analyses zeroes when

ES[2] = 0, and ones when ES[2]= 1.

1x00

1001

1110

Outer. Adjusts ESVO to the outer eye opening (i.e. lowest voltage zero, highest voltage 1) over the time interval

specified by ESLEN. 1001 analyses zeroes, 1110 analyses ones.

1010

1101

Inner. Adjusts ESVO to the inner eye opening (i.e. highest voltage zero, lowest voltage 1) over the time interval

specified by ESLEN. 1010 analyses zeroes, 1101 analyses ones.

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Table 34. Eye Scan Mode Selection (continued)

ES[3:0]

EFFECT

Timed Compare. As ES = 001x, but analyses over the time interval specified by ESLEN. Analyses zeroes when ES[2] =

0, and ones when ES[2] = 1.

1x11

When ES[3] = 0, the selected analysis runs continuously. However, when ES[3] = 1, only the number of qualified

samples specified by ESLed, as shown in Table 35. In this case, analysis is started by writing a 1 to ESRUN (it is

not necessary to set it back to 0). When analysis completes, ESDONE is set to 1.

Table 35. Eye Scan Run Length

ESLen

00

NUMBER OF SAMPLES ANALYZED

127

1023

8095

65535

01

10

11

When ESVO OVR = 1, the ESVO field determines the amount of offset voltage that is applied to the eye scan

data samplers associated with rxpi and rxni. The amount of offset is variable between 0 and 300 mV in

increments of ~10 mV, as shown Table 36. When ES[3] = 1, ESVO OVR must be 0 to allow the optimized

voltage offset to be read back via ESVO.

Table 36. Eye Scan Voltage Offset

ESVO

100000

…

OFFSET (mV)

-310

…

111110

111111

000000

000001

000010

…

-20

-10

0

10

20

…

011111

300

The phase position of the samplers associated with rxpi and rxni, is controlled to a precision of 1/32UI. When ES

is not 00, the phase position can be adjusted forwards or backwards by more than one UI using the ESPO field,

as shown in Table 37. In normal use, the range should be limited to ±0.5 UI (+15 to –16 phase steps).

Table 37. Eye Scan Phase Offset

ESPO

011111

…

OFFSET (1/32 UI)

+63

…

000001

000000

111111

…

+1

0

-1

…

100000

-64

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8.3.16 JESD204B Pattern Test

The DAC38RF82 (or DAC38RF89) supports the following test patterns for JESD204B:

•

Link layer test pattern by setting field JESD_TEST_SEQ in register JESD_LN_EN (8.5.45) and monitoring the

lane alarms (1 = fail, 0 = pass)

–

Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)

Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)

Verify repeating initial lane alignment (ILA) sequence

•

RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an

amount of time to get an estimate of BER.

Transport layer test pattern: implements a short transport layer pattern check based on F = 1, 2, 4 or 8. The

short test pattern has a duration of one frame period and is repeated continuously for the duration of the test.

Each sample has a unique value that can be identified with the position of the sample in the user data format.

The sample values are such that correct sample values will never be decoded at the receiver if there is a

mismatch between the mapping formats being used at the transmitter and receiver devices. This can

generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples

being transmitted. Refer to the JESD204B standard section 5.1.6 for more details.

The DAC38RF82 (or DAC38RF89) expects the test samples, in a frame, transmitted by an logic device as per

Table 38:

Table 38. Short Test Patterns

JESD Mode

82121

i0

7CB8, F431

7CB8

q0

6DA9, E520

F431

i1

n/a

q1

n/a

42111

n/a

22210

7CB8

F431

n/a

12410

7CB8

F431

n/a

44210

7CB8

F431

6DA9

n/a

E520

n/a

24410

7CB8

F431

41121

7CB8, F431

n/a

7C00, B800, F400, 3100, 6D00,

A900, E500, 2000

81180

24310

41380

n/a

F430

n/a

6DA0

n/a

E520

n/a

7CB0

7CB0, F430, 6DA0, E520, F870,

E960, DA50, CB40

The short test pattern has duration of one frame period and is repeated continuously for the duration of the test.

Each sample has a unique value that can be identified with the position of the sample in the user data format.

The sample values are such that correct sample values will never be decoded at the receiver if there is a

mismatch between the mapping formats being used at the transmitter and receiver devices. This can generally

be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted.

Following are the steps required to execute the short test functionality in DAC38RF82 (or DAC38RF89).

1. Configure other registers, make sure clocks are up and running.

2. Start driving short test patterns

3. Clear short test alarm by writing ‘0’ to field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP

(8.5.67). This is a paged register, one for each Multi-DUC.

4. Enable short test by writing a ‘1’ to field SHORTTEST_ENA in register MULTIDUC_CFG2 (8.5.14).

5. Read the short test alarm from field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67).

This is a paged register, one for each Multi-DUC

If the alarm read from the register is high, the short test has detected an error.

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8.3.17 Wideband DUC (wide-DUC)

Each DAC output in the DAC38RF82 ((or DAC38RF89)) can be supported by a wide band digital up-converter

(DUC), which is called a wide-DUC. Figure 33 shows the implementation and signal processing features of the

wide-DUC which is only available in the 2-TX modes (Table 9). For complex inputs, the in-phase (or I-channel) is

path AB of DAC A and the phase of the NCO in this path (7.5.19) must be set to 0 degrees. Similarly, the

quadrature phase (or Q-channel) is path AB of DAC B and the phase of the NCO in this path (7.5.19) must be

set to 90 degrees. The NCO frequency in both I and Q paths (7.5.20) must be set to the same value. The SPI

interface registers for the wide-DUC are addressed through paging, with page 1 supporting the I-channel and

page 2 supporting Q-channel configuration of the wide-DUC. Register PAGE_SET (8.5.8) is used to set the

pages. Both pages can be selected at the same time to program both channels of wide-DUC simultaneously.

The output of I and Q channels are added together using the output summation block (Figure 33). Bit 0 and Bit 2

of the register field OUTSUM_SEL must be set to for this to be accomplished.

48-bit

NCO1

cos

Input

Mux

Multiband

summation

I

Path AB

(DAC A)

x

sin(x)

PAP

Gain

xN

12/16

CMIX control

( n x Fs/4)

Delay

CMIX control

( n x Fs/4)

Q

x

sin(x)

PAP

Gain

Path AB

(DAC B)

xN

12/16

sin

48-bit

NCO2

Figure 33. DAC38RF82 Wide-DUC Signal Processing Block Diagram

8.3.18 Interpolation Block

The DAC38RF82 (or DAC38RF89) provides the optional interpolation of 2x in 12-bit input mode and 2x or 4x in

16-bit input mode. In addition, 1x interpolation can be used in 8, 12 or 16-bit input modes to pass the data

directly to the DAC output. The SPI interface registers for the multi-DUCs are addressed through paging, with

page 0 supporting the I channel and page 1 supporting the Q channel. Register PAGE_SET (8.4.8) is used to set

the pages. Both pages can be selected at the same time to program both multi-DUCs simultaneously with the

same settings.

8.3.18.1 Multi-DUC input

Each interpolation block accepts data from up to 8 SerDes lanes. A crossbar switch allows any SerDes lane to

be mapped to any other SerDes lane. The crossbar switch is controlled by fields OCTETPATHx_SEL (x = [0..7])

in Registers JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58).

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8.3.18.2 Interpolation Filters

The digital upconverter first increases the sample rate of the IQ signal from the input sample rate to the final

DAC sample rate through a series of interpolation filters. Different sets of filters are used to achieve different

rates, as shown in Table 39. The interpolation rate is selected by field INTERP in register MULTIDUC_CFG1

(8.5.13).

Table 39. FIR filters Used for Different Interpolation Rates

FILTERS USED

Interpolation Rate

FIR0 (2x)

FIR1 (2x)

2

4

x

The FIR filter coefficients are shown in Table 40 The FIR filters are design with a passband BW of 0.4 x f_INPUT, a

stopband attenuation of 90 dBc and ripple of < 0.001 dB. The composite frequency response for each

interpolation factor are shown in Figure 34to Figure 41.

20

0

20

0

-20

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

D001

D002_8x

Figure 34. Composite Magnitude Response for 6x

Interpolation

Figure 35. Composite Magnitude Response for 8x

Interpolation

20

0

20

0

-20

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

D003

D004

Figure 36. Composite Magnitude Response for 10x

Interpolation

Figure 37. Composite Magnitude Response for 12x

Interpolation

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20

0

20

0

-20

-40

-60

-80

-100

-120

-140

-100

-120

-140

-160

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

D005

D006

Figure 38. Composite Magnitude Response for 16x

Interpolation

Figure 39. Composite Magnitude Response for 18x

Interpolation

20

0

20

0

-20

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

0

0.075

0.15

0.225

f/Fdac

0.3

0.375

0.45

D007

D001

Figure 40. Composite Magnitude Response for 20x

Interpolation

Figure 41. Composite Magnitude Response for 24x

Interpolation

Table 40. FIR Filter Coefficients

tap

1

FIR0

6

FIR1

-12

0

LPFIR0_5X

-6

FIR2

29

LPFIR0_3X

-14

FIR3

3

LPFIR1_3X INVSINC

25

1

-4

2

0

-22

0

-61

0

88

3

-19

0

84

-51

-214

0

-125

-25

0

22

13

-50

592

-50

13

-4

4

0

-89

-95

-576

5

47

0

-336

0

-117

-106

-18

1209

2048

1209

0

181

150

256

150

0

-1764

-2263

491

6

681

7

-100

0

1006

0

972

8

171

347

8139

18625

26365

18625

8139

491

9

192

0

-2691

0

449

-214

0

-1475

-3519

-3528

707

-25

0

1

10

11

12

13

14

15

16

745

-342

0

10141

16384

10141

0

930

29

3

841

572

0

338

9337

19445

26299

-618

-1892

-3147

-914

0

-2691

0

-2263

-1764

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Table 40. FIR Filter Coefficients (continued)

tap

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

FIR0

1409

0

FIR1

1006

0

LPFIR0_5X

-3872

-3500

-1564

2121

7336

13430

19426

24231

26904

24231

19426

13430

7336

2121

-1564

-3500

-3872

-3147

-1892

-618

FIR2

LPFIR0_3X

19445

9337

707

FIR3

LPFIR1_3X INVSINC

-576

22

-2119

0

-336

0

88

-3528

-3519

-1475

347

25

3152

0

84

0

-4729

0

-12

972

7420

0

681

181

-13334

0

-95

-125

-61

41527

65536

41527

0

-14

-13334

0

7420

0

-4729

0

338

3152

0

841

930

-2119

0

745

449

1409

0

171

-18

-914

0

-106

-117

572

0

-89

-51

-342

0

-22

-6

192

0

-100

0

47

0

-19

0

6

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8.3.18.3 JESD204B Modes, Interpolation and Clock phase Programming

Table 41 lists the register field values required for each JESD204B mode interpolation mode and clock phase.

The register field addresses are listed in Table 42.

Table 41. Register Programming for JESD and Interpolation Mode

Mode

L-M-F-S-Hd

Register Field Programming

CLKJESD

_OUT_DI

V

CLOCK

PHASES

(1-0)

CLKJESD

_DIV

(3-0)

N_M1/N’_

M1

(4-0)

INTERP

(4-0)

L_M1

(4-0)

F_M1

(7-0)

M_M1

(7-0)

S_M1

(4-0)

Interp

HD

1 TX/2TX

(3-0)

6

8

11

10

11

01

10

11

01

10

01

10

11

01

10

11

00

01

11

00011

00100

00110

01000

00011

00100

00101

00110

01000

01001

01100

00100

00110

01000

01001

01010

01100

01000

01100

00100

00110

01000

01100

01000

01100

00000

00001

00000

000001

00010

01100

0110

0111

1010

1011

0010

0011

0101

0110

0111

1001

1010

0001

0010

0011

0100

0101

0110

0001

0010

0001

0010

0011

0110

0001

0010

0011

1100

1101

0000

0001

0011

0100

0110

0111

0011

0100

0101

0110

0111

1000

1010

0100

0110

0111

1000

1001

1010

0111

1010

0100

0110

0111

1010

0111

1010

0001

0000

0001

0000

0001

0010

1010

82121/NA

00111

00011

0x00

0x01

00001

00000

1

01111

12

16

6

8

10

12

16

18

24

8

42111/84111

1

12

16

18

20

24

16

24

8

22210/44210

00001

0x01

00000

0

01111

12410/24410

44210/88210

00000

00011

0x03

0x01

0x03

00000

0

01111

12

16

24

16

24

1

24410/48410

81180/NA

00001

00111

00011

0x03

0x00

0x02

0x03

0x00

00000

00111

0

01111

00111

01011

1

41380/82380

2

1

41121/ 82121

24310/48310

2

00011

00001

0x00

0x02

0x00

0x03

00001

00000

1

0

01111

01011

4

24

Table 42. Register Field Addresses for JESD204B Mode, Interpolation and Clock Phase Programming

Register Field Name

INTERP

Register

Register Address

Bit(s)

12-8

15-12

11-8

4-0

Hyperlink

MULTIDUC_CFG1

0x0A

8.5.13

CLKJESD_DIV

CLKJESD_OUT_DIV

L_M1

SerDes_CLK

0x25

8.5.28

JESD_K_L

0x4C

0x4B

8.5.47

8.5.46

F_M1

JESD_RBD_F

7-0

M_M1

15-8

4-0

JESD_M_S

0x4D

8.5.48

S_M1

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Table 42. Register Field Addresses for JESD204B Mode, Interpolation and Clock Phase

Programming (continued)

Register Field Name

HD

Register

Register Address

Bit(s)

6

Hyperlink

N_M1

JESD_N_HD_SCR

JESD_LN_EN

0x4E

0x4A

4-0

8.5.49

N_M1’ (NPRIME_M1)

JESD_PHASE_MODE

12-8

1-0

8.5.45

All registers are paged!

8.3.18.4 Digital Quadrature Modulator

Each DUC in the DAC38RF8x has digital quadrature modulator (DQM) blocks with independent Numerically

Controlled Oscillators (NCO) that converts the complex input signal to a real signal with flexible frequency

placement between 0 and f_DAC/2. The NCOs are enabled by fields NCOAB_ENA and NCOCD_ENA in register

MULTIDUC_CFG2 (8.5.14). The NCOs have 48-bit frequency registers (FREQ_NCOAB (8.5.25) and

FREQ_NCOCD (8.5.26)) and 16-bit phase registers (PHASE_NCOAB (8.5.23) and PHASE_NCOCD (8.5.24))

that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 42.

48

16

sin

Accumulator

CLK RESET

48

16

Look Up

Table

Frequency

Register

16

cos

16

F_DAC

NCO SYNC

via

syncsel_NCO(3:0)

Phase

Register

Figure 42. NCO Block Diagram

Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is

selected by fields SYNCSEL_NCOAB and SYNCSEL_NCOCD in register SYNCSEL1 (8.5.29). The frequency

word in the FREQ_NCOAB and FREQ_NCOCD registers are added to the accumulators every clock cycle, f_DAC

.

The frequency and phase offset of the NCOs are:

FREQ _NCOAB or CD ì f

(

)

DAC

f

=

NCOAB or CD

(

)

48

2

(1)

(2)

PHASE _NCOAB or CD

(

)

/

= 2Œ ì

AB or CD

(

)

16

2

Treating the complex channels as complex vectors of the form I + j Q, the output of the DQM is:

MIXERAB _GAIN-1

(

ì 2

AB

)

Output

= I

ìcos 2Œf

t + /

-Q

ìsin 2Œf

t + /

(

)

(

)

}

{

AB

INPUTAB

NCOAB

AB

INPUTAB

-Q ìsin 2Œf

INPUTCD

NCOAB

(3)

(4)

MIXERCD_GAIN-1

(

t + / ì2

NCOCD CD

)

Output

= I

ìcos 2Œf

t + /

CD

(

)

(

)

}

{

CD

INPUTCD

NCOCD

Where t is the time since the last resetting of the NCO accumulator and the fields MIXERAB_GAIN and

MIXERCD_GAIN in register MULTIDUC_CFG2 (8.5.13) are either 0 or 1.

The maximum output amplitude of the DQM occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and

the sine and cosine arguments are equal to an integer multiple of π/4.

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With MIXERAB_GAIN or MIXERCD_GAIN = 0, the gain through the DQM is sqrt(2)/2 or -3 dB. This loss in signal

power is in most cases undesirable, and it is recommended that the gain function be used to increase the signal

by 3 dB to compensate. With MIXERAB_GAIN or MIXERCD_GAIN = 1, the gain through the DQM is sqrt(2) or

+3 dB, which can cause clipping of the signal if I_IN(t) and Q_IN(t) are simultaneously near full scale amplitude and

should therefore be used with caution.

8.3.18.5 Low Power Coarse Resolution Mixing Modes

In addition to the NCO the DAC38RFxx also has a coarse mixer block capable of shifting the input signal

spectrum by the fixed mixing frequencies ±N x f_DAC/8. Using the coarse mixer instead of the full mixers will result

in lower power consumption.

Treating the two complex channels as complex vectors of the form I(t) + j Q(t), the outputs of the coarse mixer is

equivalent to:

Output

= I

ìcos 2Œf

t -Q

ì sin 2Œf

t

(

)

(

)

AB

INPUTAB

CMIX _ AB

INPUTAB

CMIX _ AB

(5)

(6)

Output = I

CD INPUTCD

ìcos 2Œf

t -Q

ì sin 2Œf

t

(

)

(

)

CMIX _CD

INPUTCD

CMIX _CD

Where f_{CMIX_AB}and f_{CMIX_CD}and the fixed mixing frequency selected by fields CMIX_AB or CMIX_CD in register

CMIX (8.5.21). The coarse mixer blocks are disabled by setting CMIX_AB and CMIX_CD to 0x0.

The NCO and coarse mixers can be enabled simultaneously, although this is not useful in most cases as the full

frequency range can be covered by the NCO.

8.3.18.6 Inverse Sinc Filter

The DAC38RF82 (or DAC38RF89) has a 9-tap inverse Sinc filter (INVSINC) that runs at the DAC update rate

(f_DAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-

hold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting

in the well known sin(x)/x or Sinc(x) frequency response (Figure 43, red line). The inverse sinc filter response

(Figure 43, blue line) has the opposite frequency response from 0 to 0.4 x f_DAC, resulting in the combined

response (Figure 43, green line). Between 0 to 0.4 x f_DAC, the inverse sinc filter compensates the sample-and-

hold roll-off with less than 0.03 dB error.

The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to INVSINC must be reduced

from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal

frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is

less than 1 (0 dB). For example, if the signal input to INVSINC is at 0.25 x f_DAC, the response of INVSINC is 0.9

dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The advantage of INVSINC

having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based

on its frequency.

The inverse sinc filters are enabled by field ISFIR_ENA in register MULTIDUC_CFG1 (8.5.13).

4

3

FIR4

2

1

0

Corrected

–1

–2

–3

–4

sin(x)/x

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

f/f_DAC

G056

Figure 43. Composite Magnitude Spectrum for INVSINC

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8.3.19 PA Protection Block

The DAC38RFxx incorporates an optional power amplifier protection (PAP) block to monitor when the input

signal is two large, for example when an interface error occurs, and reduces the output signal power of the DAC.

The PAP block achieves the functionality of reducing the input signal that crosses the threshold through three

main sub-blocks. These are PAP trigger generation block, PAP gain state machine and GAIN block.

The PAP block keeps track of the input signal power by maintaining a sliding window accumulation of last N

samples. N is selectable to be 32, 64 or 128 based on the setting (Table 43) of fields PAPAB_SEL_DLY in

register PAP_CFG_AB (8.5.35) and PAPCD_SEL_DLY in register PAP_CFG_CD (8.5.36). The average

amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line

(N). The result is then compared against the threshold in fields PAPAB_THRESH in register PAP_CFG_AB

(8.5.35) and PAPCD_THRESH in register PAP_CFG_CD (8.5.36). If the threshold is violated, gain state machine

is triggered which generated gain value to ramp down the DAC output signal amplitude. After the input signal

returns to normal value, the state machine ramps up the DAC output signal amplitude.

Table 43. PAP Delay Line Selection

pap_sel_dly[1:0]

# of samples averaged

00

01

10

11

32

64

128

Reserved

The generation of the PAP trigger as explained as follows:

•

The I and Q samples are treated separately – either can trigger attenuation

In dual DUC modes, each IQ pair is treated separately and has a separate gain block

8 samples at the input are put through an absolute value circuit (all 2’s complement)

Next these values are vector summed to get a 12 bit result

Then 12 bit result is placed into the delay line and summed into the accumulator

The accumulator is also subtracting out the delayed 12 bit word corresponding to N = 32, N = 64 or N = 128

Finally the accumulator output is divided down by N and rounded to 13 bits. These 13 bits are compared to

the threshold in the SPI registers. A pap_trig occurs if the threshold is exceeded.

The PAP gain state machine generates the pap gain value to be applied on the output stream to reduce the

output signal amplitude. The state machine below is used to control the attenuation of the DAC output and the

gaining up of the signal again once the trigger is released.

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pap_trig=0

pap_gain=1

Normal

pap_trig=1

Attenuate

Gain

wait_cnt_load_r=0

pap_trig=0

wait_cnt_load_r=1

Wait

pap_trig=1

Figure 44. PAP Gain State Machine

The normal operating condition for the PAP block is the NORMAL state in Figure 44. However, when the PAP

block detects an error condition it sets the pap_trig signal to ‘1’ causing a state transition from NORMAL

operation to the ATTENUATE state.

In the ATTENUTATE state the data path gain is scaled from 1.0 down to 0.0 by a programmable step amount set

by fields PAPAB_GAIN_STEP in register PAP_GAIN_AB (8.5.31) and PAPCD_GAIN_STEP in register

PAP_GAIN_CD (8.5.33). This value is always positive with the decimal place located between the MSB and

MSB-1. Unity is equal to “1000000000”. Each clock cycle (16 samples) the PAP_GAIN is stepped down by

PAPAB_GAIN_STEP and PAPCD_GAIN_STEP until the gain is 0.

After PAP_GAIN is 0, the state machine moves on to the WAIT state. Here a programmable counter counts clock

cycles to allow the condition for the pap_trig to be fixed. Fields PAPAB_WAIT in register PAP_WAIT_AB (8.5.32)

and PAPCD_WAIT in register PAP_WAIT_CD (8.5.34) are used to select the number of clock cycles (samples =

16 x PAPAB_WAIT or 16 x PAPCD_WAIT) to wait before moving to the next state. Once the WAIT counter

equals zero and pap_trig=’0’, the state machine moves on to the GAIN state. If the WAIT equals 0 but pap_trig

still equals ‘1’ then the state machine stays in the WAIT state until pap_trig =’0’.

8.3.20 Gain Block

The GAIN block also has additional output gain control through fields GAINAB in register GAINAB (8.5.39) and

GAINCD in register GAINCD (8.5.40). Similar to PAP_GAIN value, the output gain is always positive with unity

when GAINAB or GAINCD = ”010000000000”.

To reduce the power, the gain block clock has been gated whenever the pap is disabled and GAINAB or

GAINCD is set to unity.

8.3.21 Output Summation

The OUTSUM block allows addition of samples from each DUC in the multi-DUC. It is also possible to add the

output samples from the adjacent multi-DUC. Field OUTSUM_SEL in register OUTSUM (8.5.22) controls the

summation for each multi-DUC. The functionality of the block can be represented by the following equation:

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OUTSUM

output

= SAME

+ SAME

CD

+ ADJ

AB CD

AB

(7)

In order to avoid overflow, rounding operation is performed after the addition to reduce the word size back to 16-

bits. Exact number of bits rounded depends on the number of channels added. Table 44 shows the description of

round after the summation.

Table 44. OUTSUM Scaling and Rounding

# OF CHANNELS ADDED

# OF BITS ROUNDED

0

1

2

3

4

0, Use bits[15:0] from the result

Use bits[16:1] from the result and bit[0] used for rounding

Use bits[17:2] from the result and bits[1:0] used for rounding

Use bits[18:3] from the result and bit[2:0 used for rounding

Use bits[19:4] from the result and bit[3:0] used for rounding

8.3.22 Output Delay

The signal following output summation can be programmably delayed by 0-15 DACCLK cycles through field

OUTPUT_DELAY in register OUTSUM (8.5.20). The block takes 16 sample words (vec16) from both the A and B

paths and shifts the them to 32 sample long delay line.

8.3.23 Polarity Inversion

The signal following the output delay can be inverted by a 2’s complement conversion allowing the + and - DAC

outputs to be swapped by asserting field DAC_COMPLEMENT in register MULTIDUC_CFG1 (8.5.13).

8.3.24 Temperature Sensor

The DAC38RF82 (or DAC38RF89) incorporates a temperature sensor block which monitors the die temperature

by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a

successive approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted

as a twos complement value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDEN and SCLK. If the temperature sensor is enabled

by writing a 0 to field TSENSE_SLEEP in register SLEEP_CONFIG (8.5.70), a conversion takes place each time

the serial port is written or read. The data is only read and sent out by the digital block when the temperature

sensor is read in field TEMPDATA in register TEMP_PLLVOLT (8.5.7). The conversion uses the first eight clocks

of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is

then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for

the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in

sleep mode.

In order for the process described above to operate properly, the serial port read from register TEMP_PLLVOLT

must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is

greatly reduced.

8.3.25 Alarm Monitoring

The DAC38RF82 (or DAC38RF89) includes a flexible set of alarm monitoring that can be used to alert of a

possible malfunction scenario. All the alarm events can be accessed either through the SIP registers and/or

through the ALARM output. Once an alarm is set, the corresponding alarm bit must be reset through the serial

interface to allow further testing. The set of alarms includes the following conditions:

•

JESD alarms

Fields ALM_LANEx_ERR in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):

–

multiframe alignment_error. Occurs when multiframe alignment fails

frame alignment error. Occurs when multiframe alignment fails

link configuration error. Occurs when there is wrong link configuration

elastic buffer overflow. Occurs when bad RBD value is used

elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed data

code synchronization error

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–

8b/10b not-in-table decode error

8b/10b disparity error

–

Field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67): Occurs when the short pattern

test fails.

•

SerDes alarms

–

Field ALM_SD_LOTDET in register ALM_SD_DET 8.5.5): Occurs when there are loss of signal detect

from SerDes lanes.

–

Fields ALM_FIFOx_FLAGS in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):

–

FIFO write error. Occurs if write request and FIFO is full.

FIFO write full: Occurs if FIFO is full.

FIFO read error. Occurs if read request and FIFO is empty.

FIFO read empty: Occurs if FIFO is empty.

–

Field ALM_SD0_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 0

goes out of lock.

Field ALM_SD1_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 1

goes out of lock.

•

SYSREF alarm

–

Field ALM_SYSREF_ERR in register ALM_SYSREF_PAP (8.5.67): Occurs when the SYSREF is received

at an unexpected time. If too many of these occur it will cause the JESD to go into synchronization mode

again.

DAC PLL alarm

–

Field PLL_LOCK in register ALM_SYSREF_DET (8.5.6). This register field is asserted when the PLL is

unlocked. When used as an alarm output, a high signal indicates that the PLL is unlocked if the

ALM_OUT_POL bit in register RESET_CONFIG is set to 1.

PAP alarm

Field ALM_PAP in register ALM_SYSREF_PAP (8.5.67): Occurs when the average power is above the

threshold. While any alarm_pap is asserted the attenuation for the appropriate data path is applied.

–

8.3.26 Differential Clock Inputs

Figure 45 shows the preferred configuration for driving the DACCLK+/- and SYSREF+/- with a differential

ECL/PECL source.

LVPCL Driver

0.01 mF

C

100 W

AC

0.01 mF

240 W

Figure 45. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source

8.3.27 CMOS Digital Inputs

Figure 46 shows a schematic of the equivalent CMOS digital inputs of the DAC38RF82 (or DAC38RF89). SDIO,

SCLK, TCLK, SLEEP, TESTMODE and TXENABLE have internal pull-down resistors while SDEN, RESET,

TMS, TDI and TRST have internal pull-up resistors. See the Specifications table for logic thresholds. The pull-up

and pull-down circuitry is approximately equivalent to 10 kΩ.

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VDDIO18

10 kꢀ

SDIO

SCLK

TCLK

SLEEP

SDENB

RESETB

TMS

400 ꢀ

internal

digital in

internal

digital in

TDI

TXENABLE

TESTMODE

TRSTB

10 kꢀ

GND

Figure 46. CMOS Digital Equivalent Input

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8.3.28 DAC Fullscale Output Current

The DAC38RF82 (or DAC38RF89) uses a bandgap reference and control amplifier for biasing the full-scale

output current. The DAC full scale output current is set by a combination of the fixed current through the external

resistor RBIAS (connected to pin BIASJ) and current from course trim current sources:

IOUT

= I + I

RBIAS coarsetrim

FS

(8)

The bias current IBIAS through resistor R_BIASis defined by the on-chip bandgap reference voltage V_BG(nominally

0.9 V) and control amplifier. For normal operation, it is recommended that R_BIASis set to 3.6 kΩ for a fixed

current through R_BIASof 250 µA. This current is scaled 128x internally, giving:

V

0.9V

BG

I

= 128ì

= 32 mA

RBIAS

R

3.6 kꢀ

BIAS

(9)

The course trim current sources are configured through SPI register field DACFS in register DACFS (8.5.72), as

follows:

I

= 2mA × DACFS -11

(

)

coarsetrim

(10)

From the discussion above, the DAC full scale output current can be configured from 40 mA (DACFS[3:0] =

1111) down to 10 mA (DACFS[3:0] = 0000). In addition to the full scale signal current set by SPI register DACFS

(8.5.72), an extra DC bias current is required to set the operating point of the output current sources(Table 45).

Table 45. DAC output current

DACFS ( 8.5.72)

Signal current (mA)

Total bias current (mA)⁽¹⁾

0

1

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

1

2

3

4

5

6

7

8

9

2

3

4

5

6

7

8

9

10

11

12

13

14

15

(1) The bias current per each complementary output is half the total bias current

An external decoupling capacitor C_EXTof 0.1 μF should be connected externally to terminal EXTIO for

compensation. The full-scale output current can be adjusted from 40 mA down to 10 mA by varying resistor R_BIAS

From 3.6 kΩ to 14.4 kΩ.

8.3.29 Current Steering DAC Architecture

The DACs in the DAC38RF82 (or DAC38RF89) consist of a segmented array of NMOS current sources, capable

of sinking a full-scale output current up to 40 mA (see Figure 47). Differential current switches direct the current

to either one of the complimentary output nodes VOUT1/2+ or VOUT1/2-. Complimentary output currents enable

differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB

noise), dc offsets, even order distortion components, and increasing signal output power by a factor of four.

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VDDOUT18

Zext+

Zext-

VOUT1/2+

VOUT1/2-

100 W

IOUT-

IOUT+

VDEE18N

(-1.8V)

Figure 47. Current Steering DAC Architecture for DAC38RF82 (or DAC38RF89)

Referring to Figure 47, the total output current I_OUTFSis fixed, and is switched to either the + or – output by

switches S(N):

IOUT = IOUT + + IOUT-

FS

(11)

Since the output stage is a current sinking architecture, it will denote current into the DAC as + current, and the

current flows IOUT+ and IOUT- into terminals VOUT1/2+ and VOUT1/2- respectively. IOUT+ and IOUT- can be

expressed as:

IOUT ìCODE

FS

16384

IOUT+ =

(12)

IOUT ì 16383 -CODE

(

16384

)

FS

IOUT- =

(13)

where CODE is the decimal representation of the 14-bit DAC core data input word. Note the signal path up to the

DAC is 16-bits and the 2 LSBs are truncated for the DAC core data input word.

8.3.30 DAC Transfer Function

The DAC38RF82 (or DAC38RF89) has a differential output and is terminated internally with a differential 100-Ω

load. The DAC38RF82 (or DAC38RF89) output compliance range is 1.3 to 2.3 V. Note that care should be taken

not to exceed the compliance voltages at node VOUT1/2+ and VOUT1/2-, which would lead to increased signal

distortion.

Referring again to Figure 47, denote the external impedance as seen by VOUT1/2+ as Zext+ and by VOUT1/2-

as Zext-. Note that Zext+ and Zext- should terminate to VDDOUT18 to supply the output current for the DAC.

Also, Zext+ and Zext- are ideally identical to maintain the differential balance of the output. The voltage at nodes

VOUT1/2+ and VOUT1/2- generated by the current flow through the impedance is

IOUT +ì 100ꢀ + Zext +

(

)

IOUT - ìZext -

100ꢀ + Zext + +Zext -

VOUT1/ 2+ =

ì Zext + +

ì Zext +

100ꢀ + Zext + +Zext -

(

)

(

)

(14)

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IOUT - ì 100ꢀ + Zext -

(

)

ì Zext + +

IOUT +ìZext +

100ꢀ + Zext + +Zext -

VOUT1/ 2- =

ì Zext -

100ꢀ + Zext + +Zext -

(

)

(

)

(15)

The DAC38RF82 (or DAC38RF89) can be easily configured to drive a doubly terminated 50-Ω cable using a

properly selected 2:1 RF transformer (Figure 48). Note that the center tap of the primary input of the transformer

has to be connected to the VDDOUT18 supply (nominally 1.8 V) to enable a DC current flow into the DAC. The

AC load impedance as seen through 2:1 transformer is 100 Ω, which is split equally into Zext+ = Zext- = 50 Ω.

The DC impedance for the transformer is a short to the center tap of the transformer, which drives the common

mode of VOUT1/2+ and VOUT1/2- to 1.8V. To calculate the peak to peak output swing VOUT1/2PP at each

node, the equations above simplify to:

VOUT1/ 2

=VOUT1/ 2 +

-VOUT1/ 2 +

PP

IOUT+=IOUT IOUT -=0

IOUT-=IOUT ,IOUT+=0

FS

(

)

(

)

FS,

(16)

(17)

IOUT ì 50ꢀì150ꢀ IOUT ì 50ꢀì 50ꢀ

FS FS

VOUT1/ 2

=

-

= IOUT ì 25ꢀ

FS

PP

200ꢀ

With IOUT_OUTFS= 40 mA, the swing becomes 1 V_PPat each node. With the common mode at 1.8 V due to the

center tap, the voltage at VOUT1/2+ and VOUT1/2- varies between 1.3 and 2.3 V, which is the compliance range

of the DAC.

The differential output swing is 2x VOUT1/2_PP, or 2 V_PPDIFF. On the load side of the transformer, this reduces to

1.414 V_PP, for a transferred load power of 7 dBm (assuming no loss).

2 : 1

VOUT1/2+

R_LOAD

100 W

50 W

VOUT1/2-

VDDADAC18

(1.8V)

Figure 48. Driving a 50-Ω Load Using a 2:1 Impedance Ratio Transformer (DAC38RF82 (or DAC38RF89))

The DAC38RF82 (or DAC38RF89) can also be DC coupled. In this case, the termination voltage can be raised

above 1.8 V (for example 2.3 V) so that the common mode for the output pin is nominally 1.8 V.

8.4 Device Functional Modes

8.4.1 Clocking Modes

The DAC38RF82 (or DAC38RF89) has both a single ended clock input DACCLKSE and a differential clock input

DACCLK+/- to clock the device. The clock input is selected by field SEL_EXTCLK_DIFFSE in register

CLK_PLL_CFG (8.5.79). The DAC38RF82 (or DAC38RF89) can be clock directly with a high frequency input

clock at the DAC sample rate (PLL Bypass Mode), or an optional on-chip low-jitter phase-locked loop (PLL) can

be used to generate the high frequency DAC sample clock internally from a lower frequency reference clock

input (PLL Mode).

8.4.2 PLL Bypass Mode Programming

In PLL bypass mode a high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock

the DAC38RF82 (or DAC38RF89) DAC cores. This mode gives the device best performance and is

recommended for extremely demanding applications.

The bypass mode is selected by setting the following:

1. Set field PLL_ENA in register CLK_PLL_CFG (8.5.79) to “0” to bypass the PLL circuitry.

2. Set field PLL_SLEEP in register SLEEP_CONFIG (8.5.70) to “1” to put the PLL and VCO into sleep mode.

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Device Functional Modes (continued)

8.4.3 Internal PLL/VCO

The DAC38RF82 (or DAC38RF89) has an internal clock generation circuit consisting of a PLL and two selectable

VCOs, as shown in Figure 49.

High VCO

PFD

and

charge pump

Output

buffer

DAC

CLK

ó N

PLL_N(4-0)

Feedback

Low VCO

ó M

ó 4

PLL_M(7-0)

Figure 49. Internal PLL/VCO Block Diagram

DAC38RF82 (or DAC38RF89) each have a low VCO (VCO0) and high VCO (VCO1), but they are tuned to

different center frequencies in each device. The VCO frequency ranges for each device are summarized in

Electrical Characteristics - Digital Specifications. The VCO is selected through field PLL_VCOSEL in register

PLL_CONFIG2 (8.5.81), with ‘0’ selecting the low VCO and a ‘1’ the high VCO. The 7 bit VCO tuning code in

field PLL_VCO in register PLL_CONFIG2 (8.5.81) is used to tune the VCO frequency from the lowest frequency

in the range to the highest frequency for the particular VCO used. For the low VCO the center VCO frequency is

achieved with PLL_VCO = 63_decimaland for the high VCO the center frequency is achieved with PLL_VCO =

63_decimal

.

The supply current, and therefore; the analog signal amplitude in the VCO is controlled using the field

PLL_VCO_RDAC in register PLL_CONFIG1 (8.5.80). This control signal should be set 15_decimalinitially for 18 mA

supply current in the VCO and ~1.4 V_PPsingle ended oscillation amplitude.

The PLL has no prescaler, so the DAC sample rate is the VCO frequency. In the PLL feedback path a fixed ÷ 4

frequency divider block receives the VCO output clock and divides its frequency by 4. The maximum operating

frequency of the phase-frequency detector (PFD) and charge pump (CP) requires this. The M (feedback) clock

divider takes the output clock signal from the fixed ÷4 block and divides it by a programmable ratio set by the 8-

bit field in field PLL_M_M1 in register PLL_CONFIG1 (8.5.80). The programmable division ratio range is ÷1 to

÷256, and is the value of the 8 bit unsigned binary code + 1. Although it is possible to program the M divider to

÷1, ÷2 and ÷3, these values should not be used. As stated previously the PFD and CP have a finite maximum

operating frequency, which is the VCO frequency divided by the fixed divider ratio multiplied by the minimum

allowable M divider ratio.

PFD_CP

Fmax

= Fvco / Fixed _div x Mdiv

(

)

min

(18)

The N (reference) divider determines the ratio between the input reference clock frequency and the PFD

operating frequency, and is set by the 5-bit field PLL_N_M1 in register CLK_PLL_CFG (8.5.79). The division ratio

range is ÷1 to ÷32, and is the value of the 5-bit unsigned binary code + 1.

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Device Functional Modes (continued)

The charge pump output current amplitude is set using the 4-bit field PLL_CP_ADJ in in register PLL_CONFIG2

(8.5.81). The current amplitude is simply the digital code multiplied by the unit current amplitude of 100 µA. In a

nominal condition, with the DAC38RF82 VCO0 running at 5.898 GHz, and with the M divider set to ÷4, the PFD

will run at 368.625 MHz, and the change pump current should set to 6_decimal, which gives 600 µA charge pump

output current for a good phase margin of 69 degrees. If a higher M ratio (for lower PFD frequencies) are

required the charge pump output current must be increased to maintain good loop stability and prevent excessive

peaking in the phase noise response. The charge pump output current setting PLL_CP_ADJ should be adjusted

in relation to the feedback (M) divider ratio PLL_M_M1 according to the following table to maintain a constant

phase margin of 69 degrees.

Table 46. M vs Kp for Maintaining Good Stability

M

4

CP_ADJ

6

9

6

8

12

15

10

Similarly for the DAC38RF82 VCO2 running at 8.847 GHz, and with the M divider set to ÷4, the PFD will run at

552.9375 MHz as shown above. Here the change pump current should set to 6_decimal, which gives 600 µA charge

pump output current for a good phase margin of 69 degrees.

8.4.4 CLKOUT

The DAC38RF82 (or DAC38RF89) has a programmable output clock on CLKTX+/- balls that is a divided version

of the internal DAC sample clock, either with or without PLL. Two frequency dividers, either DACCLK/3 or

DACCLK/4, are available by programming field CLK_TX_DIV4 in register CLK_OUT (8.5.71). The output swing

voltage is programmable from approximately 125 to 1460 mV_PP-DIFFthrough field CLK_TX_SWING in register

CLK_OUT (8.5.71).

Field CLK_TX_IDLE in register CLK_OUT (8.5.71) enables an idle state, in which the pins are driven to the

proper common-mode levels in order to charge the external AC coupling caps but the clock output is disabled.

The output clock circuit can be put to sleep by field CLK_TX_SLEEP in register SLEEP_CONFIG (8.5.70).

8.4.5 Serial Peripheral Interface (SPI)

The serial port of the DAC38RF82 (or DAC38RF89) is a flexible serial interface which communicates with

industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers

used to define the operating modes of DAC38RF82 (or DAC38RF89). It is compatible with most synchronous

transfer formats and can be configured as a 3 or 4 terminal interface by SIF4_ENA in register IO_CONFIG

(8.5.2). In both configurations, SCLK is the serial interface input clock and SDEN is serial interface enable. For 3

terminal configuration, SDIO is a bidirectional terminal for both data in and data out. For 4 terminal configuration,

SDIO is bidirectional and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is

output from the device on the falling edge of SCLK.

The SPI registers are reset by writing a 1 to SPI_RESET in register RESET_CONFIG (8.5.1).

Each read/write operation is framed by signal SDEN (Serial Data Enable Bar) asserted low. The first frame byte

is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit

address to be accessed. Figure 50 indicates the function of each bit in the instruction cycle and is followed by a

detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 50. Instruction Byte of the Serial Interface

Bit

7 (MSB)

R/W

6

5

4

3

2

1

0

Description

A6

A5

A4

A3

A2

A1

A0

R/W - Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC38RF82 (or

DAC38RF89) and a low indicates a write operation to DAC38RF82 (or DAC38RF89)

A6:A0 - Identifies the address of the register to be accessed during the read or write operation.

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Figure 51 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) write operation. SCLK is

the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input

to DAC38RF82 (or DAC38RF89). SDIO is serial data input. Input data to DAC38RF82 (or DAC38RF89) is

clocked on the rising edges of SCLK.

Instruction Cycle

Data Transfer Cycle

SDEN\

SCLK

SDIO

rwb

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

t_S(SDEN\)

t_SCLK

SDEN\

SCLK

SDIO

t_S(SDIO) t_H(SDIO)

Figure 51. Serial Interface Write Timing Diagram

Figure 52 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) read operation. SCLK is

the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input

to DAC38RF82 (or DAC38RF89). SDIO is serial data input during the instruction cycle. In 3 pin configuration,

SDIO is data out from the DAC38RF82 (or DAC38RF89) during the data transfer cycle, while SDO is in a high-

impedance state. In 4 pin configuration, both SDIO and SDO are data out from the DAC38RF82 (or

DAC38RF89) during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the

final falling edge of SCLK until the rising edge of SDEN when they will 3-state.

Instruction Cycle

Data Transfer Cycle

SDEN\

SCLK

SDIO

SDO

rwb

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDEN\

SCLK

SDIO

SDO

Data n

Data n-1

t_d(Data)

Figure 52. Serial Interface Read Timing Diagram

n the SIF interface there are four types of registers:

8.4.5.1 NORMAL (RW)

The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the

same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect

to internal clocks. There are three subtypes of NORMAL:

1. AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are

used when it is desirable to synchronize the block after writing the register or if a single field that spans

across multiple registers. For instance, the NCO requires three 16-bit register writes to set the frequency.

Upon writing the last of these registers an autosync is generated to deliver the entire field to the NCO block

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at once, rather than in pieces after each individual register write. For a field that spans multiple registers, all

non-AUTOSYNC registers for the field must be written first before the actual AUTOSYNC register.

2. No RESET Value: These are NORMAL registers, but the reset value cannot be specified. This could be

because the register has some read only bits or some internal logic partially controls the bit values.

3. READ_ONLY (R): Registers that can only be read.

8.4.5.2 WRITE_TO_CLEAR (W0C)

These registers are just like NORMAL registers with one exception. They can be written and read, however,

when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is

written to ‘0’. This way interrupts will be captured and stay constant until cleared by the user.

8.5 Register Maps

Table 47. Register Summary

Address

Reset

Acronym

Register Name

Section

General Configuration Registers (PAGE_SET[2:0] = 000)

0x00

0x01

0x5803

0x1800

0xFFFF

0x0000

variable

0x0000

0x0008

RESET_CONFIG

IO_CONFIG

Chip Reset and Configuration

8.5.1

8.5.2

8.5.3

8.5.4

8.5.5

8.5.6

8.5.7

IO Configuration

Lane Signal Detect Alarm Mask

Clock Alarms Mask

0x02

ALM_SD_MASK

ALM_CLK_MASK

ALM_SD_DET

ALM_SYSREF_DET

TEMP_PLLVOLT

Reserved

0x03

0x04

SERDES Loss of Signal Detection Alarms

SYSREF Alignment Circuit Alarms

Temperature Sensor and PLL Loop Voltage

Reserved

0x05

0x06

0x07-0x08

0x09

PAGE_SET

Page Set

8.5.8

0x0A-0x77

0x78

Reserved

SYSREF_ALIGN_R

SYSREF12_CNT

SYSREF34_CNT

Reserved

SYSERF Align to r1 and r3 Count

SYSREF Phase Count 1 and 2

SYSREF Phase Count 3 and 4

Reserved

8.5.9

8.5.10

8.5.11

0x79

0x7A

0x7B-0x7E

0x7F

VENDOR_VER

Vendor ID and Chip Version

8.5.12

8.5.13

Multi-DUC Configuration Registers (PAGE_SET[0] = 1 for multi-DUC1, PAGE_SET[1] = 1 for multi-DUC2)

0x0A

0x0B

0x02B0

0x0000

0x2402

0x8300

0x00FF

0x1F83

0xFFFF

0x0000

0x0010

0x7700

0x0000

MULTIDUC_CFG1

Reserved

Multi-DUC Configuration (PAP, Interpolation)

Reserved

0x0C

MULTIDUC_CFG2

JESD_FIFO

Multi-DUC Configuration (Mixers)

JESD FIFO Control

Alarm Mask 1

8.5.14

8.5.15

8.5.16

8.5.17

8.5.18

8.5.19

8.5.20

0x0D

0x0E

ALM_MASK1

ALM_MASK2

ALM_MASK3

ALM_MASK4

JESD_LN_SKEW

Reserved

0x0F

Alarm Mask 2

0x10

Alarm Mask 3

0x11

Alarm Mask 4

0x12

JESD Lane Skew

0x13-0x16

0x17

Reserved

CMIX

CMIX Configuration

Reserved

8.5.21

8.5.22

0x18

Reserved

0x19

OUTSUM

Output Summation and Delay

Reserved

0x1A-0x1B

0x1C

Reserved

PHASE_NCOAB

PHASE_NCOCD

FREQ_NCOAB

FREQ_NCOCD

SYSREF_CLKDIV

SERDES_CLK

Reserved

Phase offset for AB path NCO

Phase offset for CD path NCO

Frequency for AB path NCO

Frequency for CD path NCO

SYSREF Use for Clock Divider

Serdes Clock Control

Reserved

8.5.23

8.5.24

8.5.25

8.5.26

8.5.27

8.5.28

0x1D

0x1E-0x20

0x21-0x23

0x24

0x25

0x26

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Register Maps (continued)

Table 47. Register Summary (continued)

Address

0x27

Reset

0x1144

0x0000

0x1FFF

0x0000

0x0800

0x0000

0x0044

0x190A

0x31C3

0x0000

0x0003

0x1300

0x1303

0x0100

0x0F4F

0x1CC1

0x0000

0x00FF

Acronym

SYNCSEL1

Register Name

Sync Source Selection

PAP path AB Gain Attenuation Step

PAP path AB Wait Time at Gain = 0

PAP path CD Gain Attenuation Step

PAP path CD Wait Time at Gain = 0

PAP path AB Configuration

PAP path CD Configuration

Configuration for DAC SPI Constant

DAC SPI Constant

Section

8.5.29

8.5.30

8.5.31

8.5.32

8.5.33

8.5.34

8.5.35

8.5.36

8.5.37

8.5.38

0x28

SYNCSEL2

0x29

PAP_GAIN_AB

PAP_WAIT_AB

PAP_GAIN_CD

PAP_WAIT_CD

PAP_CFG_AB

PAP_CFG_CD

SPIDAC_TEST1

SPIDAC_TEST2

Reserved

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

Reserved

0x32

GAINAB

Gain for path AB

8.5.39

8.5.40

0x33

GAINCD

Gain for path CD

0x34-0x40

0x41

Reserved

JESD_ERR_CNT

Reserved

JESD Error Counter

8.5.41

0x42-0x45

0x46

Reserved

JESD_ID1

JESD ID 1

8.5.42

8.5.43

8.5.44

0x47

JESD_ID2

JESD ID 2

0x48

JESD_ID3

JESD ID 3 and Subclass

Reserved

0x49

Reserved

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

JESD_LN_EN

JESD_RBD_F

JESD_K_L

JESD Lane Enable

8.5.45

8.5.46

8.5.47

8.5.48

8.5.49

8.5.50

8.5.51

8.5.52

8.5.53

JESD RBD Buffer and Frame Octets

JESD K and L Parameters

JESD M and S Parameters

JESD N, HD and SCR Parameters

JESD Character Match and Other

JESD Link Configuration Data

JESD Sync Request

JESD_M_S

JESD_N_HD_SCR

JESD_MATCH

JESD_LINK_CFG

JESD_SYNC_REQ

JESD_ERR_OUT

0x50

0x51

0x52

JESD Error Output

JESD Configuration Value used for ILA

Check

0x53

0x54

0x0100

0x8E60

JESD_ILA_CFG1

JESD_ILA_CFG2

8.5.54

8.5.55

JESD Configuration Value used for ILA

Check

0x55-0x5B

0x5C

0x0000

0x0001

0x0000

0x0123

0x4567

0x0000

Reserved

JESD_SYSR_MODE

Reserved

JESD SYSREF Mode

Reserved

8.5.56

0x5D-0x5E

0x5F

JESD_CROSSBAR1

JESD_CROSSBAR2

Reserved

JESD Crossbar Configuration 1

JESD Crossbar Configuration 2

Reserved

8.5.57

8.5.58

0x60

0x61-0x63

0x64

JESD_ALM_L0

JESD_ ALM_L1

JESD_ ALM_L2

JESD_ALM_L3

JESD_ALM_L4

JESD_ALM_L5

JESD_ALM_L6

JESD_ALM_L7

ALM_SYSREF_PAP

ALM_CLKDIV1

Reserved

JESD Alarms for Lane 0

JESD Alarms for Lane 1

JESD Alarms for Lane 2

JESD Alarms for Lane 3

JESD Alarms for Lane 4

JESD Alarms for Lane 5

JESD Alarms for Lane 6

JESD Alarms for Lane 7

SYSREF and PAP Alarms

Clock Divider Alarms 1

Reserved

8.5.59

8.5.60

8.5.61

8.5.62

8.5.63

8.5.64

8.5.65

8.5.66

8.5.67

8.5.68

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E-0x77

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Register Maps (continued)

Table 47. Register Summary (continued)

Address

Reset

Acronym

Register Name

Section

Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1)

0x0A

0x0B

0xFC03

0x0022

0xA002

0xF000

0x0000

0x03F3

0x1000

0x0000

0x0200

0x0308

0x4018

0x0000

0x0018

0x0000

0x0002

0x8228

0x0088

0x0909

0x0000

CLK_CONFIG

SLEEP_CONFIG

CLK_OUT

Clock Configuration

Sleep Configuration

8.5.69

8.5.70

8.5.71

8.5.72

0x0C

Divided Output Clock Configuration

DAC Fullscale Current

Reserved

0x0D

DACFS

0x0E-0x0F

0x10

Reserved

LCMGEN

Internal sysref generator

Counter for internal sysref generator

SPI SYSREF for internal sysref generator

Reserved

8.5.73

8.5.74

8.5.75

0x11

LCMGEN_DIV

LCMGEN_SPISYSREF

Reserved

0x12

0x13-0x1A

0x1B

DTEST

Digital Test Signals

8.5.76

0x1C-0x22

0x23

Reserved

SLEEP_CNTL

SYSR_CAPTURE

Reserved

Sleep Pin Control

8.5.77

8.5.78

0x24

SYSREF Capture Circuit Control

Reserved

0x25-0x30

0x31

CLK_PLL_CFG

PLL_CONFIG1

PLL_CONFIG2

LVDS_CONFIG

PLL_FDIV

Clock Input and PLL Configuration

PLL Configuration 1

8.5.79

8.5.80

8.5.81

8.5.82

8.5.83

0x32

0x33

PLL Configuration 2

0x34

LVDS Output Configuration

Fuse farm clock divider

Reserved

0x35

0x36-0x3A

0x3B

Reserved

SRDS_CLK_CFG

SRDS_PLL_CFG

SRDS_CFG1

SRDS_CFG2

SRDS_POL

Serdes Clock Configuration

Serdes PLL Configuration

Serdes Configuration 1

Serdes Configuration 2

Serdes Polarity Control

Reserved

8.5.84

8.5.85

8.5.86

8.5.87

8.5.88

0x3C

0x3D

0x3E

0x3F

0x40-0x75

0x76

Reserved

SYNCBOUT

JESD204B SYNCB Output

8.5.89

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8.5.1 Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]

Figure 53. Chip Reset and Configuration Register (RESET_CONFIG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

RW

7

0

6

0

5

0

4

0

3

0

2

0

1

0

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 48. RESET_CONFIG Field Descriptions

Bit

15

14

Field

Type

RW

Reset

Description

SPI_RESET

ALM_OUT_POL

0

1

This will reset all the SPI registers once programmed.

RW

Changes the polarity of the alarm output.

0= active low

1= active high

13

12

11

10:7

6

ALM_OUT_ENA

SYSCLK_ENA

AUTOLOAD_TRIG

Reserved

RW

0

Turn on the alarm pin

1

Turns on the dividers for the SYSCLK to the Fusefarm

Causes a Fuse AUTOLOAD to be executed.

Reserved

1

0000

ONE_DAC_ONLY

ONE_LINK_ONLY

0

When set high only the SLICE0 is available.

5

This needs to be set high when a single link setup is being

programmed to get the correct TXENABLE signal generation

4:2

1

Reserved

RW

000

1

Reserved

INIT_SLICE1

INIT_SLICE0

Puts the multi-DAC2 JESD into initialization state

Puts the multi-DAC1 JESD into initialization state

0

1

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8.5.2 IO Configuration Register (address = 0x01) [reset = 0x1800]

Figure 54. IO Configuration Register (IO_CONFIG)

15

0

14

0

13

0

12

1

11

1

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 49. IO_CONFIG Field Descriptions

Bit

Field

Type

Reset

Description

15:14

GPO0_SEL

RW

00

Selects the JESD SYNC_N signal coming out the GPO0 pin.

Both bits can be asserted which does an oring of the SYNC_N

signals from each multi-DUC.

bit 0 = 1 then multi-DUC1 SYNC_N used

bit 1 = 1 then multi-DUC2 SYNC_N is used

13:12

11:10

9:8

SYNC0B_SEL

SYNC1B_SEL

GPO1_SEL

RW

01

10

00

Selects the JESD SYNC_N signal coming out the SYNC0B pin.

Both bits can be asserted which does an oring of the SYNC_N

signals from each multi-DUC.

bit 0 = 1 then multi-DUC1 SYNC_N used

bit 1 = 1 then multi-DUC2 SYNC_N is used

Selects the JESD SYNC_N signal coming out the SYNC1B pin.

Both bits can be asserted which does an oring of the SYNC_N

signals from each multi-DUC.

bit 0 = 1 then multi-DUC1 SYNC_N used

bit 1 = 1 then multi-DUC2 SYNC_N is used

Selects the JESD SYNC_N signal coming out the GPO1 pin.

Both bits can be asserted which does an oring of the SYNC_N

signals from each multi-DUC.

bit 0 = 1 then multi-DUC1 SYNC_N used

bit 1 = 1 then multi-DUC2 SYNC_N is used

7

6

SPI4_ENA

Reserved

ATEST

RW

0

When set to a '1' the chip is in 4 pin SPI interface mode.

Reserved

0

5:0

000000

Select the analog test points:

000000: ATEST is off (ATEST Must be off during normal

operation)

000001, 010001, 000110: VSSCLK

000010: VDDPLL1

000101: VDDCLK

000111, 001010, 010000: VDDAPLL18

001011: VDDAVCO18

001101: VDDS18

001110: VDDE1

001111, 111010, 111011, 111100: DGND

010011: VDDTX1

101001, 110001: AGND

101111, 111101, 111110, 11111: VDDDIG1

110000: VDDA18

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8.5.3 Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]

Figure 55. Lane Single Detect Alarm Mask Register (ALM_SD_MASK)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 50. ALM_SD_MASK Field Descriptions

Bit

Field

Type

Reset

Description

Used to mask alarms

bit 15 - bit 8 : Reserved

bit7 : lane 7 loss of signal detect

bit6 : lane 6 loss of signal detect

bit5 : lane 5 loss of signal detect

bit4 : lane 4 loss of signal detect

bit3 : lane 3 loss of signal detect

bit2 : lane 2 loss of signal detect

bit1 : lane1 loss of signal detect

bit0 : lane 0 loss of signal detect

15:0

ALM_SD_MASK

R/W

0xFFFF

8.5.4 Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF

Figure 56. Clock Alarms Mask Register (ALM_CLK_MASK)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 51. ALM_CLK_MASK Field Descriptions

Bit

Field

Type

Reset

Description

Used to mask alarms

bit 15 - bit 8 : Reserved

bit 7 : alarm_sysrefphase4

bit 6 : alarm_sysrefphase3

bit 5 : alarm_sysrefphase2

bit 4 : alarm_sysrefphase1

bit 3 : alarm_align_to_r3

bit 2 : alarm_align_to_r1

bit 1 : alarm_sd0_pll

15:0

ALM_CLK_MASK

R/W

0xFFFF

bit 0 : alarm_sd1_pll

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8.5.5 SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]

Figure 57. SERDES Loss of Signal Detection Alarms Register (ALM_SD_DET)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

0

5

0

4

0

3

0

2

1

0

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset

Table 52. ALM_SD_DET Field Descriptions

Bit

Field

Type

Reset

Description

15:8

Reserved

W0C

0x00

Reserved

Loss of signal detect outputs from the SERDES lanes:

bit 7 = lane7 loss of signal

bit 6 = lane6 loss of signal

bit 5 = lane5 loss of signal

7:0

ALM_SD_LOSDET

W0C

0x00

bit 4 = lane4 loss of signal

bit 3 = lane3 loss of signal

bit 2 = lane2 loss of signal

bit 1 = lane1 loss of signal

bit 0 = lane0 loss of signal

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8.5.6 SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]

Figure 58. SYSREF Alignment Circuit Alarms Register (ALM_SYSREF_DET)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

0

5

0

4

0

3

0

2

1

0

1

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset

Table 53. ALM_SYSREF_DET Field Descriptions

Bit

Field

Type

Reset

Description

15:9

Reserved

W0C

0000000

Reserved

If high the sysrefphase4 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

8

7

6

5

ALM_SYSRPHASE4

ALM_SYSRPHASE3

ALM_SYSRPHASE2

ALM_SYSRPHASE1

W0C

0

If high the sysrefphase3 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

If high the sysrefphase2 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

If high the sysrefphase1 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

If high the align_to_r3 state has been observed in the sysrefalign

logic at least once since the last sysrefalign sync. TI Internal use

only.

4

3

2

ALM_ALIGN_TO_R3

ALM_ALIGN_TO_R1

ALM_SD0_PLL

W0C

0

If high the align_to_r1 state has been observed in the sysrefalign

logic at least once since the last sysrefalign sync. TI Internal use

only.

Driven high if the PLL in the Serdes 0 block goes out of lock. A

false alarm is generated at startup when the PLL is locking. User

will have to reset this bit after start to monitor accurately.

Driven high if the PLL in the Serdes 1 block goes out of lock. A

false alarm is generated at startup when the PLL is locking. User

will have to reset this bit after start to monitor accurately.

1

0

ALM_SD1_PLL

PLL_LOCK

W0C

0

Asserted when PLL is unlocked.

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8.5.7 Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]

Figure 59. Temperature Sensor and PLL Loop Voltage Register (TEMP_PLLVOLT)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

0

5

0

4

0

3

0

2

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 54. TEMP_PLLVOLT Field Descriptions

Bit

15:8

7:5

Field

Type

R

Reset

0x00

Description

TEMPDATA

PLL_LFVOLT

Reserved

8 bits of data from the tempurature sensor

PLL Loop filter voltage

R

0b000

4:0

R

Reserved

8.5.8 Page Set Register (address = 0x09) [reset = 0x0000]

Figure 60. Page Set Register (PAGE_SET)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 55. PAGE_SET Field Descriptions

Bit

Field

Type

Reset

Description

Each bit selects a page that is active. Multiple pages can be

selected at the same time. No bits asserted means that

MASTER is the only page selected.

bit 0 = page0 : multi-DUC1

15:0

PAGE_SET

R/W

0x0000

bit 1 = page1 : multi-DUC2

bit 2 = page2 : DIG_MISC

bit 3-15: Reserved

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8.5.9 SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]

Figure 61. SYSREF Align to r1 and r3 Count Register (SYSREF_ALIGN_R)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

1

5

1

4

1

3

1

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 56. SYSREF_ALIGN_R Field Descriptions

Bit

15:8

7:0

Field

Type

R

Reset

0x00

Description

ALIGN_TO_R1_CNT

ALIGN_TO_R3_CNT

Part of the SYSREF Align block

R

8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]

Figure 62. SYSREF Phase Count 1 and 2 Register (SYSREF12_CNT)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

1

5

1

4

1

3

1

2

0

1

0

1

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 57. SYSREF12_CNT Field Descriptions

Bit

15:8

7:0

Field

Type

R

Reset

0x00

Description

PHASE2_CNT

PHASE1_CNT

Part of the SYSREF Align block

R

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8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]

Figure 63. SYSREF Phase Count 3 and 4 Register (SYSREF34_CNT)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

1

5

1

4

1

3

1

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 58. SYSREF34_CNT Field Descriptions

Bit

15:8

7:0

Field

Type

R

Reset

0x00

Description

PHASE4_CNT

PHASE3_CNT

Part of the SYSREF Align block

R

8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0008]]

Figure 64. Vendor ID and Chip Version Register (VENDOR_VER)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

1

5

1

4

1

3

1

2

1

0

1

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 59. VENDOR_VER Field Descriptions

Bit

15

Field

Type

R

Reset

0

Description

AUTOLOAD_DONE

EFC_ERR

Reserved

Asserted when the Fusefarm Autoload sequence is done

The error output from the fuse farm.

Reserved

14:10

9:5

R

00000

01

R

4:3

VENDORID

VERSION

R

TI identification

2:0

R

001

Bits to determine what version of build for the chip.

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8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]

Figure 65. Multi-DUC Configuration (PAP, Interolation) Register (MULTIDUC_CFG1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

1

6

0

5

0

4

0

3

1

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. MULTIDUC_CFG1 Field Descriptions

Bit

15

14

Field

Type

R/W

Reset

Description

When asserted the SLICE uses both IQ paths

DUAL_IQ

ISFIR_ENA

0

Turns on the inverse sync filter for the AB and CD paths when

programmed to 1.

13

Not used

INTERP

R/W

0

Not used

12:8

00010

Determines the interpolation amount.

00000: 1x

00001: 2x

00010: 4x

00011: 6x

00100: 8x

00101: 10x

00110: 12x

01000: 16x

01001: 18x

01010: 20x

01100: 24x

7

6

5

4

ALM_ZEROS_TXEN

DAC_COMPLEMENT

ALM_ZEROS_JESD

ALM_OUT_ENA

R/W

1

0

1

When asserted any alarm that isn’t masked will mid-level the

DAC output by setting the txenable_from_dig to ‘0’

When asserted the DAC output will be 2's complemented. This

helps with hookup at the board level.

When asserted any alarm that isn’t masked will zero the data

coming out of the JESD block.

When asserted the output from the selected SLICE will be

passed on to the MASTER alarm control if it is also turned on

then the alarm will be sent to the pad_alarm pin.

3

2

1

0

PAPA_ENA

PAPB_ENA

PAPC_ENA

PAPD_ENA

R/W

0

Turns on the Power Amp Protection logic for path A.

Turns on the Power Amp Protection logic for path B.

Turns on the Power Amp Protection logic for path C.

Turns on the Power Amp Protection logic for path D.

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8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]

Figure 66. Multi-DUC Configuration (Mixers) Register (MULTIDUC_CFG2)

15

0

14

0

13

0

12

0

11

0

10

1

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. MULTIDUC_CFG2 Field Descriptions

Bit

Field

Type

Reset

Description

15:14

DAC_BITWIDTH

R/W

0b00

Determines the bit width of the data going to the DAC

00: 14 bits

01: 14 bits

10: 12 bits

11: 11 bits

13

ZERO_INVLD_DATA

R/W

1

When asserted; the data from the JESD block is zeroed in the

mapper to prevent goofy output from the DAC. For test purposes

this bit should be desasserted

12

11

10

9

SHORTTEST_ENA

Reserved

R/W

0

1

0

00

1

Turns on the JESD SHORT pattern test (5.1.6.2)

Reserved

MIXERAB_ENA

MIXERCD_ENA

MIXERAB_GAIN

MIXERCD_GAIN

NCOAB_ENA

NCOCD_ENA

Reserved

Turns on the mixer for the A and B streams

Turns on the mixer for the C and D streams

Adds 6dB of gain when asserted

When high the full NCO block is turned on.

Reserved

8

7

6

5

4

3:2

1

TWOS

When asserted the chip is expecting 2's complement data is

arriving through the JESD; otherwise offset binary is expected

0

Reserved

R/W

0

Reserved

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8.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300]

Figure 67. JESD FIFO Control Register (JESD_FIFO)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. JESD_FIFO Field Descriptions

Bit

Field

Type

Reset

Description

15

FIFO_ZEROS_DATA

R/W

1

When asserted FIFO errors zero the data out of the JESD block.

For test purposes this could be turned off to allow test patterns

in the FIFO.

14:13

12

NOT USED

R/W

000

0

Not Used

SRDS_FIFO_ALM_CLR

Set to 1 to clear FIFO errors. Must be set to 0 for proper FIFO

operation

11

Not used

R/W

0

Not used

10:8

FIFO_OFFSET

0000

Used to set the difference between read and write pointers in

the JESD FIFO.

7:1

0

Reserved

R/W

0

Reserved

SPI_TXENABLE

When asserted the internal value of txenable = '1'

8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]

Figure 68. Alarm Mask 1 Register (ALM_MASK1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. ALM_MASK1 Field Descriptions

Bit

Field

Type

Reset

Description

15:0

ALM_MASK1

R/W

0x00FF

Each bit is used to mask an alarm. Assertion masks the alarm:

bit 15 = mask lane7 lane errors

bit 14 = mask lane6 lane errors

bit 13 = mask lane5 lane errors

bit 12 = mask lane4 lane errors

bit 11 = mask lane3 lane errors

bit 10 = mask lane2 lane errors

bit 9 = mask lane1 lane errors

bit 8 = mask lane0 lane errors

bit 7 = mask lane7 FIFO flags

bit 6 = mask lane6 FIFO flags

bit 5 = mask lane5 FIFO flags

bit 4 = mask lane4 FIFO flags

bit 3 = mask lane3 FIFO flags

bit 2 = mask lane2 FIFO flags

bit 1 = mask lane1 FIFO flags

bit 0 = mask lane0 FIFO flags

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8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]

Figure 69. Alarm Mask 2 Register (ALM_MASK2)

15

0

14

0

13

12

11

10

9

0

8

x

0

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. ALM_MASK2 Field Descriptions

Bit

Field

Type

Reset

Description

15:0

ALMS_MASK2

R/W

0xFFFF

Each bit is used to mask an alarm. Assertion masks the alarm:

bit 15 = not used

bit 14 = not used

bit 13 = not used

bit 12 = mask SYSREF errors on link0

bit 11 = mask alarm from JESD shorttest

bit 10 = mask alarm from PAPD

bit 9 = mask alarm from PAPC

bit 8 = mask alarm from PAPB

bit 7 = mask alarm from PAPA

bit 6 = not used

bit 5 = not used

bit 4 = not used

bit 3 = not used

bit 2 = not used

bit 1 = mask alarm_clkdiv192_eq_zero

bit 0 = mask alarm_clkdiv192_eq_mult1

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8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]

Figure 70. Alarm Mask 3 Register (ALM_MASK3)

15

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

1

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 65. ALM_MASK3 Field Descriptions

Bit

Field

Type

Reset

Description

15:0

ALMS_MASK3

R/W

0xFFFF

Each bit is used to mask an alarm. Assertion masks the alarm:

bit 15 = mask alarm_clkdiv8_eq_zero

bit 14 = mask alarm_clkdiv12_eq_zero

bit 13 = mask alarm_clkdiv16_eq_zero

bit 12 = mask alarm_clkdiv18_eq_zero

bit 11 = mask alarm_clkdiv20_eq_zero

bit 10 = mask alarm_clkdiv32_eq_zero

bit 9 = mask alarm_clkdiv36_eq_zero

bit 8 = mask alarm_clkdiv40_eq_zero

bit 7 = mask alarm_clkdiv48_eq_zero

bit 6 = mask alarm_clkdiv64_eq_zero

bit 5 = mask alarm_clkdiv72_eq_zero

bit 4 = mask alarm_clkdiv80_eq_zero

bit 3 = mask alarm_clkdiv96_eq_zero

bit 2 = maskalarm_ clkdiv128_eq_zero

bit 1 = mask alarm_clkdiv144_eq_zero

bit 0 = mask alarm_clkdiv160_eq_zero

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8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]

Figure 71. Alarm Mask 4 Register (ALM_MASK4)

15

0

14

0

13

12

11

10

9

0

8

x

0

R/W

7

0

6

0

5

0

4

1

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 66. ALM_MASK4 Field Descriptions

Bit

Field

Type

Reset

Description

15:0

ALMS_MASK4

R/W

0xFFFF

Each bit is used to mask an alarm. Assertion masks the alarm:

bit 15 = mask alarm_clkdiv8_eq_mult1

bit 14 = mask alarm_clkdiv12_eq_mult1

bit 13 = mask alarm_clkdiv16_eq_mult1

bit 12 = mask alarm_clkdiv18_eq_mult1

bit 11 = mask alarm_clkdiv20_eq_mult1

bit 10 = mask alarm_clkdiv32_eq_mult1

bit 9 = mask alarm_clkdiv36_eq_mult1

bit 8 = mask alarm_clkdiv40_eq_mult1

bit 7 = mask alarm_clkdiv48_eq_mult1

bit 6 = mask alarm_clkdiv64_eq_mult1

bit 5 = mask alarm_clkdiv72_eq_mult1

bit 4 = mask alarm_clkdiv80_eq_mult1

bit 3 = mask alarm_clkdiv96_eq_mult1

bit 2 = maskalarm_ clkdiv128_eq_mult1

bit 1 = mask alarm_clkdiv144_eq_mult1

bit 0 = mask alarm_clkdiv160_eq_mult1

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8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]

Figure 72. JESD Lane Skew Register (JESD_LN_SKEW)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

0

5

0

4

1

3

0

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 67. JESD_LN_SKEW Field Descriptions

Bit

15:5

4:0

Field

Type

R

Reset

Description

NOT USED

0x0000

0b00000

Not used

MEMIN_LANE_SKEW

R

Measure of the lane skew for each link only. Bits are

READ_ONLY

8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]

Figure 73. CMIX Configuration Register (CMIX)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

1

3

0

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 68. CMIX Field Descriptions

Bit

Field

Type

Reset

Description

These bits turn on the different coarse mixing options.

Combining the different options together can result in every

possible n x Fs/8 [n=0->7]. Below is the valid programming

table:

cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4)

0000 : no mixing

0001 : -fs/4

0010 : fs/2

15:12

CMIX_AB

R/W

0x0

0100 : fs/4

1000 : fs/8

1100 : 3fs/8

1010 : 5fs/8

1110 : 7fs/8

00000000

0

11:4

Reserved

CMIX_CD

R/W

Reserved

These bits turn on the different coarse mixing options.

Combining the different options together can result in every

possible n x Fs/8 [n=0->7]. Below is the valid programming

table:

cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4)

0000 : no mixing

0001 : -fs/4

0010 : fs/2

3:0

0x0

0100 : fs/4

1000 : fs/8

1100 : 3fs/8

1010 : 5fs/8

1110 : 7fs/8

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8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]

Figure 74. Output Summation and Delay Register (OUTSUM)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

1

3

1

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 69. OUTSUM Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:4

OUTPUT_DELAY

Reserved

Delays the output to the DAC 0 to 15 clock cycles

Reserved

0x00

Selects the output summing functions. Each bit selects another

sample to sum. Multiple bits can be selected.

bit 0 = add the path AB sample

3:0

OUTSUM_SEL

R/W

0x0

bit 1 = add the path CD sample

bit 2 = add adjacent DAC path AB sample

bit 3 = add adjacent DAC path CD sample

8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]

Figure 75. NCO Phase Path AB Register (PHASE_NCOAB)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

1

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 70. PHASE_NCOAB Field Descriptions

Bit

Field

Type

Reset

Description

The phase offset for the FULL NCO1 in the AB datapath.

15:0

PHASE_NCO1

Auto

Sync

0x0000

8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]

Figure 76. NCO Phase Path CD Register (PHASE_NCOCD)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W

7

0

6

0

5

0

4

1

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 71. PHASE_NCOCD Field Descriptions

Bit

Field

Type

Reset

Description

The phase offset for the FULL NCO2 in the CD datapath.

15:0

PHASE_NCO12

Auto

Sync

0x0000

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8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]

Figure 77. NCO Frequency Path AB Register (FREQ_NCOAB)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

1

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 72. FREQ_NCOAB Field Descriptions

Bit

Field

Type

Reset

Description

0x0000

0000

47:0

FREQ_NCOAB

R/W

NCO frequency word for AB data path.

0000

8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]

Figure 78. NCO Frequency Path CD Register (FREQ_NCOCD)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 73. FREQ_NCOCD Field Descriptions

Bit

Field

Type

Reset

Description

0x0000

0000

47:0

FREQ_NCOCD

R/W

NCO frequency word for CD data path.

0000

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8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]

Figure 79. SYSREF Use for Clock Divder Register (SYSREF_CLKDIV)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

0

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 74. SYSREF_CLKDIV Field Descriptions

Bit

Field

Type

Reset

Description

15

Reserved

R/W

0

Reserved

Programmable delay the SYSREF by N dacclk cycles to the

CDRV_SER clock dividers. By offsetting the clock to the

different multi-DUC blocks, clock mixing could potentially be

reduced.

14:12

11:7

CDRVSER_SYSREF_DLY

Not used

R/W

000

00000

Not used

Determines how SYSREF is used to sync the clock dividers in

the CDRV_SER block.

000 = Don’t use SYSREF pulse

6:4

SYSREF_MODE

R/W

001

001 = Use all SYSREF pulses

010 = Use only the next SYSREF pulse

011 = Skip one SYSREF pulse then use only the next one

100 = Skip one SYSREF pulse then use all pulses.

Delays the SYSREF into the CDRV_SER capture FF through 1

of 4 choices. This allows for extra delay in case the timing of the

clock or SYSREF path isn’t as good as we think.

3:2

1:0

SYSREF_DLY

Reserved

R/W

00

Reserved

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8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]

Figure 80. Serdes Clock Control Register (SERDES_CLK)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

0

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 75. SERDES_CLK Field Descriptions

Bit

Field

Type

Reset

Description

This controls the selection of the clk_jesd output

0000 = div4

0001 = div8

0010 = div12

0011 = div16

0100 = div18

0101 = div20

15:12

CLKJESD_DIV

R/W

0x7

0110 = div24

0111 = div32

1001 = div36

1010 = div48

1011 = div64

1100 = div5.333

1101 = div10.666

1110 = div21p333

This controls the selection of the clk_jesd_out output

0000 = div8

0001 = div16

0010 = div32

0011 = div48

0100 = div64

0101 = div80

0110 = div96

0111 = div128

1000 = div144

1001 = div160

1010 = div192

11:8

7:0

CLKJESD_OUT_DIV

R/W

0x7

0x0

Reserved

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8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]

Figure 81. Sync Source Control 1 Register (SYNCSEL1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

0

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 76. SYNCSEL1 Field Descriptions

Bit

Field

Type

Reset

Description

Controls the syncing of the double buffered SPI registers for the

mixerAB block. These bits are enables so a ‘1’ in the bit place

allows the sync to pass to the block.

bit 0 = auto-sync from SPI register write

bit 1 = sysref

15:12

SYNCSEL_MIXERAB

R/W

0x1

bit 2 = sync_out from JESD

bit 3 = mem_spi_sync

Controls the syncing of the double buffered SPI registers for the

mixerCD block. These bits are enables so a ‘1’ in the bit place

allows the sync to pass to the block.

bit 0 = auto-sync from SPI register write

bit 1 = sysref

11:8

7:4

SYNCSEL_MIXERCD

SYNCSEL_NCOAB

SYNCSEL_NCOCD

R/W

0x1

0x4

bit 2 = sync_out from JESD

bit 3 = mem_spi_sync

Controls the syncing of NCOAB accumulators. These bits are

enables so a ‘1’ in the bit place allows the sync to pass to the

block.

bit 0 = ‘0’

bit 1 = sysref

bit 2 = sync_out from JESD

bit 3 = mem_spi_sync

Controls the syncing of NCOCD accumulators. These bits are

enables so a ‘1’ in the bit place allows the sync to pass to the

block.

bit 0 = ‘0’

3:0

bit 1 = sysref

bit 2 = sync_out from JESD

bit 3 = mem_spi_sync

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8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]

Figure 82. Sync Source Control 2 Register (SYNCSEL2)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

1

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 77. SYNCSEL2 Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:8

Reserved

SYNCSEL_PAPAB

0x0

Select the sync for the PAP A and B.

bit 0 = ‘0’

bit 1 = sysref

bit 2 = sync_out from JESD

bit 3 = mem_spi_sync

7:4

SYNCSEL_PAPCD

R/W

0x0

Select the sync for the PAP C and D.

bit 0 = ‘0’

bit 1 = sysref

bit 2 = sync_out from JESD

bit 3 = mem_spi_sync

3:2

1

Reserved

SPI_SYNC

Reserved

R/W

0b00

Reserved

0

This is used to generate the SPI_SYNC signal

Reserved

0

8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]

Figure 83. PAP path AB Gain Attenuation Step Register (PAP_GAIN_AB)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

1

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 78. PAP_GAIN_AB Field Descriptions

Bit

15:10

9:0

Field

Type

Reset

000000

0x000

Description

NOT USED

PAPAB_GAIN_STEP

RW

Not Used

Gain attenuation step

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8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]

Figure 84. PAP path AB Wait Time Register (PAP_WAIT_AB)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

1

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 79. PAP_WAIT_AB Field Descriptions

Bit

15:10

9:0

Field

Type

Reset

R/W

Description

Reserved

PAPAB_WAIT

000000

0x000

Reserved

R/W

Number of clock cycles to wait after gain = 0

8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]

Figure 85. PAP path CD Gain Attenuation Step Register (PAP_GAIN_CD)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 80. PAP_GAIN_CD Field Descriptions

Bit

15:10

9:0

Field

Type

R/W

Reset

000000

0x000

Description

Not Used

PAPCD_GAIN_STEP

Gain attenuation step

8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]

Figure 86. PAP path CD Wait Time Register (PAP_WAIT_CD)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 81. PAP_WAIT_CD Field Descriptions

Bit

15:10

9:0

Field

Type

R/W

Reset

000000

0x000

Description

Reserved

PAPCD_WAIT

Reserved

Number of clock cycles to wait after gain = 0

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8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]

Figure 87. PAP path AB Configuration Register (PAP_CFG_AB)

15

0

14

0

13

12

0

11

0

10

0

9

0

8

x

Reserved

R/W

7

0

6

0

5

1

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 82. PAP_CFG_AB Field Descriptions

Bit

Field

Type

Reset

Description

Controls the length of the delayline in the PAP AB logic.

00 : N =32

15:14

PAPAB_SEL_DLY

R/W

00

01 : N = 64

10 : N = 128

11 : Not Valid

13

Reserved

R/W

0

Reserved

12:0

PAPAB_THRESH

0xFFF

The threshold for the PAP AB trigger.

8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]

Figure 88. PAP path CD Configuration Register (PAP_CFG_CD)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. PAP_CFG_CD Field Descriptions

Bit

Field

Type

Reset

Description

Controls the length of the delay line in the PAP CD logic.

00 : N = 32

01 : N = 64

10 : N = 128

11 : Not Valid

15:14

PAPCD_SEL_DLY

R/W

00

13

Reserved

R/W

0

Reserved

12:0

PAPCD_THRESH

0xFFF

The threshold for the PAP CD trigger.

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8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]

Figure 89. DAC SPI Constant 1 Register (SPIDAC_TEST1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 84. SPIDAC_TEST1 Field Descriptions

Bit

Field

Type

Reset

Description

15:1

Reserved

R/W

0x0000

Reserved

When asserted the DAC output is set to the value in register

SPIDAC. This can be used for trim setting and other static tests.

0

SPIDAC_ENA

R/W

0

8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]

Figure 90. DAC SPI Constant Register (SPIDAC_TEST2)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. SPIDAC_TEST2 Field Descriptions

Bit

Field

Type

Reset

Description

This value replaces the data at the output of the JESD so that

the DAC value can be controlled

15:0

SPIDAC

R/W

0x0000

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8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0000]

Figure 91. Gain for path AB Register (GAINAB)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 86. GAINAB Field Descriptions

Bit

15

Field

Type

R/W

Reset

0

Description

GAINAB_ENA

Reserved

Turns on the path AB gain block

Reserved

14:12

0x0

Extra control of gain in the GAINAB block. This allows a fix gain

to be added to the signal if needed.

11:0

GAINAB

R/W

0x400

8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0000]

Figure 92. Gain for path CD Register (GAINCD)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. GAINCD Field Descriptions

Bit

15

Field

Type

R/W

Reset

0

Description

GAINCD_ENA

Reserved

Turns on the Path CD gain block

Reserved

14:12

0x0

Extra control of gain in the GAINCD block. This allows a fix gain

to be added to the signal if needed.

11:0

GAINCD

R/W

0x400

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8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]

Figure 93. JESD Error Counter Register (JESD_ERR_CNT)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

1

5

0

4

0

3

0

2

0

1

0

1

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. JESD_ERR_CNT Field Descriptions

Bit

Field

Type

Reset

Description

This is the error count for the JESD link. This is a 16bit value

that is not cleared until the JESD synchronization is required or

errcnt_clr is programmed to '1'

15:0

JESD_ERR_CNT

R

0x0000

8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]

Figure 94. JESD ID 1 Register (JESD_ID1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R

7

0

6

1

5

0

4

0

3

0

2

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. JESD_ID1 Field Descriptions

Bit

15:11

10:6

5:1

Field

Type

R/W

Reset

00000

00001

00010

0

Description

LID0

JESD ID for lane 0

JESD ID for lane 1

JESD ID for lane 2

Reserved

LID1

LID2

0

Reserved

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8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]

Figure 95. JESD ID 2 Register (JESD_ID2)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R

7

0

6

1

5

0

4

0

3

0

2

1

0

1

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. JESD ID 2 Register (JESD_ID2)

Bit

15:11

10:6

5:1

Field

Type

R/W

Reset

00011

00100

00101

0

Description

LID3

JESD ID for lane 3

JESD ID for lane 4

JESD ID for lane 5

Reserved

LID4

LID5

0

Reserved

8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]

Figure 96. JESD ID 3 Register (JESD_ID3)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

0

3

1

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. JESD_ID3 Field Descriptions

Bit

15:11

10:6

5:4

Field

Type

R/W

Reset

00110

00111

00

Description

LID6

JESD ID for lane 6

JESD ID for lane 7

Reserved

LID7

Reserved

Selects the JESD subclass supported. Note: “001” is subclass 1

and “000” is subclass 0 they are the only modes supported; not

used for operation but used for configuration. See field

MIN_LATENCY_ENA in register JESD_MATCH (9.5.46) for use

in subclass0

3:1

0

SUBCLASSV

JESDV

R/W

001

1

Selects the version of JESD support(0=A; 1=B) NOTE: JESD

204B is only supported version.

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8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]

Figure 97. JESD Lane Enable Register (JESD_LN_EN)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

0

3

1

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. JESD_LN_EN Field Descriptions

Bit

Field

Type

Reset

Description

Turn on each lane as needed. Signal is active high.

bit 15 : lane7 enable

bit 14 : lane6 enable

bit 13 : lane5 enable

15:8

LANE_ENA

0x00

bit 12 : lane4 enable

bit 11 : lane3 enable

bit 10 : lane2 enable

bit 9 : lane1 enable

bit 8 : lane0 enable

Set to select and verify link layer test sequences. The error for

these sequences comes out the lane alarms bit0. 1= a fail and 0

= pass.

00 : test sequence disabled

7:6

JESD_TEST_SEQ

00

01 : verify repeating D.21.5 high frequency pattern for random

jitter

10 : verify repeating K.28.5 mixed frequency pattern for

deterministic jitter

11 : verify repeating ILA sequence

5:2

1:0

Reserved

0x0

11

Reserved

Used to tell the JESD block how many clock phases are being

used for lanes.

00 = 1 phase

01 = 2 phases

10 = 4 phases

11 = 8 phases

JESD_PHASE_MODE

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8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]

Figure 98. JESD RBD Buffer and Frame Octets Register (JESD_RBD_F)

15

14

13

12

0

11

0

10

0

9

0

8

0

R/W

7

0

6

1

5

0

4

0

3

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. JESD_RBD_F Field Descriptions

Bit

Field

Type

Reset

Description

15:13

Reserved

R/W

00

Reserved

This controls the amount of elastic buffers being used in the

JESD. Larger numbers will mean more latency; but smaller

numbers may not hold enough data to capture the input skew.

This value must always be ≤ mem_k

12:8

7:0

RBD

R/W

10011

0x00

F_M1

This is the number of octets in the frame - 1

8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]

Figure 99. JESD K and L Parameters Register (JESD_K_L)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

0

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 94. JESD_K_L Field Descriptions

Bit

15:13

12:8

7:5

Field

Type

R/W

Reset

000

Description

Reserved

K_M1

Reserved

10011

0

The number of frames in a multi-frame - 1. 0 ≤ k - 1 < 32

Reserved

L_M1

4:0

00011

The number of lanes used by the JESD - 1. 0 ≤ L -1 < 8

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8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]

Figure 100. JESD M and S Parameters Register (JESD_M_S)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W

7

0

6

1

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. JESD_M_S Field Descriptions

Bit

15:8

7:5

Field

Type

R/W

Reset

0x01

000

Description

M_M1

Reserved

S_M1

The number of streams per frame - 1. 0 ≤ M - 1 < 256

Reserved

4:0

00000

The number of samples per stream per frame - 1.

8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]

Figure 101. JESD N, HD and SCR Parameters Register (JESD_N_HD_SCR)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W

7

0

6

1

5

0

4

0

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. JESD_N_HD_SCR Field Descriptions

Bit

15:13

12:8

7

Field

Type

R/W

Reset

000

01111

0

Description

Reserved

NPRIME_M1

Reserved

HD

Reserved

The number of adjusted bits per sample - 1

Reserved

6

1

High density mode. Samples can cross the lane boundary

Turn on the scrambler

5

SCR

0

4:0

N_M1

01111

The number of bits per sample - 1

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8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]

Figure 102. JESD Character Match and Other Parameters Register (JESD_MATCH)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 97. JESD_MATCH Field Descriptions

Bit

Field

Type

Reset

Description

15:8

MATCH_DATA

R/W

0x1C

The character to match for buffer release. Normally it is a

/R/=/K28.0/-0x1C but with these bits the user can program the

value.

7

6

5

MATCH_SPECIFIC

MATCH_CTRL

R/W

1

0

Match a specific charater to start the JESD buffering when

asserted; otherwise the first non-K will start the buffering.

When asserted the match character is a CONTROL character

instead of a DATA character.

NO_LANE_SYNC

Assert if the TX side does not support lane initialization. This

way the RX won’t flag errors in the configuration portion of the

ILA.

4:2

1

Not Used

R/W

000

0

Not Used

MIN_LATENCY_ENA

Enable minimum latency when set. This is needed for subclass

0 support.

0

JESD_COMMAALIGN_ENA

R/W

1

When asserted the JESD block SERDES comma align signal

will be added with the SERDES ALIGN bit(0) to control when to

shut off comma alignment. When this bit is deasserted; then the

programmed bit(spi_config62(11)) is the only control.

100

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8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]

Figure 103. JESD Link Configuration Data Register (JESD_LINK_CFG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

1

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 98. JESD_Link_CFG Field Descriptions

Bit

Field

Type

Reset

Description

15-12

ADJCNT

R/W

0x0

Lane configuration data for link. Reserved by DAC38RF8x

except for lane configuration checking.

11

10-7

6-2

ADJDIR

BID

R/W

0

Lane configuration data for link. Reserved by DAC38RF8x

except for lane configuration checking.

0x0

00000

00

Lane configuration data for link. Reserved by DAC38RF8x

except for lane configuration checking.

CF

Lane configuration data for link. Reserved by DAC38RF8x

except for lane configuration checking.

1-0

CS

Lane configuration data for link. Reserved by DAC38RF8x

except for lane configuration checking.

8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]

Figure 104. JESD Sync Request Register (JESD_SYNC_REQ)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

1

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 99. JESD_SYNC_REQ Field Descriptions

Bit

Field

Type

Reset

Description

15:8

DID

R/W

0x00

Lane configuration

These bits select which errors cause a sync request. Sync

requests take priority over the error notification; so if sync

request isn’t desired; set these bits to a ‘0’.

bit 7 = multi-frame alignment error

bit 6 = frame alignment error

7:0

SYNC_REQUEST

R/W

0xFF

bit 5 = link configuration error

bit 4 = elastic buffer overflow (bad RBD value)

bit 3 = elastic buffer end char mismatch (match_ctrl match_data)

bit 2 = code synchronization error

bit 1 = 8b/10b not-in-table code error

bit 0 = 8b/10b disparity error

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8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]

Figure 105. JESD Error Output Register (JESD_ERR_OUT)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

1

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 100. JESD_ERR_OUT Field Descriptions

Bit

Field

Type

Reset

Description

15:10

Reserved

R/W

000000

Reserved

Assertion means that errors will not be reported on the sync_n

output.

9

8

DISABLE_ERR_RPT

PHADJ

R/W

0

Lane configuration

These bits select the errors generated are counted in the err_c

for the link. The bits also control what signals are sent out the

pad_syncb pin for error notification.

bit 7 = multi-frame alignment error

bit 6 = frame alignment error

7:0

ERR_ENA

R/W

0xFF

bit 5 = link configuration error

bit 4 = elastic buffer overflow (bad RBD value)

bit 3 = elastic buffer end char mismatch (match_ctrl match_data)

bit 2 = code synchronization error

bit 1 = 8b/10b not-in-table code error

bit 0 = 8b/10b disparity error

8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]

Figure 106. JESD ILA Check 1 Register (JESD_ILA_CFG1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

1

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 101. JESD_ILA_CFG1 Field Descriptions

Bit

Field

Type

Reset

Description

JESD M-1 configuration value used only for ILA checking; may

be set independently of the actual JESD mode

15:8

ILA_M

R/W

0x01

JESD F-1 configuration value used only for ILA checking; may

be set independently of the actual JESD mode

7:0

ILA_F

R/W

0x00

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8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]

Figure 107. JESD ILA Check 2 Register (JESD_ILA_CFG2)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

1

3

0

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 102. JESD_ILA_CFG2 Field Descriptions

Bit

Field

Type

Reset

Description

JESD HD configuration value used only for ILA checking; may

be set independently of the actual JESD mode

15

ILA_HD

R/W

1

JESD L-1 configuration value used only for ILA checking; may

be set independently of the actual JESD mode

14:10

9:5

ILA_L

ILA_K

ILA_S

R/W

00011

10011

00000

JESD K-1 configuration value used only for ILA checking; may

be set independently of the actual JESD mode

JESD S-1 configuration value used only for ILA checking; may

be set independently of the actual JESD mode

4:0

8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]

Figure 108. JESD SYSREF Mode Register (JESD_SYSR_MODE)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

1

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 103. JESD_SYSR_MODE Field Descriptions

Bit

15:4

3

Field

Type

R/W

Reset

0x000

0

Description

Reserved

ERR_CNT_CLR

Reserved

A transition from 0->1 causes the error_cnt to be cleared

Determines how SYSREF is used in the JESD synchronizing

block.

000 = Don’t use SYSREF pulse

001 = Use all SYSREF pulses

2:0

SYSREF_MODE

R/W

001

010 = Use only the next SYSREF pulse

011 = Skip one SYSREF pulse then use only the next one

100 = Skip one SYSREF pulse then use all pulses.

101 = skip two SYSREFs and then use one

110 = skip two SYSREFs and then use all

103

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8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]

Figure 109. JESD Crossbar Configuration 1 Register (JESD_CROSSBAR1)

15

14

0

13

0

12

0

11

10

0

9

0

8

x

Reserved

R/W

Reserved

R/W

7

0

6

1

5

0

4

1

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 104. JESD_CROSSBAR1 Field Descriptions

Bit

Field

Type

Reset

Description

15

Reserved

R/W

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

14:12

OCTETPATH0_SEL

R/W

000

010 = treat as lane2

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

111 = treat as lane7

11

Reserved

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

010 = treat as lane2

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

10:8

OCTETPATH1_SEL

001

111 = treat as lane7

7

Reserved

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

010 = treat as lane2

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

6:4

OCTETPATH2_SEL

010

111 = treat as lane7

3

Reserved

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

010 = treat as lane2

2:0

OCTETPATH3_SEL

011

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

111 = treat as lane7

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8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]

Figure 110. JESD_CROSSBAR2 Field DBits to Determine What Version of Build for the chip.escriptions

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

1

4

0

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 105. JESD_CROSSBAR2 Field Descriptions

Bit

Field

Type

Reset

Description

15

Reserved

R/W

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

14:12

OCTETPATH4_SEL

R/W

100

010 = treat as lane2

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

111 = treat as lane7

11

Reserved

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

010 = treat as lane2

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

10:8

OCTETPATH5_SEL

101

111 = treat as lane7

7

Reserved

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

010 = treat as lane2

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

6:4

OCTETPATH6_SEL

110

111 = treat as lane7

3

Reserved

0

Reserved

These bits are used by the cross-bar switch to map any lane to

any other lane. The 3 bit term tells the mapper block what lane

this particular lane is supposed to be treated as.

000 = treat as lane0

001 = treat as lane1

010 = treat as lane2

2:0

OCTETPATH7_SEL

111

011 = treat as lane3

100 = treat as lane4

101 = treat as lane5

110 = treat as lane6

111 = treat as lane7

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8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]

Figure 111. JESD Alarms for Lane 0 Register (JBits to determine what version of build for the

chip.ESD_ALM_L0)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

0

2

1

0

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 106. JESD_ALM_L0 Field Descriptions

Bit

Field

Type

Reset

Description

Lane0 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE0_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane0 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO0_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

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8.5.60 JESD Alarms for Lane 1 Register (address = 0x65 01100101) [reset = 0x0000]

Figure 112. JESD Alarms for Lane 1 Register (JESD_ALM_L1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

0

2

1

0

1

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 107. JESD_ALM_L1 Field Descriptions

Bit

Field

Type

Reset

Description

Lane1 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE1_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane1 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO1_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

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8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]

Figure 113. JESD Alarms for Lane 2 Register (JESD_ALM_L2)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

0

2

1

0

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 108. JESD_ALM_L2 Field Descriptions

Bit

Field

Type

Reset

Description

Lane2 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE2_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane2 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO2_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

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8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]

Figure 114. JESD Alarms for Lane 3 Register (JESD_ALM_L3)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

0

2

1

0

1

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 109. JESD_ALM_L3 Field Descriptions

Bit

Field

Type

Reset

Description

Lane3 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE3_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane3 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO3_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

109

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8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]

Figure 115. JESD Alarms for Lane 4 Register (JESD_ALM_L4)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

1

2

0

1

0

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 110. JESD_ALM_L4 Field Descriptions

Bit

Field

Type

Reset

Description

Lane4 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE4_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane4 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO4_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

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8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]

Figure 116. 8.4.60 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

1

2

0

1

0

1

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 111. JESD_ALM_L5 Field Descriptions

Bit

Field

Type

Reset

Description

Lane5 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE5_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane5 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO5_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

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8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]

Figure 117. JESD Alarms for Lane 6 Register (JESD_ALM_L6)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

1

2

0

1

0

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 112. JESD_ALM_L6 Field Descriptions

Bit

Field

Type

Reset

Description

Lane6 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE6_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane6 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO6_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

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8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]

Figure 118. JESD Alarms for Lane 7 Register (JESD_ALM_L7)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

1

2

0

1

0

1

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 113. JESD Alarms for Lane 7 Register (JESD_ALM_L7)

Bit

Field

Type

Reset

Description

Lane7 errors:

bit 15 = multiframe alignment error

bit 14 = frame alignment error

bit 13 = link configuration error

bit 12 = elastic buffer overflow (bad RBD value)

bit 11 = elastic buffer match error. The first non-/K/ doesn’t

match “match_ctrl” and “match_data” programmed values.

bit 10 = code synchronization error

15:8

ALM_LANE7_ERR

W0C

0x00

bit 9 = 8b/10b not-in-table code error

bit 8 = 8b/10b disparity error

7:4

3:0

Reserved

W0C

0x0

Reserved

Lane7 FIFO errors:

bit 3 = write_error : High if write request and FIFO is full (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 2 = write_full : FIFO is FULL

ALM_FIFO7_FLAGS

bit 1 = read_error : High if read request with empty FIFO (NOTE:

only released when JESD block is initialize with mem_init_state)

bit 0 = read_empty : FIFO is empty

8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]

Figure 119. SYSREF and PAP Alarms Register (ALM_SYSREF_PAP)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

1

2

1

0

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 114. ALM_SYSREF_PAP Field Descriptions

Bit

15:13

12

Field

Type

W0C

Reset

Description

Reserved

0

Reserved

ALM_SYSREF_ERR

ALM_FROM_SHORTTEST

Alarm caused when the sysref is placed at an incorrect location

This is the alarm from JESD during the SHORT TEST checking.

11

The alarms from the PAP blocks indicated which PAP was

triggered. bit0 = PAPA bit1 = PAPB bit2 = PAPC bit3 = PAPD

10:7

6:2

1

ALM_PAP

W0C

0x0

0

Reserved

This is asserted if the clkdiv192 in the CDRV_SER shift register

is all zeros.

ALM_DIV192_ZERO

Not Used

0

Not Used

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8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]

Figure 120. Clock Divider Alarms 1 Register (ALM_CLKDIV1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

W0C

7

0

6

1

5

1

4

0

3

1

2

1

0

1

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset

Table 115. ALM_CLKDIV1 Field Descriptions

Bit

Field

Type

Reset

Description

15

ALM_DIV8_ZERO

W0C

0

Asserted if the clkdiv8 in the CDRV_SER shift register is all

zeros.

14

13

12

11

10

9

ALM_DIV12_ZERO

ALM_DIV16_ZERO

ALM_DIV24_ZERO

ALM_DIV20_ZERO

ALM_DIV32_ZERO

ALM_DIV36_ZERO

ALM_DIV40_ZERO

ALM_DIV48_ZERO

ALM_DIV64_ZERO

ALM_DIV72_ZERO

ALM_DIV80_ZERO

ALM_DIV96_ZERO

ALM_DIV128_ZERO

ALM_DIV144_ZERO

ALM_DIV160_ZERO

W0C

0

Asserted if the clkdiv12 in the CDRV_SER shift register is all

zeros.

Asserted if the clkdiv16 in the CDRV_SER shift register is all

zeros.

Asserted if the clkdiv24 in the CDRV_SER shift register is all

zeros. (Connected to the div18 port)

Asserted if the clkdiv20 in the CDRV_SER shift register is all

zeros.

Asserted if the clkdiv32 in the CDRV_SER shift register is all

zeros.

Asserted if the clkdiv36 in the CDRV_SER shift register is all

zeros.

8

Asserted if the clkdiv40 in the CDRV_SER shift register is all

zeros.

7

Asserted if the clkdiv48 in the CDRV_SER shift register is all

zeros.

6

Asserted if the clkdiv64 in the CDRV_SER shift register is all

zeros.

5

Asserted if the clkdiv72 in the CDRV_SER shift register is all

zeros.

4

Asserted if the clkdiv80 in the CDRV_SER shift register is all

zeros.

3

Asserted if the clkdiv96 in the CDRV_SER shift register is all

zeros.

2

Asserted if the clkdiv128 in the CDRV_SER shift register is all

zeros.

1

Asserted if the clkdiv144 in the CDRV_SER shift register is all

zeros.

0

Asserted if the clkdiv160 in the CDRV_SER shift register is all

zeros.

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8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xF000]

Figure 121. Clock Configuration Register (CLK_CONFIG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 116. CLK_CONFIG Field Descriptions

Bit

Field

Type

Reset

Description

15

RCLK_SYNC_ENA

RW

1

When asserted the sysref is used to sync the clock divider in the

centralclkdiv. This should be disabled after initial syncing.

14

FRCLK_DIV_ENA

RW

1

When asserted the full rate clock divider that provides the DIV4

phases to the DACs is enabled

13

12

11

10

9:2

1

DACA_FRCLK_ENA

DACB_FRCLK_ENA

DACA_DUMDATA

DACB_DUMDATA

Reserved

RW

1

When asserted the full rate clock to the DACA block is enabled

When asserted the full rate clock to the DACB block is enabled

Enables distortion enhancement for DACA when set high

Enables distortion enhancement for DACB when set high

Reserved

1

0

0x000

QRCLOCK_DACA_ENA

QRCLOCK_DACB_ENA

1

Turns on the quarter rate clock for DACA when '1'

Turns on the quarter rate clock for DACB when '1'

0

8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]

Figure 122. Clock Configuration Register (SLEEP_CONFIG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 117. SLEEP_CONFIG Field Descriptions

Bit

15:9

8

Field

Type

RW

Reset

Description

Reserved

0000000

Reserved

VBGR_SLEEP

Reserved

0

1

0

Turns off the 'bandgap-over-R' bias

Reserved

7

6

TSENSE_SLEEP

PLL_SLEEP

CLKRECV_SLEEP

Turns off the temperature sensor

5

Puts the PLL into sleep mode (FUSE Controlled)

4

When asserted the clock input receiver gets put into sleep

mode. This also affects the FIFO_OSTR receiver as well.

3

2

1

0

DACA_SLEEP

DACB_SLEEP

CLK_TX_SLEEP

Reserved

RW

0

1

0

Puts the DACA into sleep mode

Puts the DACB into sleep mode

When asserted the PLL TX clock output is in low power mode.

Reserved

115

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8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x8000]

Figure 123. Divided Output Clock Configuration Register (CLK_OUT)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 118. CLK_OUT Field Descriptions

Bit

Field

Type

Reset

Description

15

CLK_TX_IDLE

R/W

1

When high puts the CLK_TX circuitry in idle mode during which

the CLKTX+ and CLKTX- output pins are driven to the proper

common-mode levels in order to charge the external AC

coupling caps. When low allows the divided clock to be driven

onto the CLKTX+ and CLKTX- output pins.

14:13

CLK_TX_DIVSELECT

R/W

01

Selects either div2, div3 or div 4 output.

00 = divided by 3

01 = divided by 4

10 = divided by 2

11 = not valid

12

Reserved

R/W

0

Reserved

11:8

CLK_TX_SWING

0x0

Sets desired swing on CLKTX+ and CLKTX- outputs in mVpp-

diff

0x0 125

0x1 232

0x2 337

0x3 440

0x4 540

0x5 639

0x6 736

0x7 831

0x8 924

0x9 1012

0xA 1097

0xB 1178

0xC 1255

0xD 1329

0xE 1398

0xF 1462

7:3

2

Reserved

R/W

00000

Reserved

CLK_TX_FLIP

TX_SYNC_ENA

EXTREF_ENA

0

1

0

Flips the polarity of CLKTX

Syncs the CLKTX with SYSREF when asserted

1

0

Allows the chip to use an external refernce(1) or the internal

reference(0)

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8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]

Figure 124. DAC Fullscale Current Register (DACFS)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 119. DACFS Field Descriptions

Bit

Field

Type

R/W

Reset

Description

Scales the output current is 16 equal steps from 10-40mA

(10mA + 2mA*DACFS)

15:12

10:0

DACFS

Reserved

0xF

0x000

Reserved

8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]

Figure 125. Internal SYSREF Register (LCMGEN)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 120. LCMGEN Field Descriptions

Bit

15:4

3

Field

Type

R/W

Reset

Description

Reserved

0x00

Reserved

LCMGEN_ENA

0

Enables the LCM custom logic

Reset the LCM custom logic

TBD

2

LCMGEN_RESET

LCMGEN_SPI_SYSREF_ENA

LCM_SYSREF_OUTSEL

1

0

Chooses between internal and external SYSREF

8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]

Figure 126. Counter for Internal SYSREF Generator Register (LCMGEN_DIV)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 121. LCMGEN_DIV Field Descriptions

Bit

Field

Type

Reset

Description

Counter setting for the LCMGEN block

15:0

LCMGEN_DIV

R/W

0x00

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8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]

Figure 127. SPI SYSREF for Internal SYSREF Generator Register (LCMGEN_SPISYSREF)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

0

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 122. LCMGEN_SPISYSREF Field Descriptions

Bit

15:1

0

Field

Type

R/W

Reset

0x00

0

Description

Reserved

LCMGEN_SPI_SYSREF

SPI SYSREF for the LCMGEN block

8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]

Figure 128. Digital Test Signals Register (DTEST)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

0

4

1

3

1

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 123. DTEST Field Descriptions

Bit

Field

Type

Reset

Description

15

Reserved

R/W

0

Reserved

Selects the lane to check for the signals selected by field

DTEST

14:12

DTEST_LANE

R/W

000

Allows digital test signals to come out the ALARM pin.

0000 : Test disabled; normal ALARM pin function

0001 : SERDES lanes 0 – 3 PLL clock/80

0010 : SERDES lanes 4 – 7 PLL clock/80

0011 : TESTFAIL (lane selected by field DTEST_LANE)

0100 : SYNC (lane selected by field DTEST_LANE)

0101 : OCIP (lane selected by field DTEST_LANE)

0110 : EQUNDER (lane selected by field DTEST_LANE)

0111 : EQOVER (lane selected by field DTEST_LANE)

1000 – 1111 : not used

11:8

7:0

DTEST

R/W

0x0

Reserved

0x00

Reserved

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8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]

These fields control the routing of the SLEEP signal to different blocks. Assertion means that the SLEEP signal

will be sent to the block. These bits do not override the SPI bits; just the SLEEP signal from the PAD.

Figure 129. Sleep Pin Control Register (SLEEP_CNTL)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

0

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 124. SLEEP_CNTL Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:10

Reserved

11111

Reserved

9

8

CLKOUT_SLEEP

BG_SLEEP

1

Allows the output clock to sleep

Allows the band gap to sleep

Allows the temp sensor to sleep

1

7

TEMP_SLEEP

PLL_CP_SLEEP

PLL_SLEEP

CLK_RECV_SLEEP

Reserved

1

6

1

Allows the PLL charge pump to sleep

Allows the PLL to sleep

Allows the clock receiver to sleep

Reserved

5

1

4

1

3:2

1

11

1

DACB_SLEEP

DACA_SLEEP

Allows DACB to sleep

0

1

Allows DACA to sleep

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8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]

Figure 130. SYSREF Capture Circuit Control Register (SYSR_CAPTURE)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

1

5

0

4

0

3

0

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 125. SYSR_CAPTURE Field Descriptions

Bit

Field

Type

Reset

Description

sysref phase alignment tolerance window Centers sysref capture

window as follows:

00 = Centered on phase φ12 (**DEFAULT**)

01 = Centered on phase φ23

15:14

SYSR_PHASE_WDW

R/W

00

10 = Centered on phase φ34

11 = Centered on phase φ41

sysref alignment offset delay Optional alignment offset that

allows system designer to work around hardware (e.g. PCB)

alignment errors by letting him specify that the sysref pulse

should be treated as occurring one device clock earlier or later

than its observed position. Legal settings are as follows:

00 = Offset by -1 device clock cycles. Treat sysref as if it were

captured 1 cycle earlier.

13:12

SYSR_ALIGN_DLY

R/W

01

01 = No offset (**DEFAULT**)

10 = Offset by +1 device clock cycles. Treat sysref as if it were

captured 1 cycle later.

11 = Reserved

Enable alignment status monitoring Enable logic that generates

sysref alignment status information and accumulates statistics

that can be read by the user.

11

SYSR_STATUS_ENA

R/W

0

0 = Disable sysref alignment status outputs (**DEFAULT**).

Used during normal operation.

1 = Enable sysref alignment status outputs. Used when

characterizing sysref capture timing.

10:2

1

Reserved

R/W

0x000

0

Reserved

SYSR_ALIGN_SYNC

Write a ‘1’ to this bit to clear accumulated sysref align statistics

Bypass sysref alignment logic. Bypass the 4x oversampled

sysref alignment logic and instead capture the sysref signal

using the legacy implementation of a flip-flop clocked directly by

the rising edge of the device clock.

0

SYSR_BYPS_ALIGN

R/W

0

0 = Capture sysref using full-featured alignment circuit

(**DEFAULT**)

1 = Bypass sysref alignment logic

NOTE: When mem_sysref_bypass_align is enabled, the other

sysref alignment controls have no effect.

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8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]

Figure 131. Clock Input and PLL Configuration Register (CLK_PLL_CFG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 126. Clock Input and PLL Configuration Register (CLK_PLL_CFG)

Bit

Field

Type

Reset

Description

15:14

Reserved

R/W

00

Reserved

Selects the external differential or single ended clock for

DACCLK.

0 = differential

1 = single ended

13

SEL_EXTCLK_DIFFSE

R/W

0

12

11

PLL_RESET

R/W

0

When set the M divider; N divider and PFD are held reset

When asserted; the SYSREF input is used to sync the N

dividers of the PLL.

PLL_NDIVSYNC_ENA

Enables the PLL output as the DAC clock when set; the clock

provided at the DACCLKP/N is used as the PLL reference clock.

When cleared; the PLL is bypassed and the clock provided at

the DACCLKP/N pins is used as the DAC clock

10

9

PLL_ENA

R/W

0

1

Must be set to '0' for proper PLL operation.

1 = Charge pump is put to sleep and can be driven by external

source through the ATEST pins.

PLL_CP_SLEEP

R/W

8

Reserved

R/W

0

Reserved

7:3

PLL_N_M1

00000

Reference clock divider; divide by is N+1

Adjusts the lock detector sensitivity. Upper bit isn't used:

x00 - highest sensitivity x11 - lowest sensitivity

2:0

LOCKDET_ADJ

R/W

000

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8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]

Figure 132. PLL Configuration 1 Register (PLL_CONFIG1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 127. CONFIG1 Field Descriptions

Bit

15:8

7:4

Field

Type

R/W

Reset

0x03

0x0

Description

PLL_M_M1

Reserved

VCO feedback divider; divide by is 4(M+1)

Reserved

3:0

PLL_VCO_RDAC

0x8

Controls the VCO amplitude

8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]

Figure 133. PLL Configuration 2 Register (PLL_CONFIG2)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 128. PLL_CONFIG2 Field Descriptions

Bit

Field

Type

Reset

Description

Selects between two VCOs

15

PLL_VCOSEL

R/W

0

0 = 5.9 GHz VCO(2 turn inductor in upper VCO)

1 = 8.9 GHz VCO (1 turn in the lower VCO)

14:8

7:6

PLL_VCO

Reserved

R/W

1000000

000

VCO frequency range

Reserved

Adjusts the charge pump current; 0 to 1.55 mA in 50 µA steps.

Setting to 0000 will hold the LPF pin at 0 V

5:2

PLL_CP_ADJ

R/W

0110

1

0

Reserved

R/W

0

Reserved

Reserved. Always write 0

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8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]

Figure 134. LVDS Output Configuration Register (LVDS_CONFIG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

0

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 129. LVDS_CONFIG Field Descriptions

Bit

Field

Type

Reset

Description

LVDS Output current control LSB; allows output current to be

scaled from ~2 mA to ~4 mA

15

LVDS_LOPWRB

R/W

0

LVDS Output current control MSB; allows output current to be

scaled from ~2 mA to ~4 mA

14

LVDS_LOPWRA

R/W

0

SYNC LVDS output on chip termination control; 100 Ω when

cleared; 200 Ω

Output current settings for the combination of bits 15:13

110 = 4.00 mA

010 = 3.50 mA

13

LVDS_LPSEL

100 = 3.00 mA

000 = 2.50 mA – Default current

111 = 4.00 mA

011 = 3.33 mA

101 = 2.66 mA

001 = 2.00 mA

Enable LVDS bias bandgap reference voltage to the ATEST

multiplexer.

12

LVDS_EFUSE_SEL

LVDS_TRIM

R/W

0

Adjusts the LVDS 1.2 V reference. LVDS_TRIM_ENA must be

set and LVDS_EFUSE_SEL must be cleared for these bits to

have any effect.

10 +70 mV

00 -70 mV

11:10

00

01 default

11 -20 mV.

When set and LVDS_EFUSE_SEL is cleared; the LVDS_TRIM

adjustment is enabled. When cleared; the LVDS_TRIM has no

effect.

9

LVDS_TRIM_ENA

R/W

0

8

7

LVDS_SYNC0\_PD

Reserved

R/W

0

The SYNC0 LVDS output is in power down.

Reserved

SYNC0 LVDS output common mode is 1.2 V when cleared; 0.9

V when set.

6

LVDS_SYNC0\_CM

Reserved

R/W

0

5:0

0x00

Reserved

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8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]

Figure 135. Fuse Farm clock divider Register (PLL_FDIV)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

1

2

0

1

0

1

R/W

R/1W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after rese1t

Table 130. PLL_FDIV Field Descriptions

Bit

15:8

7:0

Field

Type

R/W

Reset

0

Description

Reserved

PLL_FDIV

Reserved

0x18

Clock divider for the Fuse farm

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8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x0002]

Figure 136. Serdes Clock Configuration Register (SRDS_CLK_CFG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

1

2

0

1

0

1

R/W

R/1W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after rese1t

Table 131. SRDS_CLK_CFG Field Descriptions

Bit

Field

Type

Reset

Description

Select either the PLL output of the DACCLK from the pad.

15

SERDES_CLK_SEL

R/W

0

0 = DACCLK pad

1 = PLL output

14:11

10:2

SERDES_REFCLK_DIV

Reserved

R/W

0x0

The divide amount for the serdes REFCLK minus 1

Reserved

0x000

These bits select the pre-divide on the DACCLK input clock

before the DACCLK is used in the dividers used in the SERDES

PLL REFCLK and the Fusefarm SYSCLK.

00 = if DACCLK input ≤ 2 GHz; prediv is set to div1

01 = if DACCLK input is ≤ 4 GHz and > 2 GHz, prediv is set to

div2

1:0

SERDES_REFCLK_PREDIV

R/W

10

10 = if DACCLK input is ≤ 9 GHz and > 4 GHz, prediv is set to

div4

11 = Not valid

8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]

Figure 137. Serdes PLL Configuration Register (SRDS_PLL_CFG)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 132. SRDS_PLL_CFG Field Descriptions

Bit

15

Field

Type

R/W

Reset

Description

ENDIVCLK

CLKBYP

LB

1

Enable divided by 5 output clock

Serdes clock bypass

14:3

12:11

10

00

0

Serdes PLL loop bandwidth

Serdes PLL Sleep

SLEEPPLL

VRANGE

MPY

9

1

Serdes PLL loop filter range

8:1

0

00010100 Serdes reference clock multiplication factor Table 4

AND'ed with LANE_ENA so it must be set to 1 for correct

behavior

CORRECT

0

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8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]

Figure 138. Serdes Configuration 1 Register (SRDS_CFG1)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 133. RDS_CFG1 Field Descriptions

Bit

15

Field

Type

R/W

Reset

0

Description

Reserved

TESTPATT

BSINRXN

BSINRXP

Reserved

ENOC

Reserved

14:12

11

000

0

Test pattern

Enable boundary scan - pins

Enable boundary scan + pins

Reserved

10

0

9:8

7

00

1

Enable Serdes offset compensation

Equalizer hold

6

EQHLD

EQ

0

5:3

2:0

001

000

Serdes equalizer

CDR

Clock data recovery algorithm settings

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8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]

Figure 139. Serdes Configuration 2 Register (SRDS_CFG2)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

1

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 134. SRDS_CFG2 Field Descriptions

Bit

Field

Type

Reset

Description

Enables loss of signal detection.

000 - Disable detection

100 - Enable detection

other - reserved

15:13

LOS

R/W

000

Enables external or internal symbol alignment

00 : Disabled

01 : Comma alignment

10: Align jog

12:11

10:8

ALIGN

TERM

R/W

01

Valid programming:

001 – AC coupling with common mode = 0.7 V

100 – 0 V common mode.

001

101 – 0.25 V common mode

111 – DC coupling with common mode of 0.6 V.

(NOTE: This is not compatible with JESD)

7

Reserved

RATE

R/W

0

Reserved

Selects full (00), half (01), quarter (10) or eighth (11) rate

operation.

6:5

00

Selects the parallel interface width (16 or 20 bits).

4:2

BUSWIDTH

R/W

010

0 : 20 bits

1: 16 bits

Powers the receiver down into the sleep (fast power up) state

when high.

1

0

SLEEPRX

Reserved

R/W

0

1

Reserved

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8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]

Figure 140. Serdes Polarity Control Register (SRDS_POL)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

1

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 135. SRDS_POL Field Descriptions

Bit

Field

Type

Reset

Description

15:8

Reserved

R/W

0x00

Reserved

Allows the PN pairs of the different lanes to be inverted.

bit 7 = lane7

bit 6 = lane6

bit 5 = lane5

bit 4 = lane4

bit 3 = lane3

bit 2 = lane2

bit 1 = lane1

bit 0 = lane0

7:0

INVPAIR

R/W

0x00

8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]

Figure 141. JESD204B SYNCB OUTPUT Register (SYNCBOUT)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

x

R/W

7

0

6

0

5

1

4

1

3

1

2

0

1

0

1

R/W

R/1W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 136. SYNCBOUT Field Descriptions

Bit

Field

Type

Reset

Description

15:2

Reserved

R/W

0x00

Reserved

If the CMOS SYNC outputs are turned on, this bit will show the

status of the JESD SYNCB1 signal

1

0

SYNCBOUT1

SYNCBOUT0

R/W

0

If the CMOS SYNC outputs are turned on, this bit will show the

status of the JESD SYNCB0 signal

128

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Start-up Sequence

PULL TXENABLE LOW

ñ

Provide all 1V supply rails, 1.8V rails and -1.8V rail.

ñ

Pull TRSTB pin of the JTAG port low

Provide a clock to the differential or single ended clock input

Toggle RESETB pin low then high (recommended pulse duration

>10us)

Read SPI Page 0, Register 0x7F

Bits[15:10] B 10000b

Bits[15:10]=10000b

Configure the SPI resgisters for the desired mode

Increment/decrement

VCO tune value

SPI Page 4, address

0x33, bits[14:8]

Read page 0, address 0x06

Tj = bits[15:8]

On chip PLL mode

YES

LFVOLT = bits[7:5]

NO

108/ G Çi < 125C, LFVOLT =5or6

Start SYSREF Generation

92/ G Çi < 108C, LFVOLT=4or5

26/ G Çi < 92C, LFVOLT =3or4

-40/ G Çi < 26C, LFVOLT =2or3

ñ

Reset encoder block:

Page 1/2:address 0x24:bits [6:4] = 000b

Page 1/2:address 0x5C:bits [2:0] = 000b

Page 4:address 0x0A:bit [15] = 1b

Ensure at least 2 SYSREF rising edges occur to reset the encoder

Page 4:address 0x0A:bit [15] = 0b

ñ

Put JESD204B core in reset

Page 0:address 0x00:bits [1:0] = 11b

Sync CDRV and JESD204B blocks

Page 1/2:address 0x24:bits [6:4] = 010b

Ensure at least 2 SYSREF rising edges occur to reset the CDRV

Page 1/2:address 0x5C:bits [2:0] = 011b

Ensure at least 2 SYSREF rising edges occur to reset the JESD

Take JESD Core out of reset

ñ

Page 0:address 0x00:bits [1:0] = 00b

Ensure at least 2 SYSREF rising edges occur

ñ

Clear all DAC alarms: Write 0x0000 to alarm registers on

Page0: 0x04, 0x05 and Page1/2: 0x64 to 0x6D

Stop SYSREF generation to DAC (optional)

Pull TXENABLE HIGH

图 142. DAC38RF82/89 Recommended Startup Sequence

129

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9.2 Typical Application

The block diagram of a typical DOCSIS downstream network is shown in 图 143. The physical layer (PHY) of the

cable modem termination system (or CMTS) must support normal downstream operating range from 54 MHz to

1002 MHz as well as extended operating range up to 1794 MHz. The high input bandwidth (up to 3.33 GHz) of

DAC38RF82 and DAC38RF89 makes these devices suitable for DOCSIS CMTS. Also the integrated high

performance PLL simplifies system clocking by eliminating the need to generate and distribute high frequency

sampling clock to the DAC. In the following sections, the performance of DAC38RF82 (and DAC38RF89) used to

generate DOCSIS 3.0, Annex A, 6 MHz 256-QAM carriers will be described.

CM

Hybrid fibre/coax

Network

Management

CMTS

HFC Network

Cable Modem Termination

System

CM

Cable modem

(Home Network)

图 143. DOCSIS Downstream Network

表 137. DOCSIS CMTS Design Features

9.2.1 Design Requirements

Feature

Frequency range

No of carriers

Channel width

Modulation type

Modulation rate

Data rate

Specification

54 MHz to 1002 MHz

1

6 MHz

256 QAM

5.3605 Msym/s

2.4576 GSPS

>48 dB

MER (unequalized)

ACPR

>70 dBc

9.2.2 Detailed Design Procedure

A sample rate of 4.9152 GHz is selected for the DAC. This will make it possible to meet the out of band (up to

3GHz) spurious requirement of 65 dBc by pushing the DAC images to the 2nd Nyquist zone (2.4576 MHz to

4.9152 GHz). Because the input data rate is 2.4576 GSPS, the DAC interpolation is set to 2. To generate the

4.9152 GHz sampling clock for the DAC, a low frequency 409.6 MHz clock is provided to the DAC reference

clock input. A detailed block diagram is shown in 图 144

130

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4915.2 MHz

409.6 MHz

SYSREF

Low Jitter

PLL

16 bit, real data

2.4576 GSPS

1.333 : 1

14-b

DAC

x

sin(x)

100Q

75Q

2x interp

图 144. DOCSIS Downstream Network

9.2.3 Calculating the JESD204B SerDes rate

SerDes rate = 1.25 x (M/L) x Baseband data rate x Number of bits per sample (16)

M is a JESD204B interface parameter that refers to the number of data streams from FPGA to DAC

L is a JESD204B interface parameter that refers to the number of SerDes lanes used to transmit data

1.25 is a factor due to the 8B10B encoding of the baseband data

Example,

if the baseband data rate = 2457.6 MSPS and L-M-F-S-Hd = 4-1-1-2-1

SerDes rate = 1.25 x (1/4) x 2457.6 x 16 = 12.288 Gbps

(19)

9.2.4 Calculating valid JESD204B SYSREF Frequency

Valid SYSREF frequencies depend on the following parameters:

1. Sample clock frequency

2. JESD204B internal clock divider value (CLKJESD_DIV). This depends on the DAC JESD204B L-M-F-S

mode and interpolation

3. Number of octets in a frame (F)

4. Number of frames in a multi-frame (K)

Maximum SYSREF frequency = (Sample clock frequency/N),

where N =LCM(CLKJESD_DIV,4 x K x F). N is the Least common multiple of 4 x K x F and CLKJESD_DIV.

All valid SYSREF frequencies are integer divisors of the maximum SYSREF frequency.

Example:

Given sampling clock frequency = 4.9152 GSPS, interpolation =2, DAC Mode=L-M-F-S=4-1-1-2 and K=20:

CLKJESD_DIV = 8 (CLKJESD_DIV)

Maximum SYSREF Frequency = 4915.2 MHz/80 = 61.44 MHz

Valid SYSREF Frequencies = 61.44 MHz/n, where n is any positive integer.

131

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www.ti.com.cn

9.2.5 Application Curves

图 145. ACPR Performance of 6 MHz Single Carrier at 591 MHz

图 146. ACPR performance of 6 MHz Single Carrier at 998 MHz

132

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图 147. Unequalized MER of 6 MHz Single Carrier at 591 MHz

图 148. Unequalized MER of 6 MHz Single Carrier at 998 MHz

133

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10 Power Supply Recommendations

Internally, DAC38RF82 (DAC38RF89) comprises a digital subsystem, an analog subsystem, and a clock

subsystem. Ideally, the power supply scheme should be partitioned according to these three relatively

independent blocks to minimize interactions between them. Most importantly, sensitive analog and clock circuit

power supply must be separated from digital switching noise to reduce direct coupling and mixing of switching

spurs. 表 138 shows the power supply rails for DAC38RF82 (DAC38RF89) grouped under their respective

domains.

表 138. Power Supply Domains

Supply rail

VDDIG1

Nominal voltage (V)

Domain

+1.0

+1.8

+1.0

-1.8

VDDIO18

VDDR18

VDDS18

Digital

VDDT1

VDDE1

VDDL1_1

VEE18N

VDDA1

+1.0

+1.8

+1.0

+1.8

+1.0

+1.8

Analog

VDDA18

VDDOUT18

VDDPLL1

VDDAPLL18

VDDAVCO18

VDDCLK1

VDDL2_1

VDDTX1

VDDTX18

Clock

An example power supply scheme suitable for most applications of DAC38RF82 (DAC38RF89) is shown in 图

149. It is recommended to use ferrite beads (FB) to isolate the individual rails from each other.

5Vin

1 V

TPS62085

(3 A)

VDDDIG1 (2.5 A)

1 V

VDDT1 (375 mA)

VDDL1_1 (45 mA)

VDDL2_1 (45 mA)

VDDCLK1 (425 mA)

VDDA1 (25 mA)

TPS74401

(2 A)

1 V

VDDPLL1 (30 mA)

VDDTX1 (14 mA)

VDDE1 (650 mA)

VDDA18 (45 mA)

1.8 V

TPS62085

(3 A)

VDDOUT18 (100 mA)

VDDAVCO18 (40 mA)

VDDAPLL18 (20 mA)

1.8 V

VDDR18 + VDDS18 + VDDIO18 (135 mA)

VDDTX18 (14 mA)

LM27761

(250 mA)

VEE18 (152 mA)

œ1.8 V

图 149. Power Supply Scheme for DAC38RF82 (DAC38RF89)

134

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10.1 Power Supply Sequencing

There are no power supply sequencing requirements for all the 1-V and 1.8-V power supplies. For the -1.8 V

VEE18 rail, it is recommended that this supply is the last to be enabled. Enabling VEE18 (while other supply

voltages are disabled) can cause a small negative voltage to be present at the other rails (that is, VDDA1 and

VDDDIG1). This small negative voltage can interfere with the startup of some DC-DC converters or LDO

connected to the 1 V and 1.8 V input power rails.

11 Layout

11.1 Layout Guidelines

•

DAC RF output traces

–

Differential 100 Ω co-planar wave guide for output traces is recommended.

Use short RF traces. Place DAC close to edge of PCB to shorten the length of output and clock traces.

This helps to minimize PCB loss and coupling

–

Stitch the ground plane with ground vias uniformly along the output trace.

Avoid width/spacing differences when entering a landing pad (eg. a balun) by tapering or by redefining

width/space rules for the traces

•

Power supply planes

–

Ensure sufficient lateral spacing between two power planes (about 3x the thickness of the plane is

recommended)

–

Insert ground plane between adjacent power planes where possible

图 150. Example Power Plane Routing

•

Bypass Capacitors

–

Use bypass capacitors with in-pad vias and place between the pin and the power plane. Avoid sharing

ground vias or pads of bypass caps used for different power rails

–

Minimize stubs on bypass capacitors to avoid parasitic inductance

135

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www.ti.com.cn

Layout Guidelines (接下页)

图 151. Bypass Capacitors Placed on the Power Supply Pin With In-pad Vias

High speed SerDes traces

•

–

Route all SerDes traces straight and minimized sharp curves or serpentines. Route for best signal integrity

Some skew between SerDes traces can be tolerated. It is recommended to limit skew between traces to

320ps or less

–

Place ground planes between the SerDes traces for improved isolation

图 152. Layout Example of High Speed SerDes Traces

136

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11.2 Layout Example

A

B

C

D

E

F

G

H

J

K

L

M

Rbias

12

11

10

9

Bottom Trace

Top Trace

Capacitor

Resistor

Via

8

7

6

5

4

3

2

1

图 153. Layout Example

137

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ZHCSGM6C –FEBRUARY 2017–REVISED APRIL 2020

www.ti.com.cn

12 器件和文档支持

12.1 相关链接

下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链

接。

表 139. 相关链接

器件

产品文件夹

单击此处

立即订购

单击此处

技术文档

单击此处

工具和软件

单击此处

支持和社区

单击此处

DAC38RF82

DAC38RF89

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

138

PACKAGE OUTLINE

AAV0144A

FCBGA - 1.91 mm max height

SCALE 1.400

BALL GRID ARRAY

10.15

9.85

A

B

BALL A1 CORNER

10.15

9.85

(

8)

(0.67)

1.91

1.70

(0.5)

C

SEATING PLANE

NOTE 4

BALL TYP

0.405

0.325

TYP

0.1 C

8.8 TYP

SYMM

(0.6) TYP

0.8 TYP

M

L

K

J

H

G

F

SYMM

8.8

TYP

E

D

C

B

A

0.51

0.41

144X

0.15

0.08

C A B

NOTE 3

C

1

2

3

4

5

6

7

8

9

10

11

12

0.8 TYP

4219578/C 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.

4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.

www.ti.com

EXAMPLE BOARD LAYOUT

AAV0144A

FCBGA - 1.91 mm max height

BALL GRID ARRAY

(0.8) TYP

1

3

5

6

7

8

9

10 11

4

12

2

A

B

(0.8) TYP

C

D

E

F

144X ( 0.4)

SYMM

G

H

J

K

L

M

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

(

0.4)

0.05 MAX

METAL UNDER

SOLDER MASK

0.05 MIN

METAL

EXPOSED

METAL

EXPOSED

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219578/C 05/2022

NOTES: (continued)

5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com

EXAMPLE STENCIL DESIGN

AAV0144A

FCBGA - 1.91 mm max height

BALL GRID ARRAY

(0.8) TYP

144X ( 0.4)

10 11

1

3

5

6

7

8

9

4

12

2

A

B

(0.8) TYP

C

D

E

F

SYMM

G

H

J

K

L

M

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4219578/C 05/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC38RF89IAAVR
厂家：	TEXAS INSTRUMENTS
描述：	双通道 14 位 8.4GSPS 1x-24x 内插 5GHz 和 7.5GHz PLL 数模转换器 \| AAV \| 144 \| -40 to 85 转换器数模转换器
文件：	总147页 (文件大小：4208K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC38RF89IAAVR [TI]

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