DAC5571IDBVTG4 [TI]
+2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT, 8-BIT DIGITAL-TO-ANALOG CONVERTER; + 2.7V至+ 5.5V ， I2C接口，电压输出， 8位数字 - 模拟转换器
| 型号： | DAC5571IDBVTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT, 8-BIT DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总23页 (文件大小：626K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
+2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT,
8-BIT DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
Micropower Operation: 125 µA @ 3 V
The DAC5571 is a low-power, single-channel, 8-bit
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing to be
achieved. The DAC5571 utilizes an I2C-compatible,
two-wire serial interface that operates at clock rates
up to 3.4 Mbps with address support of up to two
DAC5571s on the same data bus.
Fast Update Rate: 188 KSPS
Power-On Reset to Zero
+2.7-V to +5.5-V Power Supply
Specified Monotonic by Design
I2C™ Interface up to 3.4 Mbps
On-Chip Output Buffer Amplifier, Rail-to-Rail
Operation
Double-Buffered Input Register
Address Support for up to Two DAC5571s
Small 6 Lead SOT 23 Package
The output voltage range of the DAC is 0 V to VDD
.
The DAC5571 incorporates a power-on-reset circuit
that ensures that the DAC output powers up at zero
volts and remains there until a valid write to the
•
•
•
•
device takes place. The DAC5571 contains
a
power-down feature, accessed via the internal control
register, that reduces the current consumption of the
device to 50 nA at 5 V.
Operation From –40°C to 105°C
APPLICATIONS
The low-power consumption of this part in normal
operation makes it ideally suited for portable battery
operated equipment. The power consumption is less
than 0.7 mW at VDD = 5 V reducing to 1 µW in
power-down mode.
•
•
•
•
•
Process Control
Data Acquistion Systems
Closed-Loop Servo Control
PC Peripherals
Portable Instrumentation
DAC7571/6571/5571 are 12/10/8-bit, single-channel
I2C DACs from the same family. DAC7574/6574/5574
and
DAC7573/6573/5573
are
12/10/8-bit
quad-channel I2C DACs. Also see DAC8571/8574 for
single/quad-channel, 16-bit I2C DACs.
V
DD
GND
Power-On
Reset
Ref (+) Ref(−)
8-Bit
DAC
Register
Output
Buffer
V
OUT
DAC
2
I C
Control
Logic
Power-Down
Control Logic
Resistor
Network
A0
SCL SDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DESIG-
NATOR
SPECIFIED TEM-
PERATURE RANGE
PACKAGE
MARKING
ORDERING NUM-
BER
PRODUCT PACKAGE
TRANSPORT MEDIA
DAC5571IDBVT
DAC5571IDBVR
250-Piece Small Tape and Reel
3000-Piece Tape and Reel
DAC5571
SOT23-6
DBV
–40°C to +105°C
D571
PIN CONFIGURATIONS
(TOP VIEW)
PIN DESCRIPTION (SOT23-6)
V
A0
6
5
4
1
2
3
OUT
PIN
NAME
DESCRIPTION
GND
SCL
SDA
1
VOUT
Analog output voltage from DAC
V
DD
Ground reference point for all
circuitry
2
GND
3
4
5
6
VDD
SDA
SCL
A0
Analog Voltage Supply Input
Serial Data Input
(BOTTOM VIEW)
Serial Clock Input
1
2
3
6
5
4
Device Address Select
LOT
TRACE
CODE:
Year (3 = 2003); M onth (1–9 = JAN–SEP; A=OCT,
B=NOV, C=DEC); LL– Random code generated
when assembly is requested
Lot Trace Code
ABSOLUTE MAXIMUM RATINGS(1)
UNITS
VDD to GND
– 0.3 V to +6 V
–0.3 V to +VDD+0.3 V
– 0.3 V to +VDD+0.3 V
–40°C to +105°C
–65°C to +150°C
+150°C
Digital input voltage to GND
VOUT to GND
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
Power dissipation
(TJmax - TA)RΘJA
240°C/W
Thermal impedance, RΘJA
Lead temperature, soldering
Vapor phase (60s)
Infrared (15s)
215°C
220°C
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS
VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted.
DAC5571
PARAMETER
CONDITIONS
UNITS
MIN
TYP
MAX
STATIC PERFORMANCE(1)
Resolution
8
Bits
LSB
Relative accuracy
±0.5
±0.25
20
Differential nonlinearity
Zero code error
Assured monotonic by design
All ones loaded to DAC register
LSB
5
mV
Full-scale error
-0.15
-1.25
±1.25
% of FSR
% of FSR
µV/°C
Gain error
Zero code error drift
Gain temperature coefficient
OUTPUT CHARACTERISTICS(2)
Output voltage range
± 7
± 3
ppm of FSR/°C
0
VDD
8
V
1/4 Scale to 3/4 scale change (400H to C00H) ;
Output voltage settling time
Slew rate
6
µs
RL= ∞
1
470
1000
20
V/µs
pF
RL = ∞
RL = 2 kΩ
Capacitive load stability
pF
Code change glitch impulse
Digital feedthrough
1 LSB Change around major carry
nV-s
nV-s
Ω
0.5
1
DC output impedance
VDD = +5 V
VDD = +3 V
50
mA
mA
µs
Short-circuit current
20
Coming out of power-down mode, VDD = +5 V
Coming out of power-down mode, VDD = +3 V
2.5
5
Power-up time
µs
LOGIC INPUTS(3)
Input current
±1
µA
V
VINL, Input low voltage
VINH, Input high voltage
Pin capacitance
VDD = +3 V
VDD = +5 V
0.3×VDD
0.7×VDD
V
3
pF
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (normal operation)
VDD = +3.6 V to +5.5 V
VDD = +2.7 V to +3.6 V
IDD (all power-down modes)
VDD = +3.6 V to +5.5 V
VDD = +2.7 V to +3.6 V
POWER EFFICIENCY
IOUT/IDD
DAC active and excluding load current
VIH = VDD and VIL = GND
155
125
200
160
µA
µA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
0.2
1
1
µA
µA
0.05
ILOAD = 2 mA, VDD = +5 V
93
%
(1) Linearity calculated using a reduced code range of 3 to 253; output unloaded.
(2) Specified by design and characterization, not production tested.
(3) Specified by design and characterization, not production tested.
3
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TIMING CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
Standard mode
MIN
TYP
MAX
UNITS
kHz
kHz
MHz
MHz
µs
fSCL
SCL Clock Frequency
100
400
3.4
1.7
Fast mode
High-speed mode, CB - 100 pF max
High-Speed mode, CB - 400 pF max
Standard mode
tBUF
Bus Free Time Between a STOP
and START Condition
4.7
1.3
4.0
600
160
4.7
1.3
160
320
4.0
600
60
Fast mode
µs
tHD; tSTA
Hold Time (Repeated) START
Condition
Standard mode
µs
Fast mode
ns
High-speed mode
ns
tLOW
LOW Period of the SCL Clock
Standard mode
µs
Fast mode
µs
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
Standard mode
ns
ns
tHIGH
HIGH Period of the SCL Clock
µs
Fast mode
ns
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
Standard mode
ns
120
4.7
600
160
250
100
10
ns
tSU; tSTA
tSU; tDAT
tHD; tDAT
Setup Time for a Repeated
START Condition
µs
Fast mode
ns
High-speed mode
ns
Data Setup Time
Data Hold Time
Standard mode
ns
Fast mode
ns
High-speed mode
ns
Standard mode
0
3.45
0.9
µs
Fast mode
0
µs
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
Standard mode
0
70
ns
0
150
1000
300
40
ns
tRCL
tRCL1
tFCL
Rise Time of SCL Signal
ns
Fast mode
20 + 0.1CB
ns
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
Standard mode
10
20
ns
80
ns
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge BIT
1000
300
80
ns
Fast mode
20 + 0.1CB
ns
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
Standard mode
10
20
ns
160
300
300
40
ns
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
ns
Fast mode
20 + 0.1CB
ns
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
Standard mode
10
20
ns
80
ns
tRDA
1000
300
80
ns
Fast mode
20 + 0.1CB
ns
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
Standard mode
10
20
ns
160
300
300
80
ns
tFDA
ns
Fast mode
20 + 0.1CB
ns
High-speed mode, CB - 100 pF max
High-speed mode, CB - 400 pF max
10
20
ns
160
ns
4
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TIMING CHARACTERISTICS (continued)
SYMBOL
PARAMETER
TEST CONDITIONS
Standard mode
Fast mode
MIN
4.0
TYP
MAX
UNITS
µs
tSU; tSTO
Setup Time for STOP Condition
600
160
ns
High-speed mode
ns
CB
tSP
Capacitive Load for SDA and SCL
Pulse Width of Spike Suppressed
400
50
pF
ns
Fast mode
High-speed mode
Standard mode
Fast mode
10
ns
VNH
Noise Margin at the HIGH Level
for Each Connected Device
(Including Hysteresis)
0.2VDD
0.1VDD
V
High-speed mode
Standard mode
Fast mode
VNL
Noise Margin at the LOW Level for
Each Connected Device
V
(Including Hysteresis)
High-speed mode
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (-40°C)
CODE (+25°C )
0.5
0.5
0.4
0.3
V
= 5 V at 25°C
0.4
0.3
0.2
0.1
DD
V
= 5 V at −40°C
DD
0.2
0.1
0
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.1
−0.2
−0.3
−0.4
−0.5
0.25
0.2
0.25
0.2
0.15
0.15
0.1
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
−0.25
0.05
0
−0.05
−0.1
−0.15
−0.2
−0.25
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
Digital Input Code
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR AND
ABSOLUTE ERROR
DIFFERENTIAL LINEARITY ERROR
vs
CODE (+105°C)
16
8
0.5
0.4
0.3
V
= 5 V, T = 25°C
A
V
= 5 V at 105°C
DD
DD
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
0.25
0.2
0.15
0.1
0.05
0
−8
−0.05
−0.1
−0.15
−0.2
−16
−0.25
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
Digital Input Code
Digital Input Code
Figure 3.
Figure 4.
5
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
ZERO-SCALE ERROR
vs
FULL-SCALE ERROR
vs
TEMPERATURE
TEMPERATURE
30
30
20
10
V
= 5 V
V
= 5 V
DD
DD
20
10
0
0
−10
−10
−20
−30
−20
−30
−50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110
−50 −40 −30 −20 −10
0
10 20 30 40 50 60 70 80 90 100 110
T − Temperature − _C
T − Temperature − _C
Figure 5.
Figure 6.
IDD HISTOGRAM
SOURCE AND SINK CURRENT CAPABILITY
2500
2000
1500
1000
500
5
4
3
2
1
0
V
= 5 V
DD
DAC Loaded with FFH
DAC Loaded with 00H
0
0
5
10
15
I
− Supply Current − mA
DD
ISOURCE/SINK (mA)
Figure 7.
Figure 8.
SUPPLY CURRENT
SUPPLY CURRENT
vs
TEMPERATURE
vs
CODE
500
400
300
200
100
300
250
200
150
100
V
= 5 V
V
= 5 V
DD
DD
50
0
0
0
2
32
64
96
128 160 192 224 252 255
−50 −40−30 −20−10 0 10 20 30 40 50 60 70 80 90 100 110
T − Temperature − _C
Code
Figure 9.
Figure 10.
6
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs
SUPPLY VOLTAGE
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
+105°C
–40°C
0
+25°C
2.7
3.2
3.7
4.2
4.7
5.2
5.7
V
− Supply Voltage − V
DD
2.7
3.2
3.7
4.2
4.7
5.2
5.7
VDD (V)
Figure 11.
Figure 12.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME
CLK (5V/div)
2500
2000
1500
1000
500
VOUT (1V/div)
Full−Scale Code Change
00H to FFH
Output Loaded with
2kΩ and 200pF to GND
0
µ
Time (1 s/div)
0
1
2
3
4
5
VLOGIC (V)
Figure 13.
Figure 14.
7
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
FULL-SCALE SETTLING TIME
HALF-SCALE SETTLING TIME
CLK (5V/div)
CLK (5V/div)
VOUT (1V/div)
Half−Scale Code Change
40 H to C0H
Full−Scale Code Change
FFH to 00H
Output Loaded with
Output Loaded with
2kΩ and 200 pF to GND
2kΩ and 200pF to GND
VOUT (1V/div)
Time (1µs/div)
Time (1µs/div)
Figure 15.
Figure 16.
POWER-ON RESET TO 0V
HALF-SCALE SETTLING TIME
CLK (5V/div)
Half−Scale Code Change
C0 H to 40 H
Loaded with 2kΩ to VDD
.
Output Loaded with
2kΩ and 200pF to GND
VDD (1V/div)
VO U T (1V/div)
VOUT (1V/div)
Time (1 µs/div)
1m
Time (20µs/div)
Figure 18.
Figure 17.
EXITING POWER DOWN
(80HLoaded)
CODE CHANGE GLITCH
Loaded with 2kΩ
and 200pF to GND.
Code C hange:
80 H t o 7 FH
CLK (5V/div)
VOUT (1V/div)
Time (0.5 µs/div)
Time (5µs/div)
Figure 19.
Figure 20.
8
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: VDD = +2.7 V
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
DIFFERENTIAL LINEARITY ERROR
vs
CODE (-40°C)
CODE (+25°C)
0.5
0.4
0.5
0.4
V
= 2.7 V at 25°C
V
= 2.7 V at −40°C
DD
DD
0.3
0.3
0.2
0.2
0.1
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
−0.1
−0.2
−0.3
−0.4
−0.5
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
−0.25
0.05
0
−0.05
−0.1
−0.15
−0.2
−0.25
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
Digital Input Code
Digital Input Code
Figure 21.
Figure 22.
LINEARITY ERROR AND
ABSOLUTE ERRORS
DIFFERENTIAL LINEARITY ERROR
vs
CODE (+105°C)
0.5
0.4
16
8
V
= 2.7 V at 105°C
DD
V
= 2.7 V T = 25°C
A
0.3
DD
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
0.25
0.2
0.15
0.1
0.05
0
−8
−0.05
−0.1
−0.15
−0.2
−0.25
−16
0
32
64
96
128
160
192
224
256
32
64
96
128
160
192
224
256
0
Digital Input Code
Digital Input Code
Figure 23.
Figure 24.
ZERO-SCALE ERROR
vs
FULL-SCALE ERROR
vs
TEMPERATURE
TEMPERATURE
30
20
30
20
10
V
= 5 V
= 2.7 V
V
= 2.7 V
DD
V
DD
10
0
0
−10
−10
−20
−20
−30
−30
−50
−30
−10
10
30
50
70
90
110
−50 −30 −10 10
30
50
70
90
110
T − Temperature − _C
T − Temperature − _C
Figure 25.
Figure 26.
9
DAC5571
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SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
IDD HISTOGRAM
SOURCE AND SINK CURRENT CAPABILITY
3
2
1
0
2500
V
= 2.7 V
DD
VD D = +3V
2000
1500
1000
500
0
DAC Loaded with FFH
DAC Loaded with 00H
0
5
10
15
I
− Supply Current − mA
DD
ISO U R C E /S IN K (mA)
Figure 27.
Figure 28.
SUPPLY CURRENT
SUPPLY CURRENT
vs
TEMPERATURE
vs
CODE
300
250
200
150
100
50
500
400
300
V
= 2.7 V
DD
V
= 2.7 V
DD
200
100
0
0
0
2
32
64
96
128 160 192 224 252 255
Code
−50
−30
−10
10
30
50
70
90
110
T − Temperature − _C
Figure 29.
Figure 30.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
FULL SCALE SETTLING TIME
2500
CLK (2.7V/div)
2000
1500
1000
500
0
Full−Scale Code Change
00H to FFH
Output Loaded with
2 kΩ and 200pF to GND
VO U T (1V/div)
Time (1µs/div)
0
1
2
3
4
5
VLOGIC (V)
Figure 31.
Figure 32.
10
DAC5571
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SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
FULL-SCALE SETTLING TIME
HALF-SCALE SETTLING TIME
CLK (2.7V/div)
CLK (2.7V/div)
Full−Scale Code Change
VOUT (1V/div)
FFH to 00H
Half−Scale Code Change
40H to C0H
Output Loaded with
Output Loaded with
2kΩ and 200pF to GND
VOUT (1V/div)
Ω
pF
and 200 to GND
2 k
ms
Time (1 /div)
Time (1µs/div)
Figure 33.
Figure 34.
HALF-SCALE SETTLING TIME
POWER-ON RESET 0 V
CLK (2.7V/div)
Half−Scale Code Change
C0H to 40 H
Output Loaded with
2kΩ and 200pF to GND
VO U T (1V/div)
Tim e (1µs/div)
Time (20µs/div)
Figure 35.
Figure 36.
EXITING-POWER DOWN (80HLoaded)
CODE CHANGE GLITCH
W
Loaded with 2k
CLK (2.7V/div)
and 200pF to GND.
Code Change:
8 0H to 7FH
.
VOUT (1V/div)
Time (0.5 s/div)
Time (5µs/div)
Figure 37.
Figure 38.
11
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
THEORY OF OPERATION
D/A SECTION
The architecture of the DAC5571 consists of a string DAC followed by an output buffer amplifier. Figure 39
shows a block diagram of the DAC architecture.
V
DD
REF (+)
Resistor
String
DAC Register
V
OUT
Output
REF (-)
Amplifier
GND
Figure 39. R-String DAC Architecture
The input coding to the DAC5571 is unsigned binary, which gives the ideal output voltage as:
D
V
+ V
DD
OUT
256
where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255.
RESISTOR STRING
The resistor string section is shown in Figure 40. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
To Output
Amplifier
V
DD
GND
R
R
R
R
Figure 40. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, which
gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The
source and sink capabilities of the output amplifier can be seen in the typical characteristics curves. The slew
rate is 1 V/µs with a half-scale settling time of 7 µs with the output unloaded.
I2C Interface
I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
The DAC5571 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
12
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
THEORY OF OPERATION (continued)
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
HS-mode. The DAC5571 supports 7-bit addressing; 10-bit addressing and general call address are not
supported.
F/S-Mode Protocol
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I2C-compatible devices should
recognize a start condition.
•
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 43) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
•
•
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. On the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
HS-Mode Protocol
•
•
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the
HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps
operation.
•
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions should be used to secure the bus in HS-mode.
SDA
SCL
SDA
SCL
S
P
Start
Stop
Condition
Condition
Figure 41. START and STOP Conditions
13
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
THEORY OF OPERATION (continued)
SDA
SCL
Data Line
Change of Data Allowed
Stable;
Data Valid
Figure 42. Bit Transfer on the I2C Bus
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
8
SCL From
Master
1
2
9
S
Clock Pulse for
START
Acknowledgement
Condition
Figure 43. Acknowledge on the I2C Bus
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
MSB
Acknowledgement
Signal From Slave
Sr
Address
R/W
SCL
1
2
7
8
9
1
2
3 - 8
9
S
or
Sr
Sr
or
P
ACK
ACK
Clock Line Held Low While
Interrupts are Serviced
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Figure 44. Bus Protocol
14
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
THEORY OF OPERATION (continued)
DAC5571 I2C Update Sequence
The DAC5571 requires a start condition, a valid I2C address, a control-MSB byte, and an LSB byte for a single
update. After the receipt of each byte, DAC5571 acknowledges by pulling the SDA line low during the high period
of a single clock pulse. A valid I2C address selects the DAC5571. The CTRL/MSB byte sets the operational
mode of the DAC5571, and the four most significant bits. The DAC5571 then receives the LSB byte containing
four least significant data bits followed by four don't care bits. DAC5571 performs an update on the falling edge
of the acknowledge signal that follows the LSB byte.
For the first update, DAC5571 requires a start condition, a valid I2C address, a CTRL/MSB byte, an LSB byte.
For all consecutive updates, DAC5571 needs a CTRL/MSB byte, and an LSB byte.
Using the I2C high-speed mode (fscl= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than
the first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte,
acknowledge signal), at 188.88 KSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum
DAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC5571 releases the I2C bus and
awaits a new start condition.
Address Byte
MSB
LSB
1
0
0
1
1
0
A0
0
The address byte is the first byte received following the START condition from the master device. The first six
bits (MSBs) of the address are factory preset to 100110. The next bit of the address is the device select bit A0.
The A0 address input can be connected to VDD or digital GND, or can be actively driven by TTL/CMOS logic
levels. The device address is set by the state of this pin during the power-up sequence of the DAC5571. Up to
two devices (DAC5571) can be connected to the same I2C-Bus without requiring additional glue logic.
Broadcast Address Byte
MSB
LSB
1
0
0
1
0
0
0
0
Broadcast addressing is also supported by DAC5571. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC5571 devices. Using the broadcast address, DAC5571 responds
regardless of the state of the address pin A0.
Control - Most Significant Byte
Most Significant Byte CTRL/MSB[7:0] consists of two zeros, two power-down bits, and four most significant bits
of 8-bit unsigned binary D/A conversion data.
Least Significant Byte
Least Significant Byte LSB[7:0] consists of the four least significant bits of the 8-bit unsigned binary D/A
conversion data, followed by four don't care bits. DAC5571 updates at the falling edge of the acknowledge signal
that follows the LSB[0] bit.
15
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
Standard- and Fast-Mode:
S
SLAVE ADDRESS R/W
A
Ctrl/MS-Byte
A
LS-Byte A/A
P
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
”0” (write)
2
From Master to DAC5571
From DAC5571 to Master
DAC5571 I C-SLAVE ADDRESS:
MSB
LSB
1
0
0
1
1
0
A0 R/W
A = Acknowledge (SDA LOW)
A = Not Acknowledge (SDA HIGH)
S = START Condition
’0’ = Write to DAC5571
2
Factory Preset
Sr = Repeated START Condition
P = STOP Condition
A0 = I C Address Pin
High-Speed Mode (HS Mode):
F/S-Mode
HS Mode
Ctrl/MS-Byte
F/S Mode
S
HS-Master Code
A
Sr Slave Address R/W
A
A
LS-Byte A/A
P
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
”0” (write)
HS Mode Continues
Sr Slave Address
HS-Mode Master Code:
MSB
LSB
0
0
0
0
1
X
X
R/W
Ctrl/MS-Byte:
LS-Byte:
MSB
LSB
D4
MSB
LSB
X
0
0
PD1 PD0 D7
D6
D5
D3
D2
D1
D0
X
X
X
D7 − D0 = Data Bits
Figure 45. Master Transmitter Addressing DAC5571 as a Slave Receiver With a 7-Bit Address
16
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
POWER-ON RESET
The DAC5571 contains a power-on reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid
write sequence is made to the DAC. This is useful in applications where it is important to know the state of the
DAC output while it is in the process of powering up.
POWER-DOWN MODES
The DAC5571 contains four separate modes of operation. These modes are programmable via two bits (PD1
and PD0). Table 1 shows how the state of these bits correspond to the mode of operation.
Table 1. Modes of Operation for the DAC5571
PD1
PD0
OPERATING MODE
Normal Operation
0
0
1
1
0
1
0
1
1k Ω to AGND, PWD
100 kΩ to AGND, PWD
High Impedance, PWD
When both bits are set to zero, the device works normally with normal power consumption of 150 µA at 5 V.
However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall but the output stage is also internally switched from the output of the amplifier to a
resistor network of known values. This has the advantage that the output impedance of the device is known while
in power-down mode. There are three different options: The output is connected internally to AGND through a
1-kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (high impedance). The output stage is illustrated in
Figure 46.
Amplifier
Resistor
V
OUT
String DAC
Power-Down
Circuitry
Resistor
Network
Figure 46. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power down. The time required to exit power down is typically 2.5 µs for AVDD
5 V and 5 µs for AVDD = 3 V. See the Typical Characteristics section for more information.
=
CURRENT CONSUMPTION
The DAC5571 typically consumes 150 µA at VDD = 5 V and 120 µA at VDD = 3 V. Additional current consumption
can occur due to the digital inputs if VIH << VDD. For most efficient power operation, CMOS logic levels are
recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200 nA.
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC5571 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC5571 can operate rail-to-rail when driving a capacitive load. When the outputs of
the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output
stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity
performance of the DAC. This may occur within approximately the top 20 mV of the DAC's digital input-to-voltage
output transfer characteristic.
17
DAC5571
www.ti.com
SLAS405A–DECEMBER 2003–REVISED AUGUST 2005
OUTPUT VOLTAGE STABILITY
The DAC5571 exhibits excellent temperature stability of 5 ppm/ °C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage to stay within a ±25-µV window for a ±1°C
ambient temperature change. Combined with good dc noise performance and true 8-bit differential linearity, the
DAC5571 becomes a perfect choice for closed-loop control applications.
APPLICATIONS
USING REF02 AS A POWER SUPPLY FOR THE DAC5571
Due to the extremely low supply current required by the DAC5571, a possible configuration is to use a REF02
+5-V precision voltage reference to supply the required voltage to the DAC5571's supply input as well as the
reference input, as shown in Figure 47. This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC5571.
If the REF02 is used, the current it needs to supply to the DAC5571 is 140 µA typical. When a DAC output is
loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5-mW
load on a given DAC output) is: 140 µA + (5 mW/5 V) = 1.14 mA.
The load regulation of the REF02 is typically (0.005%×VDD)/mA, which results in an error of 0.285 mV for the
1.14-mA current drawn from it. This corresponds to a 0.015 LSB error for a 0-V to 5-V output range.
15 V
5 V
REF02
1.14 mA
A0
SCL
SDA
V
OUT
= 0 V to 5 V
2
I C
DAC5571
Interface
Figure 47. REF02 as Power Supply to DAC5571
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The power applied to VDD should be well regulated and low noise. Switching power supplies and dc/dc
converters often has high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, VDD should be connected to a +5-V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. In addition, the 1-µF to
10-µF and 0.1-µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be
required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all
designed to essentially low-pass filter the +5-V supply, removing the high-frequency noise.
18
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2006
PACKAGING INFORMATION
Orderable Device
DAC5571IDBVR
DAC5571IDBVRG4
DAC5571IDBVT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DAC5571IDBVTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
177
(mm)
DAC5571IDBVR
DAC5571IDBVT
DBV
DBV
6
6
SITE 60
SITE 60
9
9
3.2
3.2
3.1
3.1
1.39
1.39
4
4
8
8
Q3
Q3
177
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
DAC5571IDBVR
DAC5571IDBVT
DBV
DBV
6
6
SITE 60
SITE 60
0.0
0.0
0.0
0.0
0.0
0.0
Pack Materials-Page 2
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