DAC5652-EP [TI]
DUAL 10-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER; 双通道10位200 MSPS数位类比转换器
| 型号： | DAC5652-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 10-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总27页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC5652-EP
www.ti.com
SGLS341B–JUNE 2006–REVISED OCTOBER 2006
DUAL 10-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
High Third-Order Two-Tone Intermodulation
(IMD3): 78 dBc at 15.1 MHz and 16.1 MHz
•
Controlled Baseline
•
•
•
•
•
•
Independent or Single Resistor Gain Control
Dual or Interleaved Data
– One Assembly
– One Test Site
On-Chip 1.2-V Reference
– One Fabrication Site
Low Power: 290 mW
•
•
Extended Temperature Performance of
–55°C to 125°C
Power-Down Mode: 9 mW
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Package: 48-Pin Thin Quad Flat Pack (TQFP)
APPLICATIONS
•
•
•
Enhanced Product-Change Notification
•
Cellular Base Transceiver Station Transmit
Channel
(1)
Qualification Pedigree
10-Bit Dual Transmit Digital-to-Analog
Converter (DAC)
– CDMA: W-CDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE/UWC-136
Medical/Test Instrumentation
Arbitrary Waveform Generators (ARB)
Direct Digital Synthesis (DDS)
•
•
•
200-MSPS Update Rate
•
•
•
•
Single Supply: 3 V to 3.6 V
High Spurious-Free Dynamic Range (SFDR):
80 dBc at 5 MHz
Cable Modem Termination System (CMTS)
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION
The DAC5652 is a monolithic, dual-channel, 10-bit, high-speed digital-to-analog converter (DAC) with on-chip
voltage reference.
Operating with update rates of up to 200 MSPS, the DAC5652 offers exceptional dynamic performance, tight
gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF communication
applications.
Each DAC has a high-impedance differential-current output, suitable for single-ended or differential
analog-output configurations. External resistors allow scaling of the full-scale output current for each DAC
separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is
temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may
be used.
The DAC5652 has two 10-bit parallel input ports with separate clocks and data latches. For flexibility, the
DAC5652 also supports multiplexed data for each DAC on one port when operating in the interleaved mode.
The DAC5652 has been specifically designed for a differential transformer-coupled output with a 50-Ω
doubly-terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output
power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC5652-EP
www.ti.com
SGLS341B–JUNE 2006–REVISED OCTOBER 2006
DESCRIPTION (CONTINUED)
The DAC5652 is available in a 48-pin thin quad flat pack (TQFP). Pin compatibility between family members
provides 10-bit (DAC5652), 12-bit (DAC5662), and 14-bit (DAC5672) resolution. Furthermore, the DAC5652 is
pin compatible to the DAC2900 and AD9763 dual DACs. The device is characterized for operation over the
military temperature range of –55°C to 125°C.
FUNCTIONAL BLOCK DIAGRAM
WRTB
WRTA
CLKB CLKA
DE-
MUX
IOUTA1
IOUTA2
Latch A
10−b DAC
DA[9:0]
DB[9:0]
BIASJ_A
IOUTB1
IOUTB2
Latch B
10−b DAC
MODE
GSET
BIASJ_B
1.2 V Reference
EXTIO
SLEEP
DVDD
DGND
AVDD
AGND
AVAILABLE OPTIONS
PACKAGED DEVICES
48-PIN TQFP
TA
DAC5652MPFBREP
DAC5652MPFBEP
–55°C to 125°C
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SGLS341B–JUNE 2006–REVISED OCTOBER 2006
DEVICE INFORMATION
48 47 46 45 44 43 42 41 40 39 38 37
DA9 (MSB)
DA8
NC
36
1
2
3
4
5
6
7
8
9
NC
35
34
33
32
31
30
29
28
27
26
25
DA7
NC
DA6
NC
DA5
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Top View
48-Pin TQFP
PFB Package
DA4
DA3
DA2
DA1
DA0 (LSB) 10
NC 11
12
NC
13 14 15 16 17 18 19 20 21 22 23 24
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
38
I
I
Analog ground
AVDD
47
Analog supply voltage
BIASJ_A
BIASJ_B
CLKA/CLKIQ
44
O
O
I
Full-scale output current bias for DACA
Full-scale output current bias for DACB
41
18
Clock input for DACA, CLKIQ in interleaved mode
Clock input for DACB, RESETIQ in interleaved mode
Data port A. DA9 is MSB and DA0 is LSB.
CLKB/RESETIQ
DA[9:0]
DB[9:0]
DGND
19
I
1–10
I
23–32
I
Data port B. DB9 is MSB and DB0 is LSB.
15, 21
I
Digital ground
DVDD
16, 22
I
Digital supply voltage
EXTIO
43
I/O
I
Internal reference output (bypass with 0.1 µF to AGND) or external reference input
Gain-setting mode: H = 1 resistor, L = 2 resistors. Internal pullup.
DACA current output. Full scale with all bits of DA high.
DACA complementary current output. Full scale with all bits of DA low.
DACB current output. Full scale with all bits of DB high.
DACB complementary current output. Full scale with all bits of DB low.
Mode select: H – dual bus, L – interleaved. Internal pullup.
Factory use only. Pins must be connected to DGND or left unconnected.
GSET
42
IOUTA1
IOUTA2
IOUTB1
IOUTB2
MODE
46
O
O
O
O
I
45
39
40
48
NC
11–14, 33–36
Sleep function control input: H = DAC in power-down mode, L = DAC in operating mode.
Internal pulldown.
SLEEP
37
I
WRTA/WRTIQ
17
20
I
I
Input write signal for PORT A (WRTIQ in interleaving mode)
Input write signal for PORT B (SELECTIQ in interleaving mode)
WRTB/SELECTIQ
3
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SGLS341B–JUNE 2006–REVISED OCTOBER 2006
PFB PACKAGE THERMAL CHARACTERISTICS
PARAMETER
Thermal resistance, junction to ambient
Thermal resistance, junction to case
POWERPAD CONNECTED TO PCB THERMAL PLANE
63.7°C/W
19.6°C/W
1000
Wirebond Voiding Fail Mode
100
10
Electromigration Fail Mode
1
0.1
100
110
120
130
Continuous T − 5C
140
150
160
J
Figure 1. DAC5652MPFB Operating Life Derating Chart
4
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SGLS341B–JUNE 2006–REVISED OCTOBER 2006
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
–0.5 V to 4 V
–0.5 V to 4 V
–0.5 V to 0.5 V
–0.5 V to 0.5 V
–0.5 V to DVDD + 0.5 V
–0.5 V to DVDD + 0.5 V
–1 V to AVDD + 0.5 V
–0.5 V to AVDD + 0.5 V
20 mA
AVDD(2)
Supply voltage range
DVDD(3)
Voltage between AGND and DGND
Voltage between AVDD and DVDD
DA[9:0] and DB[9:0](3)
MODE, CLKA, CLKB, WRTA, WRTB(3)
IOUTA1, IOUTA2, IOUTB1, IOUTB2(2)
EXTIO, BIASJ_A, BIASJ_B, SLEEP(2)
Supply voltage range
Peak input current (any input)
Peak total input current (all inputs)
Operating free-air temperature range
Storage temperature range
Lead temperature
–30 mA
–55°C to 125°C
–65°C to 150°C
260°C
1,6 mm (1/16 in) from the case for 10 s
(4)
Junction temperature, TJ
105°C
Still air
150 lfm
19.88°C/W
(5)
Junction-to-ambient temperature, θJA
Junction-to-case temperature, θJC
14.37°C/W
0.12°C/W
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND
(3) Measured with respect to DGND
(4) Airflow or heatsinking required for sustained operation at 85°C and maximum operating conditions to maintain junction temperature.
(5) Airflow or heatsinking reduces θJA and is highly recommended.
5
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SGLS341B–JUNE 2006–REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode
(unless otherwise noted)
PARAMETER
DC Specifications
Resolution
DC Accuracy(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
Bits
INL
Integral nonlinearity
Differential nonlinearity
1 LSB = IOUTFS/210, TMIN to TMAX
1 LSB = IOUTFS/210, TMIN to TMAX
–1 ±0.25
1
LSB
LSB
DNL
–0.5 ±0.16
0.5
Analog Output
Offset error
Mid-scale value (internal reference)
Mid-scale value (internal reference)
With internal reference
±0.05
±0.03
±0.75
2
%FSR
%FSR
%FSR
mA
Offset mismatch
Gain error
Minimum full-scale output current(2)
Maximum full-scale output current(2)
Gain mismatch
20
mA
With internal reference
–2
0.2
2
%FSR
V
Output voltage compliance range(3)
–0.8
1.25
RO
CO
Output resistance
300
5
kΩ
Output capacitance
pF
Reference Output
Reference voltage
Reference output current(4)
Reference Input
1.14
0.1
1.2
1.26
1.25
V
100
nA
VEXTIO
RI
Input voltage
V
Input resistance
Small signal bandwidth
Input capacitance
1
300
100
MΩ
kHz
pF
CI
Temperature Coefficients
Offset drift
2
±20
±40
±20
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
With external reference
With internal reference
Gain drift
Reference voltage drift
(1) Measured differentially through 50 Ω to AGND.
(2) Nominal full-scale current, IOUTFS, equals 32× the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5652 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(4) Use an external buffer amplifier with high-impedance input to drive any external load.
6
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SGLS341B–JUNE 2006–REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz,
independent gain set mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
AVDD
DVDD
Analog supply voltage
Digital supply voltage
3
3
3.3
3.3
3.6
3.6
90
V
V
Including output current through load resistor
Sleep mode with clock
75
IAVDD
Supply current, analog
Supply current, digital
2.5
mA
mA
Sleep mode without clock
2.5
12
20
18
IDVDD
Sleep mode with clock
11.3
0.6
Sleep mode without clock
290
45.5
9.2
360
Sleep mode with clock
Power dissipation
mW
Sleep mode without clock
fDATA = 200 MSPS, fOUT = 20 MHz
310
–0.01
0
APSRR
DPSRR
TA
Analog power-supply rejection ratio
Digital power-supply rejection ratio
Operating free-air temperature
–0.2
–0.2
–55
0.2 %FSR/V
0.2 %FSR/V
125
°C
7
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SGLS341B–JUNE 2006–REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS
AC specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set
mode, differential 1:1 impedance ratio transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
Analog Output
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
Maximum output update rate
200
275(1)
20
MSPS
ns
Output settling time to 0.1%
(DAC)
ts
Mid-scale transition
Output rise time 10% to 90%
(OUT)
tr
tf
1.4
1.5
ns
ns
Output fall time 90% to 10%
(OUT)
IOUTFS = 20 mA
IOUTFS = 2 mA
55
30
Output noise
pA/√Hz
AC Linearity
1st Nyquist zone, TA = 25°C,
fDATA = 50 MSPS, fOUT = 1 MHz, IOUTFS = 0 dB
79
78
73
80
76
70
67
67
63
62
61
78
1st Nyquist zone, TA = 25°C,
fDATA = 50 MSPS, fOUT = 1 MHz, IOUTFS = –6 dB
1st Nyquist zone, TA = 25°C,
fDATA = 50 MSPS, fOUT = 1 MHz, IOUTFS = –12 dB
1st Nyquist zone, TA = 25°C,
fDATA = 100 MSPS, fOUT = 5 MHz, IOUTFS = 0 dB
SFDR
Spurious-free dynamic range
dBc
1st Nyquist zone, TA = 25°C,
fDATA = 100 MSPS, fOUT = 20 MHz, IOUTFS = 0 dB
1st Nyquist zone, TA = 25°C,
fDATA = 200 MSPS, fOUT = 20 MHz, IOUTFS = 0 dB
61
58
1st Nyquist zone, TA = –55°C to 125°C,
fDATA = 200 MSPS, fOUT = 20 MHz, IOUTFS = 0 dB
1st Nyquist zone, TA = 25°C,
fDATA = 200 MSPS, fOUT = 41 MHz, IOUTFS = 0 dB
1st Nyquist zone, TA = 25°C,
fDATA = 100 MSPS, fOUT = 5 MHz, IOUTFS = 0 dB
SNR
Signal-to-noise ratio
dB
1st Nyquist zone, TA = 25°C,
fDATA = 160 MSPS, fOUT = 20 MHz, IOUTFS = 0 dB
Each tone at –6 dBFS, TA = 25°C,
fDATA = 200 MSPS, fOUT = 45.4 MHz and 46.4 MHz
Third-order two-tone
intermodulation
IMD3
dBc
Each tone at –6 dBFS, TA = 25°C,
fDATA = 100 MSPS, fOUT = 15.1 MHz and 16.1 MHz
Each tone at –12 dBFS, TA = 25°C,
fDATA = 100 MSPS,
fOUT = 15.6, 15.8, 16.2, and 16.4 MHz
76
55
Each tone at –12 dBFS, TA = 25°C,
fDATA = 165 MSPS,
IMD
Four-tone intermodulation
Channel isolation
dBc
dBc
fOUT = 19, 19.1, 19.3, and 19.4 MHz
Each tone at –12 dBFS, TA = 25°C,
fDATA = 165 MSPS,
fOUT = 68.8, 69.6, 71.2, and 72 MHz
70
90
TA = 25°C, fDATA = 165 MSPS,
fOUT (CH1) = 20 MHz, fOUT (CH2) = 21 MHz
(1) Specified by design. Not production tested.
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SGLS341B–JUNE 2006–REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA
(unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Digital Input
VIH
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
2
0
3.3
0.8
V
VIL
V
IIH
±50
±10
7
µA
µA
µA
µA
µA
µA
pF
IIL
IIH(GSET)
IIL(GSET)
IIH(MODE)
IIL(MODE)
CI
High-level input current, GSET pin
Low-level input current, GSET pin
High-level input current, MODE pin
Low-level input current, MODE pin
Input capacitance
–80
–30
–80
5
SWITCHING CHARACTERISTICS
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA
(unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
Timing – Dual Bus Mode
tsu
Input setup time
1
1
ns
ns
ns
th
Input hold time
tLPH
tLAT
tPD
Input clock pulse high time
Clock latency (WRTA/B to outputs)(1)
1
4
4
4
clk
ns
Propagation delay time
1.5
Timing – Single Bus Interleaved Mode
tsu
Input setup time
0.5
0.5
ns
ns
clk
ns
th
Input hold time
Clock latency (WRTA/B to outputs)(1)
tLAT
tPD
4
Propagation delay time
1.5
(1) Specified by design
9
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TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
INPUT CODE
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
100
200
300
400
500
600
700
800
900
1000
Input Code
G001
Figure 2.
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
0.25
0.20
0.15
0.10
0.05
0.00
−0.05
−0.10
−0.15
−0.20
−0.25
0
100
200
300
400
500
600
700
800
900
1000
Input Code
G002
Figure 3.
10
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TYPICAL CHARACTERISTICS (continued)
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
100
100
95
90
85
80
75
70
65
60
f
= 52 MSPS
f
= 78 MSPS
data
data
95
90
85
80
75
70
65
60
Dual Bus Mode
Dual Bus Mode
−6 dBf
S
−6 dBf
S
0 dBf
S
−12 dBf
−12 dBf
S
S
0 dBf
25
S
0
4
8
12
16
20
0
5
10
15
20
30
f
out
− Output Frequency − MHz
f
out
− Output Frequency − MHz
G003
G004
Figure 4.
Figure 5.
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
f
= 100 MSPS
f
= 165 MSPS
data
data
Dual Bus Mode
Dual Bus Mode
−6 dBf
S
0 dBf
0 dBf
S
S
−6 dBf
S
−12 dBf
S
−12 dBf
S
0
5
10
15
20
25
30
35
0
5
10 15 20 25 30 35 40 45 50 55 60
f
out
− Output Frequency − MHz
f
out
− Output Frequency − MHz
G005
G006
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
SINGLE-TONE SPECTRUM
SINGLE-TONE SPECTRUM
0
−20
0
−20
f
f
= 78 MSPS
= 15 MHz
f
f
= 165 MSPS
= 30.1 MHz
data
data
OUT
OUT
Dual Bus Mode
Dual Bus Mode
−40
−40
−60
−60
−80
−80
−100
−100
0.0
7.8
15.6
23.4
31.2
39.0
0.0
16.5
33.0
49.5
66.0
82.5
f − Frequency − MHz
f − Frequency − MHz
G007
G008
Figure 8.
Figure 9.
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
50
f
= 78 MSPS
f
= 165 MSPS
data
data
Dual Bus Mode
Dual Bus Mode
f
= f
out1
+ 1 MHz
f
= f
out1
+ 1 MHz
out2
out2
0
5
10
15
20
25
30
35
0
10
20
30
40
50
f
− Output Frequency − MHz
f
− Output Frequency − MHz
out1
out1
G009
G010
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
TWO-TONE SPECTRUM
TWO-TONE SPECTRUM
f
f
f
= 165 MSPS
= 30.1 MHz
= 31.1 MHz
f
= 78 MSPS
= 20.1 MHz
= 21.1 MHz
data
out1
out2
data
−10
−30
−10
−30
f
f
out1
out2
Dual Bus Mode
Dual Bus Mode
−50
−50
−70
−70
−90
−90
−110
−110
19.0
19.5
20.0
20.5
21.0
21.5
22.0
29.0
29.5
30.0
30.5
31.0
31.5
32.0
f − Frequency − MHz
f − Frequency − MHz
G011
G012
Figure 12.
Figure 13.
DIGITAL INPUTS AND TIMING
Digital Inputs
The data input ports of the DAC5652 accept a standard positive coding with data bits DA9 and DB9 being the
most significant bits (MSBs). The converter outputs are specified to support a clock rate up to 200 MSPS. The
best performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle
may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within
their specified limits.
All digital inputs of the DAC5652 are CMOS compatible. Figure 14 and Figure 15 show schematics of the
equivalent CMOS digital inputs of the DAC5652. The 10-bit digital data input follows the offset positive binary
coding scheme. The DAC5652 is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.
DVDD
DA[9:0]
DB[9:0]
Internal
SLEEP
Digital In
CLKA/B
WRTA/B
DGND
Figure 14. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
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DIGITAL INPUTS AND TIMING (continued)
DVDD
Internal
GSET
Digital In
MODE
DGND
Figure 15. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
Input Interfaces
The DAC5652 features two operating modes selected by the MODE pin (see Table 1).
•
For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own
separate data input bus, clock input, and data write signal (data latch-in).
•
In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The
B-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.
Table 1. Operating Modes
MODE PIN
BUS INPUT
MODE pin connected to DGND
MODE pin connected to DVDD
Single-bus interleaved mode, clock and write input equal for both DACs
Dual-bus mode, DACs operate independently
Dual-Bus Data Interface and Timing
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5652
consist of two independent, 10-bit, parallel data ports. Each DAC channel is controlled by its own set of write
(WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRTA/B lines control the channel input latches and the
CLKA/B lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the
WRTA/B line.
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock
domains having equal periods (but possibly different phases) are input to the DAC5652. This is defined by a
minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.
This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of
the WRTA/B signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the
rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected
externally. Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together.
14
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DIGITAL INPUTS AND TIMING (continued)
DA[9:0]/DB[9:0]
Valid Data
t
su
t
h
t
LPH
WRTA/WRTB
CLKA/CLKB
t
s
t
PD
t
LAT
IOUT
or
IOUT
Figure 16. Dual-Bus-Mode Operation
Single-Bus Interleaved Data Interface and Timing
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 17 shows the timing diagram. In
interleaved mode, the A and B channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input
latch (SELECTIQ is high) or to the B-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data
value in the B-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ
is low, the data value in the A-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the A-channel input data rate is twice the update rate of the DAC core. As in dual-bus
mode, it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch
the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the A-
and B-DAC latches on the following falling edge of the write inputs. The DAC5652 clock input is divided by a
factor of two before it is presented to the DAC latches.
Correct pairing of the A- and B-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is
divided by two, which would translate to a nondeterministic relation between the rising edges of the CLKIQ and
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ, with respect
to the data at the input of the DAC latch, is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
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DIGITAL INPUTS AND TIMING (continued)
DA[9:0]
Valid Data
t
su
t
h
SELECTIQ
WRTIQ
CLKIQ
RESETIQ
t
s
t
PD
t
LAT
IOUT
or
IOUT
Figure 17. Single-Bus Interleaved-Mode Operation
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APPLICATION INFORMATION
Theory of Operation
The architecture of the DAC5652 uses a current steering technique to enable fast switching and high update
rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to
deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output current is formed by steering all currents to either
output summing node, IOUT1 or IOUT2. The complementary outputs deliver a differential output signal, which
improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),
and double the peak-to-peak output signal swing by a factor of two, as compared to single-ended operation.
The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic
performance (SFDR) and DNL. The current outputs maintain a very high output impedance of greater
than 300 kΩ.
When pin 42 (GSET) is high (simultaneous gain set mode), the full-scale output current for both DACs is
determined by the ratio of the internal reference voltage (1.2 V) and an external resistor (RSET) connected to
BIASJ_A. When GSET is low (independent gain set mode), the full-scale output current for each DAC is
determined by the ratio of the internal reference voltage (1.2 V) and separate external resistors (RSET) connected
to BIASJ_A and BIASJ_B. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC
output current that can range from 2 mA to 20 mA, depending on the value of RSET
.
The DAC5652 is split into a digital and an analog portion, each of which is powered through its own supply pin.
The digital section includes edge-triggered input latches and the decoder logic, while the analog section
comprises both the current source array with its associated switches, and the reference circuitry.
DAC Transfer Function
Each of the DACs in the DAC5652 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale
output current, IOUTFS, is the summation of the two complementary output currents:
I
+ I
) I
OUTFS
OUT1
OUT2
(1)
The individual output currents depend on the DAC code and can be expressed as:
Code
1024
ǒ Ǔ
I
+ I
OUT1
OUTFS
(2)
(3)
1023 * Code
ǒ
Ǔ
I
+ I
OUT2
OUTFS
1024
where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the
reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).
V
REF
I
+ 32 I
+ 32
OUTFS
REF
R
SET
(4)
In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage
develops at each output according to:
V
+ I
R
OUT1
OUT1
LOAD
(5)
(6)
V
+ I
R
OUT2
OUT2
LOAD
The value of the load resistance is limited by the output compliance specification of the DAC5652. To maintain
specified linearity performance, the voltage for IOUT1 and IOUT2 must not exceed the maximum allowable
compliance range.
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APPLICATION INFORMATION (continued)
The total differential output voltage is:
V
+ V
* V
OUTDIFF
OUT1
OUT2
(7)
(8)
(
)
2 Code * 1023
V
+
I
R
OUTDIFF
OUTFS
LOAD
1024
Analog Outputs
The DAC5652 provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the analog
output stage representing the differential topology is shown in Figure 18. The output impedance of IOUT1 and
IOUT2 results from the parallel combination of the differential switches, along with the current sources and
associated parasitic capacitances.
AVDD
S(1)
S(1)C
S(2)
S(2)C
S(N)
S(N)C
Current Source Array
I
I
OUT2
OUT1
R
LOAD
R
LOAD
Figure 18. Analog Outputs
The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative and
positive compliance. The negative limit of –1 V is given by the breakdown voltage of the CMOS process and
exceeding it compromises the reliability of the DAC5652 (or even causes permanent damage). With the
full-scale output set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases
to about 1 V for a selected output current of IOUTFS = 2 mA. Care must be taken that the configuration of
DAC5652 does not exceed the compliance range to avoid degradation of the distortion performance and integral
linearity.
Best distortion performance is typically achieved with the maximum full-scale output signal limited to
approximately 0.5 VPP. This is the case for a 50-Ω doubly-terminated load and a 20-mA full-scale output current.
A variety of loads can be adapted to the output of the DAC5652 by selecting a suitable transformer while
maintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configuration in
combination with a transformer is instrumental for achieving excellent distortion performance. Common-mode
errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly the case with
high output frequencies.
For those applications requiring the optimum distortion and noise performance, it is recommended to select a
full-scale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require low
power consumption, but can tolerate a slight reduction in performance level.
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APPLICATION INFORMATION (continued)
Output Configurations
The current outputs of the DAC5652 allow for a variety of configurations. As mentioned previously, utilizing the
converter’s differential outputs yield the best dynamic performance. Such a differential output circuit may consist
of an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for most
applications with ac coupling, while operational amplifiers are suitable for a dc-coupled configuration.
The single-ended configuration may be considered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to ground converts the output current into a
ground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or
operational amplifier configuration may be considered.
Differential With Transformer
Using an RF transformer provides a convenient way of converting the differential output signal into a
single-ended signal while achieving excellent dynamic performance. The appropriate transformer must be
carefully selected based on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus
improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable
impedance ratio (winding ratio), the transformer can provide optimum impedance matching while controlling the
compliance voltage for the converter outputs.
Figure 19 and Figure 20 show 50-Ω doubly-terminated transformer configurations with 1:1 and 4:1 impedance
ratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable
a dc-current flow. Applying a 20-mA full-scale output current leads to a 0.5-VPP output for a 1:1 transformer and
a 1-VPP output for a 4:1 transformer. In general, the 1:1 transformer configuration has slightly better output
distortion, but the 4:1 transformer has 6-dB higher output power.
50 Ω
1:1
I
OUT1
R
LOAD
50 Ω
AGND
100 Ω
I
OUT2
50 Ω
Figure 19. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
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APPLICATION INFORMATION (continued)
100 Ω
4:1
I
OUT1
R
LOAD
50 Ω
AGND
I
OUT2
100 Ω
Figure 20. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
Single-Ended Configuration
Figure 21 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 must be connected to AGND or terminated with a resistor of 25 Ω to AGND.
The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA full-scale
output current.
I
OUT1
R
LOAD
50 Ω
I
OUT2
50 Ω
25 Ω
AGND
Figure 21. Driving a Doubly-Terminated 50-Ω Cable Using a Single-Ended Output
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APPLICATION INFORMATION (continued)
Reference Operation
Internal Reference
The DAC5652 has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two control
amplifiers, one for each DAC. The full-scale output current, IOUTFS, of the DAC5652 is determined by the
reference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by:
V
REF
I
+ 32 I
+ 32
OUTFS
REF
R
SET
(9)
The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is
determined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, IOUTFS, results from
multiplying IREF by a fixed factor of 32.
Using the internal reference, a 2-kΩ resistor value results in a full-scale output of approximately 20 mA.
Resistors with a tolerance of 1% or better should be considered. Selecting higher values, the output current can
be adjusted from 20 mA down to 2 mA. Operating the DAC5652 at lower than 20-mA output currents may be
desirable for reasons of reducing the total power consumption, improving the distortion performance, or
observing the output compliance voltage limitations for a given load condition.
It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 µF or more. The control
amplifier is internally compensated and its small signal bandwidth is approximately 300 kHz.
External Reference
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin that,
in this case, functions as an input. The use of an external reference may be considered for applications that
require higher accuracy and drift performance or to add the ability of dynamic gain control.
While a 0.1-µF capacitor is recommended to be used with the internal reference, it is optional for the external
reference operation. The reference input, EXTIO, has a high input impedance (1 MΩ) and can easily be driven
by various sources. Note that the voltage range of the external reference must stay within the compliance range
of the reference input.
Gain Setting Option
The full-scale output current on the DAC5652 can be set two ways — either for each of the two DAC channels
independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42)
must be low (that is, connected to AGND). In this mode, two external resistors are required — one RSET
connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user
has the flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the
compensation of possible gain mismatches elsewhere within the transmit signal path.
Alternatively, bringing the GSET pin high (that is, connected to AVDD), the DAC5652 switches into the
simultaneous gain set mode. Now the full-scale output current of both DAC channels is determined by only one
external RSET resistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed;
however, this is not required since this pin is not functional in this mode and the resistor has no effect on the
gain equation.
Sleep Mode
The DAC5652 features a power-down function that can reduce the total supply current to approximately 3.1 mA
over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates the
power-down mode, while a logic low enables normal operation. When left unconnected, an internal active
pulldown circuit enables the normal operation of the converter.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
DAC5652MPFBEP
DAC5652MPFBREP
V62/06638-01XE
V62/06638-02XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PFB
48
48
48
48
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TQFP
TQFP
TQFP
PFB
PFB
PFB
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5652-EP :
Catalog: DAC5652
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC5652MPFBREP
TQFP
PFB
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PFB 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
DAC5652MPFBREP
1000
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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