DAC5675AHFG/EM [TI]
QMLV、150krad、陶瓷、14 位、单通道、400MSPS DAC | HFG | 52 | 25 to 25;
| 型号： | DAC5675AHFG/EM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QMLV、150krad、陶瓷、14 位、单通道、400MSPS DAC | HFG | 52 | 25 to 25 转换器 数模转换器 |
| 文件： | 总23页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC5675A-SP
www.ti.com ..................................................................................................................................................... SGLS387D –JULY 2007–REVISED OCTOBER 2009
CLASS V, 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC5675A-SP
1
FEATURES
•
•
QML-V Qualified, SMD 5962-07204
•
•
•
400-MSPS Update Rate
Military Temperature Range (–55°C to 125°C)
LVDS-Compatible Input Interface
APPLICATIONS
•
Spurious-Free Dynamic Range (SFDR) to
Nyquist
Cellular Base Transceiver Station Transmit
Channel:
–
69 dBc at 70 MHz IF, 400 MSPS
–
–
–
CDMA: WCDMA, CDMA2000, IS-95
TDMA: GSM, IS-136, EDGE/GPRS
Supports Single-Carrier and Multicarrier
Applications
•
W-CDMA Adjacent Channel Power Ratio
(ACPR)
–
–
73 dBc at 30.72 MHz IF, 122.88 MSPS
71 dBc at 61.44 MHz IF, 245.76 MSPS
•
Test and Measurement: Arbitrary Waveform
Generation
•
Differential Scalable Current Outputs:
2 mA to 20 mA
•
•
•
On-Chip 1.2-V Reference
Single 3.3-V Supply Operation
Power Dissipation: 660 mW at
fCLK = 400 MSPS, fOUT = 20 MHz
•
High-Performance 52-Pin Ceramic Quad Flat
Pack (HFG)
DESCRIPTION/ORDERING INFORMATION
The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675A is designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct
digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has
excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well suited for
multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).
The DAC5675A operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of
20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the
load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD
.
The DAC5675A includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input.
LVDS features a low differential voltage swing with a low constant power consumption across frequency,
allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference
(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for
high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The
DAC5675A current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered
input latches provide for minimum setup and hold times, thereby relaxing interface timing.
The DAC5675A is specifically designed for
a differential transformer-coupled output with a 50-Ω
doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an
output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is
preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to
AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC5675A-SP
SGLS387D –JULY 2007–REVISED OCTOBER 2009..................................................................................................................................................... www.ti.com
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to
adjust this output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities.
Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which
reduces the standby power to approximately 18 mW.
The DAC5675A is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for
operation over the military temperature range of –55°C to 125°C.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
(2)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
5962-0720401VXC
DAC5675AMHFG-V
–55°C to 125°C
52 / HFG
5962-0720401VXC
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTIONAL BLOCK DIAGRAM
SLEEP
DAC5675A
Bandgap
Reference
1.2V
EXTIO
Current
Source
Array
Output
Current
Switches
BIASJ
Control Amp
14
14
D[13:0]A
D[13:0]B
DAC
Latch
+
LVDS
Input
Input
Decoder
Latches
Interface
Drivers
CLK
Clock Distribution
CLKC
AVDD(4x) AGND(4x)
DVDD(2x) DGND(2x)
2
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www.ti.com ..................................................................................................................................................... SGLS387D –JULY 2007–REVISED OCTOBER 2009
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
(2)
AVDD
DVDD
–0.3 to 3.6
–0.3 to 3.6
–3.6 to 3.6
–0.3 to 0.5
–0.3 to AVDD + 0.3
–0.3 to DVDD + 0.3
–1 to AVDD + 0.3
–1 to AVDD + 0.3
20
(3)
Supply voltage range
V
AVDD to DVDD
Voltage between AGND and DGND
CLK, CLKC(2)
V
V
Digital input D[13:0]A, D[13:0]B(3), SLEEP, DLLOFF
IOUT1, IOUT2(2)
V
V
EXTIO, BIASJ(2)
V
Peak input current (any input)
mA
mA
°C
°C
°C
Peak total input current (all inputs)
Operating free-air temperature range, TA
Storage temperature range
–30
–55 to 125
–65 to 150
260
Lead temperature 1,6 mm (1/16 in) from the case for 10 s
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND
(3) Measured with respect to DGND
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DC Electrical Characteristics (Unchanged after 100 kRad)
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
DC Accuracy(1)
14
Bit
INL
Integral nonlinearity
Differential nonlinearity
TMIN to TMAX
T25C to TMAX
TMIN
–4
–2
–2
±1.5
±0.6
±0.6
4.6
2.2
2.5
LSB
LSB
DNL
Monotonicity
Monotonic 12b Level
Analog Output
IO(FS) Full-scale output current
2
20
mA
V
AVDD = 3.15 V to 3.45 V,
IO(FS) = 20 mA
Output compliance range
Offset error
AVDD – 1
AVDD + 0.3
0.01
5
%FSR
Without internal reference
With internal reference
–10
–10
10
10
Gain error
%FSR
2.5
300
5
Output resistance
Output capacitance
kΩ
pF
Reference Output
V(EXTIO) Reference voltage
Reference output current(2)
Reference Input
V(EXTIO) Input reference voltage
1.17
0.6
1.23
100
1.30
1.25
V
nA
1.2
1
V
Input resistance
MΩ
MHz
pF
Small-signal bandwidth
Input capacitance
1.4
100
Temperature Coefficients
Offset drift
12
ppm of FSR/°C
ppm/°C
ΔV(EXTIO)
Reference voltage drift
±50
Power Supply
AVDD
Analog supply voltage
3.15
3.15
3.3
3.3
3.6
3.6
V
V
DVDD
I(AVDD)
I(DVDD)
Digital supply voltage
Analog supply current(3)
Digital supply current(3)
115
85
148
130
mA
mA
Sleep mode
18
PD
Power dissipation
mW
AVDD = 3.3 V, DVDD = 3.3 V
660
±0.1
±0.1
900
0.9
0.9
APSRR
DPSRR
–0.9
–0.9
Analog and digital
power-supply rejection ratio
AVDD = 3.15 V to 3.45 V
%FSR/V
(1) Measured differential at IOUT1 and IOUT2: 25 Ω to AVDD
(2) Use an external buffer amplifier with high impedance input to drive any external load.
(3) Measured at fCLK = 400 MSPS and fOUT = 70 MHz
4
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AC Electrical Characteristics (Unchanged after 100 kRad)
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential
transformer-coupled output, 50-Ω doubly-terminated load (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
Analog Output
fCLK
Output update rate
400 MSPS
ts(DAC)
tPD
tr(IOUT)
tf(IOUT)
Output setting time to 0.1%
Output propagation delay
Output rise time, 10% to 90%
Output fall time, 90% to 10%
Transition: code x2000 to x23FF
12
1
ns
ns
ps
ps
300
300
55
IOUTFS = 20 mA
IOUTFS = 2 mA
Output noise
pA/√Hz
30
AC Linearity
fCLK = 100 MSPS,
fCLK = 160 MSPS,
fCLK = 200 MSPS,
fOUT = 19.9 MHz
fOUT = 41 MHz
70
72
68
68
fOUT = 70 MHz
THD
Total harmonic distortion
fOUT = 20.0 MHz
fOUT = 20.0 MHz, for TMIN
fOUT = 70 MHz
60
57
dBc
fCLK = 400 MSPS
67
55
70
73
70
68
fOUT = 140 MHz
fOUT = 19.9 MHz
fOUT = 41 MHz
fCLK = 100 MSPS,
fCLK = 160 MSPS,
fCLK = 200 MSPS,
fOUT = 70 MHz
Spurious-free dynamic range
to Nyquist
SFDR
fOUT = 20.0 MHz
fOUT = 20.0 MHz, for TMIN
fOUT = 70 MHz
62
61
dBc
fCLK = 400 MSPS
69
56
82
77
82
82
82
75
67
73
71
65
73
fOUT = 140 MHz
fOUT = 19.9 MHz
fOUT = 41 MHz
fCLK = 100 MSPS,
fCLK = 160 MSPS,
fCLK = 200 MSPS,
fOUT = 70 MHz
Spurious-free dynamic range
within a window, 5 MHz span
SFDR
dBc
fOUT = 20.0 MHz
fOUT = 70 MHz
fCLK = 400 MSPS
fCLK = 400 MSPS
fOUT = 140 MHz
fOUT = 20.0 MHz
SNR
Signal-to-noise ratio
60
dBc
dB
fCLK = 122.88 MSPS, IF = 30.72 MHz, See Figure 11
Adjacent channel power ratio
ACPR
WCDM A with 3.84 MHz BW, fCLK = 245.76 MSPS, IF = 61.44 MHz,
5 MHz channel spacing
fCLK = 399.36 MSPS, IF = 153.36 MHz, See Figure 13
Two-tone intermodulation
to Nyquist (each tone at
–6 dBfs)
fCLK = 400 MSPS, fOUT1 = 70 MHz, fOUT2 = 71 MHz
fCLK = 400 MSPS, fOUT1 = 140 MHz, fOUT2 = 141 MHz
fCLK = 156 MSPS, fOUT = 15.6, 15.8, 16.2, 16.4 MHz
fCLK = 400 MSPS, fOUT = 68.1, 69.3, 71.2, 72 MHz
62
82
74
IMD
dBc
Four-tone intermodulation,
15-MHz span, missing center
tone (each tone at –16 dBfs)
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SGLS387D –JULY 2007–REVISED OCTOBER 2009..................................................................................................................................................... www.ti.com
Digital Specifications (Unchanged after 100 kRad)
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
LVDS Interface: Nodes D[13:0]A, D[13:0]B
Positive-going differential input
voltage threshold
VITH+
100
mV
mV
Negative-going differential input
voltage threshold
VITH–
–100
ZT
CI
Internal termination impedance
Input capacitance
90
2
110
2
132
Ω
pF
CMOS Interface (SLEEP)
VIH
VIL
IIH
High-level input voltage
3.3
0
V
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
0.8
100
10
V
–100
–10
μA
μA
pF
IIL
2
Clock Interface (CLK, CLKC)
|CLK-CLKC|
tw(H)
Clock differential input voltage
0.4
0.8
VPP
ns
ns
%
Clock pulse width high
Clock pulse width low
Clock duty cycle
1.25
1.25
tw(L)
40
60
VCM
Common-mode voltage range
Input resistance
1.6
2
670
2
2.4
V
Node CLK, CLKC
Ω
Input capacitance
Node CLK, CLKC
Differential
pF
kΩ
pF
Input resistance
1.3
1
Input capacitance
Differential
Timing
tSU
Input setup time
1.5
0.0
ns
ns
clk
tH
Input hold time
tDD
Digital delay time (DAC latency)
3
6
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Timing Information
Figure 1. Timing Diagram
Electrical Characteristics(1)
over operating free-air temperature range, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted)
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING
COMMON-MODE
INPUT VOLTAGE
LOGICAL BIT
BINARY
EQUIVALENT
APPLIED
VOLTAGES
COMMENT
VA (V)
VB (V)
VA,B (mV)
100
VCOM (V)
1.2
1.25
1.15
2.4
2.3
0.1
0
1.15
1.25
2.3
2.4
0
1
0
1
0
1
0
1
0
1
0
1
0
–100
100
1.2
Operation with minimum differential voltage
(±100 mV) applied to the complementary inputs
versus common-mode range
2.35
2.35
0.05
0.05
1.2
–100
100
0.1
0.9
1.5
1.8
2.4
0
–100
600
1.5
0.9
2.4
1.8
0.6
0
–600
600
1.2
Operation with maximum differential voltage
(±600 mV) applied to the complementary inputs
versus common-mode range
2.1
–600
600
2.1
0.3
0.6
–600
0.3
(1) Specifications subject to change.
DVDD
VA
1.4 V
DAC5675A
VB
1 V
VA, B
0.4 V
0 V
VA, B
−0.4 V
1
VA
Logical Bit
Equivalent
VA + VB
VCOM =
0
2
DGND
VB
Figure 2. LVDS Timing Test Circuit and Input Test Levels
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HFG PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
39 AGND
38 D0B
D13A
D13B
D12A
D12B
D11A
D11B
D10A
D10B
D9A
1
2
37
36
35
34
33
D0A
D1B
D1A
D2B
D2A
D3B
D3A
D4B
D4A
D5B
D5A
3
4
5
6
7
32
31
30
29
28
27
8
9
10
11
12
13
D9B
D8A
D8B
AGND
14 15 16 17 18 19 20 21 22 23 24 25 26
8
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www.ti.com ..................................................................................................................................................... SGLS387D –JULY 2007–REVISED OCTOBER 2009
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
AGND
NO.
13, 20, 26, 39, 44, 49, 50,
52
Analog negative supply voltage (ground). Pin 13 is internally connected to the heat
slug and lid (lid is also grounded internally).
I
AVDD
BIASJ
CLK
21, 45, 48, 51
I
O
I
Analog positive supply voltage
Full-scale output current bias
External clock input
42
23
22
CLKC
I
Complementary external clock
LVDS positive input, data bits 13–0.
D13A is the most significant data bit (MSB).
D0A is the least significant data bit (LSB).
1, 3, 5, 7, 9, 11, 14, 24, 27,
29, 31, 33, 35, 37
D[13:0]A
D[13:0]B
I
I
LVDS negative input, data bits 13–0.
D13B is the most significant data bit (MSB).
D0B is the least significant data bit (LSB).
2, 4, 6, 8, 10, 12, 15, 25,
28, 30, 32, 34, 36, 38
DGND
DVDD
17, 19
16, 18
I
I
Digital negative supply voltage (ground)
Digital positive supply voltage
Internal reference output or external reference input. Requires a 0.1-μF decoupling
capacitor to AGND when used as reference output.
EXTIO
IOUT1
IOUT2
43
46
47
I/O
O
DAC current output. Full-scale when all input bits are set '0'. Connect the reference
side of the DAC load resistors to AVDD
.
DAC complementary current output. Full-scale when all input bits are '1'. Connect the
O
reference side of the DAC load resistors to AVDD
.
NC
41
40
Not connected in chip. Can be high or low.
SLEEP
I
Asynchronous hardware power-down input. Active high. Internal pulldown.
Table 2. THERMAL INFORMATION
PARAMETER
TEST CONDITIONS
TYP
21.813
0.849
UNIT
°C/W
°C/W
Junction-to-free-air thermal
resistance
RθJA
RθJC
Board mounted, per JESD 51-5 methodology
MIL-STD-883 test method 1012
Junction-to-case thermal resistance
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THERMAL NOTES
This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the
bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is
required on the surface of the PCB directly under the body of the package. During normal surface mount flow
solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an
efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a
thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat
removal. TI typically recommends an 11, 9 mm 2 board-mount thermal pad. This allows maximum area for
thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity
of thermal/electrical vias must be included to keep the device within recommended operating conditions. This
pad must be electrically ground potential.
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
100
105
110
115
120
125
130
135
140
145
150
155
160
Continuous Tj (°C)
Figure 3. Estimated Device Life at Elevated Temperatures Electromigration Fail Modes
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY (DNL)
INTEGRAL NONLINEARITY (INL)
vs
vs
INPUT CODE
INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.5
1.0
0.5
0
−
0.2
−
0.5
1.0
1.5
−
0.4
−
0.6
−
−
−
0.8
−
1.0
0
2000 4000 6000 8000 10000 12000 14000 16000
Input Code
0
2000 4000 6000 8000 10000 12000 14000 16000
Input Code
Figure 4.
Figure 5.
TWO-TONE IMD (POWER)
TWO-TONE IMD3
vs
vs
FREQUENCY
FREQUENCY
0
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
f
= 69.5 MHz, −6 dBFS
= 70.5 MHz, −6 dBFS
1
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
f
2
IMD3 = 77.41 dBc
V
= V = 3.3 V
AA
CC
f
= 200 MHz
CLK
−
f2 f1 = 1 MHz (–6 dBFS each)
CC = VAA = 3.3 V
CLK = 200 MHz
V
f
−
100
65
67
69
71
73
75
5
15
25
35
45
55
65
75
85
Frequency (MHz)
Center Frequency (MHz)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
SINGLE-TONE SPECTRUM
POWER
vs
SPURIOUS-FREE DYNAMIC RANGE
vs
FREQUENCY
FREQUENCY
80
75
70
65
60
55
50
0
10
20
30
40
50
60
70
80
90
VCC = VAA = 3.3 V
fCLK = 400 MHz
- 3 dBFS
20.1 MHz
−
−
−
−
−
−
−
−
−
VCC = VAA = 3.3 V
fclk = 400 MHz
fOUT = 20.1 MHz, 0 dBFS
SFDR = 74.75 dBc
-6 dBFS
0 dBFS
40.06 MHz
60.25 MHz
0
20
40
60
80 100 120 140 160 180 200
Frequency (MHz)
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
Output Frequency (MHz)
Figure 8.
Figure 9.
W-CDMA TM1 SINGLE CARRIER
SPURIOUS-FREE DYNAMIC RANGE
POWER
vs
vs
FREQUENCY
FREQUENCY
85
80
75
70
65
60
55
50
−
25
VCC = VAA = 3.3 V
-3 dBFS
VCC = VAA = 3.3 V
fclk= 200 MHz
−
35
45
55
65
75
85
95
fCLK = 122.88 MHz
fCENTER = 30.72 MHz
ACLR = 72.29 dB
−
−
−
−
−
−
-6 dBFS
0 dBFS
−
−
105
115
18
23
28
33
38
43
10
20
30
40
50
60
70
80
90
100
110
120
Frequency
Output Frequency (MHz)
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
W-CDMA TM1 DUAL CARRIER
W-CDMA TM1 SINGLE CARRIER
POWER
vs
ACLR
vs
FREQUENCY
OUTPUT FREQUENCY
−
−
−
−
−
−
−
30
40
50
60
70
80
90
80
78
76
74
72
70
68
66
64
62
60
V
f
= V = 3.3 V
AA
f
= 368.64 MHz
VCC = VAA = 3.3 V
CC
CLK
=
ACLR = 65 dBc
fCLK = 399.36 MHz
Single Channel
CENTER
92.16 MHz
−
−
100
110
82.2
87.2
92.2
97.2
10.2
10
30
50
70
90
110
130
150
Frequency
Output Frequency (MHz)
Figure 12.
Figure 13.
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APPLICATION INFORMATION
Detailed Description
Figure 14 shows a simplified block diagram of the current steering DAC5675A. The DAC5675A consists of a
segmented array of NPN-transistor current sources, capable of delivering a full-scale output current up to 20 mA.
Differential current switches direct the current of each current source to either one of the complementary output
nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out
common-mode noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, and even-order distortion
components, and doubling signal output power.
The full-scale output current is set using an external resistor (RBIAS) with an on-chip bandgap voltage reference
source (1.2 V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirrored internally to provide a
full-scale output current equal to 16 times IBIAS
.
The full-scale current is adjustable from
20 mA down to 2 mA by using the appropriate bias resistor value.
SLEEP
3.3 V
(AVDD
)
DAC5675A
Bandgap
Reference
1.2 V
Ω
50
IOUT
Output
1:1
EXTIO
Current
Source
Array
Output
Current
Switches
RLOAD
Ω
100
Ω
50
BIASJ
CEXT
0.1 µF
Control Amp
IOUT
3.3 V
(AVDD
)
RBIAS
Ω
Ω
50
1 k
14
14
D[13:0]A
D[13:0]B
DAC
Latch
+
3.3 V
LVDS
Input
Input
Decoder
(AVDD
)
Latches
Interface
Drivers
CLK
1:4
Clock
Input
RT
Ω
Clock Distribution
DVDD(2x)
200
CLKC
AVDD(4x)
AGND(4x)
DGND(2x)
Figure 14. Application Simplified Block Diagram
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Digital Inputs
The DAC5675A uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a low
differential voltage swing with low constant power consumption (4 mA per complementary data input) across
frequency. The differential characteristic of LVDS allows for high-speed data transmission with low
electromagnetic interference (EMI) levels. Figure 15 shows the equivalent complementary digital input interface
for the DAC5675A, valid for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110-Ω
resistors for proper termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A
common-mode level of 1.2 V and a differential input swing of 0.8 VPP is applied to the inputs.
Figure 16 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675A, valid for
the SLEEP pin.
DVDD
DAC5675A
DAC5675A
D[13..0]A
Ω
110
Internal
Termination
Digital In
Resistor
D[13..0]B
D[13:0]A
D[13:0]B
Internal
Digital In
DGND
Figure 15. LVDS Digital Equivalent Input
DVDD
DAC5675A
Internal
Digital Input
Digital In
DGND
Figure 16. CMOS/TTL Digital Equivalent Input
Clock Input
The DAC5675A features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 17 shows the
equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage
to approximately 2 V, while the input resistance is typically 670 Ω. A variety of clock sources can be ac-coupled
to the device, including a sine-wave source (see Figure 18).
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AVDD
DAC5675A
R
1
R
1
1 kΩ
1 kΩ
Internal
Clock
CLK
CLKC
R
2
R
2
2 kΩ
2 kΩ
AGND
Figure 17. Clock Equivalent Input
Optional, may be
bypassed for sine-
wave input
Swing Limitation
C
AC
0.1 µF
1:4
CLK
RT
Ω
DAC5675A
200
CLKC
Termination
Resistor
Figure 18. Driving the DAC5675A With a Single-Ended Clock Source Using a Transformer
To obtain best ac performance, the DAC5675A clock input should be driven with a differential LVPECL or
sine-wave source as shown in Figure 19 and Figure 20. Here, the potential of VTT should be set to the
termination voltage required by the driver along with the proper termination resistors (RT). The DAC5675A clock
input can also be driven single ended; this is shown in Figure 21.
CAC
ECL/PECL
Gate
0.01 µF
CLK
Single-Ended
ECL
CAC
DAC5675A
or
0.01 µF
(LV)PECL
Source
CLKC
RT
Ω
RT
Ω
50
50
VTT
Figure 19. Driving the DAC5675A With a Single-Ended ECL/PECL Clock Source
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CAC
0.01 µF
CLK
+
−
Differential
ECL
CAC
DAC5675A
or
0.01µF
(LV)PECL
Source
CLKC
RT
Ω
RT
Ω
50
50
VTT
Figure 20. Driving the DAC5675A With a Differential ECL/PECL Clock Source
DAC5675A
TTL/CMOS
CLK
Source
ROPT
Ω
22
CLKC
0.01µF
Node CLKC
Internally Biased to
AVDD/2
Figure 21. Driving the DAC5675A With a Single-Ended TTL/CMOS Clock Source
Supply Inputs
The DAC5675A comprises separate analog and digital supplies, (AVDD and DVDD) respectively. These supply
inputs can be set independently from 3.6 V down to 3.15 V.
DAC Transfer Function
The DAC5675A has a current sink output. The current flow through IOUT1 and IOUT2 is controlled by D[13:0]A
and D[13:0]B. For ease of use, D[13:0] is denoted as the logical bit equivalent of D[13:0]A and its complement
D[13:0]B. The DAC5675A supports straight binary coding with D13 being the MSB and D0 the LSB. Full-scale
current flows through IOUT2 when all D[13:0] inputs are set high and through IOUT1 when all D[13:0] inputs are
set low. The relationship between IOUT1 and IOUT2 can be expressed as Equation 1:
(1)
IO(FS) is the full-scale output current sink (2 mA to 20 mA). Because the output stage is a current sink, the current
can only flow from AVDD through the load resistors RL into the IOUT1 and IOUT2 pins.
The output current flow in each pin driving a resistive load can be expressed as shown in Figure 22, as well as in
Equation 2 and Equation 3.
Figure 22. Relationship Between D[13:0], IOUT1 and IOUT2
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(2)
(3)
where CODE is the decimal representation of the DAC input word. This would translate into single-ended
voltages at IOUT1 and IOUT2, as shown in Equation 4 and Equation 5:
(4)
(5)
Assuming that D[13:0] = 1 and the RL is 50Ω, the differential voltage between pins IOUT1 and IOUT2 can be
expressed as shown in Equation 6 through Equation 8:
(6)
(7)
(8)
If D[13:0] = 0, then IOUT2 = 0mA and IOUT1 = 20mA and the differential voltage VDIFF = –1V.
The output currents and voltages in IOUT1 and IOUT2 are complementary. The voltage, when measured
differentially, is doubled compared to measuring each output individually. Care must be taken not to exceed the
compliance voltages at the IOUT1 and IOUT2 pins to keep signal distortion low.
Reference Operation
The DAC5675A has a bandgap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS
is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals
16 times this bias current. The full-scale output current IO(FS) is thus expressed as Equation 9:
16 VEXTIO
IO FS) + 16 I
(
+
BIAS
RBIAS
(9)
where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers a stable voltage of 1.2 V.
This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap reference can
additionally be used for external reference operation. In such a case, an external buffer amplifier with high
impedance input should be selected to limit the bandgap load current to less than 100 nA. The capacitor CEXT
may be omitted. Terminal EXTIO serves as either an input or output node. The full-scale output current is
adjustable from 20 mA down to 2 mA by varying resistor RBIAS
.
Analog Current Outputs
Figure 23 shows a simplified schematic of the current source array output with corresponding switches.
Differential NPN switches direct the current of each individual NPN current source to either the positive output
node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the
stack of the current sources and differential switches and is >300 kΩ in parallel with an output capacitance
of 5 pF.
The external output resistors are referred to the positive supply AVDD
.
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3.3 V
AVDD
RLOAD
RLOAD
IOUT2
IOUT1
DAC5675A
S(1)
S(1)C S(2)
S(2)C S(N)
S(N)C
Current Sink Array
AGND
Figure 23. Equivalent Analog Current Output
The DAC5675A easily can be configured to drive a doubly-terminated 50-Ω cable using a properly selected
transformer. Figure 24 and Figure 25 show the 1:1 and 4:1 impedance ratio configuration, respectively. These
configurations provide maximum rejection of common-mode noise sources and even-order distortion
components, thereby doubling the power of the DAC to the output. The center tap on the primary side of the
transformer is terminated to AVDD, enabling a dc-current flow for both IOUT1 and IOUT2. Note that the ac
performance of the DAC5675A is optimum and specified using a 1:1 differential transformer-coupled output.
3.3 V
AVDD
Ω
50
100
50
DAC5675A
1:1
IOUT1
RLOAD
Ω
50
Ω
IOUT2
Ω
3.3 V
AVDD
Figure 24. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
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3.3 V
AVDD
Ω
100
DAC5675A
4:1
IOUT1
RLOAD
Ω
50
IOUT2
15 Ω
Ω
100
3.3 V
AVDD
Figure 25. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer
Figure 26(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 25 Ω gives a differential output swing of 1 VPP (0.5 VPP single ended) when applying a
20-mA full-scale output current. The output impedance of the DAC5675A slightly depends on the output voltage
at nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of Figure 26(b)
should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by the inverting
operational amplifier. The complementary output should be connected to AVDD to provide a dc-current path for
the current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current of
the DAC determine the value of the feedback resistor RFB. The capacitor CFB filters the steep edges of the
DAC5675A current output, thereby reducing the operational amplifier slew-rate requirements. In this
configuration, the operational amplifier should operate at a supply voltage higher than the resistor output
reference voltage AVDD as a result of its positive and negative output swing around AVDD. Node IOUT1 should be
selected if a single-ended unipolar output is desired.
3.3 V
CFB
AVDD
Ω
200
(RFB)
DAC5675A
IOUT1
DAC5675A
Ω
25
25
VOUT
1
2
IOUT1
IOUT2
V
OUT
IOUT2
VOUT
Ω
Optional, for single-
ended output
3.3 V
AVDD
referred to AVDD
3.3 V
AVDD
(a)
(b)
Figure 26. Output Configurations
Sleep Mode
The DAC5675A features a power-down mode that turns off the output current and reduces the supply current to
approximately 6 mA. The power-down mode is activated by applying a logic level one to the SLEEP pin, pulled
down internally.
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DEFINITIONS
Definitions of Specifications and Terminology
Gain error is as the percentage error in the ratio between the measured full-scale output current and the value of
16 × V(EXTIO)/RBIAS. A V(EXTIO) of 1.25 V is used to measure the gain error with an external reference voltage
applied. With an internal reference, this error includes the deviation of V(EXTIO) (internal bandgap reference
voltage) from the typical value of 1.25 V.
Offset error is as the percentage error in the ratio of the differential output current (IOUT1-IOUT2) and the half
of the full-scale output current for input code 8192.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental output
signal.
SNR is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc.
SINAD is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise and harmonics, but excluding dc.
ACPR or adjacent channel power ratio is defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a
3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio.
APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5% variation
of the analog power supply AVDD from the nominal. This is a dc measurement.
DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variation
of the digital power supply DVDD from the nominal. This is a dc measurement.
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相关型号：
DAC5675PHP
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