DAC5686PZP_技术文档

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

16-BIT, 500-MSPS, 2×–16× INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG

CONVERTER

FEATURES

•

On-Chip 1.2-V Reference

•

500 MSPS Maximum Update Rate DAC

1.8-V Digital and 3.3-V Analog Supplies

1.8-V/3.3-V CMOS Compatible Interface

•

WCDMA ACPR

– 1 Carrier: 76 dB Centered at 30.72-MHz IF,

245.76 MSPS

Power Dissipation: 950 mW at Full Maximum

Operating Conditions

– 1 Carrier: 73 dB Centered at 61.44-MHz IF,

245.76 MSPS

•

Package: 100-Pin HTQFP

– 2 Carrier: 72 dB Centered at 30.72-MHz IF,

245.76 MSPS

APPLICATIONS

•

Cellular Base Transceiver Station Transmit

Channel

– 4 Carrier: 64 dB Centered at 92.16-MHz IF,

491.52 MSPS

– CDMA: W-CDMA, CDMA2000, IS-95

– TDMA: GSM, IS-136, EDGE/UWC-136

Baseband I and Q Transmit

Input Interface: Quadrature Modulation for

Interfacing With Baseband Complex Mixing

ASICs

Single-Sideband Up-Conversion

Diversity Transmit

Cable Modem Termination System

•

Selectable 2×, 4×, 8×, and 16× Interpolation

– Linear Phase

•

– 0.05-dB Pass-Band Ripple

– 80-dB Stop-Band Attenuation

– Stop-Band Transition 0.4–0.6 f_DATA

32-Bit Programmable NCO

•

On-Chip 2×–16× PLL Clock Multiplier With

Bypass Mode

•

Differential Scalable Current Outputs: 2 mA to

20 mA

DESCRIPTION

The DAC5686 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, 8×,

and 16× interpolation filters, a numerically controlled oscillator (NCO), onboard clock multiplier, and on-chip

voltage reference. The DAC5686 has been specifically designed to allow for low input data rates between the

DAC and ASIC, or FPGA, and high output transmit intermediate frequencies (IF). Target applications include

high-speed digital data transmission in wired and wireless communication systems and high-frequency

direct-digital synthesis DDS.

The DAC5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. In

dual-channel mode, interpolation filtering increases the DAC update rate, which reduces sinx/x rolloff and

enables the use of relaxed analog post-filtering.

Single-sideband mode provides an alternative interface to the analog quadrature modulators. Channel carrier

selection is performed at baseband by mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are

input to the DAC5686, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of

the DAC5686's two DACs. An external RF quadrature modulator then performs the final single-sideband

up-conversion. The DAC5686's complex mixing frequencies are flexibly chosen with the 32-bit programmable

NCO.

Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local oscillator

feedthrough. Each DAC in the DAC5686 has an 11-bit offset adjustment and 12-bit gain adjustment, which

compensate for quadrature modulator input imbalances, thus reducing RF filtering requirements.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

In quadrature modulation mode, on-chip mixing provides baseband-to-IF up-conversion. Mixing frequencies are

flexibly chosen with a 32-bit programmable NCO. Channel carrier selection is performed at baseband by complex

mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which interpolates

the low data-rate signal to higher data rates. The single DAC output from the DAC5686 is the final IF

single-sideband spectrum presented to RF.

The 2×, 4×, 8×, and 16× interpolation filters are implemented as a cascade of half-band 2× interpolation filters.

Unused filters for interpolation rates of less than 16× are shut off to reduce power consumption. The DAC5686

provides a full bypass mode, which enables the user to bypass all the interpolation and mixing.

The DAC5686 PLL clock multiplier controls all internal clocks for the digital filters and the DAC cores. The

differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input

signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The

clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

The DAC5686 operates with an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. Digital I/Os

are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 950 mW at maximum operating conditions. The

DAC5686 provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and

differential applications. The output current can be directly fed to the load with no additional external output buffer

required. The device has been specifically designed for a differential transformer-coupled output with a 50-Ω

doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output

power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported.

The DAC5686 operational modes are configured by programming registers through a serial interface. The serial

interface can be configured to either a 3- or 4-pin interface allowing it to communicate with many

industry-standard microprocessors and microcontrollers. Data (I and Q) can be input to the DAC5686 as

separate parallel streams on two data buses, or as a single interleaved data stream on one data bus.

An accurate on-chip 1.2-V temperature-compensated band-gap reference and control amplifier allows the user to

adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control

capabilities. Alternatively, an external reference voltage can be applied for maximum flexibility. The device

features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby minimizing the

system power consumption.

The DAC5686 is available in a 100-pin HTQFP package. The device is characterized for operation over the

industrial temperature range of –40°C to 85°C.

ORDERING INFORMATION

T_A

PACKAGE DEVICES

100 HTQFP⁽¹⁾(PZP) PowerPAD™ Plastic Quad Flatpack

DAC5686IPZP

–40°C to 85°C

(1) Thermal pad size: 6 mm × 6 mm

2

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

FUNCTIONAL BLOCK DIAGRAM

Block Diagram of the DAC5686

CLKVDD CLKGND

PLLGND PLLVDD

PHSTR

SLEEP

DVDD

DGND

PLLLOCK

LPF

EXTIO

CLK1

1.2 V

Reference

EXTLO

CLK1C

2 – 16y F

data

Internal Clock Generation

2y – 16y PLL Clock Multiplier

BIASJ

CLK2

CLK2C

F

A

data

A Gain

Offset

FIR5

FIR1

FIR2

FIR3

FIR4

DEMUX

IOUTA1

IOUTA2

x

16-Bit

DAC

sin(x)

y 2

DA[15:0]

DB[15:0]

IOUTB1

IOUTB2

IOGND

IOVDD

x

16-Bit

DAC

sin(x)

y 2

TxENABLE

RESETB

cos

sin

B

B Gain

Offset

SIF

NCO

100-Pin HTQFP

SDIO SDO SDENB SCLK

AVDD

AGND

3

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

PIN ASSIGNMENTS FOR THE DAC5686

AGND

AVDD

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DB4

2

DB3

AVDD

3

DB2

AGND

IOUTB1

IOUTB2

AGND

AVDD

4

DB1

5

DB0 (LSB)

PLLLOCK

DGND

DVDD

PLLVDD

LPF

6

7

8

AGND

AVDD

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

EXTIO

AGND

BIASJ

AVDD

PLLGND

CLKGND

CLK2C

CLK2

Top View 100 HTQFP

DAC5686

EXTLO

AVDD

CLKVDD

CLK1C

CLK1

AGND

AVDD

CLKGND

DGND

DVDD

DA0 (LSB)

DA1

AGND

IOUTA2

IOUTA1

AGND

AVDD

DA2

AVDD

DA3

AGND

DA4

DEVICE INFORMATION

Terminal Functions

TERMINAL

NAME

AGND

I/O

DESCRIPTION

NO.

1, 4, 7, 9,

12, 17, 19,

22, 25

I

Analog ground return

AVDD

2, 3, 8, 10,

14, 16, 18,

23, 24

I

Analog supply voltage

4

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

DEVICE INFORMATION (continued)

Terminal Functions (continued)

TERMINAL

NAME

I/O

DESCRIPTION

NO.

BIASJ

13

59

60

62

63

I/O Full-scale output current bias

CLK1

I

External clock input; data clock input

Complementary external clock input; data clock input

CLK1C

CLK2

External clock input; sample clock for the DAC (optional if PLL disabled)

Complementary external clock input; sample clock for the DAC (optional if PLL disabled)

Ground return for internal clock buffer

CLK2C

CLKGND

CLKVDD

DA[15:0]

58, 64

61

Internal clock buffer supply voltage

34–36,

39–43,

48–55

I

A-channel data bits 0 through 15

DA15 is most significant data bit (MSB).

DA0 is least significant data bit (LSB).

DB[0:15]

71–78,

83–87,

90–92

B-channel data bits 0 through 15

DB15 is most significant data bit (MSB).

DB0 is least significant data bit (LSB).

Note: The order of the B data bus can be reversed by register rev_bbus.

DGND

DVDD

EXTIO

27, 38, 45,

57, 69, 81,

88, 93, 99

Digital ground return

26, 32, 37,

44, 56, 68,

82, 89, 100

Digital supply voltage

11

I

Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).

Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to

AGND when used as reference output

EXTLO

IOUTA1

IOUTA2

IOUTB1

IOUTB2

IOGND

IOVDD

LPF

15

I

Internal reference ground. Connect to AVDD to disable the internal reference

A-channel DAC current output. Full scale when all input bits are set to 1

A-channel DAC complementary current output. Full scale when all input bits are set to 0

B-channel DAC current output. Full scale when all input bits are set to 1

B-channel DAC complementary current output. Full scale when all input bits are set to 0

Digital I/O ground return

21

O

20

5

6

47, 79

46, 80

66

Digital I/O supply voltage

I/O PLL loop filter connection. Can be left open or connected to GND if PLL is not used (PLLVDD = 0 V).

PHSTR

94

I

The PHSTR pin has two functions. When the sync_phstr register is 0, a high on the PHSTR pin resets

the NCO phase accumulator. When the sync_phstr register is 1, a PHSTR pin low-to-high transition

sets the divided clock phase in external clock mode, and a high on the PHSTR pin resets the NCO

phase accumulator.

PLLGND

PLLVDD

PLLLOCK

65

67

70

Ground return for internal PLL

PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.

O

PLL lock status bit. In PLL clock mode, PLLLOCK is high when PLL is locked to the input clock. In

external clock mode, PLLLOCK outputs the input rate clock.

QFLAG

98

Used in the interleaved data input mode: When the qflag register bit is 1, the QFLAG pin is used as an

output to identify the interleaved data sequence. QFLAG high identifies the data as channel B. Pin can

be left open when not used.

RESETB

SCLK

95

29

28

30

I

Resets the chip when low

Serial interface clock

SDENB

SDIO

Active-low serial data enable, always an input to the DAC5686

I/O Bidirectional serial-port data in the three-pin serial interface mode. Input-only serial data in the four-pin

serial interface mode.

SDO

31

O

High-impedance state (the pin is not used) in the three-pin serial interface mode. Serial-port output data

in the four-pin serial interface mode.

SLEEP

96

I

Asynchronous hardware power-down input. Active high. Internal pulldown

TESTMODE is DGND for the user.

TESTMODE 97

5

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

DEVICE INFORMATION (continued)

Terminal Functions (continued)

TERMINAL

NAME

TxENABLE

I/O

DESCRIPTION

NO.

33

I

TxENABLE is used in interleaved mode. The rising edge of TxENABLE synchronizes the data of

channels A and B. The first data after the rising edge of TxENABLE is treated as A data, while the next

data is treated as B data and so on. In any mode, TxENABLE being low sets DAC outputs to midscale.

Internal pulldown

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

AVDD⁽²⁾

DVDD⁽³⁾

–0.5 V to 4 V

–0.5 V to 2.3 V

Supply voltage range

CLKVDD⁽²⁾

IOVDD⁽²⁾

–0.5 V to 4 V

PLLVDD⁽²⁾

–0.5 V to 4 V

Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND

–0.5 V to 0.5 V

AVDD to DVDD

DA[15:0]⁽³⁾

DB[15:0]⁽³⁾

SLEEP⁽³⁾

CLK1, CLK2, CLK1C, CLK2C⁽³⁾

RESETB⁽³⁾

–0.5 V to 2.6 V

–0.5 V to IOVDD + 0.5 V

–0.5 V to CLKVDD + 0.5 V

–0.5 V to IOVDD + 0.5 V

–0.5 V to PLLVDD + 0.5 V

–1 V to AVDD + 0.5 V

–0.5 V to AVDD + 0.5 V

–0.5 V to IOVDD + 0.5 V

±20 mA

Supply voltage range

LPF⁽³⁾

IOUT1, IOUT2⁽²⁾

EXTIO, BIASJ⁽²⁾

EXTLO⁽²⁾

Peak input current (any input)

Operating free-air temperature range, T_A: DAC5686I

Storage temperature range

–40°C to 85°C

–65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds

260°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to AGND

(3) Measured with respect to DGND

ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS)⁽¹⁾

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,

DVDD = 1.8 V, IOUT_FS= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

16

DC Accuracy⁽²⁾

INL

Integral nonlinearity

1 LSB = IOUT_FS/216, T_MINto T_MAX

±12

1.84e–4

±9

LSB

IOUT_FS

LSB

DNL

Differential nonlinearity

1.37e–4

IOUT_FS

(1) Specifications subject to change without notice.

(2) Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD

6

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,

DVDD = 1.8 V, IOUT_FS= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Output

Coarse gain linearity (INL)

Fine gain linearity (INL)

Offset error

LSB = 1/10^thof full scale

±0.016

±3

LSB

Mid-code offset

0.003

0.7

%FSR

Without internal reference

With internal reference

Gain error

%FSR

0.7

Gain mismatch

With internal reference, dual DAC,

SSB mode

–2

2

Full-scale output current⁽³⁾

Output compliance range⁽⁴⁾

Output resistance

2

20

mA

V

IOUT_FS= 20 mA

AVDD – 0.5

AVDD + 0.5

300

5

kΩ

pF

Output capacitance

Reference Output

Reference voltage

Reference output current⁽⁵⁾

1.14

0.1

1.2

1.26

1.25

V

100

nA

Reference Input

V_EXTIO

Input voltage range

Input resistance

V

1

2.5

MΩ

kHz

pF

Small-signal bandwidth

Input capacitance

100

Temperature Coefficients

ppm of

FSR/°C

Offset drift

±3

Without internal reference

With internal reference

±15

±40

±25

ppm of

FSR/°C

Gain drift

Reference voltage drift

Power Supply

ppm/°C

AVDD

DVDD

Analog supply voltage

Digital supply voltage

3

1.65

3

3.3

1.8

3.3

3.6

1.95

3.6

V

CLKVDD Clock supply voltage

IOVDD I/O supply voltage

PLLVDD PLL supply voltage

1.65

3

3.6

3.3

30

3.6

Single (quad) DAC mode;

including output current through

load resistor, mode 7

I_AVDD

Analog supply current

mA

Dual DAC mode; including output

current through load resistor,

mode 11

55

I_DVDD

Digital supply current

Clock supply current

PLL supply current

IO supply current

242

10

mA

I_CLKVDD

I_PLLVDD

I_IOVDD

f_DATA= 125 MSPS, SSB mode,

F_update= 500 MSPS, 40-MHz IF

28

< 3

(3) Nominal full-scale current, IOUT_FS, equals 16× the IBIAS current.

(4) The upper limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC5686 device. The lower limit of the output compliance is determined by the load resistors and

full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(5) Use an external buffer amplifier with high-impedance input to drive any external load.

7

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,

DVDD = 1.8 V, IOUT_FS= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

1

MAX

UNIT

mA

I_AVDD

Sleep mode, AVDD supply current

Sleep mode, DVDD supply current

I_DVDD

4

mA

I_CLKVDD

Sleep mode, CLKVDD supply

current

2

mA

Sleep mode

I_PLLVDD

I_IOVDD

Sleep mode, PLLVDD supply

current

0.5

Sleep mode, IOVDD supply current

0.25

215

mA

Mode 1⁽⁶⁾AVDD = 3.3 V,

DVDD = 1.8 V

Mode 2⁽⁷⁾AVDD = 3.3 V,

DVDD = 1.8 V

Mode 5⁽⁸⁾AVDD = 3.3 V,

DVDD = 1.8 V

Mode 7⁽⁹⁾AVDD = 3.3 V,

DVDD = 1.8 V

Mode 9⁽¹⁰⁾AVDD = 3.3 V,

DVDD = 1.8 V

495

445

754

547

855

P_D

Power dissipation

mW

Mode 11⁽¹¹⁾AVDD = 3.3 V,

DVDD = 1.8 V

950

APSRR

DPSRR

Power supply rejection ratio

–0.2

0.2 %FSR/V

(6) Mode 1: Dual DAC mode, fully bypassed, F_DAC= 160 MSPS, f_OUT= 20 MHz

(7) Mode 2: Dual DAC mode, 2× interpolation, F_DAC= 320 MSPS, f_OUT= 20 MHz

(8) Mode 5: Quadrature modulation mode, 4× interpolation, fs/4 mixing, F_DAC= 320 MSPS, f_OUT= 100 MHz

(9) Mode 7: Quadrature modulation mode, 4× interpolation, NCO running at 320 MHz, F_DAC= 320 MSPS, f_OUT= 100 MHz

(10) Mode 9: SSB modulation mode, 4× interpolation, fs/4 mixing, F_DAC= 320 MSPS, f_OUT= 100 MHz

(11) Mode 11: SSB modulation mode, 4× interpolation, NCO running at 320 MHz, f_OUT= 100 MHz, maximum operating condition

ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS)⁽¹⁾

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V,

IOUT_FS= 20 mA, external clock mode, differential transformer-coupled output, 50-Ω doubly terminated load (unless otherwise

noted)

PARAMETER

Analog Output

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_CLK

Maximum output update rate

500

MSPS

ns

t_s(DAC)

t_pd

t_r(IOUT)

t_f(IOUT)

Output settling time to 0.1% Mid-scale transition

Output propagation delay

12

2.5

ns

(2)

Output rise time 10% to 90%

ns

Output fall time 90% to 10%

ns

AC Performance—1:1 Impedance-Ratio Transformer

First Nyquist zone < f_DATA/2, 4× interpolation, dual DAC mode,

f_DATA= 52 MSPS, f_OUT= 14 MHz, T_A= 25°C

89

79

First Nyquist zone < f_DATA/2, 4× interpolation, dual DAC mode,

f_DATA= 160 MSPS, f_OUT= 20 MHz, full bypass,T_A= T_MINto

T_MAXfor MIN, 25°C for TYP, IOVDD = 1.8 V for TYP

68

SFDR

Spurious free dynamic range

dBc

2× interpolation, dual DAC mode, f_DATA= 160 MSPS, f_OUT

41 MHz, T_A= 25°C, IOVDD = 1.8 V

=

72

68

2× interpolation, dual DAC mode, f_DATA= 160 MSPS, f_OUT

61 MHz, T_A= 25°C, IOVDD = 1.8 V

=

(1) Specifications subject to change without notice

(2) Measured single-ended into 50-Ω load

8

DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V,

IOUT_FS= 20 mA, external clock mode, differential transformer-coupled output, 50-Ω doubly terminated load (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

First Nyquist zone < f_DATA/2, f_DATA= 100 MSPS,

f_OUT= 5 MHz, IOVDD = 1.8 V, f_DAC= 400 MSPS

80

SNR

Signal-to-noise ratio

dB

First Nyquist zone < f_DATA/2, f_DATA= 78 MSPS,

f_OUT= 15.6 MHz, 15.8 MHz, 16.2 MHz, 16.4 MHz,

IOVDD = 1.8 V, f_DAC= 314 MSPS

72

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,

centered at IF, TESTMODEL 1, 10 ms, f_DATA= 122.88 MSPS,

baseband, dual DAC, 2× interpolation,

f_OUT= 245 MSPS

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,

centered at IF, TESTMODEL 1, 10 ms, f_DATA= 76.8 MSPS, IF

= 19.2 MHz, dual DAC, 2× interpolation,

77

76

73

72

64

f_OUT= 153.6 MSPS

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,

centered at IF, TESTMODEL 1, 10 ms, f_DATA= 122.88 MSPS,

IF = 30.72 MHz, dual DAC, 2× interpolation, f_DAC= 245 MSPS

ACLR

Adjacent channel power ratio

dB

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,

centered at IF, TESTMODEL 1, 10 ms, f_DATA= 61.44 MSPS,

IF = 61.44 MHz, quad mode, fs/4, 4×

interpolation, f_DAC= 245 MSPS

Two-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,

centered at IF, TESTMODEL 1, 10 ms, f_DATA= 122.88 MSPS,

IF = 30.72 MHz, dual DAC, 2× interpolation, f_DAC= 245 MSPS

Four-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,

centered at IF, TESTMODEL 1, 10 ms, f_DATA= 121.88 MSPS,

complex IF - 30.72 MHz, quad mode, fs/4, 4× interpolation, IF

= 92.16 MHz

f_DATA= 160 MSPS, f_OUT= 60.1 and 61.1 MHz, 2× interp-

olation,

320 MSPS, IOVDD = 1.8 V, each tone at –6 dBFS

74

84

85

Third-order two-tone

intermodulation

IMD3

IMD

dBc

f_DATA= 100 MSPS, f_OUT= 15.1 and 16.1 MHz, 2× interp-

olation,

200 MSPS, IOVDD = 1.8 V, each tone at –6 dBFS

f_DATA= 100 MSPS, f_OUT= 15.6 MHz, 15.8 MHz, 16.2 MHz,

16.4 MHz, 4× interpolation, 400 MSPS, IOVDD = 1.8 V, each

tone at –12 dBFS

Four-tone intermodulation

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)⁽¹⁾

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8

V, IOUT_FS= 20 mA (unless otherwise noted)

PARAMETER

CMOS Interface

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

2

0

3

0

V

0.8

40

–40

µA

pF

I_IL

5

I_L= –100 µA

I_L= –8 mA

IOVDD – 0.2

High-level output voltage,

PLLLOCK, SDO, SDIO (I/O)

V_OH

V

0.8 × IOVDD

(1) Specifications subject to change without notice.

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8

V, IOUT_FS= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_L= 100 µA

MIN

TYP

MAX

0.2

UNIT

Low-level output voltage,

PLLLOCK, SDO, SDIO (I/O)

V_OL

V

I_L= 8 mA

0.22 × IOVDD

PLL

Input data rate supported

Phase noise

1

160

MSPS

At 600-kHz offset, measured at

DAC output, 25-MHz 0-dBFS tone,

f_DATA= 125 MSPS, 4× interpolation

128

151

dBc/Hz

At 6-MHz offset, measured at DAC

output, 25-MHz 0-dBFS tone, f_DATA

= 125 MSPS, 4× interpolation

VCO minimum frequency

VCO maximum frequency

PLL_rng = 00 (nominal)

120

320

MHz

500

NCO

NCO clock (DAC update rate)

MHz

Serial Port Timing

Setup time, SDENB to rising edge

of SCLK

t_su(SDENB)

t_su(SDIO)

t_h(SDIO)

20

10

5

ns

Setup time, SDIO valid to rising

edge of SCLK

Hold time, SDIO valid to rising

edge of SCLK

t_SCLK

Period of SCLK

100

40

ns

t_SCLKH

t_SCLKL

High time of SCLK

Low time of SCLK

40

Data output delay after falling

edge of SCLK

t_d(Data)

10

ns

Parallel Data Input Timing (PLL Mode, CLK1 Input)

Setup time, data valid to rising

edge of CLK1

t_su(DATA)

0.3

1.2

–0.4

0.6

ns

Hold time, data valid after rising

edge of CLK1

t_h(DATA)

Parallel Data Input Timing (Dual Clock Mode, CLK1 and CLK2 Input)

Setup time, data valid to rising

edge of CLK1

t_su(DATA)

–0.4

0.6

ns

Hold time, data valid after rising

edge of CLK1

t_h(DATA)

Timing Parallel Data Input (External Clock Mode, CLK2 Input)

High-impedance load on PLLLOCK.

Note that t_suincreases with a

lower-impedance load.

Setup time, DATA valid to rising

edge of PLLLOCK

t_su(DATA)

4.6

3

ns

High-impedance load on PLLLOCK.

Hold time, DATA valid after rising Note that t_hdecreases (becomes

t_h(DATA)

–0.8

–2.4

edge of PLLLOCK

more negative) with a

lower-impedance load.

High-impedance load on PLLLOCK.

Note that PLLLOCK delay in-

creases with a lower-impedance

load.

Delay from CLK2 rising edge to

PLLLOCK rising edge

t_d(PLLLock)

2.5

4.2

6.5

ns

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

vs

INPUT CODE

10

8

6

4

2

0

−2

−4

−6

−8

−10

0

10000

20000

30000

Input Code

Figure 1.

40000

50000

60000

70000

DIFFERENTIAL NONLINEARITY

vs

INPUT CODE

15

13

11

9

7

5

3

1

−1

0

10000

20000

30000

Input Code

Figure 2.

40000

50000

60000

70000

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

IN-BAND SPURIOUS-FREE DYNAMIC RANGE

vs

SINGLE-TONE SPECTRUM

OUTPUT FREQUENCY

90

85

80

75

70

65

60

55

50

10

f

= 125 MSPS

f

= 125 MSPS

= 20 MHz

data

Dual DAC Mode

4y Interpolation

In-band = 0–62.5 MHz

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

IN

Dual DAC Mode

4y Interpolation

–6 dBf

0 dBf

S

–12 dBf

S

10

15

20

25

30

35

40

45

50

0

50

100

150

200

250

f

O

– Output Frequency – MHz

f – Frequency – MHz

Figure 3.

Figure 4.

OUT-OF-BAND SPURIOUS-FREE DYNAMIC RANGE

vs

OUTPUT FREQUENCY

SINGLE-TONE SPECTRUM

10

80

75

70

65

60

55

50

45

40

f

= 125 MSPS

f

= 75 MSPS

= None

data

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

Dual DAC Mode

4y Interpolation

Out-of-Band = 62.5 MHz–250 MHz

IN

NCO On

= 100 MHz

f

OUT

Quad Mode

4y Interpolation

0 dBf

S

–6 dBf

S

–12 dBf

S

0

25

50

75

100

125

150

10

15

20

25

30

35

40

45

50

f – Frequency – MHz

f

O

– Output Frequency – MHz

Figure 5.

Figure 6.

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

TWO-TONE IMD3

vs

OUTPUT FREQUENCY

TWO-TONE IMD PERFORMANCE

95

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

f

= 150 MSPS

f

= 150 MSPS

1 = 19.5 MHz

2 = 20.5 MHz

data

Dual DAC Mode

2y Interpolation

IN

90

85

80

75

70

65

Dual DAC Mode

2y Interpolation

± 0.5 MHz

± 2 MHz

10 15 20 25 30 35 40 45 50 55 60

10

15

20

25

30

f

O

– Output Frequency – MHz

f – Frequency – MHz

Figure 7.

Figure 8.

TWO-TONE IMD3

vs

OUTPUT FREQUENCY

TWO-TONE IMD PERFORMANCE

90

85

80

75

70

65

60

55

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

f

= 80 MSPS

f

= 80 MSPS

1 = –0.5 MHz

2 = 0.5 MHz

data

NCO On

Quad Mode

4y Interpolation

IN

NCO = 70 MHz

Quad Mode

4y Interpolation

± 0.5 MHz

± 2 MHz

10

30

50

70

90

110

130

150

60

65

70

75

80

f

O

– Output Frequency – MHz

f – Frequency – MHz

Figure 9.

Figure 10.

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

TWO-TONE IMD PERFORMANCE

WCDMA TEST MODEL 1: SINGLE CARRIER

−20

−30

0

f

= 122.88 MSPS

= 30.72 MHz

data

f

= 80 MSPS

1 = –0.5 MHz

2 = 0.5 MHz

data

IN

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

IN

ACLR = 78.6 dB

4y Interpolation

Dual DAC Mode

IN

−40

NCO = 150 MHz

Quad Mode

4y Interpolation

−50

−60

−70

−80

−90

−100

−110

−120

−130

18

22

26

30

34

38

42

140

145

150

155

160

f – Frequency – MHz

Figure 11.

Figure 12.

WCDMA TEST MODEL 1: DUAL CARRIER

−20

−30

−20

−30

f

= 122.88 MSPS

= 30.72 MHz

f

= 122.88 MSPS

data

= Baseband Complex

IN

data

IN

ACLR = 71.69 dB

4y Interpolation

Dual DAC Mode

ACLR = 69.08 dB

2y Interpolation

Quad Mode

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−100

−110

−120

15

20

25

30

35

40

45

46

51

56

61

66

71

76

f – Frequency – MHz

Figure 13.

Figure 14.

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

WCDMA TEST MODEL 1: FOUR CARRIER

WCDMA TEST MODEL 1: DUAL CARRIER

−10

−30

f

= 122.88 MSPS

= –30.72 MHz Complex

f

= 122.88 MSPS

= 30.72 MHz Complex

data

IN

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

ACLR = 63.29 dB

4y Interpolation

Quad Mode

ACLR = 58.58 dB

4y Interpolation

Quad Mode

−50

−70

−90

−110

72

77

82

87

92

97

102 107 112

138

143

148

153

158

163

168

f – Frequency – MHz

Figure 15.

Figure 16.

VCO GAIN

vs

VCO FREQUENCY

600

500

400

300

200

100

Boost for 0%

Boost for 45%

Boost for 30%

Boost for 15%

0

100

200

300

400

500

600

700

f

– VCO Frequency – MHz

VCO

Figure 17.

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DETAILED DESCRIPTION

Dual-Channel Mode

In dual-channel mode, interpolation filtering increases the DAC update rate, thereby reducing sinx/x rolloff and

enabling relaxed analog post-filtering, and is useful for baseband I and Q modulation or two-channel low-IF

signals. The dual-channel mode is set by mode[1:0] = 00 in the config_lsb register. Figure 18 shows the data

path architecture in dual-channel mode. The A- and B-data paths, which are independent, consist of four

cascaded half-band interpolation filters, followed by an optional inverse sinc filter. Interpolation filtering is

selected as 2×, 4×, 8×, or 16× by sel[1:0] in the config_lsb register. Magnitude spectral responses of each filter

are presented following in the section on digital filtering. Full bypass of all the interpolation filters is selected by

fbypass in the config_lsb register. The inverse sinc filter is intended for use in single-sideband and quadrature

modulation modes and is of limited benefit in dual-channel mode.

A

F

2 – 16 y F

data

Offset

FIR1

FIR2

FIR3

FIR4

FIR5

DEMUX

16F

2F

data

4F

data

8F

data

IOUTA1

IOUTA2

x

16-Bit

DAC

sin(x)

y 2

DA[15:0]

DB[15:0]

A Gain

B Gain

FIR1

FIR2

FIR3

FIR4

FIR5

16F

2F

data

4F

data

8F

data

IOUTB1

IOUTB2

x

16-Bit

DAC

sin(x)

y 2

B

Offset

Figure 18. Data Path in Dual-Channel Mode

Single-Sideband Mode

Single-sideband (SSB) mode provides optimum interfacing to analog quadrature modulators. The SSB mode is

selected by mode[1:0] = 01 in the config_lsb register. Figure 19 shows the data path architecture in

single-sideband mode. Complex baseband I and Q are input to the DAC5686, which in turn performs a complex

mix, resulting in Hilbert transform pairs at the outputs of the DAC5686's two DACs. NCO mixing frequencies are

programmed through 32-bit freq (4 registers); 16-bit phase adjustments are programmed through phase (2

registers). The NCO operates at the DAC update rate; thus, increased amounts of interpolation allow for higher

IFs. More details for the NCO are provided as follows. For mixing to F_dac/4, DAC5686 provides a specific

architecture that exploits the {… –1 0 1 0 …} resultant streams from sin and cos; the NCO is shut off in this mode

to conserve power. F_dac/4 mix mode is implemented by deasserting nco in register config_msb while in

single-sideband or quadrature modulation mode.

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

F

data

cos

DEMUX

A

2 – 16 y F

data

Offset

+

y 2 – y 16

FIR5

DA[15:0]

DB[15:0]

A

x

IOUTA1

IOUTA2

16-Bit

DAC

sin

sin(x)

+/−

A Gain

y 2 – y 16

+

B Gain

B

x

IOUTB1

IOUTB2

16-Bit

DAC

cos

sin(x)

+

B

Offset

Figure 19. Data Path in SSB Mode

Figure 20 shows the DAC5686 interfaced to an RF quadrature modulator. The outputs of the complex mixer

stage can be expressed as:

A(t) = I(t)cos(ω_ct) – Q(t)sin(ω_ct) = m(t)

B(t) = I(t)sin(ω_ct) + Q(t)cos(ω_ct) = m_h(t)

where m(t) and m_h(t) connote a Hilbert transform pair. Upper single-sideband up-conversion is achieved at the

output of the analog quadrature modulator, whose output is expressed as:

IF(t) = A(t)cos(ω_c+ ω₁)t – B(t)sin(ω_c+ ω₁)t

Flexibility is provided to the user by allowing for the selection of –B(t) out, which results in lower-sideband

up-conversion. This option is selected by ssb in the config_msb register. Figure 21 depicts the magnitude

spectrum along the signal path during single-sideband up-conversion for real input. Further flexibility is provided

to the user by allowing for the inverse of sin to be used in the complex mixer by programming rspect in the

config_usb register. The four combinations of rspect and ssb allow the user to select one of four complex

spectral bands to input to a quadrature modulator (see Figure 22).

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

cos(ω t)

DAC5686

c

I

+

A(t) = I(t)cos(ω t) – Q(t)sin(ω t)

c

A

sin(ω t)

c

DAC

−

Q

cos(ω t)

LO

IF(t) = I(t)cos(ω + ω )t

c

LO

–sin(ω t)

c

– Q(t)sin(ω + ω )t

c

LO

+

0°

Quadrature

Modulator

90°

–cos(ω t)

c

sin(ω t)

LO

B

LO

B(t) = –I(t)sin(ω t) – Q(t)cos(ω t)

c

Figure 20. DAC5686 in SSB Mode With Quadrature Modulator

Real Input

Spectrum

to DAC5686

ω

0

Complex Input

Spectrum

to Quadrature Modulator

ω

c

Output Spectrum

to Quadrature Modulator

ω

– ω

ω

+ ω

LO c

LO

c

LO

Figure 21. Spectrum After First and Second Up-Converson for Real Input

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DETAILED DESCRIPTION (continued)

Complex Input

Spectrum

to DAC5686

0

ω

Complex Input

Spectrums

to Quadrature

rspect = 0

ssb = 0

–ω

ω

c

Modulator

rspect = 0

ssb = 1

–ω

ω

0

c

rspect = 1

ssb = 1

–ω

ω

c

rspect = 1

ssb = 0

–ω

ω

0

c

Figure 22. Spectrum After First and Second Up-Converson for Complex Input

To compensate for the sinx/x rolloff of the zero-order hold of the DACs, the DAC5686 provides an inverse sinc

FIR, which provides high-frequency boost. The magnitude spectral response of this filter is presented in the

Digital Filters section.

DAC Gain and Offset Control

Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local-oscillator

feedthrough. Gain and offset imbalances between the two DACs are compensated for by programming

daca_gain, dacb_gain, daca_offset, and dacb_offset in registers 0x0A through 0x0F (see the following

register descriptions). The DAC gain value controls the full-scale output current. The DAC offset value adds a

digital offset to the digital data before digital-to-analog conversion. Care must be taken when using the offset by

restricting the dynamic range of the digital signal to prevent saturation when the offset value is added to the

digital signal.

Quadrature Modulation Mode

In quadrature modulation mode, on-chip mixing of complex I and Q inputs provides the final baseband-to-IF

up-conversion. Quadrature modulation mode is selected by mode[1:0] = 10 in the config_lsb register. Figure 23

shows the data path architecture in quadrature modulation mode. Complex baseband I and Q from the

ASIC/FPGA are input to the DAC5686, which in turn quadrature modulates I and Q to produce the final IF

single-sideband spectrum. DAC A is held constant, while DAC B presents the DAC5686 quadrature modulator

mode output.

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DETAILED DESCRIPTION (continued)

NCO mixing frequencies are programmed through 32-bit freq (4 registers); 16-bit phase adjustments are

programmed through phase (2 registers). The NCO operates at the DAC update rate; thus, increased amounts

of interpolation allow for higher IFs. More details for the NCO are provided in the NCO section. For mixing to

F_dac/4, the DAC5686 provides a specific architecture that exploits the {… –1 0 1 0 …} resultant streams from sin

and cos; the NCO is shut off in this mode to conserve power. F_dac/4 mix mode is implemented by deasserting

nco in register config_msb while in single-sideband or quadrature modulation mode.

cos

sin

F

data

FIR1

FIR2

FIR3

FIR4

DEMUX

2 – 16 y F

data

y 2

+

DA[15:0]

DB[15:0]

FIR5

IOUTB1

IOUTB2

x

16-Bit

DAC

sin(x)

FIR1

FIR2

FIR3

FIR4

+/−

B

B Gain

Offset

y 2

sin

cos

Figure 23. Data Path in Quadrature Modulation Mode

In quadrature modulation mode, only one output from the complex mixer stage is routed to the B DAC. The

output can be expressed as:

B(t) = I(t)sin(ω_ct) + Q(t)cos(ω_ct)

or

B(t) = I(t)cos(ω_ct) – Q(t)sin(ω_ct)

Single-sideband up-conversion is achieved when I and Q are Hilbert transform pairs. Upper- or lower-sideband

up-conversion is selected by ssb in the config_msb register, which selects the output from the mixer stage that

is routed out.

The offset and gain features for the B DAC, as previously described, are functional in the quadrature mode.

Serial Interface

The serial port of the DAC5686 is a flexible serial interface that communicates with industry-standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of the DAC5686. It is compatible with most synchronous transfer formats and can be configured

as a 3- or 4-pin interface by sif4 in register config_msb. In both configurations, SCLK is the serial-interface

input clock and SDENB is the serial-interface enable. For the 3-pin configuration, SDIO is a bidirectional pin for

both data-in and data-out. For the 4-pin configuration, SDIO is data-in only and SDO is data-out only.

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DETAILED DESCRIPTION (continued)

Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle, which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to/from

which to transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a

detailed description of each bit. Frame bytes 2 through 5 comprise the data to be transferred.

Table 1. Instruction Byte of the Serial Interface

MSB

7

LSB

0

Bit

6

5

4

–

3

2

1

Description

R/W

N1

N0

A3

A2

A1

A0

R/W: Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation

from the DAC5686 and a low indicates a write operation to the DAC5686.

N[1:0]: Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB-first.

Table 2. Number of Transferred Bytes Within One

Communication Frame

N1

0

N0

0

DESCRIPTION

Transfer 1 byte

Transfer 2 bytes

Transfer 3 bytes

Transfer 4 bytes

0

1

0

1

A4: Unused

A[3:0]: Identifies the address of the register to be accessed during the read or write operation. For multibyte

transfers, this address is the starting address and the address decrements. Note that the address is written to the

DAC5686 MSB-first.

Serial-Port Timing Diagrams

Figure 24 shows the serial-interface timing diagram for a DAC5686 write operation. SCLK is the serial-interface

clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial

data-in. Input data to the DAC5686 is clocked on the rising edges of SCLK.

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Instruction Cycle

Data Transfer Cycle(s)

SDENB

SCLK

SDIO

R/W N1 N0

−

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

t

s(SDENB)

t

SCLK

SDENB

SCLK

SDIO

t

SCLKL

s(SDIO)

t

SCLKH

h(SDIO)

Figure 24. Serial-Interface Write Timing Diagram

Figure 25 shows the serial-interface timing diagram for a DAC5686 read operation. SCLK is the serial-interface

clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial

data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the

data transfer cycle(s), while SDO is in a high-impedance state. In the 4-pin configuration, SDO is data-out from

the DAC5686 during the data transfer cycle(s). SDO is never placed in the high-impedance state in the four-pin

configuration.

Data Transfer Cycle(s)

Instruction Cycle

SDENB

SCLK

SDIO

N1 N0

−

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

0

R/W

SDO

4-Pin Configuration 3-Pin Configuration

Output Output

SDENB

SCLK

SDIO

SDO

Data n

Data n−1

t

d(Data)

Figure 25. Serial-Interface Read Timing Diagram

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Clock Generation

In the DAC5686, the internal clocks (1×, 2×, 4×, 8×, and 16×, as needed) for the logic, FIR interpolation filters,

and DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or the

DAC output sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) is

separate from power for the other clock generation blocks (CLKVDD and CLKGND), thus minimizing phase noise

within the PLL.

The DAC5686 has three clock modes for generating the internal clocks (1×, 2×, 4×, 8×, and 16×, as needed) for

the logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in

register config_usb. A block diagram for the clock generation circuit is shown in Figure 27.

1. PLLVDD = 0V and dual_clk = 0: EXTERNAL CLOCK MODE

In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through

CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used, so the LPF circuit is not applicable. The input

data rate clock and interpolation rate are selected by the registers sel[1:0], and are output through the

PLLLOCK pin. It is common to use the PLLLOCK clock to drive the chip that sends the data to the DAC;

otherwise, there is phase ambiguity regarding how the DAC divides down to the input sample rate clock and

an external clock divider divides down. (For a divide by N, there are N possible phases.) The phase

ambiguity can also be solved by using PHSTR pin with a synchronization signal.

2. PLLVDD = 3.3V (dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE

Power for the internal PLL blocks (PLLVDD and PLLGND) is separate from power for the other clock

generation blocks (CLKVDD and CLKGND), thus minimizing PLL phase noise.

In PLL CLOCK MODE, the DAC is driven at the input sample rate (unless the data is multiplexed) through

CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC

generates the higher speed DAC sample rate clock using an internal PLL/VCO. In PLL clock mode, the user

provides a differential external reference clock on CLK1/CLK1C.

A type-4 phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback

clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is

generated by dividing the VCO output by 1×, 2×, 4×, or 8× as selected by the prescaler (div[1:0]). The output

of the prescaler is the DAC sample rate clock and is divided down to generate clocks at ÷2, ÷4, ÷8, and ÷16.

The feedback clock is selected by the registers sel[1:0], an then is fed back to the PFD for synchronization

to the input clock. The feedback clock is also used for the data input rate, so the ratio of DAC output clock to

feedback clock sets the interpolation rate of the DAC5686. The PLLLOCK pin is an output that indicates

when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user at pin LPF. See

the low-pass filter section for filter setting calculations. This is the only mode where the LPF filter applies.

3. PLLVDD = 0V and dual_clk = 1: DUAL CLOCK MODE

In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and at the input

data rate through CLK1/CLK1C. The DUAL CLOCK MODE has the advantage of a clean external clock for

the DAC sampling without the phase ambiguity. The edges of CLK1 and CLK2 must be aligned to within

±t_{_align}(See Figure 26), defined as

1

t_{_align}

+

* 0.5 ns

2F_CLK2

where F_CLK2is the clock frequency of CLK2. For example, t_{_align}= 0.5 ns at F_CLK2= 500 MHz and 1.5 ns at

F_CLK2= 250 MHz.

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

CLK2

CLK1

∆ < t

align

D[0:15]

t

h

t

s

T0002-01

Figure 26. DAC and Data Clock Mode

The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different

frequencies for this application.

Table 3 provides a summary of the clock configurations with corresponding data rate ranges.

LPF

DIV[1:0] PLLVDD

CLK1

/1

Charge

Pump

/2

/4

/8

CLK1C

clk_16x

DAC

Sample

Clock

pfd

vco

Clk Buffer

CLK2

CLK2C

clk_8x

clk_4x

clk_2x

clk_1x

/2

PLLVDD

PLLGND

0

CLKVDD

CLKGND

1

s

Data

PLLLOCK

PLLVDD

D[15:0]

SEL[1:0]

Figure 27. Clock-Generation Architecture

Table 3. Clock-Mode Configuration

CLOCK MODE

PLLVDD

DIV[1:0]

SEL[1:0]

DATA RATE (MSPS)

PLLLOCK PIN FUNCTION

Non-interleaved input data; internal PLL off; DA[15:0] data rate matches DB[15:0] data rate.

External 2×

External 4×

0 V

XX

00

01

10

11

00

01

DC to 160

DC to 125

DC to 62.5

DC to 31.25

DC to 160

DC to 125

External clk2/clk2c clock ÷ 2

External clk2/clk2c clock ÷ 4

External clk2/clk2c clock ÷ 8

External clk2/clk2c clock ÷ 16

None - held low

External 8×

External 16×

External dual clock 2×

External dual clock 4×

None - held low

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Table 3. Clock-Mode Configuration (continued)

CLOCK MODE

PLLVDD

0 V

DIV[1:0]

XX

SEL[1:0]

DATA RATE (MSPS)

DC to 62.5

PLLLOCK PIN FUNCTION

None - held low

External dual clock 8×

External dual clock 16×

10

11

0 V

XX

DC to 31.25

None - held low

Interleaved input data on the DA[15:0] input pins; internal PLL off

External 2×

External 4×

0 V

XX

00

01

10

11

00

01

10

11

DC to 80

External clk2/clk2c clock ÷ 2

External clk2/clk2c clock ÷ 4

External clk2/clk2c clock ÷ 8

External clk2/clk2c clock ÷ 16

None - held low

External 8×

DC to 62.5

DC to 31.25

DC to 80

External 16×

External dual clock 2×

External dual clock 4×

External dual clock 8×

External dual clock 16×

DC to 62.5

DC to 31.25

DC to 15.625

None - held low

Non-interleaved input data; internal PLL on; DA[15:0] data rate matches DB[15:0] data rate.

Internal 2×

Internal 4×

Internal 8×

Internal 16×

3.3 V

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

00

01

10

11

125 to 160

62.5 to 125

Internal PLL lock indicator

31.25 to 62.5

15.63 to 31.25

62.5 to 125

31.25 to 62.5

15.63 to 31.25

7.8125 to 15.625

31.25 to 62.5

15.63 to 31.25

7.8125 to 15.625

3.9 to 7.8125

15.625 to 31.25

7.8125 to 15.625

3.9062 to 7.8125

Interleaved input data on the DA[15:0] input pins; internal PLL on

Internal 2×

Internal 4×

Internal 8×

Internal 16×

3.3 V

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

Not recommended

62.5 to 80

Internal PLL lock indicator

31.25 to 62.5

15.625 to 31.25

62.5 to 80

31.25 to 62.5

15.625 to 31.25

7.8125 to 15.625

31.25 to 62.5

15.625 to 31.25

7.8125 to 15.625

3.9062 to 7.8125

15.625 to 31.25

7.8125 to 15.625

3.9062 to 7.8125

1.9531 to 3.9062

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

Dual-Bus Mode

In dual-bus mode, two separate parallel data streams (I and Q) are input to the DAC5686 on data bus DA and

data bus DB. Dual-bus mode is selected by setting INTERL to 0 in the config_msb register. Figure 28 shows

the DAC5686 data path in dual-bus mode. The dual-bus mode timing diagram is shown in Figure 29 for the PLL

clock mode and in Figure 30 for the external clock mode.

2 – 16 y F

data

F

data

FIR1

DEMUX

IOUTA1

IOUTA2

2F

data

16-Bit

DAC

• • •

y 2

DA[15:0]

DB[15:0]

Edge Triggered

Input Latches

IOUTB1

IOUTB2

2F

data

16-Bit

DAC

• • •

y 2

Figure 28. Dual-Bus Mode Data Path

CLK1

t

s(DATA)

t

h(DATA)

A

1

A

B

A

B

A

B

A

B

DA[15:0]

DB[15:0]

0

2

3

N

N+1

B

0

B

1

2

3

N

N+1

Figure 29. Dual-Bus Mode Timing Diagram (PLL Mode)

PLLLOCK

CLK2

t

d(PLLLOCK)

t

s(DATA)

t

h(DATA)

A

B

A

1

A

B

A

B

A

B

A

N+1

DA[15:0]

DB[15:0]

0

2

3

N

B

1

B

N+1

0

2

3

N

Figure 30. Dual-Bus Mode Timing Diagram (External Clock Mode)

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

Interleave Bus Mode

In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5686 on data

bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 31 shows

the DAC5686 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 32.

2 – 16 y F

data

F

data

FIR1

IOUTA1

IOUTA2

2F

data

16-Bit

DAC

• • •

y 2

DEMUX

DA[15:0]

Edge Triggered

Input Latches

IOUTB1

IOUTB2

2F

data

16-Bit

DAC

• • •

y 2

Figure 31. Interleave Bus Mode Data Path

TxENABLE

t

s(TxENABLE)

CLK1 or

PLLLOCK

t

s(DATA)

t

h(DATA)

A

0

B

0

A

1

B

1

A

N

B

N

DA[15:0]

Figure 32. Interleave Bus Mode Timing Diagram Using TxENABLE

Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels

A and B can be synchronized using either the QFLAG pin or the TxENABLE pin. When qflag in register

config_usb is 0, transitions on TxENABLE identify the interleaved data sequence. The first data after the rising

edge of TxENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed

to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an output

to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 33).

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

QFLAG

CLK1 or

PLLLOCK

t

h(DATA)

t

s(DATA)

A

0

B

0

A

1

B

1

A

N

B

N

DA[15:0]

T0001-01

Figure 33. Interleave Bus Mode Timing Diagram Using QFLAG

The dual-clock mode is selected by setting dualclk high in the config_usb register. In this mode, the DAC5686

uses both clock inputs; CLK1/CLK1C is the input data clock, and CLK2/CLK2C is the external clock. The edges

of the two input clocks must be phase-aligned within ±500 ps to function properly.

Clock Synchronization Using the PHSTR Pin in External Clock Mode

In external clock mode, the DAC5686 is clocked at the DAC output sample frequency (CLK2 and CLK2C). For an

interpolation rate N, there are N possible phases for the DAC input clock on the PLLLOCK pin (see Figure 34 for

N = 4).

CLK2

CLK2C

PLLLOCK

T0003-01

Figure 34. Four Possible PLLLOCK Phases for N = 4 in External Clock Mode

To synchronize PLLLOCK input clocks across multiple DAC5686 chips, a sync signal on the PHSTR pin is used.

During configuration of the DAC5686 chips, address sync_phstr in config_msb is set high to enable the

PHSTR input pin as a sync input to the clock dividers generating the input clock. A simultaneous low-to-high

transition on the PHSTR pin for each DAC5686 then forces the input clock on PLLLOCK to start in phase on

each DAC. See Figure 35.

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DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

1/F

= N/F

CLK2

PLLLOCK

CLK2

CLK2C

PHSTR

t

h_PHSTR

t

d_CLK

t

s_PHSTR

PLLLOCK

D[0:15]

DAC1

t

h

t

s

T0004-01

Figure 35. Using PHSTR to Synchronize PLLLOCK Input Clock for Multiple DACs in External Clock Mode

The PHSTR transition has a setup and hold time relative to the DAC output sample clock (t_{s_PHSTR}and t_{h_PHSTR}

equal to 50% of the DAC output sample clock period up to a maximum of 1 ns. At 500 MHz, the setup and hold

times are therefore 0.5 ns. The PHSTR signal can remain high after synchronization, or can return low. A new

low-to-high transition resynchronizes the input clock. Note that the PHSTR transition also resets the NCO

accumulator.

)

Digital Filters

Figure 36 through Figure 39 show magnitude spectrum responses for 2×, 4×, 8×, and 16× FIR interpolation

filtering. The transition band is from 0.4 to 0.6 f_DATAwith < 0.002-dB pass-band ripple and > 80-dB stop-band

attenuation for all four configurations. The filters are linear phase. The sel field in register config_lsb selects the

interpolation filtering rate as 2×, 4×, 8×, or 16×; interpolation filtering can be completely bypassed by setting

fullbypass in register config_lsb.

Figure 40 shows the spectral correction of the DAC sinx/x rolloff achieved with use of inverse sinc filtering.

Pass-band ripple from 0 to 0.4 f_DATAis < 0.03 dB. Inverse sinc filtering is enabled by sinc in register

config_msb.

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DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

MAGNITUDE

vs

FREQUENCY

MAGNITUDE

vs

FREQUENCY

20

0

20

0

−20

−40

−60

−80

−100

−120

−140

−160

−20

−40

−60

−80

−100

−120

−140

−160

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

f/F

Data

f/F

Data

Figure 36. Magnitude Spectrum for

Figure 37. Magnitude Spectrum for

2× Interpolation (dB)

4× Interpolation (dB)

MAGNITUDE

vs

FREQUENCY

MAGNITUDE

vs

FREQUENCY

20

0

20

0

−20

−40

−60

−80

−100

−120

−140

−160

−20

−40

−60

−80

−100

−120

−140

−160

0.0

0.5

1.0

1.5

2.0

f/F

2.5

3.0

3.5

4.0

0

1

2

3

4

5

6

7

8

f/F

Data

Figure 38. Magnitude Spectrum for

Figure 39. Magnitude Spectrum for

8× Interpolation (dB)

16× Interpolation (dB)

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

MAGNITUDE

vs

FREQUENCY

5

4

3

FIR

2

Corrected

1

0

−1

−2

−3

−4

−5

Rolloff

0.0

0.1

0.2

0.3

0.4

0.5

f/F

DAC

Figure 40. Magnitude Spectrum for Inverse Sinc Filtering

The filter taps for interpolation filters FIR1 - FIR4 and inverse sinc filter FIR5 are listed in Table 4.

Table 4. Filter Taps for FIR1–FIR5

FIR1

8

FIR2

9

FIR3

31

FIR4

-33

0

FIR5 (INVSINC)

1

–3

9

0

–24

0

–58

0

–219

0

289

512

289

0

–34

400

–34

9

58

214

0

1212

2048

1212

0

–120

0

–638

0

–33

–3

1

221

0

2521

4096

2521

0

–219

0

–380

0

31

619

0

–638

0

-971

0

214

0

1490

0

–58

0

–2288

0

9

3649

0

–6628

0

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

Table 4. Filter Taps for FIR1–FIR5 (continued)

FIR1

20750

32768

20750

0

FIR2

FIR3

FIR4

FIR5 (INVSINC)

–6628

0

3649

0

–2288

0

1490

0

–971

0

619

0

–380

0

221

0

–120

0

58

0

–24

0

8

NCO

The DAC5686 uses a numerically controlled oscillator (NCO) with a 32-bit frequency register and a 16-bit phase

register. The NCO is used in quadrature-modulation and single-sideband modes to provide sin and cos for

mixing. The NCO tuning frequency is programmed in registers 0x1 through 0x4. Phase offset is programmed is

registers 0x5 and 0x6. A block diagram of the NCO is shown in Figure 41.

32

16

sin

32

16

Accumulator

CLK RESET

Look-Up

Table

Frequency

Register

Σ

16

cos

16

F

DAC

Phase

Register

PHSTR

Figure 41. Block Diagram of the NCO

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

The NCO accumulator is reset to zero when the PHSTR pin is high and remains at zero until PHSTR is set low.

Frequency word freq in the frequency register is added to the accumulator every clock cycle. The output

frequency of the NCO is:

freq F_DAC

f_NCO

+

2³²

While the maximum clock frequency of the DACs is 500 MSPS, the maximum clock frequency the NCO can

operate at is 320 MHz; mixing at DAC rates higher than 320 MSPS requires using the fs/4 mixing option.

Register Bit Allocation Map

NAME

R/W

AD-

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DRESS

chip_ver

R/W

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

atest[4:0]

version[2:0] read only

freq_lsb

freq_int[7:0]

freq_lmidsb

freq_umidsb

freq_msb

freq_int[15:8]

freq_int[23:16]

freq_int[31:24]

phase_int[7:0]

phase_int[15:8]

phase_lsb

phase_msb

config_lsb

mode[1:0]

div[1:0]

sel[1:0]

sync_phstr

qflag

counter

sif4

fbypass

config_msb

config_usb

daca_offset_lsb

daca_gain_lsb

ssb

interl

sinc

dith

nco

twos

dual clk

dds_gain[1:0]

rspect

pll_rng[1:0]

rev_bbus

daca_offset[7:0]

daca_gain[7:0]

daca_offset_gain_

msb

daca_offset[10:8]

dacb_offset[10:8]

sleepA

daca_gain[11:8]

dacb_gain[11:8]

dacb_offset_lsb

dacb_gain_lsb

R/W

0x0D

0x0E

0x0F

dacb_offset[7:0]

dacb_gain[7:0]

dacb_offset_gain_

msb

sleepB

REGISTER DESCRIPTIONS

Register Name: chip_ver

MSB

0

LSB

1

atest[4:0]

0

chip_ver[2:0] read only

0

1

0

chip_ver[3:0]: chip_ver [3:0] stores the device version, initially 0x5. The user can find out which version of the

DAC5686 is in the system by reading this byte.

a_test[4:0]: must be 0 for proper operation.

Register Name: freq_lsb

MSB

0

LSB

0

freq_int[7:0]

0

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

freq_int[7:0]: The lower 8 bits of the frequency register in the DDS block

Register Name: freq_lmidsb

MSB

LSB

0

freq_int[15:8]

0

freq_int[15:8]: The lower mid 8 bits of the frequency register in the DDS block

Register Name: freq_umidsb

MSB

LSB

0

freq_int[23:16]

0

freq_int[23:16]: The upper mid 8 bits of the frequency register in the DDS block

Register Name: freq_msb

MSB

LSB

0

freq_int[31:24]

0

1

0

freq_int[31:24]: The most significant 8 bits of the frequency register in the DDS block

Register Name: phase_lsb

MSB

LSB

0

phase_int[7:0]

0

phase_int[7:0]: The lower 8 bits of the phase register in the DDS block

Register Name: phase_msb

MSB

LSB

0

phase_int[15:8]

0

phase_int[15:8]: The most significant 8 bits of the phase register in the DDS block

Register Name: config_lsb

MSB

LSB

Full_bypass

1

mode[1:0]

div[1:0]

sel[1:0]

counter

0

mode[1:0]: Controls the mode of the DAC5686; summarized in Table 5.

Table 5. DAC5686 Modes

mode[1:0]

DAC5686 MODE

Dual-DAC

00

01

10

11

Single-sideband

Quadrature

Dual-DAC

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

div[1:0]: Controls the PLL divider value; summarized in Table 6.

Table 6. PLL Divide Ratios

div[1:0]

00

PLL DIVIDE RATIO

1× divider

01

2× divider

10

4× divider

11

8× divider

sel[1:0]: Controls the selection of interpolating filters used; summarized in Table 7.

Table 7. DAC5686 Filter Configuration

sel[1:0]

00

INTERP. FIR SETTING

×2

× 4

01

10

× 8

11

× 16

counter: When asserted, the DAC5686 goes into counter mode and uses an internal counter as a ramp input to

the DAC. The count range is determined by the A-side input data DA[2:0], as summarized in Table 8.

Table 8. DAC5686 Counter Mode Count Range

DA[2:0]

000

COUNT RANGE

All bits D[15:0]

001

Lower 7 bits D[6:0]

Mid 4 bits D[10:7]

Upper 5 bits D[15:11]

010

100

Full_bypass: When asserted, the interpolation filters and mixer logic are bypassed and the data inputs DA[15:0]

and DB[15:0] go straight to the DAC inputs.

Register Name: config_msb

MSB

ssb

0

LSB

twos

0

interl

0

sinc

0

dith

0

sync_phstr

0

nco

0

sif4

0

ssb: In single-sideband mode, assertion inverts the B data; in quadrature modulation mode, assertion routes the

A data path to DACB instead of the B data path.

interl: When asserted, data input to the DAC5686 on channel DA[15:0] is interpreted as a single interleaved

stream (I/Q); channel DB[15:0] is unused.

sinc: Assertion enables the INVSINC filter.

dith: Assertion enables dithering in the PLL.

sync_phstr: Assertion enables the PHSTR input as a sync input to the clock dividers in external single-clock

mode.

nco: Assertion enables the NCO.

sif4: When asserted, the sif interface becomes a 4-pin interface instead of a 3-pin interface. The SDIO pin

becomes an input only and the SDO is the output.

twos: When asserted, the chip interprets the input data as 2s complement form instead of binary offset.

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Register Name: config_usb

MSB

LSB

rev_bbus

0

dualclk

0

DDS_gain[1:0]

rspect

0

qflag

0

pll_rng[1:0]

0

dualclk: When asserted, the DAC5686 uses both clock inputs; CLK1/CLK1C is the input data clock and

CLK2/CLK2C is the DAC output clock. These two clocks must be phase-aligned within ±500 ps to function

properly. When deasserted, CLK2/CLK2C is the DAC output clock and is divided down to generate the input data

clock, which is output on PLLLOCK. Dual clock mode is only available when PLLVDD = 0.

DDS_gain[1:0]: Controls the gain of the DDS so that the overall gain of the DDS is unity. It is important to

ensure that max(abs(cos(ωt) + sin(ωt))) < 1. At different frequencies, the summation produces different maximum

outputs and must be reduced. The simplest is fs/4 mode where the maximum is 1 and the gain multiply should

be 1 to maintain unity. However, due to the fact that the digital logic does a divide-by-two in this summation, the

gain necessary to achieve unity must be double (DDS_gain[1:0] = 01). Table 9 shows the digital gain necessary

and the actual signal gain needed to make the above equation have a maximum value of 1.

Table 9. Digital Gain for DDS

DDS_gain [1:0]

DIGITAL GAIN

1.40625

2

SIGNAL GAIN FOR UNITY

00

01

10

11

0.703125

1

1.59375

1.40625

0.7936

0.703125

rspect: When asserted, the sin term is negated before being used in mixing. This gives the reverse spectrum in

single-sideband mode.

qflag: When asserted, the QFLAG pin is used during interleaved data input mode to identify the Q sample. When

deasserted, the TXENABLE pin transition is used to start an internal toggling signal, which is used to interpret

the interleaved data sequence; the first sample clocked into the DAC5686 after TXENABLE goes high is routed

through the A data path.

PLL_rng[1:0]: Increases the PLL VCO VtoI current, summarized in Table 10. See Figure 17 for the effect on

VCO gain and range.

Table 10. PLL VCO Vtol Current Increase

PLL_rng[1:0]

VtoI CURRENT INCREASE

00

01

10

11

nominal

15%

30%

45%

rev_bbus[1:0]: When asserted, pin 92 changes from DB15 to DB0, pin 91 changes from DB14 to DB1, etc.,

reversing the order of the DB[15:0] pins.

Register Name: daca_offset_lsb (2s complement)

MSB

0

LSB

0

daca_offset[7:0]

0

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daca_offset[7:0]: The lower 8 bits of the DACA offset

Register Name: daca_gain_lsb (2s complement)

MSB

LSB

0

daca_gain[7:0]

0

daca_gain[7:0]: The lower 8 bits of the DACA gain control register. These lower 8 bits are for fine gain control.

This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%

range.

Register Name: daca_offset_gain_msb (2s complement)

MSB

0

LSB

0

daca_offset[10:8]

0

sleepa

0

daca_gain[11:8]

0

daca_offset[10:8]: The upper 3 bits of the DACA _offset

sleepa: When asserted, DACA is put into the sleep mode.

daca_gain[11:8]: Coarse gain control for DACA; the full-scale output current is:

ǒ

Ǔ

16 V_extio

(GAINCODE ) 1)

FINEGAIN

3072

_Bǒ_{1 *}

Ǔ

ƫ

I_fullscale

+

ƪ

16

R_biasj

where GAINCODE is the decimal equivalent of daca_gain [11:8] {0…15} and the FINEGAIN is daca_gain [1:0] as

2s complement [–127…128].

Register Name: dacb_offset_lsb (2s complement)

MSB

0

LSB

0

dacb_offset[7:0]

0

dacb_offset[7:0]: The lower 8 bits of the DACB offset

Register Name: dacb_gain_lsb (2s complement)

MSB

0

LSB

0

dacb_gain[7:0]

0

dacb_gain[7:0]: The lower 8 bits of the DACB gain control register. These lower 8 bits are for fine gain control.

This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%

range.

Register Name: dacb_offset_gain_msb (2s complement)

MSB

0

LSB

0

dacb_offset[10:8]

0

sleepb

0

dacb_gain[11:8]

0

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dacb_offset[10:8]: The upper 3 bits of the DACA _offset

sleepb: When asserted, DACB is put into the sleep mode.

dacb_gain[11:8]: Coarse gain control for DACB; the full-scale output current is:

ǒ

Ǔ

16 V_extio

(GAINCODE ) 1)

FINEGAIN

3072

_Bǒ_{1 *}

Ǔ

ƫ

I_fullscale

+

ƪ

16

R_biasj

where GAINCODE is the decimal equivalent of dacb_gain [11:8] {0…15} and the FINEGAIN is dacb_gain [1:0] as

2s complement [–127…128].

DIGITAL INPUTS

Figure 42 shows a schematic of the equivalent CMOS digital inputs of the DAC5686. DA[0:15], DB[0:15], SLEEP,

PHSTR, TxENABLE, QFLAG, SDIO, SCLK, and SDENB have pulldown resistors and RESETB has a pullup

resistor internal to the DAC5686. See the specification table for logic thresholds.

IOVDD

DA[15:0]

DB[15:0]

SLEEP

PHSTR

TxENABLE

QFLAG

SDIO

Internal

Digital In

Internal

Digital In

RESETB

SCLK

SDENB

IOGND

Figure 42. CMOS/TTL Digital Equivalent Input

CLOCK INPUT AND TIMING

Figure 43 shows an equivalent circuit for the clock input.

CLKVDD

R1

Internal

10 kΩ

Digital In

CLK

CLKC

R2

10 kΩ

CLKGND

Figure 43. Clock Input Equivalent Circuit

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CLOCK INPUT AND TIMING (continued)

Figure 44, Figure 45, and Figure 46 show various input configurations for driving the differential clock input

(CLK/CLKC).

Optional, May Be Bypassed

for Sine Wave Input

Swing Limitation

C

AC

0.1 µF

1:4

CLK

R

T

200 Ω

CLKC

Termination Resistor

Figure 44. Preferred Clock Input Configuration

C

AC

R

opt

R

opt

0.01 µF

22 Ω

1:1

TTL/CMOS

Source

TTL/CMOS

CLK

Source

Optional, Reduces

Clock Feed-Through

CLKC

0.01 µF

Node CLKC Internally Biased

to CLKVDDń2

Figure 45. Driving the DAC5686 With a Single-Ended TTL/CMOS Clock Source

C

AC

0.1 µF

+

–

CLK

Differential

ECL

C

0.1 µF

or

AC

100 Ω

(LV)PECL

Source

CLKC

R

T

R

T

R

T

R

T

130 Ω

82.5 Ω

V

TT

Figure 46. Driving the DAC5686 With a Differential ECL/PECL Clock Source

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CLOCK INPUT AND TIMING (continued)

DAC Transfer Function

The CMOS DACs consist of a segmented array of NMOS current sources, capable of delivering a full-scale

output current up to 20 mA. Differential current switches direct the current of each current source to either one of

the complementary output nodes IOUT1 or IOUT2. Complementary output currents enable differential operation,

thus canceling out common-mode noise sources (digital feed-through, on-chip, and PCB noise), dc offsets,

even-order distortion components, and increasing signal output power by a factor of two.

The full-scale output current is set using external resistor R_BIASin combination with an on-chip band-gap voltage

reference source (1.2 V) and control amplifier. Current I_BIASthrough resistor R_BIASis mirrored internally to provide

a full-scale output current equal to 16 times I_BIAS. The full-scale current can be adjusted from 20 mA down to 2

mA.

The DAC5686 delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the

approximate full-scale output current when all bits (after the digital processing) are high. Full-scale output current

flows through terminal IOUT2 when all input bits are low. The relation between IOUT1 and IOUT2 can thus be

expressed as:

IOUT1 = IOUT_FS– IOUT2

where IOUT_FSis the full-scale output current. The output currents can be expressed as:

CODE

65536

(65536 CODE)

65536

IOUT1 + IOUT_FS

IOUT2 + IOUT_FS

where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive

resistor loads R_Lor a transformer with equivalent input load resistance (R_L). This translates into single-ended

voltages VOUT1 and VOUT2 at terminals IOUT1 and IOUT2, respectively, of:

CODE

VOUT1 + IOUT1 R_L+

65536 IOUT_FS R_L

(65536 CODE)

VOUT2 + IOUT2 R_L+

65536 IOUT_FS R_L

The differential output voltage VOUT_DIFFcan thus be expressed as:

(2CODE 65536)

65536 IOUT_FS R_L

VOUT_DIFF+ IOUT1 * VOUT2 +

The latter equation shows that applying the differential output results in doubling of the signal power delivered to

the load. Because the output currents IOUT1 and IOUT2 are complementary, they become additive when

processed differentially. Note that care should be taken not to exceed the compliance voltages at nodes IOUT1

and IOUT2, which would lead to increased signal distortion.

Reference Operation

The DAC5686 comprises a band-gap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor R_BIAS. The bias current I_BIASthrough resistor R_BIAS

is defined by the on-chip band-gap reference voltage and control amplifier. The full-scale output current equals

16 times this bias current. The full-scale output current IOUT_FScan thus be expressed as (coarse gain = 15, fine

gain = 0):

16 V_EXTIO

IOUT_FS

+

R_BIAS

,

where V_EXTIOis the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage of

1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

C_EXTof 0.1 µF should be connected externally to terminal EXTIO for compensation. The band-gap reference

additionally can be used for external reference operation. In that case, an external buffer with a high-impedance

input should be used in order to limit the band-gap load current to a maximum of 100 nA. The internal reference

can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor C_EXTmay

hence be omitted. Terminal EXTIO serves as either input or output node.

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R_BIASor changing the

externally applied reference voltage. The internal control amplifier has a wide input range supporting the

full-scale output current range of 20 dB.

Analog Current Outputs

Figure 47 shows a simplified schematic of the current source array with corresponding switches. Differential

switches direct the current of each individual NMOS current source to either the positive output node IOUT1 or

its complementary negative output node IOUT2. The output impedance is determined by the stack of the current

sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5 pF.

The external output resistors are terminated to AVDD. The maximum output compliance at nodes IOUT1 and

IOUT2 is limited to AVDD + 0.5 V, determined by the CMOS process. Beyond this value, transistor breakdown

can occur, resulting in reduced reliability of the DAC5686 device. The minimum output compliance voltage at

nodes IOUT1 and IOUT2 equals AVDD – 0.5 V. Exceeding the minimum output compliance voltage adversely

affects distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended

or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed

0.5 V.

AVDD

R

LOAD

R

LOAD

IOUT1

IOUT2

S(1)

S(1)C

S(2)

S(2)C

S(N)

S(N)C

Figure 47. Equivalent Analog Current Output

The DAC5686 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF

transformer. Figure 48 and Figure 49 show the 50-Ω doubly terminated transformer configuration with 1:1 and

4:1 impedance ratios, respectively. Note that the center tap of the primary input of the transformer must be

connected to AVDD to enable a dc current flow. Applying a 20-mA full-scale output current would lead to a

0.5-Vpp output for a 1:1 transformer and a 1-Vpp output for a 4:1 transformer.

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DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

AVDD (3.3 V)

50 Ω

1:1

IOUT1

IOUT2

R

LOAD

100 Ω

50 Ω

AVDD (3.3 V)

Figure 48. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance-Ratio Transformer

AVDD (3.3 V)

100 Ω

4:1

IOUT1

R

LOAD

50 Ω

IOUT2

100 Ω

AVDD (3.3 V)

Figure 49. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance-Ratio Transformer

SLEEP MODE

The DAC5686 features a power-down mode that turns off the output current and reduces the supply current to

less than 5 mA over the supply range of 3 V to 3.6 V and temperature range of –40°C to 85°C. The power-down

mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to IOVDD). An

internal pulldown circuit at node SLEEP ensures that the DAC5686 is enabled if the input is left disconnected.

Power-up and power-down activation times depend on the value of the external capacitor at node SLEEP. For a

nominal capacitor value of 0.1 mF, it takes less than 5 ms to power down and approximately 3 ms to power up.

POWER-UP SEQUENCE

In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or

simultaneously with PLLVDD. AVDD, CLKVDD and IOVDD can be powered simultaneously or in any order.

Within AVDD, the multiple AVDD pins should be powered simultaneously.

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DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

DAC5686 EVALUATION BOARD

There is a combination EVM board for the DAC5686 digital-to-analog converter for evaluation. This board allows

the user the flexibility to operate the DAC5686 in various configurations. Possible output configurations include

transformer-coupled, resistor-terminated, inverting/non-inverting and differential amplifier outputs. The digital

inputs are designed to be driven directly from various pattern generators with the onboard option to add a

resistor network for proper load termination.

Appendix A. PLL LOOP FILTER COMPONENTS

For the external second-order filter shown in Figure 50, the components R, C1, and C2 are calculated for a

desired phase margin and loop bandwidth. Resistor R3 = 200 Ω and capacitor C3 = 8 pF are internal to the

DAC5686.

External

Internal

R3

C1

C2

C3

R1

S0006-01

Figure 50. DAC5686 Loop Filter

The VCO gain (Gvco) as a function of VCO frequency for the DAC5686 is shown in Figure 17. For a desired

VCO frequency, the loop filter values can be calculated using the following equations.

Nominal PLL design parameters include:

Charge pump current:

VCO gain:

iqp = 1 mA

K_VCO= 2π × G_VCOrad/A

N = {2, 4, 8, 16, 32}

K_d= iqp × (2πN)^–1A/rad

PLL divide ratio × interpolation:

Phase detector gain:

Let

Desired loop bandwidth = ω_d

Desired phase margin = φ_d

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DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

DAC5686 EVALUATION BOARD (continued)

Then

t2

_{C1 + t1}ǒ_{1 *}Ǔ

t3

t1 t2

C2 +

t3

t3²

t1(t3 * t2)

R +

where

K_dK

t1 +

t2 +

t3 +

^VCO(tanf_d) secf_d)

w²_d

1

w_d(tanf_d) secf_d)

tanf_d) secf_d

w_d

Example: φ_d= 70°, ω_d= 1 MHz, G_VCO= 300e6 MHz/A

N

2

R (Ω)

43

C1 (µF)

0.02

C2 (pF)

670

335

167

84

4

86

0.01

8

173

346

692

0.005

0.002

0.001

16

32

42

The calculated phase margin and loop bandwidth can be verified by plotting the gain and phase of the open-loop

transfer function given by

K_VCOK_d(1 ) sRC1)

s³RC1C2 ) s²(C1 ) C2)

H(s) +

Figure 51 shows the open-loop gain and phase for the DAC5686 evaluation-board loop filter.

−100

60

40

N = 2, 4, 8, 16, 32

−120

−140

−160

−180

20

0

−20

−40

−60

0.01

0.1

1

10

100

0.01

0.1

1

10

100

f − Frequency − MHz

G005

Figure 51. Open-Loop Phase and Gain Plots for DAC5686 Evaluation Board

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DAC5686

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SLWS147B–APRIL 2003–REVISED AUGUST 2004

The phase error (φ_err) phase and frequency step responses are given by the following equations and are plotted

in Figure 52 for the DAC5686 evaluation-board loop filter.

*w

t

_err+ Df [1 ) w_nt * (w_nt)²] e

phase step response

n

f

Dw

w_n

t

[w_nt * (w_nt)²] e^*w

frequency step response

n

f_err

+

1.0

Response to a Phase Step at Time 0

N = 2, 4, 8, 16, 32

Response to a Frequency Step at Time 0

N = 2, 4, 8, 16, 32

Increasing N

0.8

0.6

0.4

0.2

0.0

Increasing N

0.5

0.0

−0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

t − Time − µs

G006

Figure 52. Phase and Frequency Step Responses for DAC5686 Evaluation Board

45

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型号：	DAC5686PZP
厂家：	TEXAS INSTRUMENTS
描述：	SERIAL, PARALLEL, WORD INPUT LOADING, 16-BIT DAC, PQFP100, PLASTIC, QFP-100 转换器
文件：	总46页 (文件大小：1328K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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