DAC60096IZEB [TI]
具有外部转换触发器的 96 通道、12 位、低功耗、高电压 DAC | ZEB | 196 | -40 to 85;
| 型号： | DAC60096IZEB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有外部转换触发器的 96 通道、12 位、低功耗、高电压 DAC | ZEB | 196 | -40 to 85 触发器 转换器 |
| 文件： | 总51页 (文件大小：3235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
DAC60096 具有转换触发器的 96 通道、12 位、低功耗、
串行输入、高电压输出 DAC
1 特性
3 说明
1
•
高通道数
DAC60096 是一款低功耗、快速稳定、96 通道、12
位数模转换器 (DAC)。该器件可提供 ±10.5V 的未缓冲
双极性电压输出范围。DAC60096 拥有高通道数、低
功耗运行和良好线性度等特性，因此是需要大量精确模
拟输出的系统的理想解决方案。
–
–
96 通道数模转换器 (DAC)
指定单调性为 12 位
•
•
•
•
•
较宽的未缓冲输出电压范围：±10.5V
DAC 输出同时更新
清零功能
通过一个高速、四线制且兼容行业标准微处理器和微控
制器的串行接口可以与该器件进行通信。
集成参考缓冲器：2.5V 输入
专用 A-B 触发引脚
DAC60096 经过设置可同时清零或更新所有 DAC。此
外，通用外部转换触发器使得每个 DAC 通道均可作为
具有独立幅值控制的方波发生器来运行。
–
可利用切换模式生成方波
SPI™- 兼容串行接口
4 线模式，3V 至 5.5V 工作电压
•
–
•
•
•
低功耗：440mW 典型值（工作时）
工作温度范围：–40°C 至 +85°C
DAC60096 的额定工作温度范围为 –40°C 至 +85°C，
并且采用 196 焊球、15mm × 15mm、1mm 间距的球
栅阵列 (BGA) 封装。
196 焊球、15mm × 15mm NFBGA，1mm 间距
器件信息(1)
2 应用
部件号
DAC60096
封装
封装尺寸（标称值）
•
•
•
•
光电开关
NFBGA
15.0mm x 15.0mm
光衰减器
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
自动测试设备 (ATE)
仪表
典型应用
2.5-V
Reference
DAC60096
10.5 V
10.5 V
œ10.5 V
RESET
œ10.5 V
Subsystem 1
CS
SCLK
SDI
SDO
Data
Buffer 1A
Data
Register 1A
DAC1
Processor
Data
Data
Buffer 1B
Register 1B
Channel 1
LDAC
CLEAR
STATS
Channel 13
Channel 24
TRIGG
Subsystem 2
Subsystem 3
Subsystem 4
Optical
Component
DVDD AVCC AVSS
AGND DGND REFGND
3.3 V
12 V
œ12 V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS721
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
目录
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 22
7.5 Programming .......................................................... 23
7.6 Register Maps ........................................................ 25
Application and Implementation ........................ 31
8.1 Application Information............................................ 31
8.2 Typical Application ................................................. 32
Power Supply Recommendations...................... 36
9.1 Device Reset Options ............................................. 36
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics: DAC DC........................... 7
6.6 Electrical Characteristics: Square-Wave Output....... 8
6.7 Electrical Characteristics: General............................ 9
6.8 Timing Requirements.............................................. 10
6.9 Typical Characteristics: DC Mode........................... 12
6.10 Typical Characteristics: Toggle Mode................... 14
6.11 Typical Characteristics, General ........................... 15
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
8
9
10 Layout................................................................... 38
10.1 Layout Guidelines ................................................. 38
10.2 Layout Examples................................................... 38
11 器件和文档支持 ..................................................... 45
11.1 文档支持 ............................................................... 45
11.2 社区资源................................................................ 45
11.3 商标....................................................................... 45
11.4 静电放电警告......................................................... 45
11.5 Glossary................................................................ 45
12 机械、封装和可订购信息....................................... 45
7
4 修订历史记录
Changes from Original (December 2015) to Revision A
Page
•
已从“产品预览”更改为“量产数据” ............................................................................................................................................ 1
2
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
www.ti.com.cn
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
5 Pin Configuration and Functions
ZEB Package
196-Ball NFBGA
Top View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
DAC14
G4
AVSS
G4
VREFL VREFH AVCC
G4 G4 G4
REF
GND2
AVCC VREFH VREFL
AVSS
G5
DAC13
G5
14
13
12
11
10
9
DNC
REF2
DNC
G5
G5
G5
DAC15 DAC17 DAC20 DAC21 DAC22 DAC24
G4
DAC2
G3
DAC3
G5
DAC5
G5
DAC6
G5
DAC7
G5
DAC8
G5
DAC10 DAC12
G5 G5
G4
G4
G4
G4
G4
DAC16 DAC18 DAC19 DAC23
G4
DAC4
G3
DAC3
G3
DAC1
G3
DAC4
G5
DAC24 DAC23 DAC21
DAC9
G5
DAC19 DAC11
G6 G5
G4
G4
G4
G6
G6
G6
DAC10
G3
DAC8
G3
DAC6
G3
DAC5
G3
DAC24
G2
DAC1
G7
DAC22 DAC20 DAC18 DAC17
DNC
DNC
DNC
DNC
G6
G6
G6
G6
DAC11
G3
DAC9
G3
DAC7
G3
DAC5
G7
DAC7
G7
DAC16
G6
AGND
AGND
AGND
AGND
DGND
DVDD
DVDD
DGND
AGND
DGND
DVDD
DVDD
DGND
AGND
AGND
AGND
DAC12
G3
AVSS
G3
VREFL VREFH AVCC
G3 G3 G3
AVSS
S2
AVSS
S3
AVCC VREFH VREFL
G6 G6 G6
AVSS
G6
DAC15
G6
DAC13
G3
AVSS
G3
VREFL VREFH AVCC
G3 G3 G3
AVCC
S2
AVCC
S3
AVCC VREFH VREFL
G6 G6 G6
AVSS
G6
DAC14
G6
8
DAC14
G2
AVSS
G2
VREFL VREFH AVCC
G2 G2 G2
AVCC
S1
AVCC
S4
AVCC VREFH VREFL
G7 G7 G7
AVSS
G7
DAC13
G7
7
DAC15
G2
AVSS
G2
VREFL VREFH AVCC
G2 G2 G2
AVSS
S1
AVSS
S4
AVCC VREFH VREFL
AVSS
G7
DAC12
G7
6
G7
G7
G7
DAC16 DAC17 DAC20 DAC21 DAC22
DAC3
G7
DAC4
G7
DAC6
G7
DAC9
G7
DAC11
G7
5
AGND
RESET
STATS
AGND
AGND
AGND CLEAR AGND
G2
G2
G2
G2
G2
DAC10
G1
DAC7
G1
DAC19 DAC23
DAC1
G1
DAC2
G7
DAC25 DAC21
G8 G8
DAC8
G7
DAC10
G7
4
CS
SCLK
SDI
LDAC
TRIGG
AGND
AGND
G2
G2
DAC11
G1
DAC8
G1
DAC18
G2
DAC3
G1
DAC2
G1
DAC26 DAC24 DAC19 DAC17 DAC16
G8 G8 G8 G8 G8
3
SDO
DAC12
G1
DAC9
G1
DAC6
G1
DAC5
G1
DAC4
G1
DAC23 DAC22 DAC20 DAC18 DAC15
G8
2
AGND
REF1
AGND
G8
G8
G8
G8
DAC13
G1
AVSS
G1
VREFL VREFH AVCC
REF
GND1
AVCC VREFH VREFL
G8 G8 G8
AVSS
G8
DAC14
G8
1
G1
G1
G1
DAC Output
Subsystem 1
Digital I/O
Reference
AVCC
AVSS
DVDD
Ground
DAC Output
Subsystem 2
Inputs (2.5 V)
DAC Output
Subsystem 3
Reference
Compensation
DAC Output
Subsystem 4
Do Not Connect
Copyright © 2015–2016, Texas Instruments Incorporated
3
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
D10, E10,
F1, F2, F5, F10,
G2, G5, G10, H2, H10,
J1, J2, J5, J10,
K10, L10
AGND
GND Analog ground.
E1, E6, E7, E8, E9, E14,
F7, F8, J7, J8,
K1, K6, K7, K8, K9, K14
Positive analog supply voltage. (11.2 V to 12.6 V). A 100-nF bypass capacitor for each AVCC_n (n
PWR = G1, G2, G3, G4, G5, G6, G7, G8, S1, S2, S3 or S4) is required; place as close as possible to the
pins.
AVCC
AVSS
B1, B6, B7, B8, B9, B14,
F6, F9, J6, J9,
N1, N6, N7, N8, N9, N14
Negative analog supply voltage. (-12.6V to -11.2V). A 100-nF bypass capacitor for each AVSS_n (n
PWR = G1, G2, G3, G4, G5, G6, G7, G8, S1, S2, S3 or S4) is required; place as close as possible to the
pins.
Asynchronous clear control input, active low. When CLEAR is low, all DACs are loaded with code
000h. When CLEAR is high, all DACs return to normal operation
CLEAR
CS
H5
G4
I
I
Serial data enable, active low. This input is the frame synchronization signal for the serial data.
A1, A2, A3, A4,
B2, B3, B4, C2, D2, D3,
E2, E3, E4
DAC[1-13]_G1
DAC[14-26]_G2
DAC[1-13]_G3
DAC[14-24]_G4
DAC[3-13]_G5
DAC[14-26]_G6
DAC[1-13]_G7
DAC[14-26]_G8
O
Subsystem 1 Regular DAC outputs: DAC group 1 and DAC group 2. Each DAC subsystem can be
controlled independently through the serial interface.
A5, A6, A7, B5,
C3, C4, C5,
D4, D5, E5, E11
O
O
O
O
O
O
O
A8, A9, A10, A11,
B10, B11, C10, C11,
D11, E12, F12, G12, G13
Subsystem 2 Regular DAC outputs: DAC group 3 and DAC group 4. Each DAC subsystem can be
controlled independently through the serial interface.
A12, A13, A14,
B12, B13, C12, C13,
D12, D13, E13, F13
H12, H13, J13, K13, L13,
M12, M13, N13,
P12, P13, P14
Subsystem 3 Regular DAC outputs: DAC group 5 and DAC group 6. Each DAC subsystem can be
controlled independently through the serial interface.
J12, K12
L11, L12, M11, N11, N12,
P8, P9, P10, P11
K4, K5, K11, L5,
M5, M10, N4, N5, N10,
P4, P5, P6, P7
Subsystem 4 Regular DAC outputs: DAC group 7 and DAC group 8. Each DAC subsystem can be
controlled independently through the serial interface.
K2, K3, L2, L3, L4,
M2, M3, M4, N2, N3,
P1, P2, P3
DGND
DNC
G6, G9, H6, H9
GND Digital ground. Ground reference point for all digital circuitry on the device.
F11, F14, G11
H11, J11, J14
—
Reserved for factory use. For proper operation, do not connect.
Digital supply voltage. (3 V to 5.5 V). A 100-nF bypass capacitor is required; place as close as
possible to the pins.
DVDD
LDAC
G7, G8, H7, H8
J4
PWR
Synchronous DAC load control input, active low. When LDAC is low, the DAC outputs are updated
immediately after a register write. If left high during DAC register updates, bringing LDAC low
causes all DAC outputs to update simultaneously.
I
RESET
F4
H1
I
Reset input, active low. Logic low on this pin causes the device to perform a hardware reset.
Reference ground. Ground reference point for REF1. REFGND1 should be star connected at the
system GND source and not connected to the GND plane for best performance.
REFGND1
GND
Reference ground. Ground reference point for REF2. REFGND2 should be star connected at the
system GND source and not connected to the GND plane for best performance.
REFGND2
SCLK
H14
H4
GND
I
I
Serial interface clock.
Serial interface data input. Data are clocked into the input shift register on each rising edge of
SCLK.
SDI
H3
Serial interface data output. The SDO pin is in high impedance when CS is high. Data can be
clocked out of the input shift register on either rising or falling edges of SCLK as specified by
PHAINV in the CON register.
SDO
G3
O
STATS
REF1
F3
O
I
DAC output status indicator. Identifies which of the two DAC data registers is active.
Input voltage reference pin 1 (2.5 V). A 100-nF bypass capacitor between this pin and REFGND1 is
required.
G1
Input voltage reference pin 2 (2.5 V). A 100-nF bypass capacitor between this pin and REFGND2 is
required.
REF2
G14
I
4
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
www.ti.com.cn
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
Trigger input signal. Enables all DAC outputs to toggle between the two DAC data registers
associated with each DAC. This functionality enables the device to operate as a square-wave
generator. The DAC registers are prepared for toggle mode operation on a TRIGG rising edge and
the outputs are toggled on each following TRIGG falling edge.
TRIGG
J3
I
Compensation capacitor connection for the internal 10.5 V reference voltage. A 100-nF bypass
capacitor for each VREFH_n (n = G1, G2, G3, G4, G5, G6, G7 or G8) is required; place as close as
possible to the pins.
D1, D6, D7, D8, D9, D14,
L1, L6, L7, L8, L9, L14
VREFH
VREFL
O
O
Compensation capacitor connection for the internal -10.5 V reference voltage. A 100-nF bypass
capacitor for each VREFL_n (n = G1, G2, G3, G4, G5, G6, G7 or G8) is required; place as close as
possible to the pins.
C1, C6, C7, C8, C9, C14,
M1, M6, M7, M8, M9, M14
Copyright © 2015–2016, Texas Instruments Incorporated
5
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
AVCC to DGND
AVSS to DGND
13
–13
0.3
DVDD to DGND
Supply voltage
–0.3
6
V
AVCC to AVSS
–0.3
26
DGND to AGND
–0.3
0.3
DGND to REFGND[1,2]
REF1 to REFGND1
REF2 to REFGND2
DAC to DGND
–0.3
0.3
–0.3
6
–0.3
6
AVSS – 0.3
AVCC + 0.3
CLEAR, CS, LDAC, RESET, SCLK, SDI, SDO, TRIGG,
STATS to DGND
Pin voltage
–0.3
DVDD + 0.3
V
VREFH to DGND
VREFL to DGND
–0.3
AVSS – 0.3
–0.3
AVCC + 0.3
0.3
26
VREFH to adjacent VREFL
Operating, TA
–40
85
Temperature
Junction, TJ
Storage, Tstg
–40
150
150
°C
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVCC
11.2
–12.6
3
12
–12
3.3
24
12.6
–11.2
5.5
V
V
V
V
AVSS
DVDD
AVCC to AVSS
22.4
25.2
DIGITAL INPUTS
Digital input voltage
REFERENCE INPUT
Reference input voltage, VREF
TEMPERATURE
Operating ambient temperature, TA
0
2.475
–40
DVDD
2.525
85
V
V
2.5
°C
6
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
www.ti.com.cn
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
6.4 Thermal Information
DAC60096
THERMAL METRIC(1)
ZEB (NFBGA)
UNIT
196 BALLS
21.4
7.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
5.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
5.0
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics: DAC DC
at AVCC = 11.2 V to 12.6 V, AVSS = –12.6 V to –11.2 V, DVDD = 3 V to 5.5 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 =
REF2 = 2.5 V (specifications exclude any reference contributions), no load on DACs, and TA = –40°C to +85°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
12
Bits
LSB
INL
Relative accuracy
Differential nonlinearity
Gain error
±0.15
±0.1
±0.05
±2
±1
±0.9
±0.15
±7
DNL
Specified 12-bit monotonic
TA = 25°C
LSB
%FSR
mV
Zero-code error
Gain error drift
Zero-code error drift
TA = 25°C, code 000h
±1
ppm/°C
ppm/°C
±1
OUTPUT CHARACTERISTICS
Output voltage
–10.5
10.5
V
Output impedance
41
kΩ
Measured channel at code 000h, all
others transition from code 7FFh to 02Bh
DC crosstalk
0.5
LSB
DAC ouput transition:
code 800h to 7FFh to within 1 LSB,
6x load:
160
R(SERIES) = 17 kΩ, CLOAD = 300 pF
Settling time
Output noise
µs
DAC ouput transition:
code 800h to 7FFh to within 1 LSB,
1x load:
65
60
R(SERIES) = 100 kΩ, CLOAD = 50 pF
TA = 25°C, 1 kHz, code 000h
nV/√Hz
Copyright © 2015–2016, Texas Instruments Incorporated
7
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
6.6 Electrical Characteristics: Square-Wave Output
at AVCC = 11.2 V to 12.6 V, AVSS = –12.6 V to –11.2 V, DVDD = 3 V to 5.5 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 =
REF2 = 2.5 V (specifications exclude any reference contributions), no load on DACs, and TA = –40°C to +85°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC OUTPUTS – 6x LOAD: R(SERIES) = 17 kΩ, CLOAD = 300 pF
For amplitude ≥ 9.1 VRMS, amplitude = ±10.5 VPP
codes 7FFh to 801h
,
Frequency
3
kHz
Frequency = 3 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
,
,
9.1
8
VRMS
Amplitude
Frequency = 5 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
VRMS
Amplitude step precision
Amplitude temperature drift
Frequency = 3 kHz, amplitude ≥ 1 VRMS
6
5
mVRMS
mVRMS
Frequency = 3 kHz, amplitude = ±5 VPP
,
codes 3CFh to C31h
Frequency = 3 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
,
15
10
10
mVRMS
mV
Frequency = 3 kHz, amplitude = ±5 VPP
,
–10
–10
codes 3CFh to C31h
Offset voltage
Frequency = 3 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
,
,
mV
Frequency = 3 kHz, amplitude = ±10.5 VPP
10% to 90%, codes 7FFh to 801h
Rise and fall time
40
5
µs
(1)
DAC OUTPUTS – 1x LOAD: R(SERIES) = 100 kΩ, CLOAD = 50 pF
For amplitude ≥ 9.1 VRMS, amplitude = ±10.5 VPP
codes 7FFh and 801h
,
Frequency
kHz
Frequency = 3 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
,
,
10
VRMS
Amplitude
Frequency = 5 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
9.5
VRMS
Amplitude step precision
Amplitude temperature drift
Frequency = 3 kHz, amplitude ≥ 1 VRMS
7
5
mVRMS
mVRMS
Frequency = 3 kHz, amplitude = ±5 VPP
,
codes 3CFh to C31h
Frequency = 3 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
,
15
10
10
mVRMS
mV
Frequency = 3 kHz, amplitude = ±5 VPP
,
–10
–10
codes 3CFh to C31h
Offset voltage
Frequency = 3 kHz, amplitude = ±10.5 VPP
codes 7FFh to 801h
,
,
mV
Frequency = 3 kHz, amplitude = ±10.5 VPP
10% to 90%, codes 7FFh to 801h
Rise and fall time
10
µs
(1) Specified by design and characterization. Not tested during production.
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6.7 Electrical Characteristics: General
at AVCC = 11.2 V to 12.6 V, AVSS = –12.6 V to –11.2 V, DVDD = 3 V to 5.5 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 =
REF2 = 2.5 V (specifications exclude any reference contributions), no load on DACs, and TA = –40°C to +85°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL REFERENCE INPUTS
VREF
Input voltage range
REF1 and REF2 input pins
2.475
2.5
1
2.525
V
Reference input current
Per input pin
µA
DIGITAL LOGIC
VIH
VIL
High-level input voltage
0.7 × DVDD
DVDD - 0.2
V
V
Low-level input voltage
High-level output voltage
Low-level output voltage
0.3 × DVDD
0.4
VOH
VOL
ILOAD = 1 mA, SDO2x = 01
ILOAD = –1 mA, SDO2x = 01
V
V
Input capacitance
20
pF
(1)
POWER REQUIREMENTS
I(AVCC)
I(AVSS)
I(DVDD)
AVCC supply current
18.1
–18.1
2
25
10
22
10
30
mA
mA
mA
mW
mA
mA
mA
mW
mA
mA
mA
mW
6x load:
R(SERIES) = 17 kΩ, CLOAD = 300 pF
frequency = 3 kHz
48 DAC outputs, codes 7FFh and 801h
48 DAC outputs, codes 117h and EE9h
AVSS supply current
DVDD supply current
Power consumption
AVCC supply current
AVSS supply current
DVDD supply current
Power consumption
AVCC supply current
AVSS supply current
DVDD supply current
Power consumption
–25
–22
–30
440
17
I(AVCC)
I(AVSS)
I(DVDD)
1x load:
R(SERIES) = 100 kΩ, CLOAD = 50 pF
frequency = 3 kHz
48 DAC outputs, codes 7FFh and 801h
48 DAC outputs, codes 117h and EE9h
–17
2
(2)
415
25
I(AVCC)
I(AVSS)
I(DVDD)
6x load:
–25
2
R(SERIES) = 17 kΩ, CLOAD = 300 pF
frequency = 3 kHz
All DAC outputs, codes 02Bh and FD5h
10
650
760
(1) Power requirements tested unloaded during production. Load current contribution to power consumption specified by design and
characterization.
(2) Specified by design and characterization. Not tested during production.
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6.8 Timing Requirements(1)(2)
at AVCC = 11.2 V to 12.6 V, AVSS = –12.6 V to –11.2 V, DVDD = 3 V to 5.5 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 =
REF2 = 2.5 V (specifications exclude any reference contributions), no load on DACs, and TA = –40°C to +85°C (unless
otherwise noted)
MIN
NOM
MAX
UNIT
SERIAL INTERFACE – DEFAULT MODE: SDO2X = 01, PHAINV = 01
Write operation
32
18
MHz
MHz
ns
fSCLK
SCLK frequency
Read operation
Write operation
Read operation
Write operation
Read operation
14
26
14
26
5
tPH
SCLK pulse width high
SCLK pulse width low
ns
ns
tPL
ns
tSU
SDI setup
ns
tH
SDI hold
10
10
20
70
0
ns
tCSS
tCSH
tIAG
tODZ
tOZD
tOD1
CS setup
ns
CS hold
ns
Inter-access gap
SDO driven to tri-state
SDO tri-state to driven
SDO output delay
ns
Read operation
Read operation
Read operation
20
20
20
ns
0
ns
0
ns
SERIAL INTERFACE – FAST MODE: SDO2X = 10, PHAINV = 10
Write operation
32
32
MHz
MHz
ns
fSCLK
SCLK frequency
Read operation
Write operation
Read operation
Write operation
Read operation
14
14
14
14
5
tPH
SCLK pulse width high
SCLK pulse width low
ns
ns
tPL
ns
tSU
SDI setup
ns
tH
SDI hold
10
10
20
70
0
ns
tCSS
tCSH
tIAG
tODZ
tOZD
tOD2
CS setup
ns
CS hold
ns
Inter-access gap
SDO driven to tri-state
SDO tri-state to driven
SDO output delay
ns
Read operation
Read operation
Read operation
20
20
20
ns
0
ns
0
ns
DIGITAL LOGIC
Delay from power-on-reset to normal operation
Delay from hardware reset to normal operation
Delay from software reset to normal operation
100
10
250
50
µs
µs
µs
ns
ns
ns
ns
ns
ns
tRESETDLY Reset delay
10
50
tRESETWD
tLDACS
tLDACH
tTRIGH
RESET pulse width
500
0
LDAC setup
LDAC hold
0
TRIGG pulse width high
TRIGG pulse width low
STATS output delay
30
30
tTRIGL
tSTADLY
25
(1) Specified by design and characterization. Not tested during production.
(2) SDO loaded with 10-pF load capacitance for SDO timing specifications.
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tIAG
tCSH
tCSS
tODZ
/{
{/[Y
{5L
tPH
tPL
Bit 23
Bit 1
Bit 0
tSU
tH
ù
ù
{5h
tOZD
Figure 1. Serial Interface Write Timing Diagram
tIAG
tCSH
tCSS
tODZ
/{
{/[Y
{5L
tPH
tPL
Bit 16
Bit 23
tSU
tH
ù
Z
Z
{5h
PHAINV = ”01‘
Bit 15
tOD1
Bit 0
tOZD
ù
Bit 15
Bit 0
{5h
PHAINV = ”10‘
tOD2
Figure 2. Serial Interface Read Timing Diagram
tLDACS
tLDACH
/{
[5!/
tTRIGH
tTRIGL
ÇwLDD
{Ç!Ç{
tSTADLY
Figure 3. Digital Logic Timing Diagram
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6.9 Typical Characteristics: DC Mode
at AVCC = 12 V, AVSS = –12 V, DVDD = 3.3 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 = REF2 = 2.5 V (specifications
exclude any reference contributions), no load on DACs, and TA = 25°C (unless otherwise noted)
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
0
512 1024 1536 2048
0
512 1024 1536 2048
œ2048 œ1536 œ1024 œ512
œ2048 œ1536 œ1024 œ512
Code
Code
C001
C002
Figure 4. Differential Linearity Error (DNL)
Figure 5. Integral Linearity Error (INL)
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
Max DNL
Min DNL
Max INL
Min INL
10
35
60
85
œ40
œ15
10
35
60
85
œ40
œ15
TA (°C)
TA (°C)
C005
C006
Figure 6. DNL vs Temperature
Figure 7. INL vs Temperature
2.0
1.0
0.05
0.04
0.03
0.02
0.01
0.0
0.00
œ0.01
œ0.02
œ0.03
œ0.04
œ0.05
œ1.0
œ2.0
10
35
60
85
10
35
60
85
œ40
œ15
œ40
œ15
TA (°C)
TA (°C)
C007
C008
Figure 8. Zero-Code Error vs Temperature
Figure 9. Gain Error vs Temperature
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Typical Characteristics: DC Mode (continued)
at AVCC = 12 V, AVSS = –12 V, DVDD = 3.3 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 = REF2 = 2.5 V (specifications
exclude any reference contributions), no load on DACs, and TA = 25°C (unless otherwise noted)
2000
1500
1000
500
0
500
400
300
200
100
0
10
100
1K
10K
100K
1M
200
400
600
800
1000
Frequency (Hz)
Capacitive Load (pF)
C011
C012
Figure 10. DAC Output Noise vs Frequency
Figure 11. Settling Time Amplitude vs Capacitive Load
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6.10 Typical Characteristics: Toggle Mode
at AVCC = 12 V, AVSS = –12 V, DVDD = 3.3 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 = REF2 = 2.5 V (specifications
exclude any reference contributions), no load on DACs, and TA = 25°C (unless otherwise noted)
12
10
8
10
8
1X Load
6X Load
6
4
2
6
0
œ2
œ4
œ6
œ8
œ10
4
Freq = 100 Hz
Freq = 1 kHz
Freq = 3 kHz
Freq = 5 kHz
2
0
0
4
8
12
16
20
0
2
4
6
8
10
Load Multiplier (X)
Amplitude (VRMS
)
C013
C015
1x load: R(SERIES) = 100 kΩ, CLOAD = 50 pF
Figure 12. Maximum Amplitude vs Capacitive Load
Figure 13. Offset vs Amplitude
5
10
8
2.5 V
2.5 V
RMS
RMS
4
5 V
5 V
RMS
RMS
3
6
9 V
9 V
RMS
RMS
2
1
0
4
2
0
œ1
œ2
œ4
œ6
œ8
œ10
œ2
œ3
œ4
œ5
10
35
60
85
10
35
60
85
œ40
œ15
œ40
œ15
TA (°C)
TA (°C)
C016
C017
Figure 14. Amplitude Drift vs Temperature
Figure 15. Offset vs Temperature
0.5
0.4
10.0
8.0
2.5 V
2.5 VRRMS
RMS
5 VR
5 VRRMS
RMS
0.3
6.0
9 VR
RMS
9 VR
RMS
0.2
4.0
0.1
2.0
0.0
0.0
œ0.1
œ0.2
œ0.3
œ0.4
œ0.5
œ2.0
œ4.0
œ6.0
œ8.0
œ10.0
11.2
11.4
11.6
11.8
12.0
12.2
12.4
12.6
11.2
11.4
11.6
11.8
12.0
12.2
12.4
12.6
AVss and AVcc Voltage Magnitude (V)
AVss and AVcc Voltage Magnitude (V)
C020
C021
Figure 16. Amplitude Drift vs Supply Voltage
Figure 17. Offset vs Supply Voltage
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6.11 Typical Characteristics, General
at AVCC = 12 V, AVSS = –12 V, DVDD = 3.3 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 = REF2 = 2.5 V (specifications
exclude any reference contributions), no load on DACs, and TA = 25°C (unless otherwise noted)
12
10
8
10
8
6
5
30
DAC A
DAC B
SCLK
DAC
20
6
6
4
4
4
10
2
2
3
0
0
0
2
œ2
œ4
œ6
œ8
œ10
œ12
-2
-4
-6
-8
-10
œ10
œ20
œ30
1
0
œ1
0
0.5
1
1.5
2
0
150
300
450
600
750
900
Time (ms)
Time (ns)
C024
C025
DAC A: square-wave output, freq = 1 kHz, full-scale amplitude
DAC B: zero-code inputs
All DACs with zero-code inputs
SCLK frequency = 1 MHz
Figure 18. DAC to DAC Crosstalk
Figure 19. SPI to DAC Crosstalk
14
14
10
6
10
6
2
2
œ2
œ2
œ6
œ10
œ14
AVCC
AVSS
DVDD
REF(1,2)
AVCC
AVSS
DVDD
REF(1,2)
DAC
œ6
œ10
DAC
œ14
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
œ1
œ1
Time (ms)
Time (ms)
C026
C027
Figure 20. Recommended Power-Up Sequence
Figure 21. Recommended Power-Down Sequence
15
8
15
8
0
0
AVCC
AVSS
DVDD
REF(1,2)
DAC
AVCC
AVSS
DVDD
REF(1,2)
DAC
œ8
œ15
œ8
œ15
0
2
4
6
8
0
2
4
5
7
Time (ms)
Time (ms)
C028
C029
6x load: R(SERIES) = 17 kΩ, CLOAD = 300 pF
6x load: R(SERIES) = 17 kΩ, CLOAD = 300 pF
Square-wave output: freq = 1 kHz, full-scale amplitude
Square-wave output: freq = 1 kHz, full-scale amplitude
Figure 22. DVDD Collapse and Recover
Figure 23. AVCC Collapse and Recover
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Typical Characteristics, General (continued)
at AVCC = 12 V, AVSS = –12 V, DVDD = 3.3 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 = REF2 = 2.5 V (specifications
exclude any reference contributions), no load on DACs, and TA = 25°C (unless otherwise noted)
12
12
DAC
DAC
TRIGG
CLEAR
8
TRIGG
CLEAR
8
4
4
0
0
œ4
œ8
œ12
œ4
œ8
œ12
0
1
2
3
4
0
1
2
3
4
Time (ms)
Time (ms)
C031
C030
6x load: R(SERIES) = 17 kΩ, CLOAD = 300 pF
6x load: R(SERIES) = 17 kΩ, CLOAD = 300 pF
Square-wave output: freq = 1 kHz, full-scale amplitude
Square-wave output: freq = 1 kHz, full-scale amplitude
Figure 25. Clear State to Normal Transition
Figure 24. Normal to Clear State Transition
12
10.0
DAC
TRIGG
LDAC
8
4
8.0
6.0
4.0
2.0
0.0
0
œ4
œ8
œ12
0
1
2
3
4
3.0
3.5
4.0
4.5
5.0
5.5
Time (ms)
DVDD
C032
C033
6x load: R(SERIES) = 17 kΩ, CLOAD = 300 pF
No DAC load
Square-wave output: freq = 1 kHz, full-scale amplitude
Square-wave output: freq = 3 kHz, full-scale amplitude
Figure 26. LDAC DAC Transition
Figure 27. DVDD Current Consumption
300
200
100
0
œ100
œ200
AVCC
AVSS
œ300
0
512 1024 1536 2048
œ2048 œ1536 œ1024 œ512
± Code
C035
No DAC load, DVDD = 3.3 V
No DAC load, DC output, DVDD = 3.3 V
Square-wave output: freq = 3 kHz
Figure 28. Unloaded AVCC/AVSS Current Consumption
Figure 29. Unloaded AVCC/AVSS Current Consumption
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Typical Characteristics, General (continued)
at AVCC = 12 V, AVSS = –12 V, DVDD = 3.3 V, AGND = DGND = REFGND[1,2] = 0 V, REF1 = REF2 = 2.5 V (specifications
exclude any reference contributions), no load on DACs, and TA = 25°C (unless otherwise noted)
250
200
150
100
50
0
Regular: 1 kHz
Regular: 3 kHz
Regular: 5 kHz
œ50
œ100
œ150
œ200
œ250
Regular: 1 kHz
Regular: 3 kHz
Regular: 5 kHz
0
0
4
8
12
16
20
0
4
8
12
16
20
Load Multiplier (X)
Load Multiplier (X)
C036
C037
1x load: R(SERIES) = 100 kΩ, CLOAD = 50 pF, DVDD = 3.3 V
1x load: R(SERIES) = 100 kΩ, CLOAD = 50 pF, DVDD = 3.3 V
Square-wave output, full-scale amplitude
Square-wave output, full-scale amplitude
Figure 30. AVCC Load Current Consumption
Figure 31. AVSS Load Current Consumption
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7 Detailed Description
7.1 Overview
The DAC60096 is a low-power, 96-channel, 12-bit, digital-to-analog converter (DAC). The device provides
±10.5-V unbuffered bipolar voltage outputs while maintaining extremely low-power operation and good linearity.
The device integrates dedicated reference buffers that enable operation from an external 2.5-V reference source.
The DAC60096 can be set up to clear or update all DACs simultaneously. In addition a versatile external
conversion trigger allows each DAC to operate as an amplitude-independent square-wave generator. The device
incorporates a reset circuit that ensures all DAC outputs power up and remain at zero scale prior to device
configuration.
The DAC60096 features simplify the design of systems requiring a high number of precise analog control signals
such as those found in optical communications switches and attenuators.
The DAC60096 is designed as four DAC subsystems. Each DAC subsystem is configured independently through
a high speed 4-wire serial interface compatible with industry standard microprocessors and microcontrollers. The
DAC60096 is characterized for operation over the temperature range of –40°C to +85°C, and is available in a
196-ball, 15-mm × 15-mm, 1-mm pitch BGA package.
7.2 Functional Block Diagram
VREFL VREFH
(x6) (x6)
VREFH VREFL
(x6) (x6)
LDAC
TRIGG
RESET
CLEAR
STATS
REF1 REF2
DAC60096
Power-On
Reset
Control Logic
Subsystem 1
CS
SCLK
SDI
Data
Buffer 1A
Data
Register 1A
Channel1
DAC1
DAC1_G1
DAC2_G1
DAC3_G1
Channel2
Channel3
SDO
Data
Data
Buffer 1B
Register 1B
Channel11
Channel12
Channel13
DAC11_G1
DAC12_G1
DAC13_G1
DAC14_G2 œ DAC24_G2
Subsystem 2
Subsystem 3
Subsystem 4
DAC1_G3 œ DAC13_G3
DAC14_G4 œ DAC24_G4
DAC3_G5 œ DAC13_G5
DAC14_G6 œ DAC24_G6
DAC1_G7 œ DAC13_G7
DAC14_G8 œ DAC26_G8
DVDD AVCC AVSS
(ì4) (ì16) (ì16)
AGND DGND REFGND
(ì17) (ì4) (ì2)
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7.3 Feature Description
7.3.1 Digital-to-Analog Converters (DACs)
The DAC60096 is a 96-channel, 12-bit digital-to-analog converter (DAC) with integrated reference buffers. Each
DAC output consists of an R-2R ladder configuration as shown in Figure 32.
The DAC60096 includes reference buffers that enable bipolar DAC output voltages of ±10.5 V from a 2.5-V
reference source. The outputs of the reference buffers drive the R-2R ladders.
R
R
VOUT
2R
2R
S0
2R
S1
2R
S8
2R
E1
2R
E2
2R
E7
VREFH
VREFL
3-MSBs Decoded into
7 Equal Segments
9-Bit R-2R Ladder
Figure 32. R-2R Ladder Configuration
7.3.1.1 DAC Transfer Function
The DAC60096 integrates dedicated reference buffers that enable operation from an external 2.5-V reference
source. The reference buffers generate the voltages, VREFH and VREFL, required to drive the DAC R-2R
ladders.
10.5
VREFH = VREF
x
2.5
(1)
(2)
VREFL = -1 x VREFH
where VREF is the reference input voltage at pins REF1 and REF2.
Input data are written to the individual DAC data registers in 12-bit twos complement format. After power-on or a
reset event, all DAC registers are set to zero scale. The DAC transfer function is given by Equation 3.
Code
VOUT
=
x (VREFH - VREFL)
4096
(3)
where Code is the signed decimal equivalent of the binary code loaded to the DAC register and ranges from
-2048 to 2047 (See Table 1).
Table 1. DAC Data Format
DIGITAL CODE
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1000 0000 0001
1000 0000 0000
SIGNED DECIMAL VALUE
DAC OUTPUT VOLTAGE (V)
+2047
+2046
+1
10.49487
10.48975
0.005127
0
0
–1
–0.005127
–10.49487
–10.5
–2047
–2048
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7.3.1.2 DAC Register Structure
Each DAC in the device incorporates two data registers: Register A and Register B. These two data registers
and the TRIGG pin enable toggle mode operation. Alternatively, if the TRIGG pin is left fixed the device is in DC
mode operation and only one of the data registers is used to control the DAC output (Register A by default).
Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active DAC registers can be set to happen immediately (asynchronous mode) or
initiated by an LDAC trigger (synchronous mode). After data are transferred to the DAC active registers, the DAC
outputs are updated. When the host reads from a DAC data register, the value held in the DAC buffer register is
returned (not the value held in the DAC active register).
The DAC update mode is determined by the status of the LDAC input pin. If the LDAC pin is held low the device
is in asynchronous mode. In asynchronous mode, a write to a DAC data register results in an immediate update
of the DAC active register and the corresponding output. If LDAC is held high, the device is in synchronous
mode. In synchronous mode, writing to a DAC data register does not automatically update the DAC output.
Instead, the update occurs only after an LDAC trigger occurs. An LDAC trigger is generated either through a
high-to-low transition on the LDAC pin in which case all 96 DACs update at the same time or by the self-clearing
LDAC bit in each of the four subsystems CON registers (address 0x4, bit 15) which enables synchronization of
all the DACs in the selected subsystem.
After the DAC outputs have been configured, a clear event enables the DACs to be loaded with zero-code while
retaining the previously programmed values, thus allowing the possibility to return to the voltage being output
before the clear event was issued. Note that the DAC data registers can be updated while the device is in clear
state allowing the DACs to output new values upon return to normal operation. When the device exits the clear
state the DAC outputs are immediately loaded with the data in the DAC active registers.
The device is set into clear state through the CLEAR pin. Setting the CLEAR pin low forces all 96 DACs into
clear state. Setting the CLEAR pin back high returns all DACs to normal operation. Alternatively, the CLRDAC
bits in each of the four subsystems CON registers (Address 0x4, bits [5:4]) can be used to enter or exit clear
state at a subsystem level.
Serial Interface
DAC Data Register
READ
WRITE
DAC
Buffer Register
A
DAC
Active Register
A
0x0000
(asynchronous mode)
12-Bit
DAC
DAC Output
LDAC Trigger
(Synchronous Mode)
Clear State
(Asynchronous Mode)
Toggle Mode
DAC
Buffer Register
B
DAC
Active Register
B
Figure 33. DAC60096 DAC Block Diagram
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7.3.2 Reference Specifications
The DAC60096 integrates dedicated reference buffers that enable operation from an external 2.5-V reference
source. The reference buffers generate the ±10.5-V levels used to drive the DACs in the device. A 100-nF
bypass capacitor should be placed between the REF[1,2] input pins and REFGND[1,2]. Additionally a
compensation 100-nF bypass capacitor for each VREFH_n and VREFL_n pin (n = G1, G2, G3, G4, G5, G6, G7
or G8) is required and should be placed as close as possible to the pins.
100 nF
(Minimize
inductance to pin)
REF[1,2]
Reference
(2.5V)
REFGND[1,2]
C = 100nF
(Minimize
VREFH_n
+10.5V
-10.5V
inductance to pin)
DAC Reference
DAC1
12-b
C = 100nF
(Minimize
VREFL_n
DAC Reference
inductance to pin)
Figure 34. Reference Operation
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7.4 Device Functional Modes
7.4.1 Toggle Mode
Each DAC in the device incorporates two DAC registers: Register A and Register B. The TRIGG pin is used to
switch the DAC outputs back and forth between the contents of the two DAC specific registers. The DAC
registers are prepared for trigger mode operation on a TRIGG rising edge and the outputs are toggled on each
following high-to-low transition. This feature enables the generation of 96 amplitude independent square-waves.
The device incorporates an auto-populate feature that simplifies register configuration in toggle mode. Auto-
populate is enabled by the APB bits in the CON register (address 0x4, bits [1:0]). When auto-populate is
enabled, a Register A update automatically loads Register B with the negative value of the data written to A.
Although the Register B data can be modified by a direct register write, this update does not auto-populate the
Register A contents.
The STATS output pin is used to identify the active register. A logic-low is output for Register A and logic-high for
register B. The STATS pin is in high impedance mode by default and must be enabled by the SDRV bits in the
CON register for subsystem 1 (address 0x4, bits [9:8]). The SDRV bits in the other three subsystems should be
set to high impedance mode (default mode).The toggling rate of the STATS terminal is determined by the SDIV
register (address 0x9). The SDIV register should only be updated after a device reset and before configuring the
DAC outputs The STATS output pin toggles on every 2SDIV trigger pulse (SDIV = 0, 1, …, 6).
7.4.2 DC Mode
A fixed TRIGG pin puts the device in DC mode operation. In DC mode only one of the two DAC data registers is
used to control the DAC output. If no TRIGG rising edge is detected by the device after power-up, Register A is
by default the active register.
22
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7.5 Programming
The DAC60096 is controlled through a flexible four-wire serial interface that is compatible with SPI type
interfaces used on many microcontrollers and DSP controllers. The interface provides read/write access to all
registers of the DAC60096.
For simplification of the register structure, communication to the device is done at a subsystem level through the
PTR global pointer register (address 0x6). Subsystem addressing is done through SID[1:0], where subsystem 1
is the default setting. Access to all other registers in the device will affect only the subsystem selected by SID.
The DAC pointer setting, DPTR[4:0], also in the PTR register allows access to the data registers (BUFA and
BUFB) for any of the DACs in the chosen subsystem.
Each serial interface access cycle is exactly 24 bits long. A frame is initiated by asserting the CS pin low. The
frame ends when the CS pin is deasserted high. The frame's first byte input to SDI is the instruction cycle which
identifies the request as a read or write, streaming or single, and the 4-bit address to be accessed. The following
bits in the frame form the data cycle. For all writes, data are clocked on the rising edge of SCLK. On read
access, data are clocked out on the SDO pin on either the falling edge or rising edge of SCLK according to the
PHAINV setting in each of the four subsystems CON registers (address 0x4, bits [7:6]).
Table 2. Serial Interface Cycle
Bit
Field
Description
23
R/W
Identifies the communication as a read or write command to the addressed
register.
R/W = 0 sets a write operation. R/W = 1 sets a read operation.
22
S
Identifies the communication as a streaming operation.
S = 0 is used for single command instructions. Bit = 1 is used for streaming
operation.
21:18
A[3:0]
Register address.
Specifies the register to be accessed during the read or write operation.
17:16
15:0
Reserved
D[15:0]
Reserved. Set to zeros for proper operation.
Data cycle bits.
If a write command, the data cycle bits are the values to be written to the
register with address A[3:0]
If a read command, the data cycle bits are don't care values.
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
SDI
R/W S=0 A3 A2 A1 A0
0
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
All Zeros
Figure 35. Serial Interface Write Bus Cycle
CS
SCLK
SDI
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S=0 A3 A2 A1 A0
All Zeros
PHAINV = 01
SDO
SDO
All Zeros
D15 D14 D13D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PHAINV = 10
All Zeros
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 36. Serial Interface Read Bus Cycle
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In order to simplify write or read operations to multiple DACs in a subsystem, streaming mode is supported. In
streaming mode, multiple bytes of data can be written to or read from the DAC60096 without specifically
providing instructions for each byte and is implemented by continually holding the CS pin active and continuing to
shift new data in or old data out of the device.
The DAC60096 starts reading or writing data to the DAC data register selected by the PTR register and
automatically increments the DAC pointer (DPTR) as long as the CS pin is asserted. If the last DAC in the
chosen subsystem has been reached and the CS pin is still asserted, the data register for this DAC will be
overwritten with the new data.
CS
1
2
3
4
5
6
7
8
9
25
41
57
SCLK
SDI
DAC N
DAC N+1
DAC N+2
DAC N+3
R/W S=1 A3 A2 A1 A0
0
0
{D11 œ D0, 0, 0, 0, 0} {D11 œ D0, 0, 0, 0, 0} {D11 œ D0, 0, 0, 0, 0} {D11 œ D0, 0, 0, 0, 0}
SDO
All Zeros
Figure 37. Serial Interface Streaming Write Cycle
CS
SCLK
SDI
1
2
3
4
5
6
7
8
9
25
41
57
R/W S=1 A3 A2 A1 A0
0
0
DAC N
DAC N+1
DAC N+2
DAC N+3
SDO
All Zeros
{D11 œ D0, 0, 0, 0, 0} {D11 œ D0, 0, 0, 0, 0} {D11 œ D0, 0, 0, 0, 0} {D11 œ D0, 0, 0, 0, 0}
Figure 38. Serial Interface Streaming Read Cycle
7.5.1 Frame Error Checking
If the DAC60096 is used in a noisy environment, error checking can be used to check the integrity of the serial
interface data communication between the device and the host processor. The frame error checking scheme is
based on the CRC-CCITT-16 polynomial x16 + x12 + x5 + 1 (that is, 0x1021). The CRC register (address 0x5)
stores the CRC computation for each single-command or streaming serial interface data write. Reading the CRC
register resets its contents to 0xFFFF.
Only valid data cycles are included in the CRC computation. For single-command instructions CRC is calculated
and updated only after 16 data bits are received. If a data cycle is longer than 16 bits, the additional bits are not
included into the CRC calculation. For streaming commands CRC is calculated and updated on the multiple 16-
bit data cycles received. If the number of data bits received is not a multiple of 16, the modulo 16 bits are
discarded from the CRC calculation.
24
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7.6 Register Maps
Communication to the DAC60096 is done at a subsystem level. Subsystem addressing is done through the
global pointer register, SID[1:0]. Each subsystem has 16 registers. Access to the data registers of any of the
DACs in the chosen subsystem is done through a DAC pointer, DPTR[4:0].
SUB-SYSTEM 4
SUB-SYSTEM 3
SUB-SYSTEM 2
Reg6
SID[1:0]
SUB-SYSTEM 1
DPTR[4:0]
DAC
Reg0
DAC
Active
Register A
Buffer
Register
A
...DACn
DAC2
0x0000
Reg0/1
(Asynchronous Mode)
12-Bit
DAC
DAC1
LDAC Trigger
(Synchronous Mode)
Clear State
Reg4
Reg5
Reg7
Reg8
Reg9
(Asynchronous Mode)
CON
CRC
Square-Wave
Mode
DAC
DAC
Active
Register
B
Reg1
Buffer
Register
B
SWR
PWRM
SDIV
Figure 39. Register Configuration
Table 3. Register Map
ADDRESS
REGISTER SETUP
REGISTER
TYPE
RESET
A3 A2 A1 A0
D15
D14
D13
D12
D11
D10
BUFA
BUFB
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
BUFA
BUFB
R/W
R/W
--
0000
0000
0000
0000
0555
FFFF
0000
0000
CAFE
0000
0000
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
RESERVED
RESERVED
CON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
--
0
0
0
0
0
0
0
R/W
R
LDAC
SDO2x
SDRV
PHAINV
CLRDAC
0
1
APB
CRC
CRC
PTR
R
0
0
0
0
SID
0
0
0
0
0
0
0
0
0
0
DPTR
SWR
R/W
R/W
R/W
--
SWR
PWRM
SDIV
PWRM
0
0
0
0
0
0
SDIV
RESERVED
0xA – 0xF
------
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7.6.1 8.5.1 BUFA Register (address = 0x0) [reset = 0x0000]
Figure 40. BUFA Register
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
BUFA
R/W
BUFA
R/W
RESERVED
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. BUFA Register
Bit
Field
Type
Reset
Description
15:4
BUFA
R/W
0000
Double-buffer MSB aligned 12-bit data for DAC register A. The
specific DAC accessed by this register must be first set by the
subsystem address (SID) and DAC pointer (DPTR).
3:0
Reserved
R/W
0000
Not used
7.6.2 BUFB Register (address = 0x1) [reset = 0x0000]
Figure 41. BUFB Register
15
14
13
12
11
10
2
9
1
8
0
BUFB
R/W
7
6
5
4
3
BUFB
R/W
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. BUFB Register
Bit
Field
Type
Reset
Description
15:4
BUFB
R/W
0000
Double-buffer MSB aligned 12-bit data for DAC register B. The
specific DAC accessed by this register must be first set by the
subsystem address (SID) and DAC pointer (DPTR).
3:0
Reserved
R/W
0000
Not used
26
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7.6.3 CON Register (address = 0x4) [reset = 0x0555]
Figure 42. CON Register
15
14
13
12
11
10
2
9
1
8
0
LDAC
R/W
Reserved
R/W
SDO2x[1:0]
R/W
SDRV[1:0]
R/W
7
6
5
4
3
PHAINV[1:0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
CLRDAC[1:0]
Reserved
R/W
APB[1:0]
R/W
R/W
Table 6. CON Register
Bit
Field
Type
Reset
Description
15
LDAC
R/W
0
Setting this bit to 1 issues an LDAC trigger at CS rising edge.
Self-clearing bit.
14:12
11:10
Reserved
R/W
R/W
000
01
Not used.
SDO2x[1:0]
SDO 1x/2x drive strength:
01: 1x (default)
10: 2x
Writing 00 or 11 has no effect
9:8
SDRV[1:0]
R/W
01
SDRV control STATS pin drive type:
01: Hi-Z. STATS pin is disabled (default)
10: CMOS Push-pull output. Should only be enabled for
subsystem 1.
Writing 00 or 11 has no effect
7:6
5:4
PHAINV[1:0]
CLRDAC[1:0]
R/W
R/W
01
01
PHAINV controls SDO output edge:
01: SCLK NegEdge (default)
10: SCLK PosEdge
Writing 00 or 11 has no effect
Clear DAC state control:
01: Normal operating state (default)
10: Clear DAC state
Writing 00 or 11 has no effect
3:2
1:0
Reserved
APB[1:0]
R/W
R/W
01
01
Reserved for factory use
Auto populate B:
01: Auto-populates BUFB with the negative value of BUFA after
each BUFA register write. Writing to BUFB has no auto-populate
effect (default)
10: Disable auto populate B feature
Writing 00 or 11 has no effect
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7.6.4 CRC Register (address = 0x5) [reset = 0xFFF]
Figure 43. CRC Register
15
7
14
6
13
5
12
4
11
10
2
9
1
8
0
CRC[15:0]
R
3
CRC[15:0]
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. CRC Register
Bit
Field
Type
Reset
Description
15:0
CRC[15:0]
R
FFFF
Stores the CRC computation data for each SPI data write. CRC
includes stream writes. The address byte is not included in the
CRC computation.
Reading Reg CRC resets current CRC value to 0xFFFF. CRC is
calculated when CS is enabled and the data cycle contains a
multiple of 16 bits. The redundant data are not written into the
register.
CRC-CCITT polynomial is used x16 + x12 + x5 + 1, or in hex:
0x1021 with default 0xFFFF.
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
Figure 44. CRC CCITT 16
28
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DAC60096
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7.6.5 PTR Register (address = 0x6) [reset = 0x0000]
Figure 45. PTR Register
15
7
14
6
13
5
12
4
11
10
2
9
1
8
0
Reserved
R/W
SID[1:0]
R/W
Reserved
R/W
3
Reserved
R/W
DPTR[4:0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. PTR Register
Bit
Field
Type
R/W
R/W
Reset
00
Description
15:14
13:12
Reserved
SID[1:0]
Reserved for factory use
00
Subsystem address:
00: Subsystem 1
01: Subsystem 2
10: Subsystem 3
11: Subsystem 4
11:8
7:5
Reserved
Reserved
DPTR[4:0]
R/W
R/W
R/W
0000
000
Not used
Reserved for factory use
DAC pointer
4:0
0000
7.6.6 SWR Register (address = 0x7) [reset = 0x0000]
Figure 46. SWR Register
15
14
13
12
11
10
2
9
1
8
0
SWR
R/W
7
6
5
4
3
SWR
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. SWR Register
Bit
Field
Type
Reset
Description
15:0
SWR
R/W
0000
Writing 0xA5A5 to this register generates a software reset on the
CS rising edge of the command for a subsystem. The software
reset is similar to a hardware reset, which resets all registers
and logic states.
Reading this register gives the hardware version of the
subsystem.
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7.6.7 PWRM Register (address = 0x6) [reset = 0xCAFE]
Figure 47. PWRM Register
15
7
14
6
13
5
12
4
11
10
2
9
1
8
0
PWRM
R/W
3
PWRM
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. PWRM Register
Bit
Field
Type
Reset
Description
15:0
PWRM
R/W
0000
DVDD Power Monitor:
After device power up, the PWRM register is 0xCAFE. Any
register write to PWRM sets PWRM to 0xABBA. PWRM is reset
to 0xCAFE after a DVDD collapse initiated POR event. Reading
PWRM with value 0xCAFE indicates power failure or
uninitialized value.
The system controller can monitor PWRM to check for active
power status. The device toggles the PWRM value after every
PWRM register read. If the current read value is 0xABBA, the
next read value will be 0xBAAB, and vice versa.
The PWRM register only monitors DVDD power failure. AVCC is
monitored by the analog reset circuit. When there is a power
failure on AVCC all the DACs in the device go into clear state.
7.6.8 SDIV Register (address = 0x9) [reset = 0x0000]
Figure 48. SDIV Register
15
14
13
12
11
10
2
9
8
0
Reserved
R/W
7
6
5
4
3
1
Reserved
R/W
SDIV
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SDIV Register
Bit
15:3
2:0
Field
Type
R/W
R/W
Reset
0000
000
Description
Reserved
SDIV
Not Used
Status signal toggle rate:
STATS pin toggling rate is controlled by SDIV register. SDIV is
valid between 0 and 6. The STATS pin toggles on every 2SDIV
trigger pulse.
The SDIV setting should only be updated after a device reset
and before configuring the DAC outputs.
30
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ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DAC60096 is a low-power, 96-channel, 12-bit, digital-to-analog converter (DAC). The device provides
unbuffered bipolar voltage outputs up to ±10.5 V.
This device is suitable for many applications involving multichannel bipolar DACs. Such applications include
multichannel variable optical attenuators, MEMS mirror control, and ATE level drivers.
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8.2 Typical Application
An example schematic incorporating the DAC60096 device is shown in Figure 49.
U1A
DAC60096NZHR
AVCC
C1
C3
C7
C9
0.1µF
C2
E1
E6
E7
E8
E9
E14
K14
K8
K9
K6
K7
K1
F7
J14
H13
H12
J13
K13
L13
M13
M12
N13
P12
P13
P14
P8
AVCC_G1
AVCC_G2
AVCC_G2
AVCC_G3
AVCC_G3
AVCC_G4
AVCC_G5
AVCC_G6
AVCC_G6
AVCC_G7
AVCC_G7
AVCC_G8
AVCC_S1
AVCC_S2
AVCC_S3
AVCC_S4
NC
DAC3_G5
DAC4_G5
DAC5_G5
DAC6_G5
DAC7_G5
DAC8_G5
DAC9_G5
DAC10_G5
DAC11_G5
DAC12_G5
DAC13_G5
DAC14_G6
DAC15_G6
DAC16_G6
DAC17_G6
DAC18_G6
DAC19_G6
DAC20_G6
DAC21_G6
DAC22_G6
DAC23_G6
DAC24_G6
NC
0.1µF
J12-1
J12-2
DVDD
0.1µF
J12-5
J12-6
C4
1µF
C5
0.1µF
C6
0.1µF
C8
0.1µF
0.1µF
J12-8
J12-9
J12-13
J12-18
J12-21
J12-19
J12-17
J12-28
J12-27
J12-26
J12-23
J12-22
J12-20
J12-14
J12-11
J12-12
J12-16
J12-15
DGND
0.1µF
AVCC
C10
0.22µF
C12
0.22µF
C17
0.1µF
C11
C16
0.22µF
0.22µF
F8
P9
C13
10µF
C14
1µF
C15
0.1µF
J8
J7
P10
P11
N11
N12
M11
L12
L11
K12
J12
J11
PWR_GND
PWR_GND
AVSS
C18
C20
C25
C27
0.1µF
C19
B1
B6
B7
B8
B9
B14
N14
N8
N9
N6
N7
N1
F6
AVSS_G1
AVSS_G2
AVSS_G2
AVSS_G3
AVSS_G3
AVSS_G4
AVSS_G5
AVSS_G6
AVSS_G6
AVSS_G7
AVSS_G7
AVSS_G8
AVSS_S1
AVSS_S2
AVSS_S3
AVSS_S4
AVSS
0.1µF
0.1µF
C21
10µF
C22
1µF
C23
0.1µF
C24
0.1µF
C26
0.1µF
0.1µF
H11
NC
K11
K4
K5
L5
DAC1_G7
DAC2_G7
DAC3_G7
DAC4_G7
DAC5_G7
DAC6_G7
DAC7_G7
DAC8_G7
DAC9_G7
DAC10_G7
DAC11_G7
DAC12_G7
DAC13_G7
DAC14_G8
DAC15_G8
DAC16_G8
DAC17_G8
DAC18_G8
DAC20_G8
DAC19_G8
DAC21_G8
DAC22_G8
DAC23_G8
DAC24_G8
DAC25_G8
DAC26_G8
J12-10
J14-21
J14-7
PWR_GND
0.1µF
J14-3
C28
0.22µF
C30
0.22µF
C32
0.1µF
M10
M5
N10
N4
N5
P4
P5
P6
P7
P1
P2
P3
N3
N2
M2
M3
M4
L2
J12-24
J14-4
C29
C31
0.22µF
0.22µF
F9
J9
J12-25
J14-9
J6
J14-6
J14-8
DGND
PWR_GND REF_GND AGND
DVDD
J14-5
J14-2
PWR_GND
C33
0.22µF
C35
0.22µF
G7
G8
H7
H8
DVDD
DVDD
DVDD
DVDD
C34
J14-1
DGND
0.22µF
J14-14
J14-12
J14-10
J14-11
J14-13
J14-19
J14-16
J14-15
J14-20
J14-22
J14-17
J14-18
J14-23
AVCC
C36
0.22µF
U2
2
6
5
3
4
G1
H1
VIN
VOUT
TRIM/NR
TEMP
REF1
C37
0.1µF
REFGND1
REF2
C38
10µF
C39
0.1µF
7
C40
NC
C41
1µF
G14
H14
8
1
10µF
DNC
DNC
C42
0.1µF
K2
L3
GND
REFGND2
PWR_GND
REF5025IDGK
G6
G9
H6
H9
L4
DGND
DGND
DGND
DGND
REF_GND
REF_GND
K3
DVDD
DGND
J1
1
3
5
7
9
2
TP1
4
J2 142-0701-201
1
SDI
/LDAC
6
SCLK
SDO
STATS
/CLEAR
/CS
/RESET
8
10
R1
R2
R3
R4
R5
10.0k
10.0k
10.0k
10.0k
100k
DGND
DVDD
TSW-105-07-G-D
AGND
DGND
PWR_GND
PWR_GND
Figure 49. Example Schematic
32
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
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ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
8.2.1 Design Requirements
Figure 49 uses the parameters shown in Table 12.
Table 12. Design Parameters
PARAMETER
AVCC
VALUE
12 V
5 V
DVDD
AVSS
–12 V
2.5 V
2.5 V
REF1
REF2
8.2.2 Detailed Design Procedure
The following sections display components and applications that may facilitate the design process.
8.2.2.1 Power-Supply Bypassing
For accurate, high-resolution performance, all power supply pins should be bypassed to ground with low ESR
ceramic bypass capacitors. For additional noise filtering, use a 10-µF capacitor in parallel with a 0.1-µF
capacitor.
8.2.2.2 Reference Input
The internal reference buffers of the DAC60096 device require an external 2.5-V reference voltage source, which
can be driven externally through a precision voltage source or generated from a high precision voltage IC. One
such integrated circuit is the REF5025, which is a low-noise, low-drift, high precision voltage reference. The basic
connections are listed in Figure 50. A supply bypass capacitor ranging between 1 µF to 10 µF is recommended.
A 1-µF to 50-µF output capacitor must be connected from VOUT to GND. The ESR value of the output capacitor
must be less than or equal to 1.5 Ω to ensure output stability. To help minimize noise, an additional 1-µF
capacitor is connected from TRIM/NR to GND.
AVCC
U2
2
7
6
5
3
4
VIN
VOUT
TRIM/NR
TEMP
REFOUT
C24
10µF
C26
0.1µF
C27
10µF
NC
C28
1µF
8
1
DNC
DNC
GND
PWR_GND
REF5025IDGK
REF_GND
Figure 50. External Reference
8.2.2.3 TRIGG/Signal Conditioning
The TRIGG input signal provides the square waveform required for the DAC60096 device to operate as a
square-wave generator. The DAC registers are prepared for square wave operation on a TRIGG rising edge and
the outputs toggle on the falling edge. The Timing Requirements(1)(2) table specifies the timing parameters
required for proper operation.
The TRIGG input signal can be supplied from a waveform generator or voltage-to-frequency converter. An
example device with schematic is provided in Figure 51. The device highlighted is the LM231, a precision
voltage-to-frequency converter with wide range of full-scale frequency (1 Hz to 100 kHz). In Figure 51 the device
is configured to display 0.05% linearity over an output frequency range of 10 Hz to 4 kHz with and input range of
25 mV to 12.5 V. For more information, refer to the Typical Applications section of the LM231 datasheet
(SNOSBI2).
(1) Specified by design and characterization. Not tested during production.
(2) SDO loaded with 10-pF load capacitance for SDO timing specifications.
Copyright © 2015–2016, Texas Instruments Incorporated
33
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
DVDD
RS
12 kΩ
5K Gain Adjust
10 kΩ
U1
REF I
To DAC60096 TRIG Input
Freq_Out
2
6
7
8
3
1
5
4
FREQ OUT
I OUT
GND
THR
THR
THR
RIN
100 kΩ
COMP IN
R/C
CL
1 μF
+Vs
RL
100 kΩ
VS
GND
VIN
Vs
CIN
0.1 μF
LM231AN
22 kΩ
GND
Rt
6.8 kΩ
GND
Ct
0.01 μF
47 Ω
–Vs
(Optional) Offset Adjust
GND
GND
-All resistors 1% tolerance
-Caps with low dielectric absorption: NP0, C0G, polystyrene, and so on.
fout = (VIN / 2.09 V) ´ (RS / RL) ´ (1 / (Rt ´ Ct))
Figure 51. External Precision Voltage-to-Frequency Converter for TRIGG Signal
8.2.2.4 External Amplifier Selection
The outputs of the DAC60096 are unbuffered. The output impedance is specified as 41 kΩ. In applications
requiring an external buffer, the selected amplifier should exhibit both low-offset voltage and input bias current.
The input bias current of the amplifier creates a potential across the DAC output impedance. This voltage error is
equivalent to the input bias current multiplied by the DAC output impedance value. For fast settling, the slew rate
of the operational amplifier should not impede the settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but in order to minimize gain errors the input impedance of the output amplifier
should be as high as possible. Additionally, the amplifier adds another time constant, which increases the settling
time response of the system. A higher 3-dB bandwidth amplifier effectively shortens the settling time, and
additionally increases the bandwidth of the system.
VCC
1
8
U1
OPA277U
6
2
3
5
Final Output
DACOUT
VSS
Figure 52. DAC Output With External Amplifier in Voltage-Follower Configuration
8.2.2.5 Unbuffered Settling Response
For applications that use the unbuffered output, the typical settling response for different capacitive loads is
displayed in Figure 53.
34
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
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ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
8.2.3 Application Curves
500
400
300
200
100
0
200
400
600
800
1000
Capacitive Load (pF)
C012
Figure 53. DAC Settling Time vs Capacitive Load
Copyright © 2015–2016, Texas Instruments Incorporated
35
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
9 Power Supply Recommendations
It is highly recommended that AVCC is supplied prior to AVSS. DVDD sequencing is not critical. The recommended
sequence is AVCC followed by AVSS with DVDD and the REF[1,2] inputs applied last.
Table 13. Input-Voltage Recommendations
MIN
11.2
–12.6
3
TYP
12
MAX
12.6
–11.2
5.5
UNIT
AVCC
V
V
V
V
AVSS
–12
3.3
24
Supply voltage
DVDD
AVCC to AVSS
22.4
25.2
EXTERNAL REFERENCE INPUTS
VREF
Reference input voltage
REF1 and REF2 input pins
2.475
2.5
2.525
V
9.1 Device Reset Options
9.1.1 Power-on-Reset (POR)
The DAC60096 includes a power-on reset function. After the DVDD supply has been established a POR event is
issued. The POR causes all registers to initialize to their default values and communication with the device is
valid only after a 250 µs power-on-reset delay. The default value for all DACs is zero-code.
A power failure on DVDD also results in a power-on-reset event. The PWRM register (address 0x8) can be used
to monitor a DVDD power failure. After power-up the PWRM register is set to 0xCAFE. Any register write to the
PWRM register changes its contents to 0xABBA. If a PWRM register read returns 0xCAFE either the PWRM
register has not been initialized or a DVDD power failure has occured.
The device also includes an AVCC power failure detection circuit. In contrast to a DVDD power failure, a collapse
in AVCC does not result in a reset event. An AVCC power failure forces all DACs to go into clear state but does
not reset the DAC data register values which enables the device to return to normal operation once AVCC
recovers. Even though the DACs are loaded with zero-code during an AVCC power failure, it is important to note
that this does not necessarily indicate the DAC outputs will be at 0 V due to AVCC being outside of its supply
voltage range.
As long as DVDD and AVCC remain above their specified high threshold a power failure event will not occur. In
order to ensure a DVDD or AVCC collapse is registered as such by the device, these supplies must be below their
corresponding low threshold for at least 1 ms. When the supplies drop below their high threshold but remain over
the lower one (shown as the undefined region of Figure 54 and Figure 55), the device may or may not reset
(DVDD) or go into clear state (AVCC) under all specified temperature and power-supply conditions.
36
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
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ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
Device Reset Options (continued)
AVCC (V)
12.6
DVDD (V)
5.5
Specified Supply
Voltage Range
11.2
Specified Supply
Voltage Range
Normal State
bo tower-hn ꢀeseꢁ
2.7
2.2
6
4
Undefined
Clear State
Ündefined
0.7
tower-hn ꢀeseꢁ
0
0
Figure 54. Threshold Levels for DVDD POR Circuit
9.1.2 Hardware Reset
Figure 55. Threshold Levels for AVCC Clear Circuit
A device hardware reset event is initiated by a minimum 500 ns logic low on the RESET pin. A hardware reset
causes all registers to initialize to their default values and communication with the device is valid only after a 50
µs reset delay. The default value for all DACs is zero-code.
9.1.3 Software Reset
A subsystem software reset event is initiated by writing 0xA5A5 to the SWR register (address 0x7) for that
particular subsystem. The software reset command is triggered on the CS rising edge of the instruction. As with
the hardware reset, a software reset causes all registers to initialize to their default values and communication
with the device is valid only after a 50 µs. Note, however, that the reset only applies to the subsystem being
addressed during the command. In order to reset the entire device as a hardware reset does, a software reset
command should be issued to each of the four subsystems in the device.
Copyright © 2015–2016, Texas Instruments Incorporated
37
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
•
Bypass all power-supply pins to ground with a low ESR ceramic bypass capacitor. The typical recommended
bypass capacitance is 0.1-µF to 0.22-µF ceramic with a X7R or NP0 dielectric.
•
Place power supplies and VREFH/L bypass capacitors close to pins to minimize inductance and optimize
performance. Inner supply and reference pads can connect to the bypass arrangement on the bottom layer of
the PCB through vias to minimize trace length. This is illustrated in Figure 56 and Figure 59.
•
•
•
Include a 100-nF bypass capacitor for both internal reference inputs between this pin and their respective
ground pins.
Use a high-quality ceramic type NP0 or X7R for optimal performance across temperature, and low dissipation
factor.
Make sure that the digital and analog sections have proper placement with respect to the digital pins and
analog pins of the DAC60096 device. The separation of analog and digital blocks allow for better design and
practice because it reduces coupling into neighboring blocks, and minimizes the interaction between analog
and digital return currents.
10.2 Layout Examples
10.2.1 Optimal Layout Example
Optimal layout requires the addition of blind vias. This layout reduces trace length and brings the bypass
capacitor arrangements closer to the device pads. Figure 56 to Figure 59 show the board layouts.
38
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
www.ti.com.cn
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
Layout Examples (continued)
Place Bypass Capacitors
Close to Supply and
Reference Pins
1 2 3 4
6 7 8 9
5
1. 0.1uF
2. 0.15uF
3. 0.15uF
4. 0.1uF
5. 0.1uF
6. 0.1uF
7. 0.15uF
8. 0.15uF
9. 0.1uF
10. 0.1uF
11. 0.15uF
12. 0.15uF
13. 0.1uF
14. 0.1uF
15. 0.1uF
16. 0.15uF
17. 0.15uF
18. 0.1uF
Pin 1
14
15 16 17 18
10 11 12 13
Figure 56. DAC60096 Example Board Layout – Top Layer PCB
Copyright © 2015–2016, Texas Instruments Incorporated
39
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
Layout Examples (continued)
Figure 57. DAC60096 Example Board Layout – Internal AVCC and AVSS Plane
40
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
www.ti.com.cn
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
Layout Examples (continued)
Figure 58. DAC60096 Example Board Layout – DVDD Internal Plane With Select DAC Outputs
Copyright © 2015–2016, Texas Instruments Incorporated
41
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
Layout Examples (continued)
Figure 59. DAC60096 Example Board Layout – Bottom Layer PCB.
(A): Bypass Capacitor Arrangement; (B) Polygon Pours; (C) PAD With Pours
42
Copyright © 2015–2016, Texas Instruments Incorporated
DAC60096
www.ti.com.cn
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
Layout Examples (continued)
10.2.2 Standard Layout Example
Only through-hole vias are included in this layout. Bypass capacitors are placed as close to their respective
device pads. Bottom bypass brought out from device. This layout can lead to increased trace length, which will
increase the series inductance of the net making it more susceptible to noise and voltage spikes. Figure 60 to
Figure 61 show the board layouts.
Figure 60. DAC60096 Example Board Layout – Top Layer
Copyright © 2015–2016, Texas Instruments Incorporated
43
DAC60096
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
Layout Examples (continued)
Figure 61. DAC60096 Example Board Layout – Bottom Layer
44
版权 © 2015–2016, Texas Instruments Incorporated
DAC60096
www.ti.com.cn
ZHCSEG7A –DECEMBER 2015–REVISED JANUARY 2016
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
《LM231 数据表》，SNOSBI2
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola Inc.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧导航栏。
版权 © 2015–2016, Texas Instruments Incorporated
45
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC60096IZEB
ACTIVE
NFBGA
ZEB
196
126
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DAC60096
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DAC60096IZEB
ZEB
NFBGA
196
126
7 X 18
150
315 135.9 7620 17.2
11.3 16.35
Pack Materials-Page 1
PACKAGE OUTLINE
ZEB0196A
NFBGA - 1.48 mm max height
SCALE 0.900
PLASTIC BALL GRID ARRAY
15.1
14.9
A
B
BALL A1 CORNER
15.1
14.9
1.48 MAX
C
SEATING PLANE
0.12 C
0.43
0.25
TYP
BALL TYP
13 TYP
SYMM
(1) TYP
(1) TYP
SYMM
P
N
M
L
K
J
13
H
G
F
TYP
E
D
C
0.51
196X
0.41
0.15
0.08
C A
C
B
B
A
1 TYP
1
2
3
4
5
6 9 10 11 12 13 14
7
8
1 TYP
BALL A1 CORNER
4221792/B 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZEB0196A
NFBGA - 1.48 mm max height
PLASTIC BALL GRID ARRAY
(1) TYP
196X ( 0.45)
3
4
7
9
1
2
5
6
8
10 11
12 13 14
A
B
C
(1) TYP
D
E
F
SYMM
G
H
J
K
L
M
N
P
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
METAL UNDER
SOLDER MASK
0.05 MAX
0.05 MIN
(
0.45)
METAL
(
0.45)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221792/B 12/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZEB0196A
NFBGA - 1.48 mm max height
PLASTIC BALL GRID ARRAY
196X ( 0.45)
(1) TYP
3
4
7
9
1
2
5
6
8
10 11
12 13 14
A
B
C
(1) TYP
D
E
F
SYMM
G
H
J
K
L
M
N
P
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:6X
4221792/B 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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相关型号：
DAC602H
PARALLEL, WORD INPUT LOADING, 4us SETTLING TIME, 12-BIT DAC, CDIP28, 0.300 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-28
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