DAC63202RTER [TI]
具有 I²C 和 SPI 的双通道、12 位、输入和输出电压智能 DAC | RTE | 16 | -40 to 125;
| 型号： | DAC63202RTER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I²C 和 SPI 的双通道、12 位、输入和输出电压智能 DAC | RTE | 16 | -40 to 125 |
| 文件： | 总85页 (文件大小：3371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC53202, DAC63202
ZHCSQC6 –MAY 2022
DACx3202 带自动检测型I2C、PMBus™ 或SPI 接口的12 位和10 位双路电压和
电流输出智能DAC
1 特性
2 应用
• 具有灵活配置的可编程电压或电流输出：
– 电压输出：
• 机架式服务器
• 光学模块
• 数据中心间互联（地铁）
• 高性能计算
• 标准笔记本电脑
• 1 LSB INL 和DNL（10 位和8 位）
• 1x、1.5x、2x、3x 和4x 增益
– 电流输出：
3 说明
• 1LSB INL 和DNL（8 位）
• ±25 μA、±50 μA、±125 μA、±250 μA
输出范围选项
12 位 DAC63202 和 10 位 DAC53202 (DACx3202) 是
引脚兼容系列双通道、缓冲型、电压输出和电流输出智
能数模转换器 (DAC)。这些 DACx3202 器件支持高阻
态断电模式，并在断电情况下支持高阻态输出。DAC
输出提供一个强制检测选项，可用作可编程比较器和电
流阱。得益于多功能 GPIO、函数生成和 NVM，此类
智能DAC 可用于无处理器的 应用和设计复用。这些器
件自动检测 I2C、PMBus 和 SPI 接口，并包含内部基
准。
• 适合所有通道的可编程比较器模式
• 当VDD 关闭时提供高阻抗输出
• 高阻抗和电阻下拉断电模式
• 50MHz SPI 兼容型接口
• 自动检测的I2C、PMBus™ 或SPI 接口
– 1.62V VIH (VDD = 5.5V)
• 可配置为多种功能的通用输入/输出(GPIO)
• 生成预定义的波形：正弦波、余弦波、三角形波、
锯齿波
• 用户可编程的非易失性存储器(NVM)
• 内部、外部或电源作为基准
• 宽工作电压范围：
这些功能集与微型封装和低功耗相结合，使这些智能
DAC 成为电压裕量和调节、偏置和校准用直流设定点
以及波形生成等应用的理想选择。
器件信息
器件型号
封装(1)
封装尺寸（标称值）
– 电源：1.8V 至5.5V
– 温度：-40˚C 至+125˚C
DACx3202
WQFN (16)
3.00mm x 3.00mm
• 微型封装：16 引脚WQFN (3mm × 3mm)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VDD
10 kΩ
0.1 μ
1.5 μ
VREF
CAP
LDO
L
VIN
IN
PH
VOUT
Internal
Reference
NVM
SCL/SYNC
SDA/SCLK
A0/SDI
BOOT
R1
SMPS / LDO
GND
CL
CB
R3
VFB
R2
DAC
REG
DAC
BUF
VOUT/
IOUT
SENSE
R3
DAC
REG
DAC
BUF
VOUT/
IOUT
PROTECT
Output Configuration
Logic
Power-supply: 0
Power-supply: 1
DACx3202
AGND
使用DACx3202 实现电压裕量和调节
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASF47
DAC53202, DAC63202
ZHCSQC6 –MAY 2022
www.ti.com.cn
Table of Contents
6.19 Typical Characteristics: Comparator.......................26
6.20 Typical Characteristics: General............................. 27
7 Detailed Description......................................................28
7.1 Overview...................................................................28
7.2 Functional Block Diagram.........................................28
7.3 Feature Description...................................................29
7.4 Device Functional Modes..........................................30
7.5 Programming............................................................ 47
7.6 Register Map.............................................................55
8 Application and Implementation..................................73
8.1 Application Information............................................. 73
8.2 Typical Application.................................................... 73
9 Power Supply Recommendations................................77
10 Layout...........................................................................77
10.1 Layout Guidelines................................................... 77
10.2 Layout Example...................................................... 77
11 Device and Documentation Support..........................78
11.1 Documentation Support.......................................... 78
11.2 接收文档更新通知................................................... 78
11.3 支持资源..................................................................78
11.4 Trademarks............................................................. 78
11.5 Electrostatic Discharge Caution..............................78
11.6 术语表..................................................................... 78
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: Voltage Output...................7
6.6 Electrical Characteristics: Current Output...................9
6.7 Electrical Characteristics: Comparator Mode............10
6.8 Electrical Characteristics: General............................11
6.9 Timing Requirements: I2C Standard Mode............... 12
6.10 Timing Requirements: I2C Fast Mode.....................12
6.11 Timing Requirements: I2C Fast Mode Plus............. 12
6.12 Timing Requirements: SPI Write Operation............13
6.13 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 0).......................................13
6.14 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 1).......................................13
6.15 Timing Requirements: GPIO...................................15
6.16 Timing Diagrams.....................................................15
6.17 Typical Characteristics: Voltage Output.................. 17
6.18 Typical Characteristics: Current Output.................. 22
Information.................................................................... 78
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
May 2022
*
Initial Release
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5 Pin Configuration and Functions
FB0
OUT0
NC
1
2
3
4
12
11
10
9
FB1
OUT1
NC
Thermal Pad
NC
NC
Not to scale
图5-1. RTE (16-pin WQFN) Package, Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Voltage feedback pin for channel 0.
1
FB0
Input
In voltage-output mode, connect to OUT0 for closed-loop amplifier output.
In current-output mode, keep the FB0 pin unconnected to minimize leakage current.
2
3
4
OUT0
NC
Output
NC
Analog output voltage from DAC channel 0.
No connection. Leave the pin unconnected.
No connection. Leave the pin unconnected.
NC
NC
General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS.
5
6
7
8
GPIO/SDO
SCL/SYNC
A0/SDI
Input/Output For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor.
If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD.
I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using an external
pullup resistor. This pin can ramp up before VDD.
Output
Address configuration pin for I2C or serial data input for SPI.
Input
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (节7.5.2.2.1).
For SDI, this pin does not need to be pulled up or pulled down. This pin can ramp up before VDD.
Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external
pullup resistor in I2C mode. This pin can ramp up before VDD.
SDA/SCLK
Input/Output
9
NC
NC
NC
NC
No connection. Leave the pin unconnected.
No connection. Leave the pin unconnected.
Analog output voltage from DAC channel 1.
10
11
OUT1
Output
Voltage feedback pin for channel 1.
12
FB1
Input
In voltage-output mode, connect to OUT1 for closed-loop amplifier output.
In current-output mode, keep the FB1 pin unconnected to minimize leakage current.
13
14
15
CAP
AGND
VDD
Power
Ground
Power
External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.
Ground reference point for all circuitry on the device.
Supply voltage.
External reference input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND.
Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In case
an external reference is used, make sure the reference ramps up after VDD.
16
VREF
Power
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
Thermal
pad
Thermal Pad
Ground
Connect the thermal pad to AGND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
6
UNIT
V
VDD
Supply voltage, VDD to AGND
Digital inputs to AGND
CAP to AGND
VDD + 0.3
1.65
V
V
VFBX to AGND
VDD + 0.3
VDD + 0.3
VDD + 0.3
10
V
VOUTX to AGND
V
VREF
External reference, VREF to AGND
Current into any pin except the OUTx pins
Junction temperature
Storage temperature
V
mA
°C
°C
TJ
150
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
NOM
MAX UNIT
VDD
VREF
VIH
Positive supply voltage to ground (AGND
)
5.5
V
V
External reference to ground (AGND
)
1.7
VDD
1.62
V
Digital input high voltage, 1.7 V < VDD ≤5.5 V
Digital input low voltage
VIL
0.4
15
V
CCAP
TA
External capacitor on CAP pin
Ambient temperature
0.5
μF
°C
125
–40
6.4 Thermal Information
DACx3202
THERMAL METRIC(1)
RTE (WQFN)
UNIT
16 PINS
49
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
50
24.1
1.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
24.1
ΨJB
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DACx3202
RTE (WQFN)
16 PINS
THERMAL METRIC(1)
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.7
°C/W
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics: Voltage Output
at 1.7 V ≤VDD ≤5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL =
5 kΩto AGND) and capacitive load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all minimum and maximum
specifications at –40°C ≤TA ≤+125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
DAC63202
DAC53202
DAC63202
DAC53202
12
10
Resolution
Bits
4
1
–4
–1
–1
INL Integral nonlinearity(1)
LSB
LSB
DNL Differential nonlinearity(1)
1
Code 0d into DAC, external reference, VDD = 5.5 V
6
6
12
Zero-code error(4)
mV
Code 0d into DAC, internal VREF, gain = 4x,
VDD = 5.5 V
15
Zero-code error temperature
coefficient(4)
Code 0d into DAC
±10
0.3
µV/°C
1.7 V ≤VDD < 2.7 V, FBx pin shorted to OUTx, DAC
code: 32d for 12-bit resolution, 8d for 10-bit resolution
0.75
0.5
–0.75
–0.5
Offset error(4) (6)
%FSR
2.7 V ≤VDD ≤5.5 V, FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit
resolution
0.25
Offset-error temperature
coefficient(4)
FBx pin shorted to OUTx, DAC code: 32d for
12-bit resolution, 8d for 10-bit resolution
±0.0003
0.25
%FSR/°C
%FSR
Between end-point codes: 32d to 4064d for 12-bit
resolution, 8d to 1016d for 10-bit resolution
Gain error(4)
0.5
–0.5
Gain-error temperature
coefficient(4)
Between end-point codes: 32d to 4064d for 12-bit
resolution, 8d to 1016d for 10-bit resolution
±0.0008
%FSR/°C
1
1.7 V ≤VDD < 2.7 V, DAC at full-scale
2.7 V ≤VDD ≤5.5 V, DAC at full-scale
–1
Full-scale error(4) (6)
%FSR
0.5
–0.5
Full-scale-error temperature
coefficient(4)
DAC at full-scale
±0.0008
%FSR/°C
OUTPUT
Output voltage
Reference tied to VDD
0
VDD
200
V
RL = infinite, phase margin = 30°
Phase margin = 30°
CL
Capacitive load(2)
pF
1000
VDD = 1.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
15
50
60
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
Short-circuit current
mA
V
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
To VDD (DAC output unloaded, internal reference =
1.21 V), VDD ≥1.21 V ☓ gain + 0.2 V
0.2
0.8
To VDD and AGND (DAC output unloaded, external
reference at VDD, gain = 1x, the VREF pin is not
shorted to VDD)
Output-voltage headroom(2)
%FSR
To VDD and AGND (ILOAD = 10 mA at VDD = 5.5 V, ILOAD
= 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V),
external reference at VDD, gain = 1x, the VREF pin is
not shorted to VDD
10
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6.5 Electrical Characteristics: Voltage Output (continued)
at 1.7 V ≤VDD ≤5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL =
5 kΩto AGND) and capacitive load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all minimum and maximum
specifications at –40°C ≤TA ≤+125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
400
325
TYP
MAX
UNIT
DAC output enabled, internal reference (gain = 1.5x or
2x) or external reference at VDD (gain = 1x), the VREF
pin is not shorted to VDD
500
600
ZO
VFB dc output impedance(3)
kΩ
DAC output enabled, internal VREF, gain = 3x or 4x
400
485
Power supply rejection ratio
(dc)
Internal VREF, gain = 2x, DAC at midscale,
VDD = 5 V ±10%
0.25
mV/V
µs
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V
20
25
tsett Output voltage settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4x
Slew rate
VDD = 5.5 V
0.3
75
V/µs
mV
At startup (DAC output disabled)
At startup (DAC output disabled), RL = 100 kΩ
Power-on glitch magnitude
200
DAC output disabled to enabled (DAC registers at zero
scale), RL = 100 kΩ
Output-enable glitch
magnitude
250
50
mV
f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V
Output noise voltage (peak to
peak)
Vn
µVPP
Internal VREF, gain = 4x, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V
90
f = 1 kHz, DAC at midscale, VDD = 5.5 V
0.35
0.9
Output noise density
µV/√Hz
Internal VREF, gain = 4x, f = 1 kHz, DAC at midscale,
VDD = 5.5 V
Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(3)
-68
dB
±1-LSB change around midscale (including
feedthrough)
Code change glitch impulse
10
15
nV-s
mV
Code change glitch impulse
magnitude
±1-LSB change around midscale (including
feedthrough)
POWER
Normal operation, DACs at full scale, digital pins static,
IDD
Current flowing into VDD(4) (5) external reference at VDD but the VREF pin is not
shorted to VDD
150
µA/ch
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥1.21 x gain + 0.2 V, between end-point
codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4) Measured with DAC output unloaded.
(5) The total power consumption is calculated by IDD x (total number of channels powered on) + (sleep-mode current).
(6) When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show
parametric drift.
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6.6 Electrical Characteristics: Current Output
at 1.7 V ≤VDD ≤5.5 V, ±250-µA output range, digital inputs at VDD or AGND, and all minimum and maximum
specifications at –40°C ≤TA ≤+125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
–1
–1
Bits
LSB
INL Integral nonlinearity
DNL Differential nonlinearity
Offset error
DAC codes between 0d and 255d
DAC codes between 0d and 255d
DAC at midscale
1
1
LSB
±1
%FSR
%FSR
Gain error
DAC codes between 0d and 255d
±1.3
OUTPUT
Output compliance voltage(1)
To VDD and AGND
400
60
mV
ZO
IOUT dc output impedance(2)
DAC at midscale, DAC output kept at VDD/2
MΩ
Power supply rejection ratio
(dc)
DAC at midscale, all bipolar ranges, VDD changed from
4.5 V to 5.5 V
0.23
60
LSB/V
µs
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB
at 8-bit resolution, VDD = 5.5 V, common-mode voltage
at OUTx pin is VDD/2
tsett Output current settling time
Output noise current (peak to 0.1 Hz to 10 Hz, DAC at midscale,
Vn
150
1
nAPP
peak)
VDD = 5.5 V, ±250-µA output range
f = 1 kHz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range
Output noise density
nA/√Hz
±250-µA output range, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power-supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(3)
0.65
LSB/V
POWER
Normal operation, DACs at full scale, ±25-µA output
range, digital pins static
42
56
50
70
Normal operation, DACs at full scale, ±50-µA output
range, digital pins static
IDD
Current flowing into VDD(3) (4)
µA/ch
Normal operation, DACs at full scale, ±125-µA output
range, digital pins static
98
120
200
Normal operation, DACs at full scale, ±250-µA output
range, digital pins static
167
(1) Measured between DAC codes 0d and 255d.
(2) Specified by design and characterization, not production tested.
(3) The current flowing into VDD does not account for the load current sourced or sinked on the OUTx pins. The VREF pin is connected to
VDD
(4) The total power consumption is calculated by IDD x (total number of channels powered on) + (sleep-mode current).
.
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6.7 Electrical Characteristics: Comparator Mode
at 1.7 V ≤VDD ≤5.5 V, DAC reference tied to VDD, gain = 1x in voltage output mode, DAC output pin (OUT) loaded with
resistive load (RL = 5 kΩto AGND) and capacitive load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all
minimum and maximum specifications at –40°C ≤TA ≤+125°C and typical specifications at TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC PERFORMANCE
1.7 V ≤VDD ≤5.5 V, DAC at midscale, comparator
input at Hi-Z, and DAC operating with external
reference
Offset error(1) (2)
0
5
mV
mV
–5
VDD = 5.5 V, external reference, TA = 125°C, FBx in Hi-
Z mode, DAC at full scale and VFB at 0 V or DAC at
zero scale and VFB at 1.84 V, drift specified for 10
years of continuous operation
Offset error time drift(1)
4
OUTPUT
VREF connected to VDD, FBx resistor network
connected to ground
0
0
VDD
Input voltage
V
V
VREF connected to VDD, FBx resistor network
disconnected from ground
VDD (1/3 –1/100)
VOL Logic low output voltage
0.1
10
ILOAD = 100 μA, output in open-drain mode
DYNAMIC PERFORMANCE
DAC at midscale with 10-bit resolution, FBx input at Hi-
Z, and transition step at FBx node is
(VDAC –2 LSB) to (VDAC + 2 LSB), transition time
measured between 10% and 90% of output, output
current of 100 µA, comparator output configured in
push-pull mode, load capacitor at DAC output is
25 pF
tresp Output response time
µs
(1) Specified by design and characterization, not production tested.
(2) This specification does not include the total unadjusted error (TUE) of the DAC.
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6.8 Electrical Characteristics: General
at 1.7 V ≤VDD ≤5.5 V, DAC reference tied to VDD, gain = 1x in voltage output mode or ±250-µA output range in current
output mode, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) in voltage-output mode and capacitive
load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all minimum and maximum specifications at
–40°C ≤TA ≤+125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER
INTERNAL REFERENCE
Initial accuracy
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
1.1979
1.212
1.224
V
Reference output temperature
50 ppm/°C
coefficient(1) (2)
EXTERNAL REFERENCE
VREF input impedance(1) (3)
EEPROM
192
kΩ/ch
20000
1000
50
–40°C ≤TA ≤+85°C
TA = 125°C
Endurance(1)
Cycles
Years
Data retention(1)
TA = 25°C
EEPROM programming write
cycle time(1)
200
ms
Time taken from power valid (VDD ≥1.7 V) to output
valid state (output state as programmed in EEPROM),
0.5-µF capacitor on the CAP pin
Device boot-up time(1)
5
ms
DIGITAL INPUTS
Voltage output mode, DAC output static at midscale,
fast mode plus, SCL toggling
Digital feedthrough
20
10
nV-s
pF
Pin capacitance
Per pin
POWER-DOWN MODE
DAC in sleep mode, internal reference powered down,
external reference at 5.5 V
28
DAC in sleep mode, internal reference
enabled, additional current through internal reference
10
IDD
Current flowing into VDD(1)
µA
DAC channels enabled, internal reference enabled,
additional current through internal reference per DAC
channel in voltage-output mode
12.5
HIGH-IMPEDANCE OUTPUT
10
DAC in Hi-Z output mode, 1.7 V ≤VDD ≤5.5 V
VDD = 0 V, VOUT ≤1.5 V, decoupling capacitor
between VDD and AGND = 0.1 μF
200
nA
µA
Current flowing into VOUTX and
VFBX
ILEAK
VDD = 0 V, 1.5 V < VOUT ≤5.5 V, decoupling capacitor
between VDD and AGND = 0.1 μF
500
±2
100 kΩbetween VDD and AGND, VOUT ≤1.25 V,
series resistance of 10 kΩat OUTx pin
(1) Specified by design and characterization, not production tested.
(2) Measured at –40°C and +125°C and calculated the slope.
(3) Impedances for the DAC channels are connected in parallel.
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6.9 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
kHz
µs
fSCLK
tBUF
SCL frequency
100
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
4.7
4
µs
µs
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
tHIGH
tF
SCL clock high period
Clock and data fall time
Clock and data rise time
Data valid time
ns
300
1000
3.45
3.45
ns
tR
ns
tVD_DAT
tVD_ACK
µs
Data valid acknowledge time
µs
6.10 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
kHz
µs
fSCLK
tBUF
SCL frequency
400
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
0.6
µs
0.6
µs
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
tHIGH
tF
SCL clock high period
Clock and data fall time
Clock and data rise time
Data valid time
ns
300
300
0.9
0.9
ns
tR
ns
tVD_DAT
tVD_ACK
µs
Data valid acknowledge time
µs
6.11 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
0.5
µs
SCL clock high period
Clock and data fall time
Clock and data rise time
0.26
µs
120
120
ns
tR
ns
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all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
0.45
0.45
UNIT
µs
tVD_DAT
tVD_ACK
Data valid time
Data valid acknowledge time
µs
6.12 Timing Requirements: SPI Write Operation
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, and –40°C ≤TA ≤+125°C
MIN
NOM
MAX
UNIT
MHz
ns
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
Serial clock frequency
SCLK high time
50
9
9
SCLK low time
ns
SDI setup time
8
ns
tSDIH
SDI hold time
8
ns
tCSS
CS to SCLK falling edge setup time
SCLK falling edge to CS rising edge
CS hight time
18
10
50
2
ns
tCSH
ns
tCSHIGH
tDACWAIT
ns
Sequential DAC update wait time for same channel
µs
tBCASTWAIT Broadcast DAC update wait time
2
µs
6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and FSDO = 0
MIN
NOM
MAX
UNIT
MHz
ns
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
Serial clock frequency
1.25
SCLK high time
350
350
8
SCLK low time
ns
SDI setup time
ns
tSDIH
SDI hold time
8
ns
tCSS
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
SYNC hight time
400
400
1
ns
tCSH
ns
tCSHIGH
tSDODLY
µs
300
ns
SCLK rising edge to SDO falling edge, IOL ≤5 mA, CL = 20 pF.
6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and FSDO = 1
MIN
NOM
MAX
UNIT
MHz
ns
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
Serial clock frequency
SCLK high time
2.5
175
175
8
SCLK low time
ns
SDI setup time
ns
tSDIH
SDI hold time
8
ns
tCSS
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
SYNC hight time
300
300
1
ns
tCSH
ns
tCSHIGH
µs
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all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and FSDO = 1
MIN
NOM
MAX
UNIT
tSDODLY
300
ns
SCLK rising edge to SDO falling edge, IOL ≤5 mA, CL = 20 pF.
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6.15 Timing Requirements: GPIO
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, and –40°C ≤TA ≤+125°C
MIN
2
NOM
MAX
UNIT
µs
tGPIHIGH
tGPILOW
tGPAWGD
tCS2LDAC
tSTP2LDAC
tLDACW
GPI high time(1)
GPI low time(1)
2
µs
LDAC falling edge to DAC update delay(2)
SYNC rising edge to LDAC falling edge
I2C stop bit rising edge to LDAC falling edge
LDAC low time
2
µs
1
1
2
µs
µs
µs
(1) The SCL, SDA, A0, and A1 pins can be configured as GPIOs that perform different channel-specific or independent operations. The
actual response time of the GPIO is determined by the delay provided by the configured function and the settling time of the DAC.
(2) The GPIOs can be configured as channel-specific or global LDAC function.
6.16 Timing Diagrams
Low byte ACK cycle
tR
tLOW
tF
SCL
tSUSTA
tHDSTA
tHIGH
tSUSTO
tHDDAT
tSUDAT
tHDSTA
SDA
tBUF
S
P
S
P
图6-1. I2C Timing Diagram
tCSS
tCSH
tCSHIGH
SYNC
SCLK
SDI
tSCLKLOW
tSCLKHIGH
tSDIH
tSDIS
Bit 23
Bit 1
Bit 0
GPIO/
LDAC
tCS2LDAC
tLDACW
图6-2. SPI Write Timing Diagram
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tCSHIGH
tCSS
tCSH
SYNC
tSCLKLOW tSCLKHIGH
SCLK
SDI
FIRST READ COMMAND
Bit 23
ANY COMMAND
Bit 1
Bit 22
Bit 0
Bit 23
Bit 23
Bit 0
Bit 0
tSDIS tSDIH
SDO
Bit 1
FSDO = 0
tSDODLY
tSDODZ
DATA FROM FIRST READ COMMAND
SDO
Bit 23
Bit 1 Bit 0
FSDO = 1
tSDODLY
DATA FROM FIRST READ COMMAND
图6-3. SPI Read Timing Diagram
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6.17 Typical Characteristics: Voltage Output
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
4
3.2
2.4
1.6
0.8
0
4
3.2
2.4
1.6
0.8
0
-0.8
-1.6
-2.4
-3.2
-4
-0.8
-1.6
-2.4
-3.2
-4
Channel 1
Channel 0
Channel 1
Channel 0
32
544
1056 1568 2080 2592 3104 3616 4064
Code
32
544
1056 1568 2080 2592 3104 3616 4064
Code
Internal reference, gain = 4x
图6-4. Voltage Output INL vs Digital Input Code
图6-5. Voltage Output INL vs Digital Input Code
4
3.2
2.4
1.6
0.8
0
4
3.2
2.4
1.6
0.8
0
-0.8
-1.6
-2.4
-3.2
-4
-0.8
-1.6
-2.4
-3.2
-4
CH1 MAX
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
CH0 MAX
CH1 MIN
CH0 MIN
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.8
2.725
3.65
4.575
5.5
Temperature (C)
Supply Voltage (V)
图6-6. Voltage Output INL vs Temperature
Channel 1
图6-7. Voltage Output INL vs Supply Voltage
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
Channel 1
Channel 0
Channel 0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
32
544
1056 1568 2080 2592 3104 3616 4064
Code
32
544
1056 1568 2080 2592 3104 3616 4064
Code
Internal reference, gain = 4x
图6-8. Voltage Output DNL vs Digital Input Code
图6-9. Voltage Output DNL vs Digital Input Code
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.8
2.725
3.65
4.575
5.5
Temperature (C)
Supply Voltage (V)
图6-10. Voltage Output DNL vs Temperature
图6-11. Voltage Output DNL vs Supply Voltage
1.5
1.2
0.9
0.6
0.3
0
1.5
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
-1.5
-0.3
-0.6
-0.9
-1.2
-1.5
Channel 1
Channel 0
Channel 1
Channel 0
0
512 1024 1536 2048 2560 3072 3584 4095
Code
0
512 1024 1536 2048 2560 3072 3584 4095
Code
Internal reference, gain = 4x
图6-12. Voltage Output TUE vs Digital Input Code
1.5
图6-13. Voltage Output TUE vs Digital Input Code
1.5
1.2
0.9
0.6
0.3
0
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
-1.5
-0.3
-0.6
-0.9
-1.2
-1.5
Channel 1
Channel 0
Channel 1
Channel 0
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.8
2.725
3.65
4.575
5.5
Temperature (C)
Supply Voltage (V)
DAC channels at midscale
DAC channels at midscale
图6-15. Voltage Output TUE vs Supply Voltage
图6-14. Voltage Output TUE vs Temperature
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Channel 1
Channel 0
Channel 1
Channel 0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
图6-16. Voltage Output Offset Error vs Temperature
图6-17. Voltage Output Gain Error vs Temperature
10
2.76
2.758
2.756
2.754
2.752
2.75
0
-10
-20
-30
-40
-50
-60
-70
2.748
2.746
2.744
Channel 1
Channel 0
2.742
2.74
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
-5
-3.75 -2.5 -1.25
0
1.25
2.5
3.75 5
Load Current (mA)
DAC channels at midscale
图6-19. Voltage Output AC PSRR vs Frequency
图6-18. Voltage Output vs Load Current
LDAC (1 V/div)
VOUT (1 LSB/div)
LDAC (1 V/div)
VOUT (1 LSB/div)
0
10
20
30
40
50
0
10
20
30
40
50
Time (s)
Time (s)
图6-20. Voltage Output Code-to-Code Glitch - Rising Edge
图6-21. Voltage Output Code-to-Code Glitch - Falling Edge
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
0
10
20
30
40
50
0
10
20
30
40
50
Time (s)
Time (s)
Zero scale to full scale swing
Full scale to zero scale swing
图6-22. Voltage Output Setting Time - Rising Edge
图6-23. Voltage Output Setting Time - Falling Edge
VDD (1 V/div)
VOUT (1 mV/div)
VDD (1 V/div)
VOUT (15 mV/div)
0
200
400
600
800 1000 1200 1400 1600
Time (s)
0
200
400
600
800 1000 1200 1400 1600
Time (s)
DAC in Hi-Z power-down mode
图6-24. Voltage Output Power-On Glitch
DAC at zero scale
图6-25. Voltage Output Power-Off Glitch
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
Internal reference, gain = 4x
图6-26. Voltage Output Noise Density
图6-27. Voltage Output Noise Density
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
35
30
25
20
15
10
5
25
20
15
10
5
0
0
-5
-5
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Time (s)
Time (s)
Internal reference, gain = 4x, f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
图6-29. Voltage Output Flicker Noise
图6-28. Voltage Output Flicker Noise
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6.18 Typical Characteristics: Current Output
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Channel 1
Channel 0
0
32
64
96
128
160
192
224
255
-40 -25 -10
5
20 35 50 65 80 95 110 125
Code
Temperature (C)
图6-30. Current Output INL vs Digital Input Code
图6-31. Current Output INL vs Temperature
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Channel 1
Channel 0
0
32
64
96
128
Code
160
192
224
255
1.8
2.725
3.65
4.575
5.5
Supply Voltage (V)
图6-33. Current Output DNL vs Digital Input Code
图6-32. Current Output INL vs Supply Voltage
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
CH1 MAX
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
CH0 MAX
CH1 MIN
CH0 MIN
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.8
2.725
3.65
4.575
5.5
Temperature (C)
Supply Voltage (V)
图6-34. Current Output DNL vs Temperature
图6-35. Current Output DNL vs Supply Voltage
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6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
2
1.6
1.2
0.8
0.4
0
2
1.6
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2
-0.4
-0.8
-1.2
-1.6
-2
Channel 1
Channel 0
Channel 1
Channel 0
0
32
64
96
128
160
192
224
255
-40 -25 -10
5
20 35 50 65 80 95 110 125
Code
Temperature (C)
DAC channels at midscale
图6-37. Current Output TUE vs Temperature
图6-36. Current Output TUE vs Digital Input Code
1.5
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
-1.5
Channel 1
Channel 0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
DAC channels at midscale
图6-39. Current Output Offset Error vs Temperature
图6-38. Current Output TUE vs Supply Voltage
1.5
1000
800
600
400
200
0
1.2
0.9
0.6
0.3
0
-200
-0.3
-0.6
-0.9
-1.2
-1.5
-400
CH1, DAC Code = 0
CH0, DAC Code = 0
CH1, DAC Code = 255
CH0, DAC Code = 255
-600
Channel 1
Channel 0
-800
-1000
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Load Voltage (V)
图6-41. Current Output vs Load Voltage
图6-40. Current Output Gain Error vs Temperature
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6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
Trigger (1 V/div)
IOUT (Zoomed, 10A/div)
Settling Band (−1 LSB)
Settling Band (+1 LSB)
Trigger (1 V/div)
IOUT (Zoomed, 10 A/div)
Settling Band (−1 LSB)
Settling Band (+1 LSB)
0
10
20
30
40
50
0
10
20
30
40
50
Time (s)
Time (s)
图6-42. Current Output Setting Time, Rising Edge
图6-43. Current Output Setting Time, Falling Edge
VDD ( 1 V/div)
IOUT (40 A/div)
VDD (1 V/div)
IOUT (20 A/div)
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
Time (s)
Time (s)
DAC at mid scale (0 μA) stored in EEPROM
图6-44. Current Output Power-On Glitch
DAC at mid scale (0 μA)
图6-45. Current Output Power-Off Glitch
2
1.8
1.6
1.4
1.2
1
30
25
20
15
10
5
0
0.8
0.6
0.4
0.2
0
-5
-10
-15
-20
-25
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
0
1
2
3
4
5
6
7
8
9
10
Time (s)
f = 0.1 Hz to 10 Hz
图6-47. Current Output Flicker Noise
图6-46. Current Output Noise Density
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6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
500
200
100
50
20
10
5
2
1
0.5
0.2
10 20 30 50 100 200 500 10002000
Frequency (Hz)
10000 30000
图6-48. Current Output AC PSRR vs Frequency
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6.19 Typical Characteristics: Comparator
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, FBx pin in Hi-Z mode, and DAC outputs
unloaded (unless otherwise noted)
VOUT (1 V/div)
VFB (1 LSB/div)
VOUT (1 V/div)
VFB (1 LSB/div)
0
2
4
6
8
10
0
2
4
6
8
10
Time (s)
Time (s)
Comparator output in push-pull mode
Comparator output in push-pull mode
图6-49. Comparator Response Time: Low‑to‑High Transition
图6-50. Comparator Response Time: High‑to‑Low Transition
5
4
3
2
1
0
-1
-2
-3
-4
-5
Channel 1
Channel 0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
图6-51. Comparator Offset Error vs Temperature
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6.20 Typical Characteristics: General
at TA = 25°C, VDD = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
1.22
1.219
1.218
1.217
1.216
1.215
1.214
1.213
1.212
1.211
1.21
1.21314
1.213126
1.213112
1.213098
1.213084
1.21307
1.213056
1.213042
1.213028
1.213014
1.213
1.8
2.725
3.65
4.575
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Supply Voltage (V)
Internal reference
图6-53. Internal Reference vs Supply Voltage
Internal reference
图6-52. Internal Reference vs Temperature
30
27
24
21
18
15
12
9
5
4
3
2
1
0
6
VDD = 1.8 V
VDD = 3.3 V
VDD = 5.5 V
3
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0.5
3.5
6.5
9.5
12.5
15
Temperature (C)
External Capacitance on CAP Pin (F)
Sleep mode, internal reference disabled
图6-54. Power-Down Current vs Temperature
图6-55. Boot-Up Time vs Capacitance on CAP pin
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7 Detailed Description
7.1 Overview
The 12-bit DAC63202 and 10-bit DAC53202 (DACx3202) are a pin-compatible family of dual-channel buffered
voltage-output and current-output smart digital-to-analog converters (DACs). The DAC channels are
independently configurable as voltage or current output. The DAC outputs change to Hi-Z when VDD is off; a
feature useful in voltage-margining applications. These smart DACs contain nonvolatile memory (NVM), an
internal reference, automatically detectable I2C or SPI interface, PMBus-compatibility in I2C mode, force-sense
output, and a general-purpose input. These devices support Hi-Z power-down modes by default, which can be
configured to 10 kΩ-GND or 100 kΩ-GND using the NVM. The DACx3202 have a power-on-reset (POR) circuit
that makes sure all the registers start with default or user-programmed settings using NVM. The DACx3202
operate with either an internal reference, external reference, or with a power supply as the reference, and
provide a full-scale output of 1.8 V to 5.5 V.
The DACx3202 devices support I2C standard mode (100 kbps), fast mode (400 kbps), and fast mode plus
(1 Mbps). The I2C interface can be configured with four target addresses using the A0 pin. These devices also
support specific PMBus commands such as turn on/off, margin high or low, and more. SPI mode supports a 3-
wire interface by default with up to 50-MHz SCLK input. The GPIO input can be configured as SDO in the NVM
for SPI read capability. The GPIO input can alternatively be configurable as LDAC, PD, STATUS, FAULT-DUMP,
RESET, and PROTECT functions.
The DACx3202 also include digital slew rate control, and support standard waveform generation such as sine,
cosine, triangular, and sawtooth waveforms. These devices can generate pulse-width modulation (PWM) output
with the combination of the triangular or sawtooth waveform and the FB pin. The force-sense outputs of the DAC
channels can be used as programmable comparators. The comparator mode allows programmable hysteresis,
latching comparator, window comparator, and fault-dump to the NVM. These features enable the DACx3202 to
go beyond the limitations of a conventional DAC that depends on a processor to function. As a result of
processor-less operation and the smart feature set, the DACx3202 are called smart DACs.
7.2 Functional Block Diagram
CAP
VREF
VDD
LDO
Internal
Reference
A0/SDI
Nonvolatile
Memory
MUX
SCL/SYNC
SDA/SCLK
GPIO/SDO
DAC
Register
DAC
Buffer
DAC
+
OUT0-1
FB0-1
BUF
-
Power On Reset
R1
Output
Configuration
Function Generation
Power Down Logic
Channel 0
Channel 1
AGND
图7-1. Functional Block Diagram
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7.3 Feature Description
7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
The DACx3202 devices consist of a string architecture with a voltage-output amplifier, as well as an external FB
pin and voltage-to-current converter for each channel. 节 7.2 shows the DAC architecture within the block
diagram that operates from a 1.8-V to 5.5-V power supply. The DAC has an internal voltage reference of 1.21 V.
Optionally, use an external reference on the VREF pin, or use the power supply as a reference. Voltage output
mode uses one of these three reference options. Current output mode uses an internal band gap to generate the
current outputs. Both the voltage- and current-output modes support multiple programmable output ranges.
The DACx3202 devices support Hi-Z output when VDD is off, maintaining very low leakage current at the output
pins with up to 1.25 V of forced voltage. The DAC output pin also starts up in high-impedance mode by default,
making these devices an excellent choice for voltage margining and scaling applications. To change the power-
up mode to 10 kΩ-GND or 100 kΩ-GND, program the corresponding VOUT-PDN-X field in the COMMON-
CONFIG register and load these bits in the device NVM.
The DACx3202 devices support an independent comparator mode for each channel. The respective FBx pin
acts as an input for the comparator. The DAC architecture supports inversion of the comparator output using
register settings. The comparator outputs can be push-pull or open-drain. The comparator mode supports
programmable hysteresis using the margin-high and margin-low register fields, latching comparator, and window
comparator. The comparator outputs are accessible internally by the device.
The DACx3202 devices include a smart feature set to enable processor-less operation and high integration. The
NVM enables a predictable start-up. In the absence of a processor or when the processor or software fails, the
GPIO triggers the DAC output without the I2C interface. The integrated functions and the FBx pin enable PWM
output for control applications. The FBx pin enables this device to be used as a programmable comparator. The
digital slew-rate control and the Hi-Z power-down modes enable a hassle-free voltage margining and scaling
function.
7.3.2 Digital Input/Output
The DACx3202 have four digital IO pins that include I2C, SPI, PMBus, and GPIO interfaces. These devices
automatically detect I2C and SPI protocols at the first successful communication after power-on, and then
connect to the detected interface. After an interface protocol is connected, any change in the protocol is ignored.
The I2C interface uses the A0 pin to select from among four address options. The SPI interface is a 3-wire
interface by default. No readback capability is available in this mode. The GPIO pin can be configured in the
register map and then programmed in to the NVM as the SDO pin. The SPI readback mode is slower than the
write mode. The programming interface pins are:
• I2C: SCL, SDA, A0
• SPI: SCLK, SDI, SYNC, SDO/GPIO
The GPIO can be configured as multiple functions other than SDO. These are LDAC, PD, STATUS, PROTECT,
FAULT-DUMP, and RESET. All the digital pins are open-drain when used as outputs. Therefore, all the output
pins must be pulled up to the desired IO voltage using external resistors.
7.3.3 Nonvolatile Memory (NVM)
The DACx3202 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and
erasable, and retain the set values in the absence of a power supply. All the register bits, shown in the
highlighted gray cells in 节7.6, can be stored in the NVM by setting NVM-PROG = 1 in the COMMON-TRIGGER
register. The NVM-PROG is an autoresetting bit. The default values for all the registers in the DACx3202 are
loaded from NVM as soon as a POR event is issued.
The DACx3202 also implement NVM-RELOAD bit in the COMMON-TRIGGER register. Set this bit to 1 and the
device starts an NVM-reload operation. After completion, the device autoresets the NVM-RELOAD bit to 0.
During the NVM write or reload operation, all read/write operations to the device are blocked. 节6.8 provides the
timing specification for the NVM write cycle. The processor must wait for the specified duration before resuming
any read or write operation on the SPI or I2C interface.
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7.4 Device Functional Modes
7.4.1 Voltage-Output Mode
The voltage-output mode for each DAC channel can be entered by selecting the power-up option in the VOUT-
PDN-X fields in the COMMON-CONFIG register and simultaneously powering down the current output option for
the respective channels using the IOUT-PDN-X bits in the same register. Short the OUTx and FBx pins of
respective channels externally for closed-loop amplifier output. An open FBx pin saturates the amplifier output.
To achieve the desired voltage output, select the correct reference option, select the amplifier gain for the
required output range, and program the DAC code in the DAC-X-DATA register of the respective channels.
7.4.1.1 Voltage Reference and DAC Transfer Function
图 7-2 shows that there are three voltage reference options possible with the DACx3202: internal reference,
external reference, and the power supply as reference. The DAC transfer function in the voltage-output and
comparator modes changes based on the voltage reference selection.
VDD
VREF
Digital
IO
EN-INT-REF
Internal
DIS-MODE-IN
Reference
IOUT-RANGE-X
MUX
VOUT-GAIN-X
VOUT-PDN-X
IOUT-PDN-X
VOUT-PDN-X
+
–
DAC Ladder
OUTx
FBx
IOUT-PDN-X
10k /100k
Internal
Bandgap
R1
R2
CMP-X-HIZ-IN-DIS or
VOUT-PDN-X (Hi-Z)
AGND
图7-2. Voltage Reference Selection and Power-Down Logic
7.4.1.1.1 Internal Reference
The DACx3202 contain an internal reference that is disabled by default. To enable the internal reference, write 1
to bit EN-INT-REF in the COMMON-CONFIG register. The internal reference generates a fixed 1.21-V voltage
(typical). Use the VOUT-GAIN-X bit in the DAC-X-VOUT-CMP-CONFIG register to achieve gains of 1.5x, 2x, 3x,
or 4x for the DAC output voltage (VOUT). 方程式1 shows DAC transfer function using the internal reference.
DAC_DATA
V
=
× V
× GAIN
REF
(1)
OUT
N
2
where:
• N is the resolution in bits, 10 (DAC53202), or 12 (DAC63202).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit in the DAC-X-
DATA register. DAC_DATA ranges from 0 to 2N –1.
• VREF is the internal reference voltage = 1.21 V (typical).
• GAIN = 1.5x, 2x, 3x, or 4x, based on VOUT-X-GAIN bits.
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7.4.1.1.2 External Reference
By default, the DACx3202 operate from an external reference input. The external reference option can also be
selected by configuring the VOUT-GAIN-X field in the DAC-X-VOUT-CMP-CONFIG register appropriately. Write
1 to the DIS-MODE-IN bit in the DEVICE-MODE-CONFIG register to minimize IDD. The external reference can
be between 1.7 V and VDD. 方程式 2 shows DAC transfer function when the external reference is used. The
gain at the output stage of the DAC is always 1x in the external reference mode.
备注
The external reference must be less than VDD in both transient and steady-state conditions.
Therefore, the external reference must ramp up after VDD and ramp down before VDD.
DAC_DATA
V
=
× V
(2)
OUT
REF
N
2
where:
• N is the resolution in bits, 10 (DAC53202), or 12 (DAC63202).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA field in the DAC-
X-DATA register. DAC_DATA ranges from 0 to 2N –1.
• VREF is the external reference voltage.
7.4.1.1.3 Power-Supply as Reference
The DACx3202 can operate with the power-supply pin (VDD) as a reference. 方程式 3 shows DAC transfer
function when the power-supply pin is used as reference. The gain at the output stage is always 1x.
DAC_DATA
V
=
× V
(3)
OUT
DD
N
2
where:
• N is the resolution in bits, either 10 (DAC53202), or 12 (DAC63202).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit in the DAC-X-
DATA register.
• DAC_DATA ranges from 0 to 2N –1.
• VDD is used as the DAC reference voltage.
7.4.2 Current-Output Mode
To enter current-output mode for each DAC channel, disable the respective IOUT-PDN-X bits in the COMMON-
CONFIG register, and set the respective VOUT-PDN-X bits in the same register to Hi-Z power-down mode.
Select the desired current-output range by writing to the IOUT-RANGE-X bit in the DAC-X-IOUT-MISC-CONFIG
register. To minimize leakage in current-output mode, disconnect the FBx pin. For the best power-on glitch
performance, program the NVM with IOUT mode using the smallest output range before powering on the output
channel, and then immediately program the DAC code and desired output range. The transfer function of the
output current is shown in 方程式4.
DAC_DATA × I
− I
MIN
MAX
I
=
+ I
(4)
OUT
MIN
8
2
where:
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit as specified in
节7.6.8. DAC_DATA ranges from 0 to 255.
• IMAX is the signed maximum current in the IOUT-RANGE-X setting as specified in 节7.6.5.
• IMIN is the signed minimum current in the IOUT-RANGE-X setting as specified in 节7.6.5.
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7.4.3 Comparator Mode
All the DAC channels can be configured as programmable comparators in the voltage-output mode. To enter the
comparator mode for a channel, write 1 to the CMP-X-EN bit in the respective DAC-X-VOUT-CMP-CONFIG
register. The comparator output can be configured as push-pull or open-drain using the CMP-X-OD-EN bit. To
enable the comparator output on the output pin, write 1 to the CMP-X-OUT-EN bit. To invert the comparator
output, write 1 to the CMP-X-INV-EN bit. The FBx pin has a finite impedance. By default, the FBx pin is in the
high-impedance mode. To disable high-impedance on the FBx pin, write 1 to the CMP-X-HIZ-IN-DIS bit. 表 7-1
shows the comparator output at the pin for different bit settings.
备注
In the Hi-Z input mode, the comparator input range is limited to:
• For GAIN = 1x, 1.5x, or 2x: VFB ≤(VREF × GAIN) / 3
• For GAIN = 3x, or 4x: VFB ≤(VREF × GAIN) / 6
Any higher input voltage is clipped.
表7-1. Comparator Output Configuration
CMP-X-EN
CMP-X-OUT-EN
CMP-X-OD-EN
CMP-X-INV-EN
CMPX-OUT PIN
Comparator not enabled
No output
0
1
1
1
1
1
X
0
1
1
1
1
X
X
0
0
1
1
X
X
0
1
0
1
Push-pull output
Push-pull and inverted output
Open-drain output
Open-drain and inverted output
图7-3 shows the interface circuit when all the DAC channels are configured as comparators. The programmable
comparator operation is as shown in 图 7-4. Individual comparator channels can be configured in no-hysteresis,
with-hysteresis, and window-comparator modes using the CMP-X-MODE bit in the respective DAC-X-CMP-
MODE-CONFIG register, as shown in 表7-2.
VDD
10 k
0.1 μF
1.5 μF
VDD
CAP
VREF
+
-
+
-
CMP0
CMP1
CMP1-OUT
CMP0-OUT
FB0/AIN0
FB1/AIN1
(0 V to VFS/3 or 0 V to VFS
)
(0 V to VFS/3 or 0 V to VFS)
AGND
VIO
10 k
图7-3. Comparator Interface
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DAC-X-DATA
FBx/AINx
OUT-X
CMP-X-INV-EN = 0
OUT-X
CMP-X-INV-EN = 1
图7-4. Programmable Comparator Operation
表7-2. Comparator Mode Selection
COMPARATOR CONFIGURATION
CMP-X-MODE BIT FIELD
00
01
Normal comparator mode. No hysteresis or window operation.
Hysteresis comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the hysteresis.
Window comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the window
bounds.
10
11
Invalid setting
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7.4.3.1 Programmable Hysteresis Comparator
表 7-2 shows that comparator mode provides hysteresis when the CMP-X-MODE bit is set to 01b. 图 7-5 shows
that the hysteresis is provided by the DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers.
When the DAC-X-MARGIN-HIGH is set to full-code or the DAC-X-MARGIN-LOW is set to zero-code, the
comparator works as a latching comparator that is, the output is latched after the threshold is crossed. The
latched output can be reset by writing to the corresponding RST-CMP-FLAG-X bit in the COMMON-DAC-TRIG
register. 图 7-6 shows the behavior of a latching comparator with active low output, and 图 7-7 shows the
behavior of a latching comparator with active high output.
备注
The value of the DAC-X-MARGIN-HIGH register must be greater than the value of the DAC-X-
MARGIN-LOW register. The comparator output in the hysteresis mode can only be noninverting; that
is, the CMP-X-INV-EN bit in the DAC-X-VOUT-CMP-CONFIG register must be set to 0. For the reset
to take effect in latching mode, the input voltage must be within DAC-X-MARGIN-HIGH and DAC-X-
MARGIN-LOW.
DAC-X-MARGIN-HIGH
Hysteresis
FBx/AINx
DAC-X-MARGIN-LOW
OUT-X
CMP-X-INV-EN = 0
图7-5. Programmable Hysteresis Without Latching Output
DAC-X-MARGIN-HIGH
FBx/AINx
DAC-X-MARGIN-LOW
(ZERO-CODE)
OUT-X
CMP-X-INV-EN = 0
RST-CMP-FLAG-X
图7-6. Latching Comparator With Active Low Output
DAC-X-MARGIN-HIGH
(FULL-CODE)
FBx/AINx
DAC-X-MARGIN-LOW
OUT-X
CMP-X-INV-EN = 0
RST-CMP-FLAG-X
图7-7. Latching Comparator With Active High Output
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7.4.3.2 Programmable Window Comparator
Window comparator mode is enabled by setting the CMP-X-MODE bit to 10b (see also 表 7-2). 图 7-8 shows
that the window bounds are set by the DAC-X-MARGIN-HIGH and the DAC-X-MARGIN-LOW registers. The
output of the window comparator for a given channel is indicated by the respective WIN-CMP-X bit in the CMP-
STATUS register. The comparator output (WIN-CMP-X) can be latched by writing 1 to the WIN-LATCH-EN bit in
the COMMON-CONFIG register. After being latched, the comparator output can be reset using the
corresponding RST-CMP-FLAG-X bit in the COMMON-DAC-TRIG register. For the reset to take effect, the input
must be within the window bounds.
DAC-X-MARGIN-HIGH
FBx/AINx
DAC-X-MARGIN-LOW
WIN-CMP-X
WIN-LATCH-EN = 0
WIN-CMP-X
WIN-LATCH-EN = 1
RST-CMP-FLAG-X
图7-8. Window Comparator Operation
A single comparator is used per channel to check both the margin-high and margin-low limits of the window.
Therefore, the window comparator function has a finite response time (see also 节 6.7). The static behavior of
the WIN-CMP-X bit is not reflected at the output pins. Set the CMP-X-OUT-EN bit to 0. The WIN-CMP-X bit must
be read digitally using the communication interface. This bit can also be mapped to the GPIO pin (see also 表
7-19).
备注
• The value of the DAC-X-MARGIN-HIGH register must be greater than that of the DAC-X-MARGIN-
LOW register.
• Set the SLEW-RATE-X bit to 0000b (no-slew) and LOG-SLEW-EN-X bit to 0b in the DAC-X-FUNC-
CONFIG register to get the best response time from the window comparator.
• The CMP-X-OUT-EN bit in the DAC-X-VOUT-CMP-CONFIG register can be set to 0b to eliminate
undesired toggling of the OUT pin.
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7.4.4 Fault-Dump Mode
The DACx3202 provides a feature to save a few registers into the NVM when the FAULT-DUMP bit is triggered
or when the GPIO mapped to fault-dump is triggered (see also 表 7-18). This feature is useful in system-level
fault management to capture the state of the device or system just before a fault is triggered, and to allow
diagnosis after the fault has occurred. The registers saved when fault-dump is triggered, are:
• CMP-STATUS[7:0]
• DAC-0-DATA[15:8]
• DAC-1-DATA[15:8]
备注
When the fault-dump cycle is in progress, any change in the data can corrupt the final outcome. Make
sure the comparator and the DAC codes are stable during the NVM write cycle.
表7-3 shows the storage format of the registers in the NVM.
表7-3. Fault-Dump NVM Storage Format
NVM ROWS
B31-B24
B23-B16
B15-B8
B7-B0
Row1
CMP-STATUS[7:0]
DAC-1-DATA[15:8]
Don't care
Row2
Don't care
DAC-1-DATA[15:8]
The data captured in the NVM after the fault dump can be read in a specific sequence:
1. Set the EE-READ-ADDR bit to 0b in the COMMON-CONFIG register, to select row1 of the NVM.
2. Trigger the read of the selected NVM row by writing 1 to the READ-ONE-TRIG in the COMMON-TRIGGER
register; this bit autoresets. This action copies that data from the selected NVM row to SRAM addresses
0x9D (LSB 16 bits from the NVM) and 0x9E (MSB 16 bits from the NVM).
3. To read the SRAM data:
a. Write 0x009D to the SRAM-CONFIG register.
b. Read the data from the SRAM-DATA register to get the LSB 16 bits.
c. Write 0x009E to the SRAM-CONFIG register.
d. Read the data from the SRAM-DATA register again to get the MSB bits.
4. Set the EE-READ-ADDR bit to 1b in the COMMON-CONFIG register, to select row2 of the NVM. Repeat
steps 2 and 3.
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7.4.5 Application-Specific Modes
This section provides the details of application-specific functional modes available in the DACx3202.
7.4.5.1 Voltage Margining and Scaling
Voltage margining or scaling is a primary application for the DACx3202. This section provides specific features
available for this application such as Hi-Z output, slew-rate control, PROTECT input, and PMBus compatibility.
7.4.5.1.1 High-Impedance Output and PROTECT Input
All the DAC output channels remain in a high-impedance state (Hi-Z) when VDD is off. 图 7-9 shows a simplified
schematic of the DACx3202 used in a voltage-margining application. The series resistor RS is needed in voltage-
output mode, but is optional in current-output mode. Almost all linear regulators and DC/DC converters have a
feedback voltage of ≤ 1.25 V. The low-leakage currents at the outputs are maintained for VFB of ≤ 1.25 V.
Thus, for all practical purposes, the DAC outputs appear as Hi-Z when VDD of the DAC is off in voltage
margining and scaling applications. This feature allows for seamless integration of the DACx3202 into a system
without any need for additional power-supply sequencing for the DAC.
VIN
VREG
VDD
DAC
R1
Linear
Regulator
or
DC/DC
Converter
ILEAK
RS
VFB
PROTECT
1.25 V
R2
ZOUT
图7-9. High-Impedance (Hi-Z) Output and PROTECT Input
The DAC channels power down to Hi-Z at boot up. The outputs can power up with a preprogrammed code that
corresponds to the nominal output of the DC/DC converter or the linear regulator. This feature allows for smooth
power up and power down of the DAC without impacting the feedback loop of the DC/DC converter or the linear
regulator.
表7-18 shows how the GPIO pin of the DACx3202 can be configured as a PROTECT function. PROTECT takes
the DAC outputs to a predictable state with a slewed or direct transition. This function is useful in systems where
a fault condition (such as a brownout), a subsystem failure, or a software crash requires that the DAC outputs
reach a predefined state without the involvement of a processor. The detected event can be fed to the GPIO pin
that is configured as the PROTECT input. The PROTECT function can also be triggered using the PROTECT bit
in the COMMON-TRIGGER register. 表 7-4 shows how to configure the behavior of the PROTECT function in
the PROTECT-CONFIG field in the DEVICE-MODE-CONFIG register.
备注
• After the PROTECT function is triggered, the write functionality is disabled on the communication
interface until the function is completed.
• The PROTECT-FLAG bit in the CMP-STATUS register is set to 1 when the PROTECT function is
triggered. This bit can be polled by reading the CMP-STATUS register. After the PROTECT
function is complete, a read command on the CMP-STATUS register resets the PROTECT-FLAG
bit.
表7-4. PROTECT Function Configuration
PROTECT-CONFIG FIELD
FUNCTION
00
01
10
Switch to Hi-Z power-down (no slew).
Switch to DAC code stored in NVM (no slew) and then switch to Hi-Z power-down.
Slew to margin-low code and then switch to Hi-Z power-down.
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表7-4. PROTECT Function Configuration (continued)
FUNCTION
PROTECT-CONFIG FIELD
11
Slew to margin-high code and then switch to Hi-Z power-down.
7.4.5.1.2 Programmable Slew-Rate Control
When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new
code following the slew rate and settling time specified in the Electrical Characteristics.
The slew rate control feature allows the user to control the rate at which the output voltage (VOUT) changes.
When this feature is enabled (using the SLEW-RATE-X[3:0] bits), the DAC output changes from the current code
to the code in the DAC-X-MARGIN-HIGH or DAC-X-MARGIN-LOW registers (when margin high or low
commands are issued to the DAC) using the step size and time-period per step set in CODE-STEP-X and
SLEW-RATE-X bits in the DAC-X-FUNC-CONFIG register:
• SLEW-RATE-X defines the time-period per step at which the digital slew updates.
• CODE-STEP-X defines the number of LSBs by which the output value changes at each update, for the
corresponding channels.
表 7-5 and 表 7-6 show different settings available for CODE-STEP-X and SLEW-RATE-X. With the default slew
rate control setting of no-slew, the output changes immediately at a rate limited by the output drive circuitry and
the attached load.
When the slew rate control feature is used, the output changes happen at the programmed slew rate. 图 7-10
shows that this configuration results in a staircase formation at the output. Do not write to CODE-STEP-X,
SLEW-RATE-X, or DAC-X-DATA during the output slew operation. 方程式 5 provides the equation for the
calculating the slew time (tSLEW).
MARGIN-HIGH
CODE-STEP
MARGIN-LOW
TIME PERIOD
tSLEW
图7-10. Programmable Slew-Rate Control
SLEW_RATE × MARGIN_HIGH − MARGIN_LOW + 1
t
=
(5)
SLEW
CODE_STEP
where:
• SLEW_RATE is the SLEW-RATE-X setting specified in 表7-6.
• CODE_STEP is the CODE-STEP-X setting specified in 表7-5.
• MARGIN_HIGH is the DAC-X-MAGIN-HIGH specified in 节7.6.2.
• MARGIN_LOW is the DAC-X-MAGIN-LOW specified in 节7.6.3.
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表7-5. Code Step
REGISTER
CODE-STEP-X[2]
CODE-STEP-X[1]
CODE-STEP-X[0]
CODE STEP SIZE
1 LSB (default)
2 LSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3 LSB
4 LSB
DAC-X-FUNC-CONFIG
6 LSB
8 LSB
16 LSB
32 LSB
表7-6. Slew Rate
TIME PERIOD
(PER STEP)
REGISTER
SLEW-RATE-X[3]
SLEW-RATE-X[2]
SLEW-RATE-X[1]
SLEW-RATE-X[0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No slew (default)
4 µs
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
8 µs
12 µs
18 µs
27 µs
40.5 µs
60.75 µs
91.13 µs
136.69 µs
239.2 µs
418.61 µs
732.56 µs
1281.98 µs
2563.96 µs
5127.92 µs
DAC-X-FUNC-CONFIG
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7.4.5.1.3 PMBus Compatibility Mode
The PMBus protocol is an I2C-based communication standard for power-supply management. PMBus contains
standard command codes tailored to power supply applications. The DACx3202 implement some PMBus
commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well
as PMBUS revision. 图7-11 shows typical PMBus connections. The EN-PMBUS bit in the INTERFACE-CONFIG
register must be set to 1 to enable the PMBus protocol.
PMBus-compatible device #1
ALERT
CONTROL
DATA
CLOCK
Alert signal
PMBus-compatible device #2
ALERT
Control signal
CONTROL
Data
DATA
Clock
CLOCK
Optional
Required
PMBus-compatible device #3
ALERT
CONTROL
DATA
CLOCK
图7-11. PMBus Connections
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Similar to I2C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge, wrapped
between a start and stop bit. The first byte is always a 7-bit target address followed by a write bit, sometimes
called the even address, that identifies the intended receiver of the packet. The second byte is an 8-bit
command byte, identifying the PMBus command being transmitted using the respective command code. After
the command byte, the transmitter either sends data associated with the command to write to the receiver
command register (from least significant byte to most significant byte; see also 表 7-7), or sends a new start bit
indicating the desire to read the data associated with the command register from the receiver. Then the receiver
transmits the data following the same least significant byte first format; see also 表7-8.
表7-7. PMBus Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
节7.5.2.2.1
Command byte
节7.5.2.2.2
Data byte - MSDB
(Optional)
Data byte - LSDB
DB [15:8]
DB [31:24]
DB [23:16]
DB [7:0]
表7-8. PMBus Read Sequence
R/W
(0)
R/W
(1)
S
MSB
ACK
MSB
LSB
ACK Sr MSB
ACK
MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
Address byte
节7.5.2.2.1
Command byte
节7.5.2.2.2
Address byte
节7.5.2.2.1
Sr
LSDB
MSDB (Optional)
From target
From controller
Target
From controller
Target
From controller
Target
From target
Controller
Controller
The DACx3202 I2C interface implements some of the PMBus commands. 表 7-9 shows the supported PMBus
commands that are implemented in DACx3202.The DAC uses DAC-X-MARGIN-LOW, DAC-X-MARGIN-HIGH
bits, SLEW-RATE-X, and CODE-STEP-X bits for PMBUS-OPERATION-CMD-X. To access multiple channels,
write the PMBus page address specified in 表 7-21 to the PMBUS-PAGE register first, followed by a write to the
channel-specific register.
表7-9. PMBus Operation Commands
REGISTER
PMBUS-OPERATION-CMD-X[15:8]
DESCRIPTION
Turn off
00h
80h
94h
A4h
Turn on
PMBUS-OP-CMD-X
Margin low
Margin high
The DACx3202 also implement PMBus features such as group command protocol and communication timeout
failure. The CML bit in the PMBUS-CML register indicates a communication fault in the PMBus. This bit is reset
by writing 1.
To get the PMBus version, read the PMBUS-VERSION register.
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7.4.5.2 Function Generation
The DACx3202 implement a continuous function or waveform generation feature. These devices can generate a
triangular wave, sawtooth wave, and sine wave independently for every channel.
7.4.5.2.1 Triangular Waveform Generation
The triangular waveform uses the DAC-X-MARGIN-LOW and DAC-X-MARGIN-HIGH registers for minimum and
maximum levels, respectively. 方程式 6 shows that the frequency of the waveform depends on the min and max
levels, CODE-STEP and SLEW-RATE settings. An external RC load with a time-constant larger than the slew-
rate settings can be dominant over the internal frequency calculation. The CODE-STEP-X and SLEW-RATE-X
settings are available in the DAC-X-FUNC-CONFIG register. Writing 0b000 to the FUNC-CONFIG-X bit field in
the DAC-X-FUNC-CONFIG register selects triangular waveform.
1
f
=
(6)
TRIANGLE_WAVE
MARGIN_HIGH − MARGIN_LOW + 1
2 × SLEW_RATE ×
CODE_STEP
where:
• SLEW_RATE is the SLEW-RATE-X setting specified in 表7-6.
• CODE_STEP is the CODE-STEP-X setting specified in 表7-5.
• MARGIN_HIGH is the DAC-X-MAGIN-HIGH specified in 节7.6.2.
• MARGIN_LOW is the DAC-X-MAGIN-LOW specified in 节7.6.3.
7.4.5.2.2 Sawtooth Waveform Generation
The sawtooth and the inverse sawtooth waveforms use the DAC-X-MARGIN-LOW and DAC-X-MARGIN-HIGH
registers for minimum and maximum levels, respectively. 方程式 7 shows that the frequency of the waveform
depends on the min and max levels, CODE-STEP and SLEW-RATE settings. An external RC load with a time
constant larger than the slew-rate settings can be dominant over the internal frequency calculation. The CODE-
STEP-X and SLEW-RATE-X settings are available in the DAC-X-FUNC-CONFIG register. Write 0b001 to the
FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG register to select sawtooth waveform, and write 0b010
to select inverse sawtooth waveform.
1
f
=
(7)
SAWTOOTH_WAVE
MARGIN_HIGH − MARGIN_LOW + 1
SLEW_RATE ×
CODE_STEP
where:
• SLEW_RATE is the SLEW-RATE-X setting specified in 表7-6.
• CODE_STEP is the CODE-STEP-X setting specified in 表7-5.
• MARGIN_HIGH is the DAC-X-MAGIN-HIGH specified in 节7.6.2.
• MARGIN_LOW is the DAC-X-MAGIN-LOW specified in 节7.6.3.
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7.4.5.2.3 Sine Waveform Generation
The sine wave function uses 24 preprogrammed points per cycle. 方程式 8 shows that the frequency of the sine
wave depends on the SLEW-RATE settings:
1
f
=
(8)
SINE_WAVE
24 × SLEW_RATE
where SLEW_RATE is the SLEW-RATE-X setting specified in 表7-6.
An external RC load with a time constant greater than the slew-rate settings can be dominant over the internal
frequency calculation. The SLEW-RATE-X setting is available in the DAC-X-FUNC-CONFIG register. Writing
0b100 to the FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG register selects sine wave. The codes for
the sine wave are fixed. Use the gain settings at the output amplifier for changing the full-scale output using the
internal reference option. The gain settings are accessible through the VOUT-GAIN-X bits in the DAC-X-VOUT-
CMP-CONFIG register. 表 7-10 shows the list of hard-coded discrete points for the sine wave with 12-bit
resolution and 图 7-12 shows the pictorial representation of the sine wave. There are four phase settings
available for the sine wave that are selected using the PHASE-SEL-X bit in the DAC-X-FUNC-CONFIG register.
表7-10. Sine Wave Data Points
SEQUENCE
12-BIT VALUE
SEQUENCE
12-BIT VALUE
0
1
0x800
12
13
14
15
16
17
18
19
20
21
22
23
0x800
0x9A8
0x658
2
0xB33
0x4CD
0x379
3
0xC87
0xD8B
0xE2F
0xE66
4
0x275
5
0x1D1
0x19A
0x1D1
0x275
6
7
0xE2F
0xD8B
0xC87
0xB33
8
9
0x379
10
11
0x4CD
0x658
0x9A8
6
5
7
4
8
3
9
2
10
1
11
TIME PERIOD
0
12
0
13
23
14
22
15
21
16
20
17
19
18
图7-12. Sine Wave Generation
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7.4.6 Device Reset and Fault Management
This section provides the details of power-on-reset (POR), software reset, and other diagnostics and fault-
management features of DACx3202.
7.4.6.1 Power-On Reset (POR)
The DACx3202 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to default values, and communication with the device is valid only after a POR (boot-up) delay. The
default value for all the registers in the DACx3202 is loaded from NVM as soon as the POR event is issued.
When the device powers up, a POR circuit sets the device to the default mode. 图 7-13 indicates that the POR
circuit requires specific VDD levels to make sure that the internal capacitors discharge and reset the device at
power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to
less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or may not
reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD
remains greater than 1.65 V, a POR does not occur.
VDD (V)
5.5 V
Specified supply
voltage range
No power-on reset
1.71 V
1.65 V
Undefined
0.7 V
Power-on reset
0 V
图7-13. Threshold Levels for VDD POR Circuit
7.4.6.2 External Reset
An external reset to the device can be triggered through the GPIO pin or through the register map. To initiate a
device software reset event, write the reserved code 1010 to the RESET field in the COMMON-TRIGGER
register. A software reset initiates a POR event. 表7-18 shows how the GPIO pin can be configured as a RESET
pin. This configuration must be programmed into the NVM so that the setting is not cleared after the device
reset. The RESET input must be a low pulse. The device starts the boot-up sequence after the falling edge of
the RESET input. The rising edge of the RESET input does not have any effect.
7.4.6.3 Register-Map Lock
The DACx3202 implement a register-map lock feature that prevents an accidental or unintended write to the
DAC registers. The device locks all the registers when the DEV-LOCK bit in the COMMON-CONFIG register is
set to 1. However, the software reset function through the COMMON-TRIGGER register is not blocked when
using the I2C interface. To bypass the DEV-LOCK setting, write 0101 to the DEV-UNLOCK bits in the COMMON-
TRIGGER register.
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7.4.6.4 NVM Cyclic Redundancy Check (CRC)
The DACx3202 implement a cyclic redundancy check (CRC) feature for the NVM to make sure that the data
stored in the NVM is uncorrupted. There are two types of CRC alarm bits implemented in DACx3202:
• NVM-CRC-FAIL-USER
• NVM-CRC-FAIL-INT
The NVM-CRC-FAIL-USER bit indicates the status of user-programmable NVM bits, and the NVM-CRC-FAIL-
INT bit indicates the status of internal NVM bits The CRC feature is implemented by storing a 16-bit CRC
(CRC-16-CCITT) along with the NVM data each time NVM program operation (write or reload) is performed and
during the device start up. The device reads the NVM data and validates the data with the stored CRC. The CRC
alarm bits (NVM-CRC-FAIL-USER and NVM-CRC-FAIL-INT in the GENERAL-STATUS register) report any
errors after the data are read from the device NVM. The alarm bits are set only at boot up.
7.4.6.4.1 NVM-CRC-FAIL-USER Bit
A logic 1 on NVM-CRC-FAIL-USER bit indicates that the user-programmable NVM data are corrupt. During this
condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written
to or read from. To reset the alarm bits to 0, issue a software reset (see also 节 7.4.6.2) command, or cycle
power to the DAC. A software reset or power-cycle also reloads the user-programmable NVM bits. In case the
failure persists, reprogram the NVM.
7.4.6.4.2 NVM-CRC-FAIL-INT Bit
A logic 1 on NVM-CRC-FAIL-INT bit indicates that the internal NVM data are corrupt. During this condition, all
registers in the DAC are initialized with factory reset values, and any DAC registers can be written to or read
from. In case of a temporary failure, to reset the alarm bits to 0, issue a software reset (see also 节 7.4.6.2)
command or cycle power to the DAC. A permanent failure in the NVM makes the device unusable.
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7.4.7 Power-Down Mode
The DACx3202 output amplifier and internal reference can be independently powered down through the EN-INT-
REF, VOUT-PDN-X, and IOUT-PDN-X bits in the COMMON-CONFIG register (see also 图7-2). At power up, the
DAC output and the internal reference are disabled by default. In power-down mode, the DAC outputs (OUTx
pins) are in a high-impedance state. To change this state to 10 kΩ-AGND or 100 kΩ-AGND in the voltage-output
mode (at power up), use the VOUT-PDN-X bits. The power-down state for current-output mode is always high-
impedance.
The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. 表
7-11 shows the DAC power-down bits. The individual channel power-down bits or the global device power-down
function can be mapped to the GPIO pin using the GPIO-CONFIG register.
表7-11. DAC Power-Down Bits
REGISTER
VOUT-PDN-X[1]
VOUT-PDN-X[0]
IOUT-PDN-X
DESCRIPTION
Power up VOUT-X.
0
0
1
Power down VOUT-X with 10 kΩ to AGND.
0
1
1
1
1
0
1
1
1
1
1
0
Power down IOUT-X to Hi-Z.
Power down VOUT-X with 100 kΩ to AGND.
Power down IOUT-X to Hi-Z.
COMMON-CONFIG
Power down VOUT-X to Hi-Z.
Power down IOUT-X to Hi-Z (default).
Power down VOUT-X to Hi-Z.
Power up IOUT-X.
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7.5 Programming
The DACx3202 are programmed through either a 3-wire SPI or 2-wire I2C interface. A 4-wire SPI mode is
enabled by mapping the GPIO pin as SDO. The SPI readback operates at a lower SCLK than the standard SPI
write operation. The type of interface is determined based on the first protocol to communicate after device
power up. After the interface type is determined, the device ignores any change in the type while the device is
on. The interface type can be changed after a power cycle.
7.5.1 SPI Programming Mode
An SPI access cycle for DACx3202 is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. The SPI frame for DACx3202 is 24 bits
long. Therefore, the SYNC pin must stay low for at least 24 SCLK falling edges. The access cycle ends when the
SYNC pin is deasserted high. If the access cycle contains less than the minimum clock edges, the
communication is ignored. By default, the SDO pin is not enabled (three-wire SPI). In the three-wire SPI mode, if
the access cycle contains more than the minimum clock edges, only the first 24 bits are used by the device.
When SYNC is high, the SCLK and SDI signals are blocked, and SDO becomes Hi-Z to allow data readback
from other devices connected on the bus.
表 7-12 and 图 7-14 describe the format for the 24-bit SPI access cycle. The first byte input to SDI is the
instruction cycle. The instruction cycle identifies the request as a read or write command and the 7-bit address
that is to be accessed. The last 16 bits in the cycle form the data cycle.
表7-12. SPI Read/Write Access Cycle
BIT
FIELD
DESCRIPTION
23
R/W
Identifies the communication as a read or write command to the address register: R/W = 0 sets a write
operation. R/W = 1 sets a read operation
22-16
15-0
A[6:0]
Register address: specifies the register to be accessed during the read or write operation
DI[15:0]
Data cycle bits: If a write command, the data cycle bits are the values to be written to the register with
address A[6:0]. If a read command, the data cycle bits are don't care values.
SYNC
1
8
9
24
1
8
9
24
SCLK
Write command
D16
Any command
D16
D23
D15
D0
D23
D23
D15
D0
D0
SDI
Write command echo
D16 D15
HiZ
HiZ
HiZ
SDO
图7-14. SPI Write Cycle
Read operations require that the SDO pin is first enabled by setting the SDO-EN bit in the INTERFACE-CONFIG
register. This configuration is called four-wire SPI. A read operation is initiated by issuing a read command
access cycle. After the read command, a second access cycle must be issued to get the requested data. 表7-13
and 图7-15 show the output data format. Data are clocked out on the SDO pin either on the falling edge or rising
edge of SCLK according to the FSDO bit (see also 图6-3).
表7-13. SDO Output Access Cycle
BIT
23
FIELD
R/W
DESCRIPTION
Echo R/W from previous access cycle
22-16
A[6:0]
Echo register address from previous access cycle
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表7-13. SDO Output Access Cycle (continued)
DESCRIPTION
BIT
FIELD
15-0
DI[15:0]
Readback data requested on previous access cycle
SYNC
1
8
9
24
1
8
9
24
SCLK
Read command
D16
Any command
D16
D23
D15
D0
D23
D23
D15
D15
D0
SDI
Read Data
HiZ
HiZ
HiZ
SDO
D16
D0
图7-15. SPI Read Cycle
The daisy-chain operation is also enabled with the SDO pin. 图 7-16 shows that in daisy-chain mode, multiple
devices are connected in a chain with the SDO pin of one device is connected to SDI pin of the following device.
The SPI host drives the SDI pin of the first device in the chain. The SDO pin of the last device in the chain is
connected to the POCI pin of the SPI host. In four-wire SPI mode, if the access cycle contains multiples of 24
clock edges, only the last 24 bits are used by the device first device in the chain. If the access cycle contains
clock edges that are not in multiples of 24, the SPI packet is ignored by the device. 图7-17 describes the packet
format for the daisy-chain write cycle.
VIO
VIO
VIO
C
B
A
RPULL-UP
RPULL-UP
RPULL-UP
TI SPI Device
TI SPI Device
TI SPI Device
SDO
SDO
SDO
SDI
SDI
SDI
SCLK
SYNC
SCLK
SCLK
SYNC
SYNC
图7-16. SPI Daisy-Chain Connection
SYNC
SCLK
1
8
9
24
25
48
49
72
Device A command
D16 D15
Device B command
D23 – D1
Device C command
D23 – D1
D23
D0
SDI-C
D0
D0
SDO-C
Device A command
Device B command
图7-17. SPI Daisy-Chain Write Cycle
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7.5.2 I2C Programming Mode
The DACx3202 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0); see also 图
5-1. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle,
both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through the open
drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a controller, and the devices
that are controlled by the controller are called targets. The controller generates the SCL signal. The controller
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the controller. The controller on
an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3202 family operates as a
target on the I2C bus. A target acknowledges controller commands, and upon controller control, receives or
transmits data.
Typically, the DACx3202 family operates as a target receiver. A controller writes to the DACx3202, a target
receiver. However, if a controller requires the DACx3202 internal register data, the DACx3202 operate as a
target transmitter. In this case, the controller reads from the DACx3202. According to I2C terminology, read and
write refer to the controller.
The DACx3202 family supports the following data transfer modes:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred
to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes.
The DACx3202 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device
supports the general call reset function. Sending the following sequence initiates a software reset within the
device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the
ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during
the high period of the ninth clock cycle. 图7-18 depicts a not-acknowledge, when the SDA line is left high during
the high period of the ninth clock cycle.
Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
2
9
1
8
SCL from
controller
S
Clock pulse for
acknowledgement
Start
condition
图7-18. Acknowledge and Not Acknowledge on the I2C Bus
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7.5.2.1 F/S Mode Protocol
The following steps explain a complete transaction in F/S mode.
1. The controller initiates data transfer by generating a start condition. 图7-19 shows that the start condition is
when a high-to-low transition occurs on the SDA line while SCL is high. All I2C-compatible devices recognize
a start condition.
2. The controller then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the controller makes sure that data are valid. 图7-20 shows
that a valid data condition requires the SDA line to be stable during the entire high period of the clock pulse.
All devices recognize the address sent by the controller and compare the address to the respective internal
fixed address. Only the target device with a matching address generates an acknowledge by pulling the SDA
line low during the entire high period of the 9th SCL cycle (see also 图7-18). When the controller detects this
acknowledge, the communication link with a target has been established.
3. The controller generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the target.
In either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can
be generated by the controller or by the target, depending on which is the receiver. The 9-bit valid data
sequences consists of eight data bits and one acknowledge-bit, and can continue as long as necessary.
4. 图7-19 shows that to signal the end of the data transfer, the controller generates a stop condition by pulling
the SDA line from low-to-high while the SCL line is high. This action releases the bus and stops the
communication link with the addressed target. All I2C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all target devices then wait for a start condition followed
by a matching address.
SDA
SDA
SCL
SCL
S
P
Start
condition
Stop
condition
Change of data
allowed
Data line stable
Data valid
图7-19. Start and Stop Conditions
图7-20. Bit Transfer on the I2C Bus
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7.5.2.2 I2C Update Sequence
表7-14 shows that for a single update, the DACx3202 require a start condition, a valid I2C address byte, a
command byte, and two data bytes.
表7-14. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
节7.5.2.2.1
Command byte
节7.5.2.2.2
Data byte - MSDB
DB [15:8]
Data byte - LSDB
DB [7:0]
DB [31:24]
DB [23:16]
图 7-21 shows that after each byte is received, the DACx3202 family acknowledges the byte by pulling the SDA
line low during the high period of a single clock pulse. These four bytes and acknowledge cycles make up the 36
clock cycles required for a single update to occur. A valid I2C address byte selects the DACx3202.
Recognize
START or
REPEATED
START
condition
Recognize
STOP or
REPEATED
START
Generate ACKNOWLEDGE
signal
condition
P
SDA
Sr
MSB
Acknowledgement
signal from target
Address
R/W
1
SCL
1
7
8
9
2 - 8
9
Sr
or
P
S
or
Sr
ACK
ACK
START or
REPEATED
START
REPEATED
START or
STOP
condition
condition
图7-21. I2C Bus Protocol
The command byte sets the operating mode of the selected DACx3202 device. For a data update to occur when
the operating mode is selected by this byte, the DACx3202 device must receive two data bytes: the most
significant data byte (MSDB) and least significant data byte (LSDB). The DACx3202 device performs an update
on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using fast mode
plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received,
the DACx3202 device releases the I2C bus and awaits a new start condition.
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7.5.2.2.1 Address Byte
表 7-15 depicts the address byte, the first byte received from the controller device following the start condition.
The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address are
controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin, and consequently responds to that particular address according to 表7-16.
表7-15. Address Byte
COMMENT
MSB
LSB
AD6
1
AD5
0
AD4
0
AD3
AD2
AD1
AD0
R/W
—
See 表7-16
General address
1
0
0 or 1
0
(target address column)
Broadcast address
1
0
0
1
1 1
表7-16. Address Format
TARGET ADDRESS
A0 PIN
000
001
010
011
AGND
VDD
SDA
SCL
The DACx3202 supports broadcast addressing, which is used for synchronously updating or powering down
multiple DACx3202 devices. When the broadcast address is used, the DACx3202 responds regardless of the
address pin state. Broadcast is supported only in write mode.
7.5.2.2.2 Command Byte
表7-21 lists the command byte in the ADDRESS column.
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7.5.2.3 I2C Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a target address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the target address and the R/W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The controller must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
The broadcast address cannot be used for reading.
表7-17. Read Sequence
R/W
(0)
R/W
(1)
S
MSB
ACK
MSB
LSB
ACK Sr MSB
ACK
MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
Address byte
节7.5.2.2.1
Command byte
节7.5.2.2.2
Address byte
节7.5.2.2.1
Sr
MSDB
LSDB
From controller
Target
From controller
Target
From controller
Target
From target
Controller
From target
Controller
7.5.3 General-Purpose Input/Output (GPIO) Modes
Together with I2C and SPI, the DACx3202 also support a GPIO that can be configured in the NVM for multiple
functions. This pin allows for updating the DAC output channels and reading status bits without using the
programming interface, thus enabling processor-less operation. In the GPIO-CONFIG register, write 1 to the
GPI-EN bit to set the GPIO pin as an input, or write 1 to the GPO-EN bit to set the pin as output. There are
global and channel-specific functions mapped to the GPIO pin. For channel-specific functions, select the
channels using the GPI-CH-SEL field in the GPIO-CONFIG register. 表 7-18 lists the functional options available
for the GPIO as input and 表 7-19 lists the options for the GPIO as output. Some of the GP input operations are
edge-triggered after the device boots up. After the power supply ramps up, the device registers the GPI level and
executes the associated command. This feature allows the user to configure the initial output state at power-on.
By default, the GPIO pin is not mapped to any operation. When the GPIO pin is mapped to a specific input
function, the corresponding software bit functionality is disabled to avoid a race condition. When used as a
RESET input, the GPIO pin must transmit an active-low pulse for triggering a device reset. All other constraints
of the functions are applied to the GPIO-based trigger.
备注
Pull the GPIO pin high or low when not used. When the GPIO pin is used as RESET, the configuration
must be programmed into the NVM. Otherwise, the setting is cleared after the device resets.
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表7-18. General-Purpose Input Function Map
GPIO EDGE /
REGISTER
BIT FIELD
VALUE
CHANNELS
FUNCTION
LEVEL
Falling edge
Rising edge
Falling edge
Rising edge
Trigger FAULT-DUMP
No effect
0010
All
IOUT power-down
IOUT power-up
0011
0100
As per GPI-CH-SEL
As per GPI-CH-SEL
VOUT power-down. Pulldown
resistor as per the VOUT-PDN-X
setting
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
VOUT power-up
Trigger PROTECT function
No effect
0101
0111
All
All
Trigger CLR function
No effect
As per GPI-CH-SEL, both the
SYNC-CONFIG-X and the
GPI-CH-SEL must be
Trigger LDAC function
1000
Rising edge
No effect
configured for every channel.
GPIO-CONFIG
GPI-CONFIG
Falling edge
Rising edge
Falling edge
Rising edge
Stop function generation
Start function generation
Trigger margin-low
1001
1010
As per GPI-CH-SEL
As per GPI-CH-SEL
Trigger margin-high
Trigger device RESET. The RESET
configuration must be programmed
into the NVM.
Low pulse
1011
1100
All
All
Rising edge
Falling edge
Rising edge
Falling edge
No effect
Allows NVM programming
Blocks NVM programming
Allows register map update
Blocks register map write except a
write to the DEV-UNLOCK field
through I2C or SPI and the RESET
fields through I2C
1101
All
Rising edge
N/A
Others
N/A
Not applicable
表7-19. General-Purpose Output (STATUS) Function Map
REGISTER
BIT FIELD
VALUE
FUNCTION
NVM-BUSY
DAC-1-BUSY
DAC-0-BUSY
WIN-CMP-1
WIN-CMP-0
Not applicable
0001
0100
0111
GPIO-CONFIG
GPO-CONFIG
1000
1011
Others
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7.6 Register Map
表7-20. Register Map
MOST SIGNIFICANT DATA BYTE (MSDB)
LEAST SIGNIFICANT DATA BYTE (LSDB)
REGISTER(1) (2)
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
NOP
NOP
DAC-X-MARGIN-
HIGH
DAC-X-MARGIN-HIGH
DAC-X-MARGIN-LOW
X
X
DAC-X-MARGIN-
LOW
DAC-X-VOUT-
CMP-CONFIG
CMP-X-OD-
EN
CMP-X-
OUT-EN
CMP-X-HIZ- CMP-X-INV-
IN-DIS EN
X
X
VOUT-X-GAIN
X
CMP-X-EN
DAC-X-IOUT-MISC-
CONFIG
IOUT-X-RANGE
X
DAC-X-CMP-
MODE-CONFIG
X
CMP-X-MODE
VOUT-PDN-0
X
DAC-X-FUNC-
CLR-SEL-X
CONFIG
SYNC-
CONFIG-X
BRD-
CONFIG-X
FUNC-GEN-CONFIG-BLOCK-X
DAC-X-DATA
DAC-X-DATA
IOUT-PDN-0
X
WIN-
COMMON-CONFIG
LATCH-EN
EE-READ-
ADDR
DEV-LOCK
EN-INT-REF
X
VOUT-PDN-1
IOUT-PDN-1
COMMON-
TRIGGER
FAULT-
DUMP
READ-ONE-
TRIG
NVM-
RELOAD
DEV-UNLOCK
RESET
LDAC
CLR
X
PROTECT
NVM-PROG
COMMON-DAC-
TRIG
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-1
RST-CMP- TRIG-MAR- TRIG-MAR-
FLAG-0 LO-0 HI-0
START-
FUNC-0
X
FLAG-1
LO-1
HI-1
X
NVM-CRC- NVM-CRC-
DAC-
BUSY-0
DAC-
BUSY-1
GENERAL-STATUS
X
NVM-BUSY
DEVICE-ID
FAIL-INT
GF-EN
FAIL-USER
PROTECT-
FLAG
CMP-
FLAG-0
CMP-
FLAG-1
CMP-STATUS
GPIO-CONFIG
X
WIN-CMP-0
X
WIN-CMP-1
X
X
GPO-EN
GPO-CONFIG
GPI-CH-SEL
RESERVED
GPI-CONFIG
GPI-EN
DEVICE-MODE-
CONFIG
DIS-MODE-
IN
RESERVED
RESERVED
PROTECT-CONFIG
X
INTERFACE-
CONFIG
TIMEOUT-
EN
FAST-SDO-
EN
X
X
EN-PMBUS
X
X
SDO-EN
SRAM-CONFIG
SRAM-DATA
X
SRAM-ADDR
SRAM-DATA
BRDCAST-DATA
PMBUS-PAGE
PMBUS-OP-CMD
PMBUS-CML
BRDCAST-DATA
X
PMBUS-PAGE
PMBUS-OPERATION-CMD-X
X
Not applicable
Not applicable
Not applicable
Not applicable
CML
X
PMBUS-VERSION
PMBUS-VERSON
(1) The highlighted gray cells indicate the register bits or fields that are stored in the NVM.
(2) X = Don't care.
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表7-21. Register Names
PMBUS REGISTER ADDR
I2C/SPI ADDRESS
00h
01h
02h
03h
04h
05h
06h
13h
14h
15h
16h
17h
18h
19h
1Ch
1Fh
20h
21h
22h
23h
24h
25h
26h
2Bh
2Ch
50h
NA
PMBUS PAGE ADDR
REGISTER NAME
NOP
SECTION
节7.6.1
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.1
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.8
节7.6.8
节7.6.9
节7.6.10
节7.6.11
节7.6.12
节7.6.13
节7.6.14
节7.6.15
节7.6.16
节7.6.17
节7.6.18
节7.6.19
节7.6.20
节7.6.21
节7.6.21
节7.6.21
节7.6.21
节7.6.22
节7.6.23
FFh
00h
D0h
25h
26h
D1h
D2h
D3h
D4h
25h
26h
DDh
DEh
DFh
E0h
21h
21h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EFh
F0h
F1h
00h
01h
01h
01h
01h
78h
98h
DAC-1-MARGIN-HIGH
DAC-1-MARGIN-LOW
DAC-1-VOUT-CMP-CONFIG
DAC-1-IOUT-MISC-CONFIG
DAC-1-CMP-MODE-CONFIG
DAC-1-FUNC-CONFIG
DAC-0-MARGIN-HIGH
DAC-0-MARGIN-LOW
DAC-0-VOUT-CMP-CONFIG
DAC-0-IOUT-MISC-CONFIG
DAC-0-CMP-MODE-CONFIG
DAC-0-FUNC-CONFIG
DAC-1-DATA
00h
FFh
FFh
FFh
FFh
03h
03h
FFh
FFh
FFh
FFh
00h
03h
DAC-0-DATA
FFh
COMMON-CONFIG
COMMON-TRIGGER
COMMON-DAC-TRIG
GENERAL-STATUS
CMP-STATUS
FFh
FFh
FFh
FFh
FFh
GPIO-CONFIG
FFh
DEVICE-MODE-CONFIG
INTERFACE-CONFIG
SRAM-CONFIG
FFh
FFh
FFh
SRAM-DATA
FFh
BRDCAST-DATA
All pages
00h
PMBUS-PAGE
NA
PMBIS-OP-CMD-0
PMBUS-OP-CMD-1
PMBUS-OP-CMD-2
PMBUS-OP-CMD-3
PMBUS-CML
NA
01h
NA
02h
NA
03h
NA
All pages
All pages
NA
PMBUS-VERSION
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表7-22. Access Type Codes
Access Type
Code
Description
X
X
Don't care
Read Type
R
R
W
Read
Write Type
W
Write
Reset or Default Value
-n
Value after reset or the default value
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7.6.1 NOP Register (address = 00h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D0h
图7-22. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
R-0h
表7-23. NOP Register Field Descriptions
Bit
15-0
Field
NOP
Type
Reset
Description
R
0000h
No operation
7.6.2 DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
PMBus page address = 03h, 00h, PMBus register address = 25h
图7-23. DAC-X-MARGIN-HIGH Register (X = 0, 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC63202: DAC-X-MARGIN-HIGH[11:0]
DAC53202: DAC-X-MARGIN-HIGH[9:0]
X
R/W-0h
X-0h
表7-24. DAC-X-MARGIN-HIGH Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
DAC63202:
R/W
000h
Margin-high code for DAC output
DAC-X-MARGIN-HIGH[11:0]
DAC53202:
Data are in straight-binary format. MSB left aligned.
Use the following bit alignment:
DAC-X-MARGIN-HIGH[9:0]
DAC63202: {DAC-X-MARGIN-HIGH[11:0]}
DAC53202: {DAC-X-MARGIN-HIGH[9:0], X, X}
X = Don't care bits.
3-0
X
X
0
Don't care
7.6.3 DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
PMBus page address = 03h, 00h, PMBus register address = 26h
图7-24. DAC-X-MARGIN-LOW Register (X = 0, 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC63202: DAC-X-MARGIN-LOW[11:0]
DAC53202: DAC-X-MARGIN-LOW[9:0]
X
R/W-0h
X-0h
表7-25. DAC-X-MARGIN-LOW Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
DAC63202: DAC-X-MARGIN-LOW[11:0]
DAC53202: DAC-X-MARGIN-LOW[9:0]
R/W
000h
Margin-low code for DAC output
Data are in straight-binary format. MSB left aligned.
Use the following bit alignment:
DAC63202: {DAC-X-MARGIN-HIGH[11:0]}
DAC53202: {DAC-X-MARGIN-HIGH[9:0], X, X}
X = Don't care bits.
3-0
X
X
0
Don't care
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7.6.4 DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = DDh, D1h
图7-25. DAC-X-VOUT-CMP-CONFIG Register (X = 0, 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
VOUT-GAIN-X
X
CMP- CMP- CMP-X- CMP- CMP-
X-OD- X-OUT- HIZ-IN- X-INV- X-EN
EN
EN
DIS
EN
X-0h
R/W-0h
X-0h
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
表7-26. DAC-X-VOUT-CMP-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12-10
X
X
0h
Don't care
VOUT-GAIN-X
R/W
0h
000: Gain = 1x, external reference on VREF pin
001: Gain = 1x, VDD as reference
010: Gain = 1.5x, internal reference
011: Gain = 2x, internal reference
100: Gain = 3x, internal reference
101: Gain = 4x, internal reference
Others: Invalid
9-5
4
X
X
0h
0
Don't care
CMP-X-OD-EN
R/W
0: Set OUTx pin as push-pull
1: Set OUTx pin as open-drain in comparator mode (CMP-X-EN =
1 and CMP-X-OUT-EN = 1)
3
2
CMP-X-OUT-EN
R/W
R/W
0
0
0: Generate comparator output but consume internally
1: Bring comparator output to the respective OUTx pin
CMP-X-HIZ-IN-DIS
0: FBx input has high-impedance. Input voltage range is limited.
1: FBx input is connected to resistor divider and has finite
impedance. Input voltage range is same as full-scale.
1
0
CMP-X-INV-EN
CMP-X-EN
R/W
R/W
0
0
0: Don't invert the comparator output
1: Invert the comparator output
0: Disable comparator mode
1: Enable comparator mode. Current-output must be in power-
down. Voltage-output mode must be enabled.
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7.6.5 DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = DEh, D2h
图7-26. DAC-X-IOUT-MISC-CONFIG Register (X = 0, 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
IOUT-RANGE-X
R/W-0h
X
X-0h
X-0h
表7-27. DAC-X-IOUT-MISC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12-9
X
X
0h
Don't care
IOUT-RANGE-X
R/W
0000
1000: ‒25 μA to +25 μA
1001: ‒50 μA to +50 μA
1010: ‒125 μA to +125 μA
1011: ‒250 μA to +250 μA
Others: Invalid
8-0
X
X
000h
Don't care
7.6.6 DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = DFh, D3h
图7-27. DAC-X-CMP-MODE-CONFIG Register (X = 0, 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
CMP-X-MODE
R/W-0h
X
X-0h
X-0h
表7-28. DAC-X-CMP-MODE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
00h
00
Description
15-12
11-10
X
X
Don't care
CMP-X-MODE
R/W
00: No hysteresis or window function
01: Hysteresis provided using DAC-X-MARGIN-HIGH and DAC-
X-MARGIN-LOW registers
10: Window comparator mode with DAC-X-MARGIN-HIGH and
DAC-X-MARGIN-LOW registers setting window bounds
11: Invalid
9-0
X
X
000h
Don't care
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7.6.7 DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E0h, D4h
图7-28. DAC-X-FUNC-CONFIG Register (X = 0, 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR-SEL-X
SYNC-
BRD-
FUNC-GEN-CONFIG-BLOCK
CONFIG-X CONFIG-X
R/W-0h
R/W-0h R/W-0h
R/W-0h
表7-29. DAC-X-FUNC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CLR-SEL-X
R/W
0
0: Clear DAC-X to zero-scale
1: Clear DAC-X to mid-scale
14
13
SYNC-CONFIG-X
R/W
R/W
0
0
0: DAC-X output updates immediately after a write command
1: DAC-X output updates with LDAC pin falling-edge or when the
LDAC bit in the COMMON-TRIGGER register is set to 1
BRD-CONFIG-X
0: Don't update DAC-X with broadcast command
1: Update DAC-X with broadcast command
表7-30. Linear-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12-11
PHASE-SEL-X
R/W
0
00: 0°
01: 120°
10: 240°
11: 90°
10-8
FUNC-CONFIG-X
R/W
0
000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7
LOG-SLEW-EN-X
CODE-STEP-X
R/W
R/W
0
0
0: Enable linear slew
6-4
CODE-STEP for linear slew mode:
000: 1-LSB
001: 2-LSB
010: 3-LSB
011: 4-LSB
100: 6-LSB
101: 8-LSB
110: 16-LSB
111: 32-LSB
3-0
SLEW-RATE-X
R/W
0
SLEW-RATE for linear slew mode:
0000: No slew for margin-high and margin-low. Invalid for
waveform generation.
0001: 4 µs/step
0010: 8 µs/step
0011: 12 µs/step
0100: 18 µs/step
0101: 27.04 µs/step
0110: 40.48 µs/step
0111: 60.72 µs/step
1000: 91.12 µs/step
1001: 136.72 µs/step
1010: 239.2 µs/step
1011: 418.64 µs/step
1100: 732.56 µs/step
1101: 1282 µs/step
1110: 2563.96 µs/step
1111: 5127.92 µs/step
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表7-31. Logarithmic-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12-11
PHASE-SEL-X
R/W
0
00: 0°
01: 120°
10: 240°
11: 90°
10-8
FUNC-CONFIG-X
LOG-SLEW-EN-X
R/W
R/W
0
0
000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7
1: Enable logarithmic slew.
In logarithmic slew mode, the DAC output moves from the DAC-
X-MARGIN-LOW code to the DAC-X-MARGIN-HIGH code, or
vice versa, in 3.125% steps.
When slewing in the positive direction, the next step is
(1 + 0.03125) times the current step.
When slewing in the negative direction, the next step is
(1 –0.03125) times the current step.
When DAC-X-MARGIN-LOW is 0, the slew starts from code 1.
The time interval for each step is defined by RISE-SLEW-X and
FALL-SLEW-X.
6-4
3-1
0
RISE-SLEW-X
FALL-SLEW-X
X
R/W
R/W
X
0
0
0
SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-LOW to
DAC-X-MARGIN-HIGH):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-HIGH
to DAC-X-MARGIN-LOW):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
Don't care
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7.6.8 DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
PMBus page address = 03h, 00h, PMBus register address = 21h
图7-29. DAC-X-DATA Register (X = 0, 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC63202: DAC-X-DATA[11:0]
DAC53202: DAC-X-DATA[9:0]
X
R/W-0h
X-0h
表7-32. DAC-X-DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
DAC63202: DAC-X-DATA[11:0]
DAC53202: DAC-X-DATA[9:0]
R/W
000h
Data for DAC output
Data are in straight-binary format. MSB left-aligned. MSB left-
aligned. Use the following bit-alignment:
DAC63202: {DAC-X-MARGIN-HIGH[11:0]}
DAC53202: {DAC-X-MARGIN-HIGH[9:0], X, X}
X = Don't care bits.
Don't care
3-0
X
X
0h
7.6.9 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
PMBus page address = FFh, PMBus register address = E3h
图7-30. COMMON-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WIN-
LATCH- LOCK
EN
DEV-
EE-READ-
ADDR
EN-INT-
REF
VOUT-PDN-0
IOUT-
PDN-0
Don't care
VOUT-PDN-1
IOUT-
PDN-1
R/W-0h R/W-0h
R/W-0h
R/W-0h
R/W-11b
R/W-1b
X-11h
R/W-11b
R/W-1b
表7-33. COMMON-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
WIN-LATCH-EN
R/W
0
0: Non-latching window-comparator output
1: Latching window-comparator output
14
DEV-LOCK
R/W
0
0: Device not locked
1: Device locked, the device locks all the registers. To set this bit
back to 0 (unlock device), write to the unlock code to the DEV-
UNLOCK field in the COMMON-TRIGGER register first, followed
by a write to the DEV-LOCK bit as 0.
13
12
EE-READ-ADDR
EN-INT-REF
R/W
R/W
0
0
0: Fault-dump read enable at address 0x00
1: Fault-dump read enable at address 0x01
0: Disable internal reference
1: Enable internal reference. This bit must be set before using
internal reference gain settings.
11-10, 2-1 VOUT-PDN-X
R/W
11
00: Power-up VOUT-X
01: Power-down VOUT-X with 10 kΩto AGND
10: Power-down VOUT-X with 100 kΩto AGND
11: Power-down VOUT-X with Hi-Z to AGND
9, 0
8-3
IOUT-PDN-X
X
R/W
X
1
0: Power-up IOUT-X
1: Power-down IOUT-X
11h
Don't care
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7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E4h
图7-31. COMMON-TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEV-UNLOCK
RESET
LDAC
CLR
X
FAULT- PROTECT
DUMP
READ-
ONE-
TRIG
NVM-
PROG RELOAD
NVM-
R/W-0h
R/W-0h
R/W-0h R/W-0h X-0h R/W-0h
R/W-0h
R/W-0h R/W-0h R/W-0h
表7-34. COMMON-TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-8
7
DEV-UNLOCK
R/W
0000
0101: Device unlocking password
Others: Don't care
RESET
W
0000
0
1010: POR reset triggered. This bit self-resets.
Others: Don't care
LDAC
R/W
0: LDAC operation not triggered
1: LDAC operation triggered if the respective SYNC-CONFIG-X
bit in the DAC-X-FUNC-CONFIG register is 1. This bit self-resets.
6
CLR
R/W
0
0: DAC registers and outputs unaffected
1: DAC registers and outputs set to zero-code or mid-code based
on the respective CLR-SEL-X bit in the DAC-X-FUNC-CONFIG
register. This bit self-resets.
5
4
X
X
0
0
Don't care
FAULT-DUMP
R/W
0: Fault-dump is not triggered
1: Triggers fault-dump sequence. This bit self-resets.
3
2
1
0
PROTECT
R/W
R/W
R/W
R/W
0
0
0
0
0: PROTECT function not triggered
1: Trigger PROTECT function. This bit is self-resetting.
READ-ONE-TRIG
NVM-PROG
0: Fault-dump read not triggered
1: Read one row of NVM for fault-dump. This bit self-resets.
0: NVM write not triggered
1: NVM write triggered. This bit self-resets.
NVM-RELOAD
0: NVM reload not triggered
1: Reload data from NVM to register map. This bit self-resets.
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7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E5h
图7-32. COMMON-DAC-TRIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET-
CMP-
FLAG-1
TRIG-
MAR-
LO-1
TRIG-
MAR-
HI-1
START-
FUNC-1
Don't care
RESET- TRIG-
TRIG- START-
MAR- FUNC-0
HI-0
CMP-
MAR-
LO-0
FLAG-0
W-0h
W-0h
W-0h
R/W-0h
X-0h
W-0h
W-0h
W-0h R/W-0h
表7-35. COMMON-DAC-TRIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15, 3
RESET-CMP-FLAG-X
W
0
0: Latching-comparator output unaffected
1: Reset latching-comparator and window-comparator output.
This bit self-resets.
14, 2
13, 1
12, 0
TRIG-MAR-LO-X
TRIG-MAR-HI-X
START-FUNC-X
W
0
0
0
0: Don't care
1: Trigger margin-low command. This bit self-resets.
W
0: Don't care
1: Trigger margin-high command. This bit self-resets.
R/W
0: Stop function generation
1: Start function generation as per FUNC-GEN-CONFIG-X in the
DAC-X-FUNC-CONFIG register.
11-4
X
X
0h
Don't care
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7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
PMBus page address = FFh, PMBus register address = E6h
图7-33. GENERAL-STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NVM-
CRC-
FAIL-INT
NVM-
CRC-
FAIL-
USER
X
DAC-0-
BUSY
X
DAC-1-
BUSY
X
DEVICE-ID
VERSION-ID
R-0h
R-0h
R-0h
R-0h
X-0h
R-0h
X-0h
R
R-0h
表7-36. GENERAL-STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
NVM-CRC-FAIL-INT
R
0
0: No CRC error in OTP
1: Indicates a failure in OTP loading. A software
reset or power-cycle can bring the device out of
this condition in case of temporary failure.
14
NVM-CRC-FAIL-USER
R
0
0: No CRC error in NVM loading
1: Indicates a failure in NVM loading. The register
settings are corrupted. The device allows all
operations during this error condition. Reprogram
the NVM to get original state. A software reset
brings the device out of this temporary error
condition.
13
12
X
R
R
0
0
Don't care
DAC-0-BUSY
0: DAC-0 channel can accept commands
1: DAC-0 channel does not accept commands
11-10
9
X
X
R
0
0
Don't care
DAC-1-BUSY
0: DAC-1 channel can accept commands
1: DAC-1 channel does not accept commands
8
X
R
R
0
Don't care
7-2
DEVICE-ID
DAC63202: 06h
DAC53202: 07h
Device identifier.
1-0
VERSION-ID
R
00
Version identifier.
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7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E7h
图7-34. CMP-STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
PROTECT- WIN-
X
WIN- CMP-
CMP-1 FLAG-
0
X
CMP-
FLAG-
1
FLAG
CMP-0
X-0h
R-0h
R-0h
X-0h
R-0h
R-0h
X-0h
R-0h
表7-37. CMP-STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-9, 6-5,
2-1
X
X
0
Don't care
8
PROTECT-FLAG
WIN-CMP-X
R
R
R
0
0
0
0: PROTECT operation not triggered.
1: PROTECT function is completed or in progress. This bit resets
to 0 when read.
7, 4
3, 0
Window comparator output from respective channels. The output
is latched or unlatched based on the WINDOW-LATCH-EN
setting in the COMMON-CONFIG register.
CMP-FLAG-X
Synchronized comparator output from respective channels.
7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E8h
图7-35. GPIO-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GF-EN
R/W-0h
X
GPO-EN
R/W-0h
GPO-CONFIG
R/W-0h
GPI-CH-SEL
R/W-0h
GPI-CONFIG
R/W-0h
GPI-EN
R/W-0h
X-0h
表7-38. GPIO-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
GF-EN
R/W
0
0: Glitch filter disabled for GP input. This setting provides faster
response.
1: Glitch filter enabled for GPI. This setting introduces additional
propagation delay but provides robustness.
14
13
X
X
0
0
Don't care.
GPO-EN
R/W
0: Disable output mode for GPIO pin.
1: Enable output mode for GPIO pin.
12-9
GPO-CONFIG
R/W
0000
STATUS function setting. The GPIO pin is mapped to the
following register bits as output:
0001: NVM-BUSY
0100: DAC-1-BUSY
0111: DAC-0-BUSY
1000: WIN-CMP-1
1011:WIN-CMP-0
Others: NA
8-5
GPI-CH-SEL
R/W
0000
Two bits correspond to two DAC channels. 0b is disabled and 1b
is enabled.
GPI-CH-SEL[0]: Channel 1
GPI-CH-SEL[3]: Channel 0
Example: when GPI-CH-SEL is 1001, both channel-0 and
channel-1 are enabled.
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表7-38. GPIO-CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4-1
GPI-CONFIG
R/W
0000
GPIO pin input configuration. Global settings act on the entire
device. Channel-specific settings are dependent on the channel
selection by the GPI-CH-SEL bits:
0010: FAULT-DUMP (global). GPIO falling edge triggers fault
dump, GPIO = 1 has no effect.
0011: IOUT power up-down (channel-specific). GPIO falling edge
triggers power down, GPIO rising edge triggers power up.
0100: VOUT power up-down (channel-specific). The output load
is as per the VOUT-PDN-X setting. GPIO falling edge triggers
power down, GPIO rising edge triggers power up.
0101: PROTECT input (global). GPIO falling edge asserts
PROTECT function, GPIO = 1 has no effect.
0111: CLR input (global). GPIO = 0 asserts CLR function, GPIO =
1 has no effect.
1000: LDAC input (channel-specific). GPIO falling edge asserts
LDAC function, GPIO = 1 has no effect. Both the SYNC-CONFIG-
X and the GPI-CH-SEL must be configured for every channel.
1001: Start and stop function generation (channel-specific). GPIO
falling edge stops function generation. GPIO rising edge starts
function generation.
1010: Trigger margin high-low (channel-specific). GPIO falling
edge triggers margin low. GPIO rising edge triggers margin high.
1011: RESET input (global). The falling edge of the GPIO pin
asserts the RESET function. The RESET input must be a pulse.
The GPIO rising edge brings the device out of reset. The RESET
configuration must be programmed into the NVM. Otherwise the
setting is cleared after the device reset.
1100: NVM write protection (global). GPIO falling edge allows
NVM programming. GPIO rising edge blocks NVM programming.
1101: Register-map lock (global). GPIO falling edge allows
update to the register map. GPIO rising edge blocks any register
map update except a write to the DEV-UNLOCK field through I2C
or SPI and to the RESET field through I2C.
Others: Invalid
0
GPI-EN
R/W
0
0: Disable input mode for GPIO pin.
1: Enable input mode for GPIO pin.
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7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E9h
图7-36. DEVICE-MODE-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
DIS-
MODE-IN
RESERVED
PROTECT-
CONFIG
RESERVED
X
R/W-0h
R/W-0h
R/W-0h
R/W-0h
X-0h
表7-39. DEVICE-MODE-CONFIG Register Field Descriptions
Bit
15-14
13
Field
RESERVED
Type
R/W
R/W
R/W
R/W
Reset
Description
00
0
Always write 0b00
DIS-MODE-IN
RESERVED
Write 1 to this bit for low-power consumption.
Always write 0b000
12-10
9-8
0
PROTECT-CONFIG
00
00: Switch to Hi-Z power-down (no slew)
01: Switch to DAC code stored in NVM (no slew) and then switch
to Hi-Z power-down
10: Slew to margin-low code and then switch to Hi-Z power-down
11: Slew to margin-high code and then switch to Hi-Z power-down
7-5
4-0
RESERVED
X
R/W
R/W
0
Always write 0b000
Don't care
00h
7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
图7-37. INTERFACE-CONFIG Register
15
14
X
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMEOUT-
EN
X
EN-PMBUS
X
FSDO-
EN
X
SDO-
EN
X-0h
R/W-0h
X-0h
R/W-0h
X-0h
R/W-0h X-0h R/W-0h
表7-40. INTERFACE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12
X
X
0h
Don't care
TIMEOUT-EN
R/W
0
0: I2C timeout disabled
1: I2C timeout enabled
11-9
8
X
X
0h
0
Don't care
EN-PMBUS
R/W
0: PMBus disabled
1: Enable PMBus
7-3
2
X
X
00h
0
Don't care
FSDO-EN
R/W
0: Fast SDO disabled
1: Fast SDO enabled
1
0
X
X
0
0
Don't care
SDO-EN
R/W
0: SDO disabled
1: SDO enabled on GPIO pin
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7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
PMBus page address = FFh, PMBus register address = EFh
图7-38. SRAM-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
SRAM-ADDR
R/W-0h
X-0h
表7-41. SRAM-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-0
X
X
0h
Don't care
SRAM-ADDR
R/W
0h
8-bit SRAM address. Writing to this register field configures the
SRAM address to be accessed next. This address automatically
increments after a write to the SRAM.
7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
PMBus page address = FFh, PMBus register address = F0h
图7-39. SRAM-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRAM-DATA
R/W-0h
表7-42. SRAM-DATA Register Field Descriptions
Bit
15-0
Field
SRAM-ADDR
Type
Reset
Description
R/W
0h
16-bit SRAM data. This data is written to or read from the address
configured in the SRAM-CONFIG register.
7.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = F1h
图7-40. BRDCAST-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC63202: BRDCAST-DATA[11:0]
DAC53202: BRDCAST-DATA[9:0]
X
R/W-0h
X-0h
表7-43. BRDCAST-DATA Register Field Descriptions
Bit
15-4
Field
Type
Reset
Description
DAC63202: BRDCAST-DATA[11:0]
DAC53202: BRDCAST-DATA[9:0]
R/W
000h
Broadcast code for all DAC channels
Data are in straight-binary format. MSB left-aligned. Use the
following bit-alignment:
DAC63202: {DAC-X-MARGIN-HIGH[11:0]}
DAC53202: {DAC-X-MARGIN-HIGH[9:0], X, X}
X = Don't care bits.
The BRD-CONFIG-X bit in the DAC-X-FUNC-CONFIG register
must be enabled for the respective channels.
3-0
X
X
0h
Don't care.
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7.6.20 PMBUS-PAGE Register [reset = 0300h]
PMBus page address = X, PMBus register address = 00h
图7-41. PMBUS-PAGE Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS-PAGE
R/W-03h
X
X-00h
表7-44. PMBUS_OPERATION Register Field Descriptions
Bit
Field
Type
R/W
X
Reset
Description
15-8
7-0
PMBUS-PAGE
X
03h
8-bit PMBus page address as specified in 表7-21.
00h
Not applicable
7.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 01h
图7-42. PMBUS-OP-CMD-X Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS-OPERATION-CMD-X
R/W-00h
X
X-00h
表7-45. PMBUS-OP-CMD-X Register Field Descriptions
Bit
15-8
Field
Type
Reset
Description
PMBUS-OPERATION-CMD-X
R/W
00h
PMBus operation commands:
00h: Turn off
80h: Turn on
A4h: Margin high, DAC output margins high to DAC-X-MARGIN-
HIGH code
94h: Margin low, DAC output margins low to DAC-X-MARGIN-
LOW code
7-0
X
X
00h
Not applicable
7.6.22 PMBUS-CML Register [reset = 0000h]
PMBus page address = X, PMBus register address = 78h
图7-43. PMBUS-CML Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
CML
R/W-0h
X
N/A
X-00h
X-0h
X-00h
表7-46. PMBUS-CML Register Field Descriptions
Bit
Field
Type
Reset
00h
0h
Description
15-10
9
X
X
Don't care
CML
R/W
0: No communication fault
1: PMBus communication fault for write with incorrect number of
clocks, read before write command, invalid command address,
and invalid or unsupported data value; reset this bit by writing 1.
8
X
X
X
X
0h
Don't care
7-0
00h
Not applicable
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7.6.23 PMBUS-VERSION Register [reset = 2200h]
PMBus page address = X, PMBus register address =98h
图7-44. PMBUS-VERSION Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS-VERSION
R-22h
X
X-00h
表7-47. PMBUS-VERSION Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-0
PMBUS-VERSION
X
R
22h
PMBus version
Not applicable
X
00h
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DACx3202 are dual-channel buffered, force-sense output, voltage-output and current-output smart DACs
that include an NVM and internal reference, and available in a tiny 3-mm × 3-mm package.
• In voltage-output mode, short the OUTx and FBx pins for each channel. In current-output mode, leave the
FBx pins unconnected. The FBx pins function as inputs in comparator mode.
• The external reference must not exceed VDD, either during transient or steady-state conditions. For the best
Hi-Z output performance, use a pullup resistor on the VREF pin to VDD. In case the VDD remains floating
during the off condition, place a 100-kΩresistor to AGND for proper detection of the VDD off condition.
• All the digital outputs are open drain; use external pullup resistors on these pins.
• The interface protocol is detected at power-on, and the device locks to the protocol as long as VDD is on.
• When allocating nonoverlapping I2C addresses on a system I2C bus, consider the broadcast address as well.
I2C timeout can be enabled for robustness.
• SPI mode is 3-wire by default. Configure the GPIO pin as SDO in the NVM for SPI readback capability. The
SPI clock speed in readback mode is slower than that in write mode.
• Power-down mode sets the DAC outputs in Hi-Z by default. Change the configuration appropriately for
different power-down settings. The DAC channels can also power-up with a programmed DAC code in the
NVM.
8.2 Typical Application
A power-supply margining and scaling circuit is used to trim, scale, or test the output of a power converter. This
example circuit is used to test a system by margining the power supplies for adaptive voltage scaling or to
program a desired value at the output. Adjustable power supplies, such as low-dropout regulators (LDOs) and
DC/DC converters, provide a feedback or adjust the input that is used to set the desired output. A precision
voltage-output DAC is the best choice for controlling the power-supply output linearly. 图 8-1 shows a control
circuit for a switch-mode power supply (SMPS) using the DACx3202. Typical applications of power-supply
margining are communications equipment, enterprise servers, test and measurement, and general-purpose
power-supply modules.
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VDD
10 kΩ
0.1 μ
1.5 μ
VREF
CAP
LDO
L
VIN
IN
PH
VOUT
Internal
Reference
NVM
SCL/SYNC
SDA/SCLK
A0/SDI
BOOT
R1
SMPS / LDO
GND
CL
CB
R3
VFB
R2
DAC
REG
DAC
BUF
VOUT/
IOUT
SENSE
R3
DAC
REG
DAC
BUF
VOUT/
IOUT
PROTECT
Output Configuration
Logic
Power-supply: 0
Power-supply: 1
DACx3202
AGND
图8-1. Voltage Margining and Scaling
表8-1. Design Parameters
8.2.1 Design Requirements
PARAMETER
VALUE
Power-supply nominal output
3.3 V
0.6 V
Reference voltage of the converter (VFB
Margin
)
±10% (that is, 2.97 V to 3.63 V)
DAC output range
1.8 V
Nominal current through R1 and R2
100 µA
8.2.2 Detailed Design Procedure
The DACx3202 features a Hi-Z power-down mode that is set by default at power-up, unless the device is
programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R3 is zero and the
SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers
up, bring up the device at the same output as VFB (that is 0.6 V). This configuration makes sure there is no
current through R3 even at power-up. Calculate R1 as (VOUT –VFB) / 100 µA = 27 kΩ.
To achieve ±10% margin-high and margin-low conditions, the DAC must sink or source additional current
through R1. Calculate the current from the DAC (IMARGIN) using 方程式9 as 12 µA.
V
× 1 + MARGIN − V
OUT
FB
I
=
− I
(9)
MARGIN
NOMINAL
R
1
where
• IMARGIN is the margin current sourced or sinked from the DAC.
• MARGIN is the percentage margin value divided by 100.
• INOMINAL is the nominal current through R1 and R2.
• VOUT is the output voltage of the respective DAC channel.
• VFB is the reference voltage at the SENSE node of the power converter.
• R1 is the resistance between the output and SENSE pin of the power converter.
To calculate the value of R3, first decide the DAC output range, and make sure to avoid the codes near zero-
scale and full-scale for safe operation in the linear region. A DAC output of 20 mV is a safe consideration as the
minimum output, and (1.8 V – 0.6 V – 20 mV = 1.18 V) as the maximum output. When the DAC output is at 20
mV, the power supply goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to
margin low. Calculate the value of R3 using 方程式 10 as 48.3 kΩ. Choose a standard resistor value and adjust
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the DAC outputs. Choosing R3 = 47 kΩ makes the DAC margin high code as 1.164 V and the DAC margin low
code as 36 mV.
V
− V
FB
DAC
I
R =
(10)
3
MARGIN
When the DACx3202 are set to current-output mode, series resistor R3 is not required. Set the DAC output at
the current-output range of –25 µA to +25 µA, and set the DAC code accordingly to achieve a margin current of
±12 µA.
The DACx3202 have a slew-rate feature that is used to toggle between margin high, margin low, and nominal
outputs with a defined slew rate; see also 节7.6.7.
备注
The DAC-X-MARGIN-HIGH register value in DACx3202 results in the margin-low value at the power
supply output. Similarly, the DAC-X-MARGIN-LOW register value in DACx3202 results in the margin-
high value at the power-supply output.
The pseudocode for getting started with a power-supply control application is as follows:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Write DAC code for nominal output (repeat for all DAC channels)
//For
a 1.8-V output range, the 10-bit hex code for 0.6 V is 0x155. With 16-bit left alignment,
this becomes 0x5540
WRITE DAC_0_DATA(0x1C), 0x55, 0x40
//Power-up voltage output on both the channels, enables internal reference
WRITE COMMON-CONFIG(0x1F), 0x12, 0x01
//Set channel 0 gain setting to 1.5x internal reference (1.8 V)
WRITE DAC-0-VOUT-CMP-CONFIG(0x15), 0x08, 0x00
//Set channel 1 gain setting to 1.5x internal reference (1.8 V)
WRITE DAC-1-VOUT-CMP-CONFIG(0x3), 0x08, 0x00
//Configure GPI for Margin-High, Low trigger for all channels
WRITE GPIO-CONFIG(0x24), 0x01, 0x35
//Set slew rate and code step (repeat for all channels)
//CODE_STEP: 2 LSB, SLEW_RATE: 60.72 µs/step
WRITE DAC-0-FUNC-CONFIG(0x18), 0x00, 0x17
//Write DAC margin high code (repeat for all channels)
//For a 1.8-V output range, the 10-bit hex code for 1.164 V is 0x296. With 16-bit left alignment,
this becomes 0xA540
WRITE DAC-0-MARGIN-HIGH(0x13), 0xA5, 0x40
//Write DAC margin low code (repeat for all channels)
//For a 1.8-V output range, the 10-bit hex code for 36 mV is 0x14. With 16-bit left alignment, this
becomes 0x0500
WRITE DAC-0-MARGIN-LOW(0x14), 0x05, 0x00
//Save settings to NVM
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02
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8.2.3 Application Curves
图8-3. Power-Supply Margin Low
图8-2. Power-Supply Margin High
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9 Power Supply Recommendations
The DACx3202 family of devices does not require specific power-supply sequencing. These devices require a
single power supply, VDD. However, make sure the external voltage reference is applied after VDD. Use a 0.1-µF
decoupling capacitor for the VDD pin. Use a bypass capacitor with a value approximately 1.5 µF for the CAP pin.
10 Layout
10.1 Layout Guidelines
The DACx3202 pin configuration separates the analog, digital, and power pins for an optimized layout. For
signal integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.
10.2 Layout Example
VREF Pullup
Resistor
VDD
VDD
Decoupling
Capacitor
LDO Bypass
Capacitor
GND
GND
GND
VREF Bypass
Capacitor
GND
DACx3202
1
2
3
4
12
11
10
9
FB0
FB1
OUT0
OUT1
VIO
VIO
VIO
VIO
图10-1. Layout Example
Note: The ground and power planes have been omitted for clarity. Connect the thermal pad to ground.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
The following EVM user's guide is available: DACx3204 Evaluation Module user's guide
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
PMBus™ is a trademark of SMIF, Inc..
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC53202RTER
DAC63202RTER
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
D53202
D63202
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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