DAC715UG4 [TI]

16-BIT DIGITAL-TO-ANALOG CONVERTER with 16-Bit Bus Interface; 16位数字 - 模拟转换器，具有16位总线接口


型号：	DAC715UG4
厂家：	TEXAS INSTRUMENTS
描述：	16-BIT DIGITAL-TO-ANALOG CONVERTER with 16-Bit Bus Interface 16位数字 - 模拟转换器，具有16位总线接口转换器
文件：	总14页 (文件大小：230K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC715

FPO

DAC715

16-BIT DIGITAL-TO-ANALOG CONVERTER

with 16-Bit Bus Interface

FEATURES

● HIGH-SPEED 16-BIT PARALLEL DOUBLE-

DESCRIPTION

The DAC715 is a complete monolithic digital-to-

analog converter including a +10V temperature com-

pensated reference, current-to-voltage amplifier, 16-bit

parallel interface that is double buffered, and an asyn-

chronous clear function which immediately sets the

output voltage to one-half of full-scale.

BUFFERED INTERFACE

● VOLTAGE OUTPUT: 0 to +10V

● 13-, 14-, 15-BIT LINEARITY GRADES

● 16-BIT MONOTONIC OVER

TEMPERATURE (L GRADE)

The output voltage range is 0 to +10V while operating

from ±12V or ±15V supplies. The gain and bipolar

offset adjustments are designed so that they can be set

via external potentiometers or external D/A converters.

The output amplifier is protected against short circuit to

ground.

● POWER DISSIPATION: 600mW max

● GAIN AND OFFSET ADJUST: Convenient

for Auto-Cal D/A Converters

● 28-LEAD DIP AND SOIC PACKAGES

The 28-pin DAC715 is available in a 0.3" plastic DIP

and wide-body plastic SOIC package. The DAC715P,

U, PB, and UB are specified over the –40°C to +85°C

temperature range while the DAC715PK, UK, PL, and

UL are specified over the 0°C to +70°C range.

D15

A₁

A₀

Input Latch

CLR

D/A Latch

Reference

Circuit

16-Bit D/A Converter

V_OUT

V_{REF OUT}

+10V

Offset Adjust

Gain Adjust

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

•

Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1306D

Printed in U.S.A. July, 1997

SBAS046

SPECIFICATIONS

ELECTRICAL

At T_A= +25°C, V_CC= ±15V, and after a 10-minute warm-up, unless otherwise noted.

DAC715P, U

TYP

DAC715PB, UB

TYP

DAC715PK, UK

TYP

DAC715PL, UL

TYP

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

INPUT

RESOLUTION

✻

Bits

DIGITAL INPUTS

Input Code

Binary Two’s Complement

+2.0 +V_CC– 1.4

✻

Logic Levels⁽¹⁾: V_IH

V_IL

✻

µA

+0.8

±10

I_IH(V_I= +2.7V)

I_IL(V_I= +0.4V)

µA

TRANSFER CHARACTERISTICS

ACCURACY

Linearity Error

T_MINto T_MAX

Differential Linearity Error

T_MINto T_MAX

±4

±8

±4

±8

±2

±4

±2

±4

±2

±1

LSB

Monotonicity Over Temp

Gain Error⁽³⁾

Bits

±0.1

±0.2

±0.1

±0.2

±0.003

±0.1

±0.15

✻

T_MINto T_MAX

Offset Error⁽³⁾

% FSR⁽²⁾

% FSR

% FSR/%V_CC

PPM FSR/%V_CC

T_MINto T_MAX

Power Supply Sensitivity Of Full Scale

±30

✻

DYNAMIC PERFORMANCE

Settling Time (to ±0.003%FSR,

5kΩ ll 500pF Load)⁽⁴⁾

10V Output Step

✻

µs

V/µs

1 LSB Output Step⁽⁵⁾

Output Slew Rate

Total Harmonic Distortion + Noise

0dB, 1001Hz, f_S= 100kHz

–20dB, 1001Hz, f_S= 100kHz

–60dB, 1001Hz, f_S= 100kHz

SINAD

0.005

0.03

3.0

✻

1001Hz, f_S= 100kHz

✻

nV-s

Digital Feedthrough⁽⁵⁾

Digital-to-Analog Glitch Impulse⁽⁵⁾

Output Noise Voltage

(includes Reference)

120

✻

nV√Hz

ANALOG OUTPUT

Output Voltage Range

+V_CC, –V_CC= ±11.4V

Output Current

Output Impedance

Short Circuit to ACOM

Duration

0 to +10

±5

✻

Ω

0.1

✻

Indefinite

REFERENCE VOLTAGE

Voltage

T_MINto T_MAX

Output Resistance

Source Current

Short Circuit to ACOM, Duration

+9.975

+9.960

+10.000

+10.025

+10.040

✻

Ω

✻

Indefinite

POWER SUPPLY REQUIREMENTS

Voltage: +V_CC

–V_CC

+11.4

–16.5

+15

–15

+16.5

–11.4

✻

Current (no load, ±15V Supplies)

+V_CC

–V_CC

Power Dissipation

525

600

✻

TEMPERATURE RANGE

Specification All Grades

–40

–60

+85

+150

✻

+70

✻

°C

Storage

Thermal Resistance θ_JA

DIP Package

SOIC Package

✻

°C/W

✻

Specifications are the same as grade to the left.

NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for

0 to +10V output, FSR = 10V.

(3) Errors externally adjustable to zero. (4) Maximum represents greater than the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes: FFFF_Hto 0000_Hand 0000_Hto

FFFF_H. These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.

DAC715

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

TIMING DIAGRAM

+V_CCto COMMON ...................................................................... 0V, +17V

–V_CCto COMMON ...................................................................... 0V, –17V

+V_CCto –V_CC^{...........................................................................................................................}34V

Digital Inputs to COMMON .....................................................–1V to +V_CC

External Voltage Applied to BPO and Range Resistors..................... ±V_CC

V_{REF OUT}...................................................... Indefinite Short to COMMON

V_OUT............................................................ Indefinite Short to COMMON

Power Dissipation .......................................................................... 750mW

Storage Temperature ...................................................... –60°C to +150°C

Lead Temperature (soldering, 10s)................................................ +300°C

t_AW

t_AH

A₀, A₁

t_DW

D0-D15

t_DH

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

t_WP

PACKAGE INFORMATION

TIMING SPECIFICATIONS

PACKAGE DRAWING

T_A= –40°C to +85°C, +V_CC= +12V or +15V, –V_CC= –12V or –15V.

PRODUCT

PACKAGE

NUMBER⁽¹⁾

SYMBOL

PARAMETER

MIN

MAX UNITS

DAC715P

Plastic DIP

Plastic SOIC

Plastic DIP

Plastic SOIC

Plastic DIP

Plastic SOIC

Plastic DIP

Plastic SOIC

246

217

246

217

246

217

246

217

DAC715U

DAC715PB

DAC715UB

DAC715PK

DAC715UK

DAC715PL

DAC715UL

t_DW

t_AW

t_AH

t_DH

Data Valid to End of WR

A₀, A₁Valid to End of WR

A₀, A₁Hold after End of WR

Data Hold after end of WR

Write Pulse Width

(1)

t_WP

t_CP

CLEAR Pulse Width

200

NOTES: (1) For single-buffered operation, t_WPis 80ns min. Refer to page 10.

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

TRUTH TABLE

A₀

A₁

CLR

DESCRIPTION

ORDERING INFORMATION

1 → 0 → 1

Load Input Latch

Load D/A Latch

No Change

Latches Transparent

No Change

DIFFERENTIAL

LINEARITY

ERROR MAX

TEMPERATURE

RANGE

PRODUCT

PACKAGE

at +25°C

Reset D/A Latch

DAC715P

Plastic DIP

Plastic SOIC

Plastic DIP

Plastic SOIC

Plastic DIP

Plastic SOIC

Plastic DIP

Plastic SOIC

–40°C to +85°C

0°C to 70°C

±4LSB

±2LSB

±1LSB

DAC715U

DAC715PB

DAC715UB

DAC715PK

DAC715UK

DAC715PL

DAC715UL

ELECTROSTATIC

DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per-

formancedegradationtocompletedevicefailure.Burr-Brown

Corporationrecommendsthatallintegratedcircuitsbehandled

and stored using appropriate ESD protection methods.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet published speci-

fications.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

DAC715

PIN CONFIGURATION

PIN DESCRIPTIONS

LABEL

DESCRIPTION

DCOM

ACOM

V_OUT

Offset Adjust

V_{REF OUT}

Gain Adjust

+V_CC

Digital Ground

Analog Ground

0 to +10V D/A Output

Offset Adjust

Voltage Reference Output

Gain Adjust

+12V to +15V Supply

–12V to –15V Supply

CLEAR. Sets D/A output to Half Scale

(Active Low)

Write (Active Low)

Enable for D/A latch (Active Low)

Enable for Input latch (Active Low)

Data Bit 15 (Most Significant Bit)

Data Bit 14

Data Bit 13

Data Bit 12

Data Bit 11

Data Bit 10

Data Bit 9

Data Bit 8

Data Bit 7

Data Bit 6

DCOM

ACOM

28 D0 (LSB)

27 D1

26 D2

25 D3

24 D4

23 D5

22 D6

21 D7

20 D8

19 D9

18 D10

17 D11

16 D12

15 D13

V_OUT

–V_CC

CLR

Offset Adjust

V_{REF OUT}

Gain Adjust

+V_CC

A₁

A₀

D15

D14

D13

D12

D11

D10

DAC715

–V_CC

CLR

WR 10

A₁11

A₀12

Data Bit 5

Data Bit 4

Data Bit 3

Data Bit 2

Data Bit 1

Data Bit 0 (Least Significant Bit)

D15 (MSB) 13

D14 14

DAC715

TYPICAL PERFORMANCE CURVES

At T_A= +25°C, and V_CC= ±15V, unless otherwise noted.

POWER SUPPLY REJECTION vs

POWER SUPPLY RIPPLE FREQUENCY

LOGIC vs V LEVEL

2.0

–V_CC

100

1.0

WR, A₀, A₁

CLR

+V_CC

DATA

–1.0

–2.0

0.1

100

10k

100k

–0.85

0.85 1.7 2.55 3.4 4.25 5.1 5.95 6.8

V Digital Input

Frequency (Hz)

FULL-SCALE OUTPUT SWING

SETTLING TIME, +10V TO 0V

2500

2000

1500

1000

500

+5V

–500

–1000

–1500

–2000

–2500

Time (10µs/div)

Time (1µs/div)

Spectral Noise Density

SETTLING TIME, 0V TO +10V

1000

2500

2000

1500

1000

500

+5V

100

–500

–1000

–1500

–2000

–2500

100

10k

100k

10M

Time (1µs/div)

Frequency (Hz)

DAC715

DIGITAL FEEDTHROUGH

DISCUSSION OF

SPECIFICATIONS

LINEARITY ERROR

When the D/A is not selected, high frequency logic activity

on the digital inputs is coupled through the device and shows

up as output noise. This noise is digital feedthrough.

Linearity error is defined as the deviation of the analog

output from a straight line drawn between the end points of

the transfer characteristic.

OPERATION

The DAC715 is a monolithic integrated-circuit 16-bit D/A

converter complete with 16-bit D/A switches and ladder

network, voltage reference, output amplifier and micropro-

cessor bus interface.

DIFFERENTIAL LINEARITY ERROR

Differential linearity error (DLE) is the deviation from

1LSB of an output change from one adjacent state to the

next. A DLE specification of ±1/2LSB means that the output

step size can range from 1/2LSB to 3/2LSB when the digital

input code changes from one code word to the adjacent code

word. If the DLE is more positive than –1LSB, the D/A is

said to be monotonic.

INTERFACE LOGIC

The DAC715 has double-buffered data latches. The input

data latch holds a 16-bit data word before loading it into the

second latch, the D/A latch. This double-buffered organiza-

tion permits simultaneous update of several D/A converters.

All digital control inputs are active low. Refer to the block

diagram shown in Figure 1.

MONOTONICITY

A D/A converter is monotonic if the output either increases

or remains the same for increasing digital input values.

Monotonicity of DAC715 is guaranteed over the specifica-

tion temperature range to 13-, 14-, 15-, and 16-bits for

performance grades DAC715P/U, DAC715PB/UB,

DAC715PK/UK, and DAC715PL/UL respectively.

All latches are level-triggered. Data present when the enable

inputs are logic “0” will enter the latch. When the enable

inputs return to logic “1”, the data is latched.

The CLR input resets both the input latch and the D/A latch

to give a half scale output.

LOGIC INPUT COMPATIBILITY

SETTLING TIME

The DAC715 digital inputs are TTL compatible (1.4V switch-

ing level), low leakage, and high impedance. Thus the inputs

are suitable for being driven by any type of 5V logic family,

such as CMOS logic. An equivalent circuit for the digital

inputs is shown in Figure 2.

Settling time is the total time (including slew time) for the

D/A output to settle to within an error band around its final

value after a change in input. Settling times are specified to

within ±0.003% of Full Scale Range (FSR) for an output

step change of 10V and 1LSB. The 1LSB change is mea-

sured at the Major Carry (FFFF_Hto 0000_H, and 0000_Hto

FFFF_H: BTC codes), the input transition at which worst-case

settling time occurs.

The inputs will float to logic “0” if left unconnected. It is

recommended that any unused inputs be connected to DCOM

to improve noise immunity.

Digital inputs remain high impedance when power is off.

TOTAL HARMONIC DISTORTION

Total harmonic distortion is defined as the ratio of the square

root of the sum of the squares of the values of the harmonics

to the value of the fundamental frequency. It is expressed in

% of the fundamental frequency amplitude at sampling rate

f_S.

INPUT CODING

The DAC715 is designed to accept binary two’s comple-

ment (BTC) input codes. For unipolar analog output con-

figuration, a digital input of 7FFF_Hgives a full scale output,

8000_Hgives a zero output, and 0000_Hgives half scale output.

SIGNAL-TO-NOISE

AND DISTORTION RATIO (SINAD)

INTERNAL REFERENCE

SINAD includes all the harmonic and outstanding spurious

components in the definition of output noise power in

addition to quantizing and internal random noise power.

SINAD is expressed in dB at a specified input frequency and

sampling rate, f_S.

The DAC715 contains a +10V reference. The reference

output may be used to drive external loads, sourcing up to

2mA. The load current should be constant, otherwise the

gain of the converter will vary.

OUTPUT VOLTAGE SWING

DIGITAL-TO-ANALOG GLITCH IMPULSE

The output amplifier of the DAC715 is committed to a 0 to

+10V output range. It will provide a 0 to +10V output swing

while operating on ±11.4V or higher voltage supplies.

The amount of charge injected into the analog output from

the digital inputs when the inputs change state. It is mea-

sured at half scale at the input codes where as many as

possible switches change state—from FFFF_Hto 0000_H.

DAC715

V_{REF OUT}

+V_CC

– V_CC

Gain Adjust

170Ω

15kΩ

+10V

Reference

Offset

Adjust

10kΩ

5kΩ

+2.5V

–V_CC

D/A Switches

CLR

V_OUT

16-Bit D/A Latch

16-Bit Input Latch

A₁11

A₀12

WR 10

DCOM

D15

ACOM

LSB

MSB

FIGURE 1. DAC715 Block Diagram.

Range of

Gain Adjust

≈ ±0.3%

+ Full Scale

+V_CC

ESD Protection Circuit

R = 1kΩ: A₀, A₁, WR, CLR

3kΩ: D0...D15

Full Scale

Range

Gain Adjust

Rotates the Line

Digital

Input

6.8V

5pF

–V_CC

Range of

Offset Adjust

Zero

Offset Adj.

Translates

the Line

≈ ±0.3%

8000_H

0000_H

Digital Input

7FFF_H

FIGURE 2. Equivalent Circuit of Digital Inputs.

FIGURE 3. Relationship of Offset and Gain Adjustments.

GAIN AND OFFSET ADJUSTMENTS

Figure 3 illustrates the relationship of offset and gain adjust-

ments for a unipolar connected D/A converter. Offset should

be adjusted first to avoid interaction of adjustments. See

Table I for calibration values and codes. These adjustments

have a minimum range of ±0.3%.

Offset Adjustment

Apply the digital input code that produces zero output

voltage and adjust the offset potentiometer or the offset

adjust D/A converter for 0V.

DAC715

DAC715 CALIBRATION VALUES

1 LEAST SIGNIFICANT BIT = 152µV

DCOM

ACOM

V_OUT

DIGITAL INPUT CODE

BINARY TWO’S

COMPLEMENT, BTC

ANALOG

OUTPUT

(V)

DESCRIPTION

7FFF_H

4000_H

0001_H

9.999847

Full Scale –1LSB

7.5

3/4 Scale

Half Scale + 1LSB

Half Scale

V_{REF OUT}

5.000152

+12V to +15V

–12V to –15V

0000_H

4.999847

2.5

+V_CC

–V_CC

FFFF_H

C000_H

8000_H

Half Scale – 1LSB

1/4 Scale

0.01µF

Zero

TABLE I. Digital Input and Analog Output Voltage Calibra-

tion Values.

Gain Adjustment

Apply the digital input that gives the maximum positive

voltage output. Adjust the gain potentiometer or the gain

adjust D/A converter for this positive full scale voltage.

FIGURE 4. Power Supply Connections.

well as at +V_CC. The capacitors should be located close to the

package.

INSTALLATION

GENERAL CONSIDERATIONS

The DAC715 has separate ANALOG COMMON and DIGI-

TAL COMMON pins. The current through DCOM is mostly

switching transients and are up to 1mA peak in amplitude.

The current through ACOM is typically 5µA for all codes.

Due to the high-accuracy of the DAC715, system design

problems such as grounding and contact resistance become

very important. A 16-bit converter with a 10V full-scale

range has a 1LSB value of 152µV. With a load current of

5mA, series wiring and connector resistance of only 60mΩ

will cause a voltage drop of 300µV. To understand what this

means in terms of a system layout, the resistivity of a typical

1 ounce copper-clad printed circuit board is 1/2 mΩ per

square. For a 5mA load, a 10 milliinch wide printed circuit

conductor 60 milliinches long will result in a voltage drop of

150µV.

Use separate analog and digital ground planes with a single

interconnection point to minimize ground loops. The analog

pins are located adjacent to each other to help isolate analog

from digital signals. Analog signals should be routed as far

as possible from digital signals and should cross them at

right angles. A solid analog ground plane around the D/A

package, as well as under it in the vicinity of the analog and

power supply pins, will isolate the D/A from switching

currents. It is recommended that DCOM and ACOM be

connected directly to the ground planes under the package.

The analog output of DAC715 has an LSB size of 152µV

(–96dB). The noise floor of the D/A must remain below this

level in the frequency range of interest. The DAC715’s noise

spectral density (which includes the noise contributed by the

internal reference) is shown in the Typical Performance

Curves section.

If several DAC715s are used or if DAC715 shares supplies

with other components, connecting the ACOM and DCOM

lines together once at the power supplies rather than at each

chip may give better results.

Wiring to high-resolution D/A converters should be routed

to provide optimum isolation from sources of RFI and EMI.

The key to elimination of RF radiation or pickup is small

loop area. Signal leads and their return conductors should be

kept close together such that they present a small capture

cross-section for any external field. Wire-wrap construction

is not recommended.

LOAD CONNECTIONS

Since the reference point for V_OUTand V_{REF OUT}is the ACOM

pin, it is important to connect the D/A converter load

directly to the ACOM pin. Refer to Figure 5.

Lead and contact resistances are represented by R₁through

R₃. As long as the load resistance R_Lis constant, R₁simply

introduces a gain error and can be removed by gain adjust-

ment of the D/A or system-wide gain calibration. R₂is part

of R_Lif the output voltage is sensed at ACOM.

POWER SUPPLY AND

REFERENCE CONNECTIONS

In some applications it is impractical to return the load to the

ACOM pin of the D/A converter. Sensing the output voltage

at the SYSTEM GROUND point is reasonable, because

there is no change in DAC715 ACOM current, provided that

Power supply decoupling capacitors should be added as

shown in Figure 4. Best performance occurs using a 1 to

10µF tantalum capacitor at –V_CC. Applications with less

critical settling time may be able to use 0.01µF at –V_CCas

DAC715

R₃is a low-resistance ground plane or conductor. In this case

you may wish to connect DCOM to SYSTEM GROUND as

well.

converters outputs are at approximately half scale, 0V.

DIGITAL INTERFACE

BUS INTERFACE

GAIN AND OFFSET ADJUST

Connections Using Potentiometers

The DAC715 has a 16-bit double-buffered data interface

with control lines for easy connection to a 16-bit bus. The

double-buffered feature permits update of several D/As

simultaneously.

GAIN and OFFSET adjust pins provide for trim using

external potentiometers. 15-turn potentiometers provide suf-

ficient resolution. Range of adjustment of these trims is at

least ±0.3% of Full Scale Range. Refer to Figure 6.

A₀is the enable control for the DATA INPUT LATCH. A₁

is the enable for the D/A LATCH. WR is used to strobe data

into latches enabled by A₀, and A₁. Refer to the block

diagram of Figure 1 and to Timing Diagram on page 3.

Using D/A Converters

The GAIN ADJUST and OFFSET ADJUST circuits of

the DAC715 have been arranged so that these points may

be easily driven by external D/A converters. Refer to

Figure 7. 12-bit D/A converters provide an OFFSET adjust

resolution and a GAIN adjust resolution of 30µV to 50µV

per LSB step.

CLR sets the INPUT DATA LATCH and D/A LATCH to

0000_H(5V at the D/A output).

SINGLE-BUFFERED OPERATION

Nominal values of GAIN and OFFSET occur when the D/A

DAC715

10kΩ

5kΩ

V_REF

R₁

V_OUT

Bus

Interface

Sense

Output

R_L

DCOM

ACOM

R₂

Alternate Ground

Sense Connection

R₃

To +V_CC

0.01µF⁽¹⁾

0.01µF

Analog

Power

Supply

System Ground

To –V_CC

NOTE: (1) Locate close to DAC715 package.

FIGURE 5. System Ground Considerations for High-Resolution D/A Converters.

DAC715

To operate the DAC715 interface as a single-buffered latch,

the DATA INPUT LATCH is permanently enabled by

connecting A₀to DCOM. If A₁is not used to enable the

D/A, it should be connected to DCOM also. For this mode

of operation, the width of WR will need to be at least 80ns

minimum to pass data through the DATA INPUT LATCH

and into the D/A LATCH.

The digital interface of the DAC715 can be made transpar-

ent by asserting A_O, A₁, and WR LOW, and asserting CLR

HIGH.

TRANSPARENT INTERFACE

Internal

+10V Reference

V_{REF OUT}

P₁

1kΩ

170Ω

R₁

100Ω

Gain Adjust

+V_CC

R₂

2MΩ

Offset Adjust

P₂

15kΩ

10kΩ – 100kΩ

10kΩ

–V_CC

5kΩ

R₃

27kΩ

≈ +2.5V

+10V V_OUT

IDAC

0-2mA

For no external adjustments, pins 4 and 6 are not connected.

External resistors R1 - R4 are standard ±1% values. Range of

adjustment at least ±0.03% FSR.

ACOM

FIGURE 6. Manual Offset and Gain Adjust Circuits.

DAC715

Internal

+10V Reference

V_{REF OUT}

R₁

392Ω

170Ω

Gain Adjust

R₂

33kΩ

10kΩ

5kΩ

Offset Adjust

15kΩ

–10 to 10V

DAC

R₃

1MΩ

–10 to 10V

DAC

0 to 2mA

V_OUT

R₁- R₃tolerance: ±1%, Range of

adjustment at least ±0.3% FSR.

DAC715

FIGURE 7. Gain and Offset Adjustment Using D/A Converters.

DAC715

PACKAGE OPTION ADDENDUM

www.ti.com

3-Nov-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

DAC715P

DAC715PB

NRND

PDIP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU N / A for Pkg Type

Green (RoHS

& no Sb/Br)

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-3-260C-168 HR

DAC715PBG4

DAC715PG4

DAC715PK

NRND

Green (RoHS

& no Sb/Br)

NRND

Green (RoHS

& no Sb/Br)

NRND

Green (RoHS

& no Sb/Br)

DAC715PKG4

DAC715PL

NRND

Green (RoHS

& no Sb/Br)

NRND

Green (RoHS

& no Sb/Br)

DAC715PLG4

DAC715U

NRND

Green (RoHS

& no Sb/Br)

ACTIVE

Green (RoHS

& no Sb/Br)

DAC715UB

DAC715UBG4

DAC715UG4

DAC715UK

DAC715UKG4

DAC715UL

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

DAC715ULG4

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

3-Nov-2011

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

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DAC715UG4 [TI]

相关型号：

DAC715UK

DAC715UK

DAC715UKG4

DAC715UL

DAC715UL

DAC715ULG4

DAC716

DAC716

DAC716P

DAC716P

DAC716PB

DAC716PB