概述
规格参数
数据手册
替代型号DAC7558IRHBTG4 概述
12 位、八路、超低毛刺脉冲、电压输出数模转换器 | RHB | 32 | -40 to 105 DA转换器 数模转换器
DAC7558IRHBTG4 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | QFN |
| 包装说明： | HVQCCN, LCC32,.2SQ,20 | 针数： | 32 |
| Reach Compliance Code： | compliant | Factory Lead Time： | 6 weeks |
| 风险等级： | 5.33 | 最大模拟输出电压： | 5.5 V |
| 最小模拟输出电压： | 转换器类型： | D/A CONVERTER | |
| 输入位码： | BINARY, 2'S COMPLEMENT BINARY | 输入格式： | SERIAL |
| JESD-30 代码： | S-PQCC-N32 | JESD-609代码： | e4 |
| 长度： | 5 mm | 最大线性误差 (EL)： | 0.0244% |
| 湿度敏感等级： | 2 | 位数： | 12 |
| 功能数量： | 1 | 端子数量： | 32 |
| 最高工作温度： | 105 °C | 最低工作温度： | -40 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | HVQCCN |
| 封装等效代码： | LCC32,.2SQ,20 | 封装形状： | SQUARE |
| 封装形式： | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 3/5 V | 认证状态： | Not Qualified |
| 采样速率： | 0.5 MHz | 座面最大高度： | 1 mm |
| 最大稳定时间： | 5 µs | 子类别： | Other Converters |
| 最大压摆率： | 1.8 mA | 标称供电电压： | 3 V |
| 表面贴装： | YES | 温度等级： | INDUSTRIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | NO LEAD |
| 端子节距： | 0.5 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 5 mm |
| Base Number Matches： | 1 |
DAC7558IRHBTG4 数据手册
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PDF下载DAC7558
www.ti.com
SLAS435–MAY 2005
12-BIT, OCTAL, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.7-V to 5.5-V Single Supply
The DAC7558 is a 12-bit, octal-channel, voltage
output DAC with exceptional linearity and
monotonicity. Its proprietary architecture minimizes
undesired transients such as code to code glitch and
channel to channel crosstalk. The low-power
DAC7558 operates from a single 2.7-V to 5.5-V
supply. The DAC7558 output amplifiers can drive a
2-kΩ, 200-pF load rail-to-rail with 5-µs settling time;
the output range is set using an external voltage
reference.
12-Bit Linearity and Monotonicity
Rail-to-Rail Voltage Output
Settling Time: 5 µs (Max)
Ultralow Glitch Energy: 0.1 nVs
Ultralow Crosstalk: –100 dB
Low Power: 1.8 mA (Max)
Per-Channel Power Down: 2 µA (Max)
Power-On Reset to Zero Scale and Mid Scale
SPI-Compatible Serial Interface: Up to 50 MHz
Simultaneous or Sequential Update
Asynchronous Clear
The 3-wire serial interface operates at clock rates up
to 50 MHz and is compatible with SPI, QSPI,
Microwire™, and DSP interface standards. The out-
puts of all DACs may be updated simultaneously or
sequentially. The parts incorporate a power-on-reset
circuit to ensure that the DAC outputs power up to
zero volts and remain there until a valid write cycle to
Binary and Twos-Complement Capability
Daisy-Chain Operation
the device takes place. The parts contain
a
1.8-V to 5.5-V Logic Compatibility
Specified Temperature Range: –40°C to 105°C
Small, 5-mm x 5-mm, 32-Lead QFN Package
power-down feature that reduces the current con-
sumption of the device to under 2 µA.
The small size and low-power operation makes the
DAC7558 ideally suited for battery-operated portable
applications. The power consumption is typically 7.5
mW at 5 V, 3.7 mW at 3 V, and reduces to 1 µW in
power-down mode.
APPLICATIONS
•
•
•
•
•
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
The DAC7558 is available in a 32-lead QFN package
and is specified over –40°C to 105°C.
Industrial Process Control
FUNCTIONAL BLOCK DIAGRAM
V
IOV
DD
VREF1
VREF2
DD
VFBA
−
+
V
A
OUT
String
DAC A
Input
Register
DAC
Register
SCLK
SYNC
Interface
Logic
VFBH
SDIN
SDO
−
+
V
H
OUT
String
DAC H
DAC
Register
Input
Register
Power-On
Reset
Power-Down
Logic
DCEN RST RSTSEL
AGND
DGND VREF3 VREF4
PD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Microwire is a trademark of National Semiconductor Corp..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
DAC7558
www.ti.com
SLAS435–MAY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT PACKAGE
DAC7558IRHBT
DAC7558IRHBR
250-piece Tape and
Reel
DAC7558
32 QFN
RHB
–40°C TO 105°C
D758
3000-piece Tape
and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VDD to GND
–0.3 V to 6 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD+ 0.3 V
–40°C to 105°C
–65°C to 150°C
150°C
Digital input voltage to GND
Vout to GND
Operating temperature range
Storage temperature range
Junction temperature (TJ Max)
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
DAC7558
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SLAS435–MAY 2005
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless
otherwise specified
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
±0.35
±0.08
Bits
LSB
Relative accuracy
Differential nonlinearity
Offset error
±1
±0.5
±12
Specified monotonic by design
LSB
mV
Zero-scale error
All zeroes loaded to DAC register
VDD = 5 V, VREF = 4.096 V
VDD = 5 V, VREF = 4.096 V
±12
mV
Gain error
±0.15
±0.5
%FSR
%FSR
µV/°C
ppm of FSR/°C
mV/V
Full-scale error
Zero-scale error drift
Gain temperature coefficient
PSRR
7
3
VDD = 5 V
0.75
OUTPUT CHARACTERISTICS(2)
Output voltage range
Output voltage settling time
Slew rate
0
VREF
5
V
µs
RL = 2 kΩ; 0 pF < CL < 200 pF
1.8
470
V/µs
pF
Capacitive load stability
RL = ∞
RL = 2 kΩ
1000
0.1
Digital-to-analog glitch impulse
Channel-to-channel crosstalk
1 LSB change around major carry
nV-s
dB
1-kHz full-scale sine wave,
outputs unloaded
–100
Digital feedthrough
0.1
nV-s
Output noise density (10-kHz offset
frequency)
120
nV/rtHz
Total harmonic distortion
FOUT = 1 kHz, FS = 1 MSPS, BW = 20
kHz
–85
dB
DC output impedance
Short-circuit current
1
50
20
15
Ω
VDD = 5 V
VDD = 3 V
mA
Power-up time
Coming out of power-down mode,
VDD = 5 V
µs
Coming out of power-down mode,
VDD = 3 V
15
REFERENCE INPUT
VREF Input range
0
VDD
V
Reference input impedance
Reference current
VREF1 through VREF4 shorted together
12.5
400
kΩ
µA
VREF = VDD = 5 V,
VREF1 through VREF4 shorted together
650
425
VREF = VDD = 3 V,
240
VREF1 through VREF4 shorted together
LOGIC INPUTS(2)
Input current
±1
µA
V
VIN_L, Input low voltage
VIN_H, Input high voltage
Pin capacitance
IOVDD ≥ 2.7 V
IOVDD ≥ 2.7 V
0.3 IOVDD
0.7 IOVDD
V
3
pF
(1) Linearity tested using a reduced code range of 30 to 4065; output unloaded.
(2) Specified by design and characterization, not production tested. For 1.8 V < IOVDD < 2.7 V, it is recommended that VIH = IOVDD , VIL
GND.
=
3
DAC7558
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SLAS435–MAY 2005
ELECTRICAL CHARACTERISTICS (Continued)
VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless
otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER REQUIREMENTS
(1)
VDD, IOVDD
2.7
5.5
IDD(normal operation)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (all power-down modes)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
DAC active and excluding load current
VIH = IOVDD and VIL = GND
1.1
1
1.8
1.7
mA
VIH = IOVDD and VIL = GND
0.2
2
2
µA
0.05
ILOAD = 2 mA, VDD = 5 V
93%
(1) IOVDD operates down to 1.8 V with slightly degraded timing, as long as VIH = IOVDD and VIL = GND.
4
DAC7558
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SLAS435–MAY 2005
TIMING CHARACTERISTICS(1)(2)
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified
PARAMETER
TEST CONDITIONS
VDD = 2.7 V to 3.6 V
MIN
20
20
10
10
10
10
4
TYP
MAX
UNITS
(3)
t1
t2
t3
t4
t5
t6
t7
t8
t9
SCLK cycle time
ns
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
SCLK HIGH time
SCLK LOW time
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNC falling edge to SCLK falling edge setup
time
4
5
Data setup time
5
4.5
4.5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC HIGH time
SCLK falling edge to SDO valid
CLR pulse width low
0
20
20
10
10
10
10
t10
(1) All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram Figure 1.
(3) Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
t
1
SCLK
t
2
t
8
t
3
t
7
t
4
SYNC
SDIN
t
t
6
5
D23
D22
D21
D19
D1
D0
D23
D20
D0
D0
Input Word n
Input Word n+1
D22
t
9
SDO
CLR
D23
Input Word n
Undefined
t
10
Figure 1. Serial Write Operation
5
DAC7558
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SLAS435–MAY 2005
PIN DESCRIPTION
RHB PACKAGE
(TOP VIEW)
24 23 22 21 20 19 18 17
VREF4
DCEN
PD
25
26
27
28
29
30
31
VREF3
SYNC
SCLK
SDIN
16
15
14
13
12
11
10
VDD
AGND
RSTSEL
RST
DGND
IOVDD
SDO
32
1
9
8
VREF1
VREF2
2
3
4
5
6
7
Terminal Functions
TERMINAL
DESCRIPTION
NO.
1
NAME
VFBA
DAC A amplifier sense input
2
VOUTA
VOUTB
VFBB
Analog output voltage from DAC A
Analog output voltage from DAC B
DAC B amplifier sense input
3
4
5
VFBC
DAC C amplifier sense input
6
VOUTC
VOUTD
VFBD
Analog output voltage from DAC C
Analog output voltage from DAC D
DAC D amplifier sense input
7
8
9
VREF2
SDO
Positive reference voltage input for DAC C and DAC D
Serial data output
10
11
12
13
14
15
IOVDD
DGND
SDIN
I/O voltage supply input
Digital ground
Serial data input
SCLK
Serial clock input
SYNC
Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out
to the DAC7558.
16
17
18
19
20
21
22
23
24
VREF3
VFBE
Positive reference voltage input for DAC E and DAC F
DAC E amplifier sense input
VOUTE
VOUTF
VFBF
Analog output voltage from DAC E
Analog output voltage from DAC F
DAC F amplifier sense input
VFBG
DAC G amplifier sense input
VOUTG
VOUTH
VFBH
Analog output voltage from DAC G
Analog output voltage from DAC H
DAC H amplifier sense input
6
DAC7558
www.ti.com
SLAS435–MAY 2005
PIN DESCRIPTION (continued)
Terminal Functions (continued)
25
26
27
28
29
30
31
VREF4
DCEN
PD
Positive reference voltage input for DAC G and DAC H
Daisy-chain enable
Power down
VDD
Analog voltage supply input
AGND
RSTSEL
RST
Analog ground
Reset select. If this pin is low, input coding is binary; if high, then 2s compliment.
Asynchronous reset. Active low. If RST pin is low, all DAC channels reset either to zero scale (RSTSEL = 0) or to
midscale (RSTSEL = 1).
32
VREF1
Positive reference voltage input for DAC A and DAC B
TYPICAL CHARACTERISTICS
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
0.5
0
1
Channel B
V
= 4.096 V
V
= 5 V
DD
Channel A
V
= 4.096 V
V
= 5 V
DD
REF
REF
0.5
0
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 2.
Figure 3.
7
DAC7558
www.ti.com
SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vsDIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs
DIGITAL INPUT CODE
1
1
0.5
0
Channel D
V
= 4.096 V
V
= 5 V
DD
Channel C
V
= 4.096 V
V
= 5 V
DD
REF
REF
0.5
0
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 4.
Figure 5.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
0.5
0
1
0.5
0
Channel F
V
= 4.096 V
V
= 5 V
DD
REF
Channel E
V
= 4.096 V
V
= 5 V
DD
REF
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 6.
Figure 7.
8
DAC7558
www.ti.com
SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
0.5
0
1
Channel G
V
= 4.096 V
V
= 5 V
DD
Channel H
V
= 4.096 V
V
= 5 V
DD
REF
REF
0.5
0
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 8.
Figure 9.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
0.5
0
1
0.5
0
Channel A
V
= 2.5 V
V
= 2.7 V
DD
REF
Channel B
V
= 2.5 V
V
= 2.7 V
DD
REF
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
Digital Input Code
2048
2560
3072
3584
4096
Digital Input Code
Figure 10.
Figure 11.
9
DAC7558
www.ti.com
SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
1
0.5
0
Channel D
V
= 2.5 V
V
= 2.7 V
DD
Channel C
V
= 2.5 V
V
= 2.7 V
DD
REF
REF
0.5
0
−0.5
−1
−0.5
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 12.
Figure 13.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
0.5
0
1
0.5
0
Channel E
V
= 2.5 V
V
= 2.7 V
DD
Channel F
V
= 2.5 V
V
= 2.7 V
DD
REF
REF
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 14.
Figure 15.
10
DAC7558
www.ti.com
SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
1
0.5
0
Channel G
V
= 2.5 V
V
= 2.7 V
DD
REF
Channel H
V
= 2.5 V
V
= 2.7 V
DD
REF
0.5
0
−0.5
−1
−0.5
−1
0.5
0.25
0
0.5
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 16.
Figure 17.
ZERO-SCALE ERROR
vs
FREE-AIR TEMPERATURE
ZERO-SCALE ERROR
vs
FREE-AIR TEMPERATURE
4
4
V
V
= 2.7 V,
DD
CHE
= 2.5 V
REF
V
V
= 5 V,
DD
CHE
= 4.096 V
REF
2
0
2
0
CHD
CHD
CHF
CHF
−2
−2
−4
CHA, B, C, G, H
CHA, B, C, G, H
50 80
−4
−40
−10
20
−40
−10
20
50
80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 18.
Figure 19.
11
DAC7558
www.ti.com
SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.1
0.1
0.05
0
V
V
= 5 V,
V
V
= 2.7 V,
DD
DD
= 4.096 V
= 2.5 V
REF
REF
0.05
CHE
CHA
CHD
0
−0.05
−0.1
CHD
−0.05
CHA, B, C, F, G, H
CH B, C, E, F, G, H
−0.1
−40
−10
20
50
80
−40
−10
20
50
80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 20.
Figure 21.
INTEGRAL LINEARITY ERROR
INTEGRAL LINEARITY ERROR
(MAXIMUM)
(MINIMUM)
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
0.5
0
1
0.5
0
V
= 5 V,
= 4.096 V
V
V
= 5 V,
DD
DD
V
REF
= 4.096 V
REF
CH A, B, C, D, E, F, G, H
CH A, B, C, D, E, F, G, H
−0.5
−1
−0.5
−1
−40
−10
20
50
80
−40
−10
20
50
80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 22.
Figure 23.
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DAC7558
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TYPICAL CHARACTERISTICS (continued)
SINK CURRENT AT NEGATIVE RAIL
SOURCE CURRENT AT POSITIVE RAIL
Typical for all Channels
0.2
5.50
5.40
Typical for all Channels
0.15
V
DD
= 2.7 V, V
= 2.5 V
REF
0.1
0.05
0
DAC Loaded With FFF
H
V
DD
= V
= 5.5 V
REF
5.30
5.20
V
DD
= 5.5 V, V
= 4.096 V
REF
DAC Loaded With 000
10
H
0
5
15
0
5
10
15
I
− Sink Current − mA
I
− Sink Current − mA
SINK
SOURCE
Figure 24.
Figure 25.
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
SOURCE CURRENT AT POSITIVE RAIL
1400
1200
1000
800
600
400
200
0
2.7
2.6
Typical for all Channels
V
DD
= 5.5 V, V
= 4.096 V
REF
V
DD
= 2.7 V, V
= 2.5 V
REF
2.5
2.4
DAC Loaded With FFF
H
V
DD
= V
= 2.7 V
REF
All Channels Powered, No Load
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
0
5
10
15
I
− Sink Current − mA
SOURCE
Figure 26.
Figure 27.
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DAC7558
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SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1600
1400
1200
1000
800
1600
All Channels Powered, No Load
All DACs Powered,
No Load,
= 2.5 V
1400
V
REF
V
DD
= 5.5 V, V
= 4.096 V
REF
1200
1000
800
600
400
200
0
V
DD
= 2.7 V, V
= 2.5 V
REF
600
400
All Channels Powered, No Load
20 50 80
2.7
3.1
3.4
V
3.8
4.1
4.5
4.8
5.2
5.5
−40
−10
110
− Supply Voltage − V
T
A
− Free-Air Temperature − 5C
DD
Figure 28.
Figure 29.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V
2200
1800
4000
3000
2000
1000
0
T
= 255C,
V
REF
= 5.5 V,
DD
A
SCL Input (All Other Inputs = GND)
V
= 4.096 V
V
DD
= 5.5 V, V
= 4.096 V
REF
1400
1000
600
V
= 2.7 V, V
3
= 2.5 V
4
DD
REF
200
0
1
2
5
600 700 800 900 10001100 1200 130014001500
V
LOGIC
− Logic Input Voltage − V
I
− Current Consumption − mA
DD
Figure 30.
Figure 31.
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DAC7558
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SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V
TOTAL ERROR - 5 V
0.005
0.0025
0
4000
V
REF
A
= 5 V,
V
V
= 2.7 V,
= 2.5 V
DD
DD
REF
V
T
= 4.096,
E
D
3500
3000
= 255C
2500
2000
1500
1000
A
−0.0025
−0.005
B, C, F, G, H
500
0
0
512 1024 1536 2048 2560 3072 3584 4095
Digital Input Code
600 700 800 900 10001100 1200 1300 1400 1500
I
− Current Consumption − mA
DD
Figure 32.
Figure 33.
TOTAL ERROR - 2.7 V
EXITING POWER-DOWN MODE
0.005
0.0025
0
5
4
3
2
1
0
V
V
= 5 V,
REF
Powerup to Code 4000
DD
V
REF
A
= 2.7 V,
E
DD
= 4.096 V,
V
T
= 2.5 V,
= 255C
D
A
−0.0025
B, C, F, G, H
−0.005
0
512 1024 1536 2048 2560 3072 3584 4095
Digital Input Code
t − Time − 4 ms/div
Figure 35.
Figure 34.
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DAC7558
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SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
LARGE-SIGNAL SETTLING TIME - 5 V
LARGE-SIGNAL SETTLING TIME - 2.7 V
3
2
5
4
3
2
1
0
V
= 2.5 V,
V
= 5 V,
DD
DD
Output Loaded
1
0
Output Loaded
With 200 pF to GND,
Code 41 to 4055
With 200 pF to GND,
Code 41 to 4055
t − Time − 5 ms/div
t − Time − 5 ms/div
Figure 36.
Figure 37.
MIDSCALE GLITCH
WORST-CASE GLITCH
V
DD
= 5 V, V
= 4.096 V
V
DD
= 5 V, V
= 4.096 V
REF
REF
Trigger Pulse
Trigger Pulse
t − Time − 400 nS/div
t − Time − 400 nS/div
Figure 38.
Figure 39.
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DAC7558
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SLAS435–MAY 2005
TYPICAL CHARACTERISTICS (continued)
CHANNEL-TO-CHANNEL CROSSTALK
FOR A FULL-SCALE SWING
DIGITAL FEEDTHROUGH ERROR
V
DD
= 5 V, V
= 4.096 V
V
DD
= 5 V, V
= 4.096 V
REF
REF
Trigger Pulse
Trigger Pulse
t − Time − 400 nS/div
t − Time − 400 nS/div
Figure 40.
Figure 41.
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
−40
−50
−60
−70
−80
−90
−100
V
= 5 V, V
= 4.096 V
DD
REF
− 1dB FSR Digital Input, Fs = 1 Msps
Measurement Bandwidth = 20 kHz
THD
2nd Harmonic
3rd Harmonic
0
1
2
3
4
5
6
7
8
9
10
Output Frequency − kHz
Figure 42.
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DAC7558
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SLAS435–MAY 2005
3-Wire Serial Interface
The DAC7558 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.
Table 1. Serial Interface Programming
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15–DB4
DB3–DB0
DESCRIPTION
A1
A0
LD1
0
LD0
0
SEL2 SEL1 SEL0 PWD
MSB–LSB Don't Care
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Data
Data
Data
Data
Data
Data
Data
Data
Data
X
X
X
X
X
X
X
X
X
Write to buffer A with data
Write to buffer B with data
Write to buffer C with data
Write to buffer D with data
Write to buffer E with data
Write to buffer F with data
Write to buffer G with data
Write to buffer H with data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(000, 001, 010, 011,
100, 101, 110, 111)
Write to buffer with data and load DAC
(selected by DB19, DB18, and DB17)
1
0
(000, 001, 010, 011,
100, 101, 110, 111)
0
Data
X
Write to buffer with data and load DAC
(selected by DB19, DB18, and DB17) and
load all other DACs with buffer data
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
Data
Data
Data
Data
Data
Data
Data
Data
X
X
X
X
X
X
X
X
Load DACs A and B with current buffer
data
(Both A1 and
A0 should be
set to zero for
normal device
operation.
DAC(s) do not
respond if any
other combi-
nation is used)
Load DACs A, B, C, and D with current
buffer data
Load DACs A, B, C, D, E, and F with
current buffer data
Load DACs A, B, C, D, E, F, G, and H
with current buffer data
Write to buffer with new data and load
DACs A and B simultaneously
Write to buffer with new data and load
DACs A, B, C, and D simultaneously
Write to buffer with new data and load
DACs A, B, C, D, E, and F simultaneously
Write to buffer with new data and load
DACs A, B, C, D, E, F, G, and H
simultaneously
Write to buffer and load DAC with
Power-Down command to individual chan-
nel (selected by DB19, DB18, and DB17)
(000, 001, 010, 011,
100, 101, 110, 111)
X
X
0
1
1
1
See Table 2
X
X
Write to buffer and load DACs with
Power-Down command to multiple chan-
nels (selected by DB19, DB18, and DB17)
(000, 001, 010, 011,
100, 101, 110, 111)
See Table 2
and Table 3
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DAC7558
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THEORY OF OPERATION
OUTPUT BUFFER AMPLIFIERS
D/A SECTION
The architecture of the DAC7558 consists of a string
DAC followed by an output buffer amplifier. Figure 43
shows a generalized block diagram of the DAC
architecture.
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, which gives an
output range of 0 V to VDD. It is capable of driving a
load of 2 kΩ in parallel with up to 1000 pF to GND.
The source and sink capabilities of the output ampli-
fier can be seen in the typical curves. The slew rate is
1 V/µs with a half-scale settling time of 3 µs with the
output unloaded.
V
REF
100 kW
100 kW
V
FB
50 kW
_
Ref +
V
OUT
DAC External Reference Input
+
Resistor String
DAC Register
Ref −
Four separate reference pins are provided for eight
DACs, providing maximum flexibility. VREF1 serves
DAC A and DAC B, VREF2 serves DAC C and DAC
D, VREF3 serves DAC E and DAC F, and VREF4
serves DAC G and DAC H. VREF1 through VREF4
can be externally shorted together for simplicity.
GND
Figure 43. Typical DAC Architecture
The input coding to the DAC7558 is unsigned binary,
which gives the ideal output voltage as:
It is recommended to use a buffered reference in the
external circuit (e.g., REF3140). The input impedance
is typically 50 kΩ for each reference input pin.
VOUT = VREF× D/4096
Where D = decimal equivalent of the binary code that
is loaded to the DAC register which can range from 0
to 4095.
Amplifier Sense Input
The DAC7558 contains eight amplifier feedback input
pins, VFBA ... VFBH. For voltage output operation,
VFBA ... VFBH must externally connect to VOUTA ...
VOUTH respectively. For better DC accuracy, these
connections should be made at load points. The
VFBA ... VFBH pins are also useful for a variety of
applications, including digitally controlled current
sources. Each feedback input pin is internally connec-
ted to the DAC amplifier's negative input terminal
through a 100-kΩ resistor; and, the amplifier's nega-
tive input terminal internally connects to ground
through another 100-kΩ resistor (See Figure 43). This
forms a gain-of-two, non-inverting amplifier configur-
ation. Overall gain remains one because the resistor
string has a divide-by-two configuration. The resist-
ance seen at each VFBx pin is approximately 200 kΩ
to ground.
To Output
Amplifier
V
REF
R
R
R
R
GND
Figure 44. Typical Resistor String
RESISTOR STRING
The resistor string section is shown in Figure 44. It is
simply a string of resistors, each of value R. The
DAC7558 uses eight separate resistor strings. Each
VREFx input pin provides the external reference
voltage for two resistor strings. A resistor string has
100 kΩ total resistance to ground, including a 50 kΩ
divide-by-two resistor. Since each VREFx pin con-
nects to two resistor strings, the resistance seen by
each VREFx pin is approximately 50 kΩ. The div-
ide-by-two function provided by the resistor string is
compensated by a gain-of-two amplifier configuration.
The voltage is tapped off by closing one of the
switches connecting the string to the amplifier. Be-
cause it is a string of resistors, it is specified
monotonic. The DAC7558 architecture uses eight
separate resistor strings to minimize chan-
nel-to-channel crosstalk.
Power-On Reset
On power up, all internal registers are cleared and all
channels are updated with zero-scale voltages. Until
valid data is written, all DAC outputs remain in this
state. This is particularly useful in applications where
it is important to know the state of the DAC outputs
while the device is powering up. In order not to turn
on ESD protection devices, VDD should be applied
before any other pin is brought high.
During power up, all digital input pins should be set at
logic-low voltages. Shortly after power up, if RSTSEL
pin is low, then all DAC outputs are at their
zero-scale voltages. If RSTSEL pin is brought high,
then all DAC outputs are at their mid-scale voltages.
19
DAC7558
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SLAS435–MAY 2005
Power Down
brought low. The RST signal resets all internal
registers, and therefore behaves like the Power-On
Reset. The DAC7558 updates at the first rising edge
of the SYNC signal that occurs after the RST pin is
brought back to high.
The DAC7558 has a flexible power-down capability
as described in Table 2 and Table 3. Individual
channels can be powered down separately, or mul-
tiple channels can be powered down simultaneously.
During a power-down condition, the user has flexi-
bility to select the output impedance of each channel.
If the PD pin is brought low, then all channels can
simultaneously be powered down, with the output at
high impedance state (High-Z).
If the RSTSEL pin is high, RST signal going low
resets all outputs to midscale. If the RSTSEL pin is
low, RST signal going low resets all outputs to
zero-scale.
Input Data Format Selection
The DAC7558 has DB16 as a power-down flag. If this
flag is set, then DB11 and DB10 select one of the
three power-down modes of the device as described
in Table 2.
DAC7558 can use unsigned binary (USB) or binary
twos complement (BTC) input data formats. Format
selection is done by the RSTSEL pin. If the RSTSEL
is kept low, the 12-bit input data is assumed to have
USB format, and any asynchronous clear operation
generates zero-scale outputs. If the RSTSEL pin is
kept high, the 12-bit input data is assumed to have
BTC format and any asynchronous clear operation
generates mid-scale outputs.
Table 2. DAC7558 Power-Down Modes
DB11
DB10
OPERATING MODE
PWD Hi-Z
0
0
1
1
0
1
0
1
PWD 1 kΩ
PWD 100 kΩ
PWD Hi-Z
SERIAL INTERFACE
The DAC7558 is controlled over a versatile 3-wire
serial interface, which operates at clock rates up to
50 MHz and is compatible with SPI, QSPI, Microwire,
and DSP interface standards.
The DAC7558 can also be powered down using the
PD pin. When the PD pins is brought low, all
channels simultaneously power down and all outputs
become high impedance. When the PD pin is brought
high, the device resumes its state before the power
down condition.
24-Bit Word and Input Shift Register
The input shift register is 24 bits wide. DAC data is
loaded into the device as a 24-bit word under the
control of a serial clock input, SCLK, as shown in the
Figure 1 timing diagram. The 24-bit word, illustrated
in Table 1, consists of 8 control bits, followed by 12
data bits and 4 don't care bits. Data format is straight
binary (RSTSEL pin = 0) or binary twos complement
(RSTSEL = 1), where the most significant DAC data
bit is DB15. Data is loaded MSB first (DB23) where
the first two bits (DB23 and DB22) should be set to
zero for DAC7558 to work. The DAC7558 does not
respond to any other combination other than 00.
DB21 and DB20 (LD1 and LD0) determine if the input
register, DAC register, or both are updated with shift
register input data. DB19, DB18, and DB17 (SEL2,
SEL1, and SEL0) bits select the desired DAC(s).
DB16 is the power-down bit. If DB16 = 0, then it is a
normal operation, if DB16 = 1, then DB11 and DB10
determine the power-down mode (Hi-Z, 1 kΩ, or 100
kΩ). DB20 bit also gives the user the option of
powering down either a single channel or multiple
channels at the same time. See Power Down section
for more details.
The DAC7558 also has an option to power down
individual channels, or multiple channels simul-
taneously selected by DB20. If DB20 = 0, then the
user can power down the selected individual chan-
nels. If DB20 = 1, then the user can power down the
multiple channels simultaneously as explained in
Table 3. Power-down mode is selected by DB11 and
DB10.
Table 3. DAC7558 Power-Down Modes for Multiple
Channels
DB19
DB18
DB17
OPERATING MODE
PWD Channel A-B
PWD Channel A-C
PWD Channel A-D
PWD Channel A-E
PWD Channel A-F
PWD Channel A-G
PWD Channel A-H
PWD Channel A-H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The SYNC input is a level-triggered input that acts as
a frame-synchronization signal and chip enable. Data
can only be transferred into the device while SYNC is
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC-to-SCLK
Asynchronous Clear
The DAC7558 output is asynchronously set to
zero-scale voltage immediately after the RST pin is
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DAC7558
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SLAS435–MAY 2005
falling-edge setup time, t4. After SYNC goes low,
serial data is shifted into the device's input shift
register on the falling edges of SCLK for 24 clock
pulses. Any data and clock pulses after the
twenty-fourth falling edge of SCLK are ignored. No
further serial data transfer occurs until SYNC is taken
high and low again.
edges are received (following a falling SYNC), the
data stream becomes complete, and SYNC can be
brought high to update n devices simultaneously.
SDO operation is specified at a maximum SCLK
speed of 10 MHz.
Daisy-chain operation is also possible between
octal-channel DAC7558, dual-channel DAC7552, and
single-channel DAC7551 devices. Dasy chaining en-
ables communication with any number of DAC chan-
nels using a single serial interface. As long as the
correct number of bits are shifted using a daisy-chain
setting, a rising edge of SYNC properly updates all
chips in the system. Following a rising edge of SYNC,
all devices on the daisy chain respond according to
the control bits they receive.
SYNC may be taken high after the falling edge of the
twenty-fourth SCLK pulse, observing the minimum
SCLK Loop falling-edge to SYNC rising-edge time, t7.
After the end of serial data transfer, data is automati-
cally transferred from the input shift register to the
input register of the selected DAC. If SYNC is taken
high before the twenty-fourth falling edge of SCLK,
the data transfer is aborted and the DAC input
registers are not updated.
IOVDD and Level Shifters
When DCEN is low, the SDO pin is brought to a Hi-Z
state. The first 24 data bits that follow the falling edge
of SYNC are stored in the shift register. The rising
edge of SYNC that follows the 24th data bit updates
the DAC(s). If SYNC is brought high before the 24th
data bit, no action occurs.
The DAC7558 can be used with different logic famil-
ies that require a wide range of supply voltages (from
1.8 V to 5.5 V). To enable this useful feature, the
IOVDD pin must be connected to the logic supply
voltage of the system. All DAC7558 digital input and
output pins are equipped with level-shifter circuits.
Level shifters at the input pins ensure that external
logic high voltages are translated to the internal logic
high voltage, with no additional power dissipation.
Similarly, the level shifter for the SDO pin translates
the internal logic high voltage (AVDD) to the external
logic high level (IOVDD). For single supply operation,
the IOVDD pin can be tied to the AVDD pin.
In daisy-chain mode (DCEN = 1) the DAC7558
requires a falling SCLK edge after the rising SYNC, in
order to initialize the serial interface for the next
update.
When DCEN is high, data can continuously be shifted
into the shift register, enabling the daisy-chain oper-
ation. The SDO pin becomes active and outputs
SDIN data with 24 clock-cycle delay. A rising edge of
SYNC loads the shift register data into the DAC(s).
The loaded data consists of the last 24 data bits
received into the shift register before the rising edge
of SYNC.
INTEGRAL AND DIFFERENTIAL LINEARITY
The DAC7558 uses precision thin-film resistors pro-
viding exceptional linearity and monotonicity. Integral
linearity error is typically within (+/-) 0.35 LSBs, and
differential linearity error is typically within (+/-) 0.08
LSBs.
If daisy-chain operation is not needed, DCEN should
permanently be tied to a logic-low voltage.
GLITCH ENERGY
Daisy-Chain Operation
The DAC7558 uses a proprietary architecture that
minimizes glitch energy. The code-to-code glitches
are so low, they are usually buried within the
wide-band noise and cannot be easily detected. The
DAC7558 glitch is typically well under 0.1 nV-s. Such
low glitch energy provides more than 10X improve-
ment over industry alternatives.
When the DCEN pin is brought high, daisy chaining is
enabled. Serial data output (SDO) pin is provided to
daisy-chain multiple DAC7558 devices in a system.
As long as SYNC is high or DCEN is low the SDO pin
is in a high-impedance state. When SYNC is brought
low the output of the internal shift register is tied to
the SDO pin. As long as SYNC is low and DCEN is
high, SDO duplicates the SDIN signal with 24-cycle
delay. To support multiple devices in a daisy-chain,
SCLK and SYNC signals are shared across all
devices and SDO of one DAC7558 should be tied to
the SDIN of the next DAC7558. For n devices in such
a daisy chain, 24n SCLK cycles are required to shift
the entire input data stream. After 24n SCLK falling
CHANNEL-TO-CHANNEL CROSSTALK
The DAC7558 architecture is designed to minimize
channel-to-channel crosstalk. The voltage change in
one channel does not affect the voltage output in
another channel. The DC crosstalk is in the order of a
few microvolts. AC crosstalk is also less than –100
dBs. This provides orders of magnitude improvement
over certain competing architectures.
21
DAC7558
www.ti.com
SLAS435–MAY 2005
APPLICATION INFORMATION
glitches can also slow the loop down. With its 1
MSPS (small-signal) maximum data update rate,
DAC7558 can support high-speed control loops.
Ultra-low glitch energy of the DAC7558 significantly
improves loop stability and loop settling time.
Waveform Generation
Due to its exceptional linearity, low glitch, and low
crosstalk, the DAC7558 is well suited for waveform
generation (from DC to 10 kHz). The DAC7558
large-signal settling time is 5 µs, supporting an
update rate of 200 KSPS. However, the update rates
can exceed 1 MSPS if the waveform to be generated
consists of small voltage steps between consecutive
DAC updates. To obtain a high dynamic range,
REF3140 (4.096 V) or REF02 (5.0 V) are rec-
ommended for reference voltage generation.
Generating Industrial Voltage Ranges:
For control loop applications, DAC gain and offset
errors are not important parameters. This could be
exploited to lower trim and calibration costs in a
high-voltage control circuit design. Using a quad
operational amplifier (OPA4130), and a voltage refer-
ence (REF3140), the DAC7558 can generate the
wide voltage swings required by the control loop.
Generating ±5-V, ±10-V, and ± 12-V Outputs For
Precision Industrial Control
V
tail
DAC7558
Industrial control applications can require multiple
feedback loops consisting of sensors, ADCs, MCUs,
DACs, and actuators. Loop accuracy and loop speed
are the two important parameters of such control
loops.
R1
REF3140
R2
V
ref
_
REFIN
V
OUT
V
dac
DAC7558
+
Loop Accuracy:
OPA4130
In a control loop, the ADC has to be accurate. Offset,
gain, and the integral linearity errors of the DAC are
not factors in determining the accuracy of the loop.
As long as a voltage exists in the transfer curve of a
monotonic DAC, the loop can find it and settle to it.
On the other hand, DAC resolution and differential
linearity do determine the loop accuracy, because
each DAC step determines the minimum incremental
change the loop can generate. A DNL error less than
–1 LSB (non-monotonicity) can create loop instability.
A DNL error greater than +1 LSB implies unnecess-
arily large voltage steps and missed voltage targets.
With high DNL errors, the loop looses its stability,
resolution, and accuracy. Offering 12-bit ensured
monotonicity and ± 0.08 LSB typical DNL error, 755X
DACs are great choices for precision control loops.
Figure 45. Low-cost, Wide-swing Voltage Gener-
ator for Control Loop Applications
The output voltage of the configuration is given by:
R2
R1
Din
4096
R2
R1
REFǒ ) 1Ǔ
V
+ V
* V
OUT
tail
(1)
Fixed R1 and R2 resistors can be used to coarsely
set the gain required in the first term of the equation.
Once R2 and R1 set the gain to include some
minimal over-range, four DAC7558 channels could be
used to precisely set the required offset voltages.
Residual errors are not an issue for loop accuracy
because offset and gain errors could be tolerated.
Four DAC7558 channels can provide the Vtail volt-
ages to minimize offset error, while the other four
DAC7558 channels provide Vdac voltages to gener-
ate four high-voltage outputs.
Loop Speed:
Many factors determine control loop speed. Typically,
the ADC's conversion time, and the MCU's compu-
tation time are the two major factors that dominate
the time constant of the loop. DAC settling time is
rarely a dominant factor because ADC conversion
times usually exceed DAC conversion times. DAC
offset, gain, and linearity errors can slow the loop
down only during the start-up. Once the loop reaches
its steady-state operation, these errors do not affect
loop speed any further. Depending on the ringing
characteristics of the loop's transfer function, DAC
For ±5-V operation: R1=10 kΩ, R2 = 15 kΩ, Vtail
3.33 V, VREF = 4.096 V
=
=
=
For ±10-V operation: R1=10 kΩ, R2 = 39 kΩ, Vtail
2.56 V, VREF = 4.096 V
For ±12-V operation: R1=10 kΩ, R2 = 49 kΩ, Vtail
2.45 V, VREF = 4.096 V
22
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
QFN
QFN
Drawing
DAC7558IRHBR
DAC7558IRHBT
ACTIVE
ACTIVE
RHB
32
32
3000
250
TBD
TBD
CU NIPDAU Level-2-235C-1 YEAR
CU NIPDAU Level-2-235C-1 YEAR
RHB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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DAC7558IRHBTG4 CAD模型
引脚图
封装焊盘图
DAC7558IRHBTG4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| DAC7558IRHBR | TI | 12-BIT, OCTAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | 类似代替 |
|
| DAC7558IRHBT | TI | 12-BIT, OCTAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | 类似代替 |
|
DAC7558IRHBTG4 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| DAC7562 | TI | DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT | 获取价格 |
|
| DAC7562-Q1 | TI | 具有 2.5V、4ppm/°C 基准的 12 位、双路、低功耗、超低毛刺脉冲、缓冲电压输出 DAC | 获取价格 |
|
| DAC7562SDGSR | TI | DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT | 获取价格 |
|
| DAC7562SDGST | TI | DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT | 获取价格 |
|
| DAC7562SDSCR | TI | DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT | 获取价格 |
|
| DAC7562SDSCT | TI | DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT | 获取价格 |
|
| DAC7562SQDGSRQ1 | TI | 具有 2.5V、4ppm/°C 基准的 12 位、双路、低功耗、超低毛刺脉冲、缓冲电压输出 DAC | DGS | 10 | -40 to 125 | 获取价格 |
|
| DAC7562T | TI | DAC7562T 双通道、12 位、低功耗、电压输出 DAC，具有 2.5V、4ppm/°C、内部基准电压和 5V TTL I/O | 获取价格 |
|
| DAC7562TDGSR | TI | DAC7562T 双通道、12 位、低功耗、电压输出 DAC，具有 2.5V、4ppm/°C、内部基准电压和 5V TTL I/O | DGS | 10 | -40 to 125 | 获取价格 |
|
| DAC7562TDGST | TI | DAC7562T 双通道、12 位、低功耗、电压输出 DAC，具有 2.5V、4ppm/°C、内部基准电压和 5V TTL I/O | DGS | 10 | -40 to 125 | 获取价格 |
|
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