DAC7641YB [TI]
16-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER;
| 型号： | DAC7641YB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总22页 (文件大小：1200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC7641
DAC7641
®
For most current data sheet and other product
information, visit www.burr-brown.com
16-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● LOW POWER: 2.5mW
DESCRIPTION
The DAC7641 is a 16-bit, voltage output digital-to-
analog converter (DAC) with guaranteed 15-bit mono-
tonic performance over the specified temperature range.
It accepts 16-bit parallel input data, has double-buffered
DAC input logic (allowing asynchronous update), and
provides a readback mode of the internal input registers.
Programmable asynchronous reset clears all registers to
a mid-scale code of 8000H or to a zero-scale of 0000H.
The DAC7641 can operate from a single +5V supply or
from +5V and –5V supplies.
● UNIPOLAR OR BIPOLAR OPERATION
● SETTLING TIME: 10µs to 0.003%
● 15-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
● DATA READBACK
● DOUBLE-BUFFERED DATA INPUTS
Low power and small size per DAC make the DAC7641
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-
loop servo-control. The DAC7641 is available in a
TQFP-32 package, and offers guaranteed specifica-
tions over the –40°C to +85°C temperature range.
APPLICATIONS
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
● DAC-PER-PIN PROGRAMMERS
VREF
L
VREFH
Sense
Sense
VREF
L
VREFH
VDD
VSS
VCC
16
I/O
Buffer
Input
Register
DAC
Register
DATA I/O
DAC
VOUT
VOUT Sense
CS
Control
Logic
R/W
DAC7641
AGND DGND
RST
RSTSEL
LDAC
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
• Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
•
© 2000 Burr-Brown Corporation
Printed in U.S.A. June, 2000
PDS-1532A
SBAS118
SPECIFICATIONS (Dual Supply)
At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted.
DAC7641Y
DAC7641YB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error
±3
±2
±4
±3
±2
±1
±3
±2
LSB
LSB
Bits
mV
ppm/°C
mV
Differential Linearity Error
Monotonicity, TMIN to TMAX
Bipolar Zero Error
Bipolar Zero Error Drift
Full-Scale Error
14
15
±1
5
±1
5
±3
10
±3
10
100
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
Full-Scale Error Drift
Power Supply Rejection Ratio (PSRR)
ppm/°C
ppm/V
At Full Scale
10
ANALOG OUTPUT
Voltage Output
Output Current
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
VREF = –2.5V, RL = 10kΩ, VSS = –5V
No Oscillation
VREF
–1.25
L
VREF
+1.25
H
✻
✻
✻
✻
V
mA
pF
500
–10, +30
Indefinite
✻
✻
✻
mA
GND or VCC or VSS
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
VREFL + 1.25
–2.5
+2.5
VREFH – 1.25
✻
✻
✻
✻
V
V
µA
µA
500
–500
✻
✻
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
Digital Feedthrough
Output Noise Voltage
DAC Glitch
To ±0.003%, 5V Output Step
8
2
60
40
10
✻
✻
✻
✻
✻
µs
nV-s
nV/√Hz
nV-s
f = 10kHz
7FFFH to 8000H or 8000H to 7FFFH
DIGITAL INPUT
VIH
VIL
IIH
0.7 • VDD
✻
✻
V
V
µA
µA
0.3 • VDD
±10
±10
✻
✻
✻
IIL
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.2mA
3.6
4.5
0.3
✻
✻
V
V
0.4
✻
POWER SUPPLY
VDD
VCC
VSS
ICC
IDD
ISS
+4.75
+4.75
–5.25
+5.0
+5.0
–5.0
0.4
15
–0.5
4
+5.25
+5.25
–4.75
0.5
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
mA
µA
mA
mW
–0.6
–40
–0.4
5.5
✻
✻
Power
✻
✻
TEMPERATURE RANGE
Specified Performance
+85
°C
✻ Specifications same as DAC7641Y.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
DAC7641
SPECIFICATIONS (Single Supply)
At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, unless otherwise noted.
DAC7641Y
DAC7641YB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error(1)
±3
±2
±4
±3
±2
±1
±3
±2
LSB
LSB
Bits
mV
ppm/°C
mV
Differential Linearity Error
Monotonicity, TMIN to TMAX
Zero Scale Error
Zero Scale Error Drift
Full-Scale Error
14
15
±1
5
±1
5
±3
10
±3
10
100
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
Full-Scale Error Drift
Power Supply Rejection Ratio (PSRR)
ppm/°C
ppm/V
At Full Scale
10
ANALOG OUTPUT
Voltage Output
Output Current
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
V
REFL = 0V, VSS = 0V, RL = 10kΩ
No Oscillation
0
VREF
+1.25
H
✻
✻
✻
✻
V
mA
pF
–1.25
500
±30
Indefinite
✻
✻
✻
mA
GND or VCC
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
VREFL + 1.25
0
+2.5
VREFH – 1.25
✻
✻
✻
✻
V
V
µA
µA
250
–250
✻
✻
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
Digital Feedthrough
Output Noise Voltage, f = 10kHz
DAC Glitch
To ±0.003%, 2.5V Output Step
8
2
60
40
10
✻
✻
✻
✻
✻
µs
nV-s
nV/√Hz
nV-s
7FFFH to 8000H or 8000H to 7FFFH
DIGITAL INPUT
VIH
VIL
IIH
0.7 • VDD
✻
✻
V
V
µA
µA
0.3 • VDD
±10
±10
✻
✻
✻
IIL
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.2mA
3.6
4.5
0.3
✻
✻
V
V
0.4
✻
POWER SUPPLY
VDD
VCC
VSS
ICC
IDD
Power
+4.75
+4.75
0
+5.0
+5.0
0
0.4
15
+5.25
+5.25
0
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
mA
µA
mW
0.5
1.8
2.5
✻
✻
TEMPERATURE RANGE
Specified Performance
–40
+85
✻
°C
✻ Specifications same as DAC7641Y.
NOTE: (1) If VSS = 0V specification applies at Code 0040H and above due to possible negative zero-scale error.
®
3
DAC7641
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
VSS to VSS ............................................................................. –0.3V to 11V
V
V
V
V
DD to GND .......................................................................... –0.3V to 5.5V
REFL to GND ............................................................ –0.3V to (VSS – VCC
REFH to GND ........................................................... –0.3V to (VSS – VCC
REFH to VREFL .................................................................... –0.3V to +11V
)
)
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DAC7641Y
±4
"
±3
"
±3
"
±2
"
TQFP-32
351
"
351
"
–40°C to +85°C
DAC7641Y/250
DAC7641Y/2K
DAC7641YB/250
DAC7641YB/2K
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
"
"
"
DAC7641YB
"
TQFP-32
"
–40°C to +85°C
"
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “DAC7641Y/2K” will get a single 2000-piece Tape and Reel.
®
4
DAC7641
PIN CONFIGURATION
DB15
DB14
DB13
DB12
DB11
DB10
DB9
1
2
3
4
5
6
7
8
24 VSS
23 VOUT Sense
22 VOUT
21 RSTSEL
20 RST
DAC7641
19 LDAC
18 R/W
DB8
17 CS
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
1
2
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CS
Data Bit 15, MSB
Data Bit 14
Data Bit 13
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
19
20
LDAC
RST
DAC Load Strobe, rising-edge triggered.
Reset,rising-edgetriggered.Dependingonthestate
of RSTSEL, the DAC registers are set to either mid-
scale or zero.
3
4
21
RSTSEL
Reset Select. Determines the action of RST. If
HIGH, a RST command will set the DAC registers to
mid-scale. IfLOW, aRSTcommandwillsettheDAC
registers to zero.
5
6
7
8
Data Bit 8
22
23
VOUT
DAC Voltage Output
9
Data Bit 7
V
OUT Sense
DAC Output Amplifier Inverting Input. Used to close
the feedback loop at the load.
10
11
12
13
14
15
16
17
18
Data Bit 6
24
VSS
AGND
VCC
Negative Power Supply
Data Bit 5
Data Bit 4
25
26
27
28
29
30
31
32
Analog Ground
Data Bit 3
Positive Power Supply
DAC Reference High Sense Input
DAC Reference High Input
DAC Reference Low Sense Input
DAC Reference Low Input
Digital Ground
Data Bit 2
V
REFH Sense
Data Bit 1
VREFH
Data Bit 0, LSB
V
REFL Sense
VREFL
Chip Select, active low.
R/W
EnabledbyCS,controlsdatareadandwritefromthe
input register.
DGND
VDD
Positive Power Supply
®
5
DAC7641
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
(+85°C)
3.0
2.0
3.0
2.0
1.0
1.0
0
0
–1.0
–2.0
–3.0
–1.0
–2.0
–3.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(–40°C)
ZERO-SCALE ERROR vs TEMPERATURE
2
3.0
2.0
1.0
Code (0040H)
1.5
1
0
–1.0
–2.0
–3.0
0.5
0
2.0
1.5
–0.5
–1
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–1.5
–2
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Digital Input Code
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
Code (FFFFH)
V
REFH CURRENT vs CODE
2
1.5
1
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.5
0
–0.5
–1
–1.5
–2
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Digital Input Code
®
6
DAC7641
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
VREFL CURRENT vs CODE
POWER SUPPLY CURRENT vs TEMPERATURE
1.0
0.8
0.00
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
Data = FFFFH
No Load
0.6
ICC
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Temperature (°C)
Digital Input Code
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +2.5V)
0.50
+5V
LDAC
0
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Large-Signal Settling Time: 0.5V/div
Small-Signal Settling Time: 4LSB/div
ICC
0000H 0200H 0400H 0800H 1000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Time (2µs/div)
Digital Input Code
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
OUTPUT VOLTAGE vs SETTLING TIME
(+2.5V to 2mV)
+5V
LDAC
0
+5V
LDAC
0
Small-Signal Settling Time: 4LSB/div
7FFFH to 8000H
Large-Signal Settling Time: 0.5V/div
Time (1µs/div)
Time (2µs/div)
®
7
DAC7641
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
BROADBAND NOISE
vs MIDSCALE GLITCH PERFORMANCE
+5V
LDAC
0
8000H to 7FFFH
BW = 10kHz
Code = 8000H
Time (1µs/div)
Time (10ms/div)
LOGIC SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DATA BITS
OUTPUT NOISE VOLTAGE vs FREQUENCY
12
10
8
1000
100
10
6
4
2
0
0
1
2
3
4
5
10
100
1000
10000
100000
1000000
Logic Input Level for Data Bits (V)
Frequency (Hz)
OUTPUT VOLTAGE vs RLOAD
5
4
3
2
1
0
Source
Sink
0.01
0.1
1
10
100
RLOAD (kΩ)
®
8
DAC7641
TYPICAL PERFORMANCE CURVES: VSS = –5V
At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+85°C)
3.0
2.0
3.0
2.0
1.0
1.0
0
0
–1.0
–2.0
–3.0
–1.0
–2.0
–3.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(–40°C)
VREFH CURRENT vs CODE
3.0
0.30
2.0
1.0
0
–1.0
–2.0
–3.0
0.25
0.20
0.15
0.10
0.05
0.00
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
ZERO-SCALE ERROR vs TEMPERATURE
(Code 8000H)
VREFL CURRENT vs CODE
0.00
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Digital Input Code
®
9
DAC7641
TYPICAL PERFORMANCE CURVES: VSS = –5V (Cont.)
At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFFH)
(Code 0000H)
2
1.5
1
2
1.5
1
0.5
0
0.5
0
–0.5
–1
–0.5
–1
–1.5
–2
–1.5
–2
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
POWER SUPPLY CURRENT
vs TEMPERATURE
OUTPUT VOLTAGE vs RLOAD
1.0
0.8
5
4
Data = FFFFH
No Load
0.6
Source
3
ICC
0.4
2
0.2
1
0.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–5
ISS
Sink
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
0.01
0.1
1
10
100
Temperature (°C)
RLOAD (kΩ)
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
OUTPUT VOLTAGE vs SETTLING TIME
(–2.5V to +2.5V)
+5V
LDAC
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Large-Signal Settling Time: 1V/div
Small-Signal Settling Time: 2LSB/div
ICC
0000H 0200H 0400H 0800H 1000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Time (2µs/div)
Digital Input Code
®
10
DAC7641
TYPICAL PERFORMANCE CURVES: VSS = –5V (Cont.)
At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE vs SETTLING TIME
(+2.5V to –2.5V)
+5V
LDAC
0
Small-Signal Settling Time:
2LSB/div
Large-Signal Settling Time: 1V/div
Time (2µs/div)
references VREFL and VREFH, respectively. The digital input
THEORY OF OPERATION
is a 16-bit parallel word and the DAC input register offers a
readback capability. The converters can be powered from
either a single +5V supply or a dual ±5V supply. The device
offers a reset function which immediately sets all DAC
output voltages and DAC registers to mid-scale code 8000H
or to zero-scale code 0000H. See Figures 2 and 3 for the
basic operation of the DAC7641.
The DAC7641 is a voltage output, 16-bit digital-to-analog
converter (DAC). The architecture is an R-2R ladder con-
figuration with the three MSBs segmented, followed by an
operational amplifier that serves as a buffer (see Figure 1).
The minimum voltage output (zero-scale) and maximum
voltage output (full-scale) are set by the external voltage
RF
VOUT Sense
VOUT
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREF
VREFH Sense
VREF
H
L
VREFL Sense
FIGURE 1. DAC7641 Architecture.
®
11
DAC7641
+5V
1µF
+
0.1µF
AGND
0V
+2.5000V
DGND
32 31 30 29 28 27 26 25
VDD
VREFL
VREFH
VCC
DGND
VREFL
Sense
VREFH
Sense
AGND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DB15
VSS
DB14
DB13
DB12
DB11
DB10
DB9
VOUT Sense
VOUT
0V to +2.5V
DAC7641
RSTSEL
RST
DAC RESET MODE SELECT
DAC RESET
LDAC
R/W
DAC LOAD STROBE
READ/WRITE STROBE
CHIP SELECT
DB8
CS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10 11 12 13 14 15 16
9
FIGURE 2. Single-Supply Operation.
+5V
1µF
+
1µF
+
0.1µF
0.1µF
–2.500V +2.500V
–5V
DGND
VDD
32 31 30 29 28 27 26 25
AGND
VREFL
VREFH
VCC
DGND
VREFH
Sense
AGND
VREFL
Sense
1
24
23
22
21
20
19
18
17
DB15
VSS
2
DB14
VOUT Sense
VOUT
3
DB13
–2.5V to +2.5V
4
DAC7641
DB12
RSTSEL
RST
DAC RESET MODE SELECT
DAC RESET
5
DB11
6
DB10
LDAC
R/W
DAC LOAD STROBE
READ/WRITE STROBE
CHIP SELECT
7
DB9
8
DB8
CS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10 11 12 13 14 15 16
9
FIGURE 3. Dual-Supply Operation.
®
12
DAC7641
ANALOG OUTPUTS
+V
When VSS = –5V (dual supply operation), the output ampli-
fier can swing to within 2.25V of the supply rails, guaran-
teed over the –40°C to +85°C temperature range. With VSS
= 0V (single-supply operation), and with RLOAD also con-
nected to ground, the output can swing to ground. Care must
be taken when measuring the zero-scale error with VSS = 0V.
Since the output voltage cannot swing below ground, the
output voltage may not change for the first few digital input
codes (0000H, 0001H, 0002H, etc.) if the output amplifier has
a negative offset. At the negative limit of –2mV, the first
specified output starts at code 0040H.
+2.5V
VSS
24
RW1
23
22
VOUT Sense
VOUT
VOUT
Due to the high accuracy of these D/A converters, system
design problems such as grounding and contact resistance
become very important. A 16-bit converter with a 2.5V full-
scale range has a 1LSB value of 38µV. With a load current
of 1mA, series wiring and connector resistance (see Figure
4) of only 40mΩ (RW2) will cause a voltage drop of 40µV.
To understand what this means in terms of a system layout,
the resistivity of a typical 1 ounce copper-clad printed circuit
board is 1/2 mΩ per square. For a 1mA load, a 10 milli-inch
wide printed circuit conductor 600 milli-inches long will
result in a voltage drop of 30µV.
RW2
DAC7641
FIGURE 4. Analog Output Closed-Loop Configuration. RW
represents wiring resistances.
connected to ground or must be in the range of –4.75V to
–5.25V. The voltage on VSS sets several bias points within
the converter. If VSS is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not guaranteed.
The DAC7641 offers a force and sense output configuration
for the high open-loop gain output amplifier. This feature
allows the loop around the output amplifier to be closed at the
load (see Figure 4), thus ensuring an accurate output voltage.
The current into the VREFH input and out of VREFL depends
on the DAC output voltages and can vary from a few
microamps to approximately 0.5mA. The reference input
appears as a varying load to the reference. If the reference
can sink or source the required current, a reference buffer is
not required. The DAC7641 features a reference drive and
sense connection such that the internal errors caused by the
changing reference current and the circuit impedances can
be minimized. Figures 5 through 13 show different reference
configurations and the effect on the linearity and differential
linearity.
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 2.5V and VCC – 2.5V provided that VREFH is
at least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
that VSS (the negative power supply) must either be
OPA2234
–2.5V
500pF
–V
+V
500pF
+2.5V
VSS
24
23
22
VOUT Sense
VOUT
VOUT
DAC7641
FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance Curves.
13
®
DAC7641
OPA2350
2200pF
2200pF
100Ω
100Ω
2kΩ
0.05V
1000pF
1000pF
+V
98kΩ
+2.5V
VSS
24
23
22
VOUT Sense
VOUT
VOUT
DAC7641
NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage
drops across the 100Ω resistor and the output stage of the buffer op amp.
FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 8. Integral Linearity and Differential Linearity
Error Curves for Figure 9.
FIGURE 7. Integral Linearity and Differential Linearity
Error Curves for Figure 6.
®
14
DAC7641
OPA2350
+V
+V
2200pF
100Ω
100Ω
+1.25V
+2.5V
1000pF
1000pF
2200pF
VSS
24
23
22
VOUT Sense
VOUT
VOUT
DAC7641
FIGURE 9. Single-Supply Buffered Reference with VREFL = +1.25V and VREFH = +2.5V.
+V
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
+2.5V
100Ω
OPA350
3.0
2.5
2.0
1.5
1.0
0.5
0
1000pF
2200pF
–0.5
–1.0
2.0
1.5
VSS
24
23
22
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
VOUT Sense
VOUT
VOUT
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DAC7641
Digital Input Code
FIGURE 10. Single-Supply Buffered VREFH.
FIGURE 11. Linearity and Differential Linearity Error Curves
for Figure 10.
®
15
DAC7641
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
+V
2.5
2.0
+2.5V
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VSS
24
23
22
2.0
1.5
1.0
VOUT Sense
VOUT
0.5
0
–0.5
–1.0
–1.5
–2.0
VOUT
DAC7641
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
FIGURE 12. Low Cost Single-Supply Configuration.
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
DIGITAL TIMING
DIGITAL INTERFACE
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7641.
Table I shows the basic control logic for the DAC7641. Note
that the internal register is edge triggered and not level
triggered. When the LDAC signal is transitioned to HIGH,
the digital word currently in the register is latched.
DIGITAL INPUT CODING
The DAC7641 input data is in Straight Binary format. The
output voltage is given by Equation 1.
The double-buffered architecture is designed so that the
DAC input register can be written to at any time.
V
REFH – VREFL • N
(
)
VOUT = VREFL +
(1)
INPUT
65,536
R/W
CS
RST RSTSEL LDAC REGISTER
REGISTER
MODE
L
H
X
X
X
X
L
L
H
H
X
X
H
H
H
H
↑
X
X
X
X
L
X
X
↑
H
X
X
Write
Read
Hold
Hold
Hold
Hold
Write
Write Input
Read Input
Update
Hold
Reset to Zero
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
Hold
Reset to Zero
Reset to Midscale Reset to Midscale
↑
H
TABLE I. DAC7641 Logic Truth Table.
®
16
DAC7641
tWCS
CS
tRCS
tWS
tWH
CS
R/W
tRDH
tRDS
tLH
R/W
tLS
tLWD
tLX
tDZ
±0.003% of FSR
LDAC
Data Out
Data Valid
tCSD
Error Band
tDH
tDS
Data In
tS
Data Read Timing
VOUT
Data Write Timing
±0.003% of FSR
Error Band
tSS
tSH
RSTSEL
tRSH
tRSS
RST
+FS
VOUT, RSTSEL LOW
–FS
+FS
MS
VOUT, RSTSEL HIGH
–FS
DAC7641 Reset Timing
FIGURE 14. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
CS LOW for Read
R/W HIGH to CS LOW
MIN
TYP
MAX
UNITS
tRCS
tRDS
tRDH
tDZ
tCSD
tWCS
tWS
tWH
tLS
tLH
tLX
tDS
tDH
tLWD
tSS
tSH
tRSS
tRSH
tS
150
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
10
100
150
100
40
0
R/W LOW to CS LOW
R/W LOW after CS HIGH
CS LOW to LDAC HIGH
CS LOW after LDAC HIGH
LDAC HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LDAC LOW
10
30
100
100
0
10
100
0
RSTSEL Valid Before RESET HIGH
RSTSEL Valid After RESET HIGH
RESET LOW Before RESET HIGH
RESET LOW After RESET HIGH
Settling Time
200
10
10
10
TABLE II. Timing Specifications (TA = –40°C to +85°C).
®
17
DAC7641
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
Figure 15 shows a DAC7641 in a 4mA to 20mA current
output configuration. The output current can be determined
by Equation 3:
The DAC7641 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7641 offers
both a differential reference input as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows transistor
to be placed within the loop to implement a digitally-
programmable, uni-directional current source. The availabil-
ity of a differential reference also allows programmability
for both the full-scale and zero-scale currents. The output
current is calculated as:
(3)
2.5V – 0.5V
N Value
65,536
0.5V
IOUT
=
•
+
125Ω
125Ω
At full-scale, the output current is 16mA plus the 4mA for
the zero current. At zero scale the output current is the offset
current of 4mA (0.5V/125Ω).
VREFH – VREF
RSENSE
L
N Value
65,536
(2)
IOUT
=
•
+ VREFL / RSENSE
(
)
OPA2350
2200pF
100Ω
20kΩ
+0.50v
1000pF
80kΩ
+V
100Ω
2200pF
+2.5V
1000pF
IOUT
VSS
24
23
22
VOUT Sense
VOUT
DAC7641
VPROGRAMMED
RSENSE
125Ω
FIGURE 15. 4-to-20mA Digitally Controlled Current Source.
®
18
DAC7641
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
PACKAGING INFORMATION
Orderable Device
DAC7641Y/250
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PBS
32
32
32
32
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
DAC7641Y/250G4
DAC7641YB/250
DAC7641YB/250G4
TQFP
TQFP
TQFP
PBS
PBS
PBS
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
DAC7641Y/250
DAC7641YB/250
TQFP
TQFP
PBS
PBS
32
32
250
250
177.8
177.8
16.4
16.4
7.2
7.2
7.2
7.2
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC7641Y/250
DAC7641YB/250
TQFP
TQFP
PBS
PBS
32
32
250
250
190.5
190.5
212.7
212.7
31.8
31.8
Pack Materials-Page 2
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