DAC7714U/1K [TI]
Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER; 四，串行输入， 12位电压输出数位类比转换器
| 型号： | DAC7714U/1K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总17页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC7714
DAC7714
®
Quad, Serial Input, 12-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 250mW (max)
The DAC7714 is a quad, serial input, 12-bit, voltage
output Digital-to-Analog Converter (DAC) with guar-
anteed 12-bit monotonic performance over the –40°C
to +85°C temperature range. An asynchronous reset
clears all registers to either mid-scale (800H) or zero-
scale (000H), selectable via the RESETSEL pin. The
device can be powered from a single +15V supply or
from dual +15V and –15V supplies.
● UNIPOLAR OR BIPOLAR OPERATION
● SETTLING TIME: 10µs to 0.012%
● 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● USER SELECTABLE RESET TO MID-
SCALE OR ZERO-SCALE
Low power and small size makes the DAC7714 ideal
for process control, data acquisition systems, and
closed-loop servo-control. The device is available in a
SO-16 package, and is guaranteed over the –40°C to
+85°C temperature range.
● SECOND-SOURCE for DAC8420
● SMALL SO-16 PACKAGE
APPLICATIONS
● ATE PIN ELECTRONICS
● PROCESS CONTROL
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
VCC
VREFH
GND
● DATA ACQUISITION SYSTEMS
DAC
DAC A
Register A
VOUTA
SDI
DAC
Register B
DAC B
DAC C
Serial-to-
Parallel
Shift
VOUTB
VOUTC
VOUTD
12
Register
DAC
Register C
CLK
CS
DAC
Select
DAC
Register D
DAC D
VREFL VSS
LOADDACS
RESET
RESETSEL
International Airport Industrial Park
Twx: 910-952-1111 • Cable: BBRCORP
http://www.burr-brown.com/
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
http://www.ti.com/
• Tel: (520) 746-1111
•
Telex: 066-6491
•
•
Copyright © 2000, Texas Instruments Incorporated
PDS-1533A
Printed in U.S.A. September, 2000
SBAS119
SPECIFICATIONS (Dual Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, unless otherwise noted.
DAC7714U
DAC7714UB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error
±2
±2
±1
±1
±1
±1
LSB(1)
LSB
Linearity Matching(2)
Differential Linearity Error
Monotonicity
LSB
TMIN to TMAX
Code = 000H
12
✻
Bits
Zero-Scale Error
±2
✻
LSB
Zero-Scale Drift
Zero-Scale Matching(2)
1
✻
✻
ppm/°C
LSB
±2
±2
±2
±1
✻
Full-Scale Error
Code = FFFH
At Full Scale
LSB
Full-Scale Matching(2)
Power Supply Sensitivity
±1
LSB
10
ppm/V
ANALOG OUTPUT
Voltage Output(3)
Output Current
VREFL
–5
VREFH
+5
✻
✻
✻
✻
V
mA
pF
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
No Oscillation
500
±20
✻
✻
✻
mA
To VSS, VCC, or GND
Indefinite
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
VREFL +1.25
–10
+10
✻
✻
✻
✻
V
V
VREFH – 1.25
Ref High Input Current
Ref Low Input Current
–0.5
–3.5
3.0
0
✻
✻
✻
✻
mA
mA
DYNAMIC PERFORMANCE
Settling Time
To ±0.012%, 20V Output Step
8
0.25
2
10
✻
✻
✻
✻
µs
LSB
Channel-to-Channel Crosstalk
Digital Feedthrough
Full-Scale Step
nV-s
Output Noise Voltage
f = 10kHz
65
✻
nV/√Hz
DIGITAL INPUT
Logic Levels
VIH
IIH ≤ ±10µA
IIL ≤ ±10µA
3.325
✻
V
V
VIL
1.575
✻
Data Format
Straight Binary
✻
POWER SUPPLY REQUIREMENTS
VCC
+14.25
–15.75
+15.75
–14.25
8.5
✻
✻
✻
✻
✻
V
V
VSS
ICC
6
✻
✻
✻
mA
mA
mW
ISS
–8
–6
✻
Power Dissipation
180
250
✻
TEMPERATURE RANGE
Specified Performance
–40
+85
✻
✻
°C
NOTES: (1) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within
the specified error band. (3) Ideal output voltage does not take into account zero or full-scale error.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
DAC7714
SPECIFICATIONS (Single Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = GND, VREFH = +10V, VREFL = 0V, unless otherwise noted.
DAC7714U
DAC7714UB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error(1)
±2
±2
±1
±1
±1
±1
LSB(2)
LSB
Linearity Matching(3)
Differential Linearity Error
Monotonicity
LSB
TMIN to TMAX
Code = 004H
12
✻
Bits
Zero-Scale Error
±4
✻
LSB
Zero-Scale Drift
Zero-Scale Matching(3)
2
✻
✻
ppm/°C
LSB
±4
±4
±4
±2
✻
Full-Scale Error
Code = FFFH
At Full Scale
LSB
Full-Scale Matching(3)
Power Supply Sensitivity
±2
LSB
20
ppm/V
ANALOG OUTPUT
Voltage Output(4)
Output Current
VREFL
–5
VREFH
+5
✻
✻
✻
V
mA
pF
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
No Oscillation
500
±20
✻
✻
✻
mA
To VCC or GND
Indefinite
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
VREFL +1.25
0
+10
✻
✻
✻
✻
V
V
VREFH – 1.25
Ref High Input Current
Ref Low Input Current
–0.3
–2.0
1.5
0
✻
✻
✻
✻
mA
mA
DYNAMIC PERFORMANCE
Settling Time(5)
To ±0.012%, 10V Output Step
8
0.25
2
10
✻
✻
✻
✻
µs
LSB
Channel-to-Channel Crosstalk
Digital Feedthrough
nV-s
Output Noise Voltage
f = 10kHz
65
✻
nV/√Hz
DIGITAL INPUT/OUTPUT
Logic Levels
VIH
IIH ≤ ±10µA
IIL ≤ ±10µA
3.325
✻
✻
✻
V
V
VIL
1.575
15.75
✻
Data Format
Straight Binary
✻
POWER SUPPLY REQUIREMENTS
VCC
14.25
–40
✻
✻
V
ICC
3.0
45
✻
✻
mA
mW
Power Dissipation
TEMPERATURE RANGE
Specified Performance
+85
✻
°C
NOTES: (1) If VSS = 0V, specification applies at code 004H and above. (2) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals 0V, then one
LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error.
(5) Full-scale positive 10V step and negative step from code FFFH to 020H.
®
3
DAC7714
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
VCC to VSS ........................................................................... –0.3V to +32V
DISCHARGE SENSITIVITY
V
V
V
V
V
V
CC to GND ......................................................................... –0.3V to +16V
SS to GND ......................................................................... +0.3V to –16V
REFH to GND ....................................................................... –9V to +11V
REFL to GND (VSS = –15V) ................................................. –11V to +9V
REFL to GND (VSS = 0V) .................................................... –0.3V to +9V
REFH to VREFL ....................................................................... –1V to +22V
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Digital Input Voltage to GND .............................................. –0.3V to 5.8V
Digital Output Voltage to GND ............................................ –0.3V to 5.8V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM
LINEARITY
ERROR
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
(LSB)
PACKAGE
DAC7714U
±2
"
±1
"
±1
"
±1
"
SO-16
211
"
211
"
–40°C to +85°C
DAC7714U
DAC7714U/1K
DAC7714UB
Rails
Tape and Reel
Rails
"
"
SO-16
"
"
DAC7714UB
–40°C to +85°C
"
"
DAC7714UB/1K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7714UB/1K” will get a single 1000-piece Tape and Reel.
ESD PROTECTION CIRCUITS
VCC
VCC
REFH
VOUT
REFL
VSS
VSS
Internal VDD
GND
Typical of Each
Logic Input Pin
®
4
DAC7714
PIN DESCRIPTIONS—U Package
PIN CONFIGURATION—U Package
PIN
LABEL
DESCRIPTION
Top View
SO
1
2
3
4
VCC
Positive Analog Supply Voltage, +15V nominal.
DAC D Voltage Output
VOUTD
VOUTC
VREFL
DAC C Voltage Output
Reference Input Voltage Low. Sets minimum
output voltage for all DACs.
5
VREFH
Reference Input Voltage High. Sets maximum
output voltage for all DACs.
VCC
VOUTD
VOUTC
VREFL
VREFH
VOUTB
VOUTA
VSS
1
2
3
4
5
6
7
8
16 RESETSEL
15 RESET
14 LOADDACS
13 NIC
6
7
8
VOUTB
VOUTA
VSS
DAC B Voltage Output
DAC A Voltage Output
Negative Analog Supply Voltage, 0V or –15V
nominal.
9
GND
SDI
Ground
DAC7714U
10
11
12
13
14
Serial Data Input
Serial Data Clock
Chip Select Input
Not Internally Connected
12 CS
CLK
11 CLK
CS
10 SDI
NIC
9
GND
LOADDACS
The selected DAC register becomes transparent
when LOADDACS is LOW. It is in the latched
state when LOADDACS is HIGH.
15
16
RESET
Asynchronous Reset Input. Sets all DAC
registers to either zero-scale (000H) or mid-
scale (800H) when LOW. RESETSEL determines
which code is active.
RESETSEL
When LOW, a LOW on RESET will cause all
DAC registers to be set to code 000H. When
RESETSEL is HIGH, a LOW on RESET will set
the registers to code 800H.
®
5
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
(Typical of Each Output Channel)
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
000H 200H
400H 600H
800H
A00H C00H
E00H FFFH
000H 200H
400H 600H
800H
A00H C00H
E00H FFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
ZERO-SCALE ERROR vs TEMPERATURE
(Code 004H)
(Typical of Each Output Channel)
2.0
1.5
0.5
0.4
0.3
0.2
0.1
DAC C
DAC A
0
1.0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0
0.5
0.4
–0.5
–1.0
–1.5
–2.0
DAC B
DAC D
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
000H 200H
400H 600H
800H
A00H C00H
E00H FFFH
Temperature (°C)
Digital Input Code
CURRENT vs CODE
All DACs Set to Indicated Code
FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
VREFH
2.0
1.5
1.2
1.0
0.8
0.6
0.4
0.2
0
DAC C
DAC B
1.0
0.5
–0.2
–0.4
DAC A
VREFL
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–0.5
–1.0
–1.5
–2.0
DAC D
000H 200H
400H 600H
800H
A00H C00H
E00H FFFH
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Digital Input Code
®
6
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
POSITIVE SUPPLY CURRENT
POWER SUPPLY CURRENT vs TEMPERATURE
vs DIGITAL INPUT CODE
4.5
3.5
6.00
5.00
4.00
3.00
2.00
1.00
0
No Load, All 4 DACs Set to Indicated Code
ICC
2.5
ICC
1.5
0.5
–0.5
000H 200H 400H 600H 800H A00H C00H E00H FFFH
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
Temperature (°C)
Digital Input Code
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to Code 020H)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
Large Signal
Settling Time: 5V/div
Large Signal
Settling Time: 5V/div
Small Signal
Small Signal
Settling Time: 1LSB/div
Settling Time: 1LSB/div
+5V
+5V
LOADDACS
0
LOADDACS
0
Time (2µs/div)
Time (2µs/div)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
MID-SCALE GLITCH PERFORMANCE
7FFH to 800H
800H to 7FFH
+5V
+5V
LOADDACS
0
LOADDACS
0
Time (1µs/div)
Time (1µs/div)
®
7
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT NOISE vs FREQUENCY
OUTPUT VOLTAGE vs RLOAD
1000
100
10
15
12
9
Code 020H
Source
6
Code FFFH
3
Sink
0
0
0.1
1
10
100
1000
10000
0.01
0.1
1
10
100
Frequency (kHz)
R
LOAD (kW)
SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE
Short to Ground
POWER SUPPLY REJECTION RATIO vs FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
20
15
10
5
+15V
0
–5
–10
–15
–20
Short to VCC
101
102
103
104
105
106
000H 200H 400H 600H 800H A00H C00H E00H FFFH
Frequency (Hz)
Digital Input Code
®
8
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
(Typical of Each Output Channel)
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
000H 200H
400H 600H
800H
A00H C00H
E00H FFFH
000H 200H
400H 600H
800H
A00H C00H
E00H FFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
CURRENT vs CODE
All DACs Set to Indicated Code
VREFH
(Typical of Each Output Channel)
0.5
0.4
2.5
2.0
1.5
1.0
0.5
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
VREFL
0.5
0.4
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H 200H
400H 600H
800H
A00H C00H E000H FFFH
000H 200H
400H 600H
800H
A00H C00H
E00H FFFH
Digital Input Code
Digital Input Code
BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE
(Code 800H)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
2.0
1.5
2.0
1.5
DAC C
1.0
1.0
DAC C
0.5
0.5
DAC B
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
DAC D
DAC A
DAC D
DAC B
DAC A
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
®
9
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
POWER SUPPLY CURRENT vs TEMPERATURE
(Code 000H)
8
6
2.0
1.5
ICC
DAC C
4
1.0
DAC A
2
0.5
0
0
–2
–4
–6
–8
–0.5
–1.0
–1.5
–2.0
DAC B
DAC D
ISS
Data = FFFH (all DACs)
No Load
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
OUTPUT VOLTAGE vs RLOAD
SUPPLY CURRENT vs CODE
8
6
15
ICC
10
5
Source
4
No Load, All 4 DACs Set to Indicated Code
2
0
0
–2
–4
–6
–8
–5
–10
–15
Sink
ISS
000H 200H 400H 600H 800H A00H C00H E00H FFFH
0.01
0.1
1
10
100
R
LOAD (kΩ)
Digital Input Code
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to –10V)
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
Large Signal
Settling Time: 5V/div
Large Signal
Settling Time: 5V/div
Small Signal
Settling Time: 0.5LSB/div
Small Signal
Settling Time: 0.5LSB/div
+5V
+5V
LOADDACS
0
LOADDACS
0
Time (2µs/div)
Time (2µs/div)
®
10
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
DUAL SUPPLY CURRENT LIMIT vs INPUT CODE
POWER SUPPLY REJECTION RATIO vs FREQUENCY
SHORT TO GROUND
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
20
15
10
5
–15V
0
+15V
–5
–10
–15
–20
101
102
103
104
105
106
000H 200H 400H 600H 800H A00H C00H E00H FFFH
Frequency (Hz)
Digital Input Code
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
BROADBAND NOISE
7FFH to 800H
800H to 7FFH
+5V
LOADDACS
0
Time (1ms/div)
Time (1µs/div)
OUTPUT NOISE vs FREQUENCY
1000
100
Noise at any code
10
0
0.1
1
10
100
1000
10000
Frequency (kHz)
®
11
DAC7714
At the negative offset limit of –4LSB (–9.76mV), for the
single-supply case, the first specified output starts at code
004H.
THEORY OF OPERATION
The DAC7714 is a quad, serial input, 12-bit, voltage output
DAC. The architecture is a classic R-2R ladder configura-
tion followed by an operational amplifier that serves as a
buffer. Each DAC has its own R-2R ladder network and
output op amp, but all share the reference voltage inputs, as
shown in Figure 1. The minimum voltage output (“zero-
scale”) and maximum voltage output (“full-scale”) are set by
external voltage references (VREFL and VREFH, respectively).
The digital input is a 16-bit serial word that contains the
12-bit DAC code and a 2-bit address code that selects one of
the four DACs (the two remaining bits are unused). The
converter can be powered from a single +15V supply or a
dual ±15V supply. Each device offers a reset function which
immediately sets all DAC output voltages and internal
registers to either zero-scale (code 000H) or mid-scale (code
800H). The reset code is selected by the state of the
RESETSEL pin (LOW = 000H, HIGH = 800H). Figures 2
and 3 show the basic operation of the DAC7714.
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 4V and VCC – 4V provided that VREFH is at
least 1.25V greater than VREFL. The minimum output of
each D/A is equal to VREFL – 1LSB plus a small offset
voltage (essentially, the offset of the output op amp). The
maximum output is equal to VREFH plus a similar offset
voltage. Note that VSS (the negative power supply) must
either be connected to ground or must be in the range of
–14.75V to –15.75V. The voltage on VSS sets several bias
points within the converter. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 3mA. The reference input appears as a vary-
ing load to the reference. If the reference can sink or source
the required current, a reference buffer is not required. See
“Reference Current vs Code” in the Typical Performance
Curves.
ANALOG OUTPUTS
When VSS = –15V (dual supply operation), the output
amplifier can swing to within 4V of the supply rails, over the
–40°C to +85°C temperature range. With VSS = 0V (single-
supply operation), the output can swing to ground. Note that
the settling time of the output op amp will be longer with
voltages very near ground. Care must also be taken when
measuring the zero-scale error when VSS = 0V. If the output
amplifier has a negative offset, the output voltage may not
change for the first few digital input codes (000H, 001H,
002H, etc.) since the output voltage cannot swing below
ground.
The analog supplies must come up before the reference
power supplies, if they are separate. If the power supplies for
the references come up first, then the VCC and VSS supplies
will be powered from the reference via the ESD protection
diodes (see page 4).
RF
VOUT
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREFH
VREFL
FIGURE 1. DAC7714 Architecture.
®
12
DAC7714
+15V
+
DAC7714
1µF to 10µF
0.1µF
0.1µF
1
2
3
4
5
6
7
8
VCC
RESETSEL 16
Reset DACs(1)
VOUTD
VOUTC
VREFL
VREFH
VOUTB
VOUTA
VSS
RESET 15
LOADDACS 14
NIC 13
0V to +10.0V
0V to +10.0V
Update Selected Register
+10.000V
Chip Select
Clock
CS 12
CLK 11
0V to +10.0V
0V to +10.0V
Serial Data In
SDI 10
GND
9
NOTE: (1) As configured, RESET LOW sets all internal registers to code 000H (0V).
If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (5V).
FIGURE 2. Basic Single-Supply Operation of the DAC7714.
DAC7714
+15V
+
1µF to 10µF
0.1µF
+5V
1
2
3
4
5
6
7
8
VCC
RESETSEL 16
Reset DACs(1)
VOUTD
VOUTC
VREFL
VREFH
VOUTB
VOUTA
VSS
RESET 15
LOADDACS 14
NIC 13
–10V to +10V
–10V to +10V
Update Selected Register
–10.0V
0.1µF
0.1µF
Chip Select
Clock
CS 12
+10.0V
CLK 11
Serial Data In
SDI 10
–10V to +10V
–10V to +10V
GND
9
–15V
1µF to 10µF
0.1µF
+
NOTE: (1) As configured, RESET LOW sets all internal registers to code 800H (0V).
If RESETSEL is LOW, RESET LOW sets all internal registers to code 000H (–10V).
FIGURE 3. Basic Dual-Supply Operation of the DAC7714.
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter-
nal to the DAC7714 (see the block diagram on the front of
this data sheet). These two inputs are completely inter-
changeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong DAC.
DIGITAL INTERFACE
Figure 4 and Table I provide the basic timing for the
DAC7714. The interface consists of a serial clock (CLK),
serial data (SDI), and a load DAC signal (LOADDACS). In
addition, a chip select (CS) input is available to enable serial
communication when there are multiple serial devices. An
asynchronous reset input (RESET) is provided to simplify
start-up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface (see Figure 4). The first two bits select the DAC
register that will be updated when LOADDACS goes LOW
(see Table II). The next two bits are not used. The last 12 bits
is the DAC code which is provided, most significant bit first.
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
®
13
DAC7714
(MSB)
D11
(LSB)
D0
SDI
A1
A0
X
X
D10
D9
D3
D2
D1
CLK
CS
tCSH
t
css
tLD2
tLD1
LOADDACS
tLDDW
tDS
tDH
SDI
tCL
tCH
CLK
tLDDW
LOADDACS
VOUT
tS
tS
1 LSB
ERROR BAND
1 LSB
ERROR BAND
tRSTW
RESET
tRSSH
RESETSEL
FIGURE 4. DAC7714 Timing.
SYMBOL
DESCRIPTION
MIN
TYP MAX UNITS
STATE OF
SELECTED
DAC
SELECTED
DAC
REGISTER
tDS
Data Valid to CLK Rising
25
20
30
50
55
15
40
15
45
25
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tDH
Data Held Valid after CLK Rises
CLK HIGH
A1
A0
LOADDACS RESET
REGISTER
tCH
L(1)
L
L
H
L
L
L
H(2)
H
A
B
Transparent
Transparent
Transparent
Transparent
(All Latched)
Reset(4)
tCL
CLK LOW
tCSS
tCSH
tLD1
tLD2
tLDDW
tRSSH
tRSTW
tS
CS LOW to CLK Rising
CLK HIGH to CS Rising
LOADDACS HIGH to CLK Rising
CLK Rising to LOADDACS LOW
LOADDACS LOW Time
RESETSEL Valid to RESET LOW
RESET LOW Time
H
L
H
C
H
X(3)
H
X
X
L
H
D
H
X
H
NONE
ALL
X
L
NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care.
(4) Resets to either 000H or 800H, per the RESETSEL state
(LOW = 000H, HIGH = 800H). When RESET rises, all registers that are in
their latched state retain the reset value.
Settling Time
TABLE I. Timing Specifications (TA = –40°C to +85°C).
TABLE II. Control Logic Truth Table.
®
14
DAC7714
CS(1)
CLK(1) LOADDACS RESET
SERIAL SHIFT REGISTER
LAYOUT
H(2)
L(4)
L
X(3)
L
H
H
H
H
No Change
No Change
A precision analog component requires careful layout, ad-
equate bypassing, and clean, well-regulated power supplies.
As the DAC7714 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to achieve good
performance from the converter.
(5)
↑
H
H
Advanced One Bit
Advanced One Bit
No Change
↑
L
X
X
H
H
H(6)
H(6)
L(7)
H
H
L(8)
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LOADDACS is LOW, the selected DAC register will change as
the shift register bits “flow” through A1 and A0. This will corrupt the data in
each DAC register that has been erroneously selected. (8) RESET LOW
causes no change in the contents of the serial shift register.
Because the DAC7714 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through the GND pin. Ideally, GND would be con-
nected directly to an analog ground plane. This plane would
be separate from the ground connection for the digital
components until they were connected at the power entry
point of the system.
TABLE III. Serial Shift Register Truth Table.
The power applied to VCC (as well as VSS, if not grounded)
should be well regulated and low noise. Switching power
supplies and DC/DC converters will often have high-fre-
quency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-fre-
quency spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage through
various paths between the power connections and analog
output.
Digital Input Coding
The DAC7714 input data is in Straight Binary format. The
output voltage is given by the following equation:
(VREFH – VREFL ) • N
VOUT = VREFL
+
4096
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
®
15
DAC7714
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
DAC7714U
DAC7714U/1K
DAC7714UB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
48
1000
48
DAC7714UB/1K
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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相关型号：
DAC7714UG4
Quad, Serial Input, 12-Bit, Voltage Output Digital-To-Analog Converter 16-SOIC -40 to 85
TI
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