DAC7734 [TI]
16 位四路电压输出串行输入数模转换器;
| 型号： | DAC7734 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 位四路电压输出串行输入数模转换器 转换器 数模转换器 |
| 文件： | 总30页 (文件大小：1302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC7734
D
A
C
7
7
3
4
www.ti.com
SBAS138A – DECEMBER 1999 – REVISED OCTOBER 2008
16-Bit, Quad Voltage Output, Serial Input
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
FEATURES
The DAC7734 is a 16-bit, quad voltage output, digital-to-
analog converter (DAC) with ensured 16-bit monotonic
performance over the specified temperature range. It accepts
24-bit serial input data, has double-buffered DAC input logic
(allowing simultaneous update of all DACs), and provides a
serial data output for daisy-chaining multiple DACs.
Programmable asynchronous reset clears all registers to a
mid-scale code of 8000h or to a zero-scale of 0000h. The
DAC7734 can operate from a single +15V supply or from
+15V and –15V, and +5V supplies.
ꢀ LOW POWER: 200mW
ꢀ UNIPOLAR OR BIPOLAR OPERATION
ꢀ SINGLE SUPPLY OUTPUT RANGE: +10V
ꢀ DUAL SUPPLY OUTPUT RANGE: ±10V
ꢀꢀSETTLING TIME: 10µs to 0.003%
ꢀ 16-BIT MONOTONICITY: –40°C to +85°C
ꢀ PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
ꢀ DOUBLE-BUFFERED DATA INPUTS
ꢀ ±1 LSB DNL: –40°C to +85°C
Low power and small size per DAC make the DAC7734
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-loop
servo-control. The DAC7734 is available in a 48-lead
SSOP package and offers ensured specifications over the
–40°C to +85°C temperature range.
APPLICATIONS
ꢀ PROCESS CONTROL
ꢀ ATE PIN ELECTRONICS
ꢀ CLOSED-LOOP SERVO-CONTROL
ꢀꢀMOTOR CONTROL
ꢀꢀDATA ACQUISITION SYSTEMS
ꢀꢀDAC-PER-PIN PROGRAMMERS
VREF
L
VREF
H
AB Sense
AB Sense
VREFL AB VREFH AB
VDD
VSS
VCC
DAC7734
SDI
Input
Register A
DAC
Register A
DAC A
Shift
VOUT
A
A
Register
SDO
VOUT
Sense
Sense
Sense
Sense
Input
Register B
DAC
Register B
DAC B
DAC C
DAC D
VOUT
B
B
VOUT
Input
Register C
DAC
Register C
CS
CLOCK
RST
VOUT
C
C
Control
Logic
VOUT
RESTSEL
LDAC
Input
Register D
DAC
Register D
VOUT
D
D
LOAD
VOUT
VREFL CD VREFH CD
VREF
L
VREF
H
AGND
DGND
CD Sense
CD Sense
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999-2008, Texas Instruments Incorporated
www.ti.com
SPECIFICATIONS (Dual Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, and VREFL = –10V, unless otherwise noted.
DAC7734E
TYP
DAC7734EB
TYP
DAC7734EC
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error (INL)
TMIN to TMAX
T = 25°C
±3
±4
ꢀ
ꢀ
±2
±3
LSB
LSB
Linearity Match
±4
ꢀ
±2
LSB
Differential Linearity Error (DNL)
T = 25°C
±3
±3
±2
±2
±1
±1
LSB
LSB
T
MIN to TMAX
Monotonicity, TMIN to TMAX
Bipolar Zero Error
Bipolar Zero Error, TMIN to TMAX
Full-Scale Error
Full-Scale Error, TMIN to TMAX
Bipolar Zero Matching
14
15
16
Bits
T = 25°C
T = 25°C
±0.01
±0.025
±0.05
±0.025
±0.05
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
Channel-to-Channel
Matching
±0.024
Full-Scale Matching
Channel-to-Channel
Matching
±0.024
ꢀ
ꢀ
ꢀ
ꢀ
% of FSR
ppm/V
Power Supply Rejection Ratio (PSRR)
At Full Scale
25
ANALOG OUTPUT
Voltage Output
Output Current
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
VREF
±5
L
VREF
H
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
mA
pF
500
±20
Indefinite
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
mA
To VSS, VCC or GND
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
VREFL + 1.25
–10
–0.3
+10
VREFH – 1.25
2.6
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
mA
mA
ꢀ
ꢀ
ꢀ
ꢀ
Ref Low Input Current
–3.2
–0.3
DYNAMIC PERFORMANCE
Settling Time
To ±0.003%, 20V
Output Step
9
11
ꢀ
ꢀ
ꢀ
ꢀ
µs
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
See Figure 5
0.5
2
60
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
LSB
nV-s
nV/√Hz
f = 10kHz
DIGITAL INPUT
VIH
VIL
IIH
0.7 • VDD
VDD
0.3 • VDD
±10
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
0
ꢀ
ꢀ
ꢀ
IIL
±10
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.6mA
3.6
4.5
0.3
ꢀ
ꢀ
ꢀ
ꢀ
V
V
0.4
ꢀ
ꢀ
POWER SUPPLY
VDD
VCC
VSS
IDD
ICC
ISS
+4.75
+14.25
–14.25
+5.0
+15.0
–15.0
50
6
–5
+5.25
+15.75
–15.75
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
µA
mA
mA
mW
Power
170
200
+85
TEMPERATURE RANGE
Specified Performance
–40
ꢀ
ꢀ
ꢀ
ꢀ
°C
ꢀ Specifications same as grade to the left.
DAC7734
2
SBAS138A
www.ti.com
SPECIFICATIONS (Single Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, and VREFL = +50mV, unless otherwise noted.
DAC7734E
TYP
DAC7734EB
TYP
DAC7734EC
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error(1) (INL)
T = 25°C
±3
±4
ꢀ
ꢀ
±2
±3
LSB
LSB
T
MIN to TMAX
Linearity Match
±4
ꢀ
±2
LSB
Differential Linearity Error (DNL)
T = 25°C
±3
±3
±2
±2
±1
±1
LSB
LSB
T
MIN to TMAX
Monotonicity, TMIN to TMAX
Unipolar Zero
Unipolar Zero Error, TMIN to TMAX
Full-Scale Error
Full-Scale Error, TMIN to TMAX
Unipolar Zero Matching
14
15
16
Bits
T = 25°C
T = 25°C
±0.01
±0.025
±0.05
±0.025
±0.05
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
Channel-to-Channel
Matching
±0.024
Full-Scale Matching
Channel-to-Channel
Matching
±0.024
ꢀ
ꢀ
ꢀ
ꢀ
% of FSR
ppm/V
Power Supply Rejection Ratio (PSRR)
At Full Scale
25
ANALOG OUTPUT
Voltage Output
VREFL = 0V, VSS = 0V
0
VREF
H
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
R = 10kΩ
Output Current
±5
mA
pF
mA
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
500
±20
Indefinite
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
To VCC or GND
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
VREFL + 1.25
0
–0.3
–1.5
+10
VREFH – 1.25
1.0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
mA
mA
ꢀ
ꢀ
ꢀ
ꢀ
Ref Low Input Current
–0.3
DYNAMIC PERFORMANCE
Settling Time
To ±0.003%, 10V
Output Step
8
10
ꢀ
ꢀ
ꢀ
ꢀ
µs
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
See Figure 6
0.5
2
60
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
LSB
nV-s
nV/√Hz
f = 10kHz
DIGITAL INPUT
VIH
VIL
IIH
0.7 • VDD
VDD
0.3 • VDD
±10
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
0
ꢀ
ꢀ
ꢀ
IIL
±10
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.6mA
3.6
4.5
0.3
ꢀ
ꢀ
ꢀ
ꢀ
V
V
0.4
ꢀ
ꢀ
POWER SUPPLY
VDD
VCC
VSS
IDD
ICC
Power
+4.75
+14.25
+5.0
+15.0
0
50
3.5
50
+5.25
+15.75
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
µA
mA
mW
70
TEMPERATURE RANGE
Specified Performance
–40
+85
ꢀ
ꢀ
ꢀ
ꢀ
°C
ꢀ Specifications same as grade to the left.
NOTE: (1) If VSS = 0V, the specification applies at code 0021H and above, due to possible negative zero scale error.
DAC7734
SBAS138A
3
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
VCC to VSS ........................................................................... –0.3V to +32V
V
V
CC to AGND ...................................................................... –0.3V to +16V
SS to AGND ...................................................................... +0.3V to –16V
AGND to DGND ................................................................. –0.3V to +0.3V
V
V
V
V
REFH to AGND ..................................................................... –9V to +11V
REFL to AGND ...................................................................... –11V to +9V
DD to GND ........................................................................... –0.3V to +6V
REFH to VREFL ........................................................................ –1V to 22V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION(1)
LINEARITY
ERROR
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE
DAC7734E
±4
±3
SSOP-48
333
–40°C to +85°C
DAC7734E
Rails, 30
"
"
"
"
"
"
DAC7734E/1K
Tape and Reel, 1000
DAC7734EB
±4
±2
SSOP-48
333
–40°C to +85°C
DAC7734EB
Rails, 30
"
"
"
"
"
"
DAC7734EB/1K
Tape and Reel, 1000
DAC7734EC
±3
±1
SSOP-48
333
–40°C to +85°C
DAC7734EC
Rails, 30
"
"
"
"
"
"
DAC7734EC/1K
Tape and Reel, 1000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
ESD PROTECTION CIRCUITS
VCC
VCC
VOUT Sense
RefH
RefH Sense
VOUT
AGND
RefL Sense
RefL
VSS
VSS
1 of 2
1 of 4
VDD
VDD
Typ of Each
Logic Input Pin
DGND
DGND
SDO
DAC7734
4
SBAS138A
www.ti.com
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
Top View
SSOP
1
2
3
4
5
6
7
NC
NC
No Connection
No Connection
Serial Data Input
Digital Ground
Data Clock Input
Digital Ground
NC
NC
1
2
3
4
5
6
7
8
9
48 VOUTA Sense
47 VOUT
SDI
A
DGND
CLK
SDI
46 AGND
45 VSS
DGND
LDAC
DGND
CLK
DAC Register Load Control, Rising Edge
Triggered
44 VREFL AB Sense
43 VREFL AB
8
DGND
LOAD
DGND
CS
Digital Ground
DGND
LDAC
DGND
LOAD
9
DAC Input Register Load Control, Active Low
Digital Ground
10
11
12
13
14
15
42
41 VREFH AB Sense
40
OUTB Sense
39 VOUT
38 VOUTC Sense
VREFH AB
Chip Select, Active Low
Digital Ground
DGND
SDO
Serial Data Output
V
DGND
RSTSEL
Digital Ground
DGND 10
CS 11
B
Reset Select. Determines the action of RST. If
HIGH, a RST common will set the DAC registers
to mid-scale (8000H). If LOW, a RST command
will set the DAC registers to zero (0000H).
DGND 12
SDO 13
DGND 14
RSTSEL 15
DGND 16
RST 17
37
36
V
V
OUTC
DAC7734
16
17
DGND
RST
Digital Ground
REFH CD Sense
Reset, Rising Edge Triggered. Depending on the
state of RSTSEL, the DAC registers are set to
either mid-scale or zero.
35 VREFH CD
34
33
V
V
REFL CD
18
19
20
21
22
23
24
DGND
NC
Digital Ground
No Connection
REFL CD Sense
NC
No Connection
32 VOUTD Sense
DGND
DGND
VDD
Digital Ground
Digital Ground
DGND 18
NC 19
31 VOUT
30 VSS
29 VSS
D
Digital +5V Power Supply
Digital +5V Power Supply
VDD
NC 20
25
26
27
28
29
30
31
32
VCC
VCC
Analog +15V Power Supply
Analog +15V Power Supply
Analog Ground
DGND 21
DGND 22
VDD 23
28 AGND
27 AGND
26 VCC
AGND
AGND
VSS
Analog Ground
Analog –15V Power Supply or 0V Single Supply
Analog –15V Power Supply or 0V Single Supply
DAC D Output Voltage
VSS
VDD 24
25 VCC
VOUT
D
V
OUTD Sense
DAC D’s Output Amplifier Inverting Input. Used
to close feedback loop at load.
33
34
35
36
37
38
VREFL CD Sense DAC C and D Reference Low Sense Input
VREFL CD
REFH CD
DAC C and D Reference Low Input
DAC C and D Reference High Input
V
V
REFH CD Sense DAC C and D Reference High Sense Input
VOUT
C
DAC C Output Voltage
V
OUTC Sense
DAC C’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
39
40
V
OUTB
DAC B Output Voltage
VOUTB Sense
DAC B’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
41
42
43
44
45
46
47
48
V
REFH AB Sense DAC A and B Reference High Sense Input
V
REFH AB
DAC A and B Reference High Input
DAC A and B Reference Low Input
VOUTL AB
V
REFL AB Sense DAC A and B Reference Low Sense Input
VSS
Analog –15V Power Supply or 0V Single Supply
Analog Ground
AGND
VOUTA
DAC A Output Voltage
VOUTA Sense
DAC A’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
DAC7734
SBAS138A
5
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
+25°C
(DAC B, +25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
2.0
2.0
1.5
1.0
1.5
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
+85°C
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
DAC7734
6
SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
+85°C (cont.)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
–40°C
(DAC A, –40°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
DAC7734
SBAS138A
7
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
POSITIVE FULL-SCALE ERROR
vs TEMPERATURE
ZERO-SCALE ERROR vs TEMPERATURE
Code (0000H)
2
1.5
1
2
1.5
1
Code (FFFFH)
DAC B
DAC D
DAC A
DAC D
0.5
0
0.5
0
DAC C
DAC B
–0.5
–1
–0.5
–1
DAC C
DAC A
–1.5
–2
–1.5
–2
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC C and D)
VREFH
VREFH
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.2
–0.4
VREFL
VREFL
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER SUPPLY CURRENT vs TEMPERATURE
4.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Data = FFFFH (all DACs)
No Load
ICC
No Load
ICC
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
IDD
IDD
–0.5
–0.5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
0
2000H
4000H
6000H
8000H
A000H
C000H
E000H
FFFFH
Temperature (°C)
Digital Input Code
DAC7734
8
SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to 0V)
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time:
3LSB/div
Small-Signal Settling Time:
3LSB/div
Large-Signal Settling Time: 5V/div
+5V
LDAC
0
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
MIDSCALE GLITCH PERFORMANCE
MIDSCALE GLITCH PERFORMANCE
7FFFH to 8000H
8000H to 7FFFH
+5V
LDAC
0
+5V
LDAC
0
Time (1µs/div)
Time (1µs/div)
BROADBAND NOISE
OUTPUT NOISE VOLTAGE vs FREQUENCY
120
100
80
60
40
20
0
BW = 10kHz
Code = 8000H
100
1k
10k
100k
1M
Time (100µs/div)
Frequency (Hz)
DAC7734
SBAS138A
9
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
POWER SUPPLY REJECTION RATIO vs FREQUENCY
OUTPUT VOLTAGE vs RLOAD
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
16
14
12
10
8
Source
+15V
6
+5V
4
2
Sink
0
100
1k
10k
100k
1M
0.01
0.1
1
10
100
Frequency (Hz)
RLOAD (kΩ)
CLOCK FEEDTHROUGH
SINGLE-SUPPLY CURRENT LIMIT vs INPUT CODE
Short to Ground
30
25
20
15
10
5
0
–5
–10
–15
–20
–25
–30
Short to VCC
+5V
CLK
0V
0000H
2000H
4000H
6000H
8000H
A000H
C000H
E000H
FFFFH
Time (50ns/div)
Input Code
DAC7734
10
SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
+25°C
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
2.0
2.0
1.5
1.0
1.5
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
+85°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
DAC7734
SBAS138A
11
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
+85°C (cont.)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
–40°C
(DAC A, –40°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
DAC7734
12
SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC C and D)
VREFH
VREFH
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–0.5
VREFL
V
REFL
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFFH)
BIPOLAR ZERO SCALE ERROR vs TEMPERATURE
(Code 8000H)
2
2
1.5
1.0
1.5
1
DAC A
DAC A
DAC B
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1
DAC D
DAC C
DAC D
DAC B
DAC C
–1.5
–2
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 0000H)
POWER SUPPLY CURRENT vs TEMPERTURE
2
1.5
7
6
5
4
3
2
1
ICC
1.0
DAC A
DAC B
0.5
0
0
–1
–2
–3
–4
–5
–6
–7
–0.5
–1.0
–1.5
–2.0
IDD
DAC C
ISS
DAC D
Data = FFFFH (all DACs)
No Load
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
DAC7734
SBAS138A
13
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
SUPPLY CURRENT vs CODE
OUTPUT VOLTAGE vs RLOAD
7
6
5
4
3
15
10
5
ICC
Source
2
1
0
IDD
0
–1
–2
–3
–4
–5
–6
–7
–5
–10
–15
ISS
Sink
0000H
2000H
4000H
6000H
8000H
A000H
C000H
E000H
FFFFH
0.01
0.1
1
10
100
Digital Input Code
RLOAD (kΩ)
OUTPUT VOLTAGE vs SETTLING TIME
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
(+10V to –10V)
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time: 3LSB/div
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time: 3LSB/div
+5V
LDAC
0
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
DUAL-SUPPLY CURRENT LIMIT vs INPUT CODE
(Short-to-Ground)
POWER SUPPLY REJECTION RATIO vs FREQUENCY
20
15
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10
5
0
–15V
+15V
–5
–10
–15
–20
+5V
0000H
2000H
4000H
6000H
8000H
A000H
C000H
E000H
FFFFH
100
1k
10k
100k
1M
Digital Input Code
Frequency (Hz)
DAC7734
14
SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
MID-SCALE GLITCH PERFORMANCE
7FFFH to 8000H
8000H to 7FFFH
+5V
LDAC
0
+5V
LDAC
0
Time (1µs/div)
Time (1µs/div)
DAC7734
SBAS138A
15
www.ti.com
The digital input is a 24-bit serial word that contains a 2-bit
address code for selecting one of four DACs, a quick load
bit, five unused bits, and the 16-bit DAC code (MSB first).
The converters can be powered from either a single +15V
supply or a dual ±15V supply and a +5V logic supply. The
device offers a reset function that immediately sets all DAC
output voltages and DAC registers to mid-scale code 8000H
or to zero-scale, code 0000H. See Figures 2 and 3 for the
basic operation of the DAC7734.
THEORY OF OPERATION
The DAC7734 is a quad voltage output, 16-bit Digital-to-
Analog Converter (DAC). The architecture is an R-2R
ladder configuration with the three MSBs segmented, fol-
lowed by an operational amplifier that serves as a buffer.
Each DAC has its own R-2R ladder network, segmented
MSBs, and output op amp, as shown in Figure 1. The
minimum voltage output (zero-scale) and maximum voltage
output (full-scale) are set by the external voltage references
VREFL and VREFH.
RF
VOUT Sense
VOUT
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREF
VREFH Sense
VREF
H
L
VREFL Sense
FIGURE 1. DAC7734 Architecture.
1
2
3
4
5
6
7
8
9
NC
NC
SDI
VOUTA Sense 48
0V to +10V
V
OUTA 47
AGND 46
VSS 45
Serial Data In
Clock
DGND
CLK
VREFL AB Sense 44
DGND
LDAC
DGND
LOAD
V
REFL AB 43
REFH AB 42
REFH AB Sense 41
OUTB Sense 40
OUTB 39
OUTC Sense 38
OUTC 37
REFH CD Sense 36
+10.000V
V
Load DAC Registers
Load
V
V
0V to +10V
0V to +10V
+10.000V
10 DGND
11 CS
V
V
Chips Select
Serial Data Out
12 DGND
13 SDO
14 DGND
15 RSTSEL
16 DGND
17 RST
18 DGND
19 NC
DAC7734
V
V
V
REFH CD 35
REFL CD 34
REFL CD Sense 33
OUTD Sense 32
V
V
Reset DAC Registers
V
0V to +10V
V
OUTD 31
VSS 30
VSS 29
20 NC
21 DGND
22 DGND
23 VDD
AGND 28
AGND 27
VCC 26
+5V
+
1µF
0.1µF
0.1µF
1µF
+
24 VDD
VCC 25
+15V
NC = No Connection
FIGURE 2. Basic Single-Supply Operation of the DAC7734.
DAC7734
16
SBAS138A
www.ti.com
1
2
3
4
5
6
7
8
9
NC
VOUTA Sense 48
OUTA 47
–10V to +10V
NC
V
SDI
AGND 46
VSS 45
Serial Data In
Clock
–15V
DGND
CLK
VREFL AB Sense 44
–10.000V
DGND
LDAC
DGND
LOAD
VREFL AB 43
+10.000V
VREFH AB 42
VREFH AB Sense 41
VOUTB Sense 40
Load DAC Registers
Load
–10V to +10V
–10V to +10V
+10.000V
10 DGND
11 CS
V
OUTB 39
VOUTC Sense 38
VOUT
37
Chips Select
Serial Data Out
12 DGND
13 SDO
14 DGND
15 RSTSEL
16 DGND
17 RST
18 DGND
19 NC
DAC7734
C
V
REFH CD Sense 36
VREFH CD 35
+5V
V
REFL CD 34
REFL CD Sense 33
OUTD Sense 32
–10.000V
V
Reset DAC Registers
V
–10V to +10V
V
OUTD 31
VSS 30
VSS 29
–15V
20 NC
0.1µF
0.1µF
1µF
+
+
21 DGND
22 DGND
23 VDD
AGND 28
AGND 27
VCC 26
1µF
0.1µF
1µF
+
+5V
+15V
24 VDD
VCC 25
NC = No Connection
FIGURE 3. Basic Dual-Supply Operation of the DAC7734.
The DAC7734 offers a force and sense output configuration
for the high open-loop gain output amplifier. This feature
allows the loop around the output amplifier to be closed at
the load (as shown in Figure 4), thus ensuring an accurate
output voltage.
ANALOG OUTPUTS
When VSS = –15V (dual-supply operation), the output am-
plifier can swing to within 4V of the supply rails, ensured
over the –40°C to +85°C temperature range. When
VSS = 0V (single-supply operation), and with RLOAD also
connected to ground, the output can swing to ground. Care
must also be taken when measuring the zero-scale error
when VSS = 0V. Since the output voltage cannot swing
below ground, the output voltage may not change for the
first few digital input codes (0000H, 0001H, 0002H, etc.) if
the output amplifier has a negative offset. At the negative
limit of –5mV, the first specified output starts at code 0021H.
RW1
VOUTA Sense 48
RW2
VOUT
VOUT
A
47
AGND 46
VSS 45
DAC7734
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 10V full-scale
range has a 1LSB value of 152µV. With a load current of
1mA, series wiring and connector resistance of only 150mΩ
(RW2) will cause a voltage drop of 150µV, as shown in
Figure 4. To understand what this means in terms of a
system layout, the resistivity of a typical 1-ounce copper-
clad printed circuit board is 1/2 mΩ per square. For a 1mA
load, a 20 milli-inch wide printed circuit conductor 6 inches
long will result in a voltage drop of 150µV.
VREFL AB Sense 44
+V
VREFL AB 43
+10V
VREFH AB 42
VREFH AB Sense 41
RW1
VOUTB Sense 40
VOUT
B
39
RW2
VOUT
FIGURE 4. Analog Output Closed-Loop Configuration
(1/2 DAC7734). RW represents wiring resis-
tances.
DAC7734
SBAS138A
17
www.ti.com
The current into the VREFH input and out of VREFL depends
on the DAC output voltages, and can vary from a few
microamps to approximately 2.0mA. The reference input
appears as a varying load to the reference. The DAC7734
features a reference drive and sense connection such that the
internal errors caused by the changing reference current and
the circuit impedances can be minimized. Figures 5 through
9 show different reference configurations, and the effect on
the linearity and differential linearity.
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 4V and VCC – 4V, provided that VREFH is at
least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
that VSS (the negative power supply) must either be
connected to ground or must be in the range of –14.25V to
–15.75V. The voltage on VSS sets several bias points within
the converter. If VSS is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not ensured.
The analog supplies must come up first. If VCC and VSS do not
come up together, then VSS should come up first. If the power
supplies for the reference come up first, then the VCC and VSS
supplies will be powered from the reference via the ESD
protection diode; see the ESD protection circuits on page 4.
+V
VOUTA Sense 48
OPA2234
VOUT
V
OUTA 47
AGND 46
45
VREFL AB Sense 44
REFL AB 43
REFH AB 42
REFH AB Sense 41
OUTB Sense 40
OUTB 39
DAC7734
2200pF
–10V
100Ω
–15V
VSS
–V
V
1000pF
1000pF
+V
V
100Ω
V
+10V
2200pF
V
V
VOUT
–V
FIGURE 5. Dual-Supply Configuration-Buffered References, used for Dual-Supply Performance (1/2 DAC7734).
+V
VOUTA Sense 48
VOUT
VOUT
A
47
AGND 46
VSS 45
DAC7734
500Ω
2200pF
100Ω
OPA350
OPA227
+0.050V
50Ω
VREFL AB Sense 44
VREFL AB 43
+V
99.5kΩ
1000pF
1000pF
VREFH AB 42
+10V
100Ω
VREFH AB Sense 41
VOUTB Sense 40
2200pF
VOUT
B
39
VOUT
NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp.
FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV used for Single-Supply Performance Curves
(1/2 DAC7734).
DAC7734
18
SBAS138A
www.ti.com
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25°C)
2.0
2.0
1.5
1.0
1.5
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 8.
+V
VOUTA Sense 48
OPA2234
VOUT
VOUTA 47
AGND 46
VSS 45
DAC7734
2200pF
–5V
100Ω
VREFL AB Sense 44
–V
V
REFL AB 43
REFH AB 42
REFH AB Sense 41
OUTB Sense 40
OUTB 39
1000pF
1000pF
+V
V
100Ω
V
+5V
2200pF
V
V
VOUT
–V
FIGURE 8. Dual-Supply Buffered Reference with VREFL = –5V and VREFH = +5V (1/2 DAC7734).
DAC7734
SBAS138A
19
www.ti.com
VOUT
VOUTA Sense 48
VOUT
47
+V
A
AGND 46
VSS 45
DAC7734
VREFL AB Sense 44
VREFL AB 43
1kΩ
100Ω
2200pF
2200pF
OPA350
OPA227
1000pF
0.05V
50Ω
100Ω
VREFH AB 42
99kΩ
VREFH AB Sense 41
+V
1000pF
V
OUTB Sense 40
VOUT
39
B
+5V
VOUT
NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp.
FIGURE 9. Single-Supply Buffered Reference with a Reference Low of 50mV and Reference High of +5V.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 25°C)
2.0
2.0
1.5
1.0
1.5
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 10. Integral Linearity and Differential Linearity Error Curves for Figure 9.
DAC7734
20
SBAS138A
www.ti.com
DIGITAL INTERFACE
device, all of the DAC outputs can be updated simulta-
neously by the rising edge of LDAC. Additionally, it allows
the DAC input registers to be written to at any point, then the
DAC output voltages can be synchronously changed via a
trigger signal (LDAC).
Table I shows the basic control logic for the DAC7734. The
interface consists of a Signal Data Clock (CLK) input, Serial
Data (SDI), DAC Input Register Load Control Signal
(LOAD), and DAC Register Load Control Signal (LDAC).
In addition, a Chip Select (CS) input is available to enable
serial communication when there are multiple serial devices.
An asynchronous Reset (RST) input, by the rising edge, is
provided to simplify start-up conditions, periodic resets, or
emergency resets to a known state, depending on the status
of the reset select (RSTSEL) signal.
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is LOW when CS rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both CS and CLK are used, CS should rise only when CLK
is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table II for more information.
The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Table I). The first two bits
shifted into the shift register, B23 and B22, are the DAC
register address. These bits select the input register that will
be updated when LOAD goes LOW. The third bit, B21, is a
“Quick Load” bit such that if HIGH, the code in the shift
register is loaded into ALL DAC input registers when the
LOAD signal goes LOW, independent of the state of the
address bits, B23 and B22. If the “Quick Load” bit is LOW,
the contents of the shift register is loaded only to the DAC
register that is addressed. Bits B20 through B16 are not used
and can assume any logical value. The last sixteen bits, B15
through B0, make up the DAC code to be loaded into the
selected input register.
CS(1)
CLK(1)
LOAD
RST
SERIAL SHIFT REGISTER
H(2)
L(4)
L
X(3)
L
H
H
H
H
H
H
H
No Change
No Change
(5)
↑
H
Advanced One Bit
Advanced One Bit
No Change
↑
L
X
X
H
H(6)
H(6)
L(7)
H
(8)
↑
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from advancing
the shift register and changing the shift register. (7) If data is clocked into the
serial register while LOAD is LOW, the selected DAC register will change as
the shift register bits “flow” through A1 and A0. This will corrupt the data in
each DAC register that has been erroneously selected. (8) Rising edge of RST
causes no change in the contents of the serial shift register.
The internal DAC register is edge-triggered and not level-
triggered. When the LDAC signal is transitioned from LOW
to HIGH, the digital word currently in the DAC input
register is latched. The first set of registers (the DAC input
registers) are level triggered via the LOAD signal. This
double-buffered architecture has been designed so that new
data can be entered for each DAC without disturbing the
analog outputs. When the new data has been entered into the
TABLE II. Serial Shift Register Truth Table.
SERIAL DATA INPUT
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
QUICK
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
A1
A0
X
X
X
X
X
D15 D14 D13 D12 D11 D10 D9
LOAD
INPUT
DAC
A1
A0
CS
RST
RSTSEL
LDAC
LOAD
REGISTER
REGISTER
MODE
DAC
L
L
L
H
L
H
X
X
X
X
L
L
L
H
H
H
H
H
H
↑
X
X
X
X
X
X
L
X
X
X
X
↑
H
X
X
L
L
L
Write
Write
Write
Write
Hold
Hold
Hold
Hold
Hold
Write
Write Input
Write Input
Write Input
Write Input
Update
A
B
C
H
H
X
X
X
X
L
L
D
H
H
X
X
H
H
X
X
All
All
All
All
Hold
Hold
Hold
Reset to Zero
Reset to Midscale
Reset to Zero
Reset to Midscale
Reset to Zero
Reset to Midscale
↑
H
TABLE I. DAC7734 Logic Truth Table.
DAC7734
SBAS138A
21
www.ti.com
SERIAL-DATA OUTPUT
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
The Serial-Data Output (SDO) is the internal shift register
output. For DAC7734, the SDO is a driven output and does
not require an external pull-up. Any number of DAC7734s
can be daisy-chained by connecting the SDO pin of one
device to the SDI pin of the following device in the chain,
as shown in Figure 11.
The DAC7734 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7734 offers
both a differential reference input, as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows a transistor
to be placed within the loop to implement a digitally-
programmable, unidirectional current source. The availabil-
ity of a differential reference allows programmability for
both the full-scale and zero-scale currents. The output cur-
rent is calculated as:
DIGITAL TIMING
Figure 12 and Table III provide detailed timing for the
digital interface of the DAC7734.
DIGITAL INPUT CODING
The DAC7734 input data is in Straight Binary format. The
output voltage is given by Equation 1.
VREFH – VREF
RSENSE
L
N
(2)
IOUT
=
•
65,536
+ VREFL / RSENSE
(
V
REFH – VREFL • N
)
(
)
(1)
VOUT = VREFL +
65,536
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
DAC7734
DAC7734
LDAC
DAC7734
LDAC
SCK
DIN
LDAC
CLK
SDI
LDAC
CLK
SDI
CS
CLK
SDI
CS
SDO
LOAD
SDO
LOAD
SDO
LOAD
CS
CS
To
Other
Serial
Devices
LOAD
FIGURE 11. Daisy-Chaining DAC7734.
DAC7734
22
SBAS138A
www.ti.com
(LSB)
D0
(MSB)
A1
QUICK
LOAD
SDI
A0
XXXXX D15 D14 D13
D3
D2
D1
CLK
CS
tCSH
t
css
tLDDD
tLD2
tLD1
LOAD
tLDRW
LDAC
tDS
tDH
SDI
tSDO
tCL
tCH
CLK
SDO
tLDDL
tLDDH
LDAC
VOUT
tS
tS
±0.003%
ERROR BAND
±0.003%
ERROR BAND
tRSTL
tRSTH
RESET
tRSSH
tRSSS
RESETSEL
FIGURE 12. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
tDS
tDH
tCH
Data Valid to CLK Rising
Data Held Valid after CLK Rises
CLK HIGH
10
20
25
25
15
0
10
30
30
40
40
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tCL
CLK LOW
tCSS
tCSH
tLD1
CS LOW to CLK Rising
CLK HIGH to CS Rising
LOAD HIGH to CLK Rising
CLK Rising to LOAD LOW
LOAD LOW Time
tLD2
tLDRW
tLDDL
tLDDH
tSDO
tRSSS
tRSSH
tRSTL
tRSTH
tLDDD
tS
LDAC LOW Time
LDAC HIGH Time
SDO Propagation Delay
RESETSEL Valid to RESET HIGH
RESET HIGH to RESETSEL Not Valid
RESET LOW Time
RESET HIGH Time
LOAD LOW to LDAC Rising Time
Settling Time
45
100
10
10
40
11 (dual) /10(single)
TABLE III. Timing Specifications (TA = –40°C to +85°C).
DAC7734
SBAS138A
23
www.ti.com
Figure 13 shows a DAC7734 in a 4mA to 20mA current
output configuration. The output current can be determined
by Equation 3:
At full-scale, the output current is 16mA, plus the 4mA, for
the zero current. At zero scale, the output current is the offset
current of 4mA (1V/250Ω).
(3)
5V –1V
N
1V
IOUT
=
•
+
250Ω
65,536
250Ω
IOUT
VPROGRAMMED
RSENSE
250Ω
+V
VOUTA Sense 48
OUTA 47
OPA2350
V
AGND 46
VSS 45
DAC7734
20kΩ
2200pF
100Ω
1.0V
VREFL AB Sense 44
VREFL AB 43
+V
80kΩ
1000pF
1000pF
VREFH AB 42
5V
100Ω
V
REFH AB Sense 41
VOUTB Sense 40
2200pF
VOUT
B
39
IOUT
VPROGRAMMED
RSENSE
250Ω
FIGURE 13. 4-to-20mA Digitally Controlled Current Source (1/2 DAC7734).
DAC7734
24
SBAS138A
www.ti.com
Revision History
DATE
REVISION PAGE
SECTION
—
DESCRIPTION
1
Updated front page format to current standard; some page layout changed.
Changed symbol from "tLDDWL" to "tLDDL" (typo).
10/08
A
23
Table III
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DAC7734
SBAS138A
25
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC7734E
DAC7734E/1K
DAC7734EB
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
DL
DL
DL
48
48
48
25
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
DAC7734E
Samples
Samples
Samples
1000 RoHS & Green
NIPDAU
NIPDAU
DAC7734E
25
25
RoHS & Green
RoHS & Green
DAC7734E
B
DAC7734EC
ACTIVE
ACTIVE
SSOP
SSOP
DL
DL
48
48
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
DAC7734E
C
Samples
Samples
DAC7734EC/1K
1000 RoHS & Green
NIPDAU
DAC7734E
C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DAC7734E
DAC7734EB
DAC7734EC
DL
DL
DL
SSOP
SSOP
SSOP
48
48
48
25
25
25
473.7
473.7
473.7
14.24
14.24
14.24
5110
5110
5110
7.87
7.87
7.87
Pack Materials-Page 1
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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