DAC7741YC/250 [TI]
具有内部 +10V 参考和并行 I/F 的 16 位单通道数模转换器 | PT | 48 | -40 to 85;
| 型号： | DAC7741YC/250 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有内部 +10V 参考和并行 I/F 的 16 位单通道数模转换器 | PT | 48 | -40 to 85 转换器 数模转换器 |
| 文件： | 总23页 (文件大小：767K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC7741
D
A
C
7
7
4
1
SBAS248B – DECEMBER 2001 – REVISED AUGUST 2007
16-Bit, Single Channel
DIGITAL-TO-ANALOG CONVERTER
With Internal Reference and Parallel Interface
DESCRIPTION
FEATURES
ꢀ LOW POWER: 150mW MAXIMUM
The DAC7741 is a 16-bit Digital-to-Analog Converter (DAC)
which provides 16 bits of monotonic performance over the
specified operating temperature range and offers a +10V,
low-drift internal reference. Designed for automatic test equip-
ment and industrial process control applications, the DAC7741
output swing can be configured in a ±10V, ±5V, or +10V
range. The flexibility of the output configuration allows the
DAC7741 to provide both unipolar and bipolar operation by
pin strapping. The DAC7741 includes a high-speed output
amplifier with a maximum settling time of 5µs to ±0.003%
FSR for a 20V full-scale change and only consumes 100mW
(typical) of power.
ꢀ +10V INTERNAL REFERENCE
ꢀ UNIPOLAR OR BIPOLAR OPERATION
ꢀ SETTLING TIME: 5µs to ±0.003% FSR
ꢀ 16-BIT MONOTONICITY, –40°C TO +85°C
ꢀ ±10V, ±5V OR +10V CONFIGURABLE VOLTAGE
OUTPUT
ꢀ RESET TO MIN-SCALE OR MID-SCALE
ꢀ DOUBLE-BUFFERED DATA INPUT
ꢀ INPUT REGISTER DATA READBACK
ꢀ SMALL LQFP-48 PACKAGE
The DAC7741 features a standard 16-bit parallel interface with
double buffering to allow asynchronous updates of the analog
output and data read-back to support data integrity verification
prior to an update. A user-programmable reset control allows
the DAC output to reset to min-scale (0000H) or mid-scale
(8000H) overriding the DAC register values. The DAC7741 is
available in a LQFP-48 package and four performance grades
specified to operate from 0°C to +70°C and –40°C to +85°C.
APPLICATIONS
ꢀ PROCESS CONTROL
ꢀ ATE PIN ELECTRONICS
ꢀ CLOSED-LOOP SERVO CONTROL
ꢀꢀMOTOR CONTROL
ꢀꢀDATA ACQUISITION SYSTEMS
REFOUT REFIN
VDD VSS VCC
REFADJ
VREF
ROFFSET
Buffer
RFB2
REFEN
CS
+10V
Reference
R/W
Control
Logic
RFB1
SJ
RST
RSTSEL
Input
Register
DAC
Register
I/O
Buffer
Data I/O
DAC
16
VOUT
AGND
DGND
LDAC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2007, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
VCC to VSS ........................................................................... –0.3V to +34V
V
V
CC to AGND ...................................................................... –0.3V to +17V
SS to AGND ...................................................................... –17V to +0.3V
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
AGND to DGND ................................................................. –0.3V to +0.3V
REFIN to AGND ............................................................. 0V to VCC – 1.4V
V
DD to DGND ........................................................................ –0.3V to +6V
Digital Input Voltage to DGND ................................. –0.3V to VDD + 0.3V
Digital Output Voltage to DGND .............................. –0.3V to VDD + 0.3V
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Junction Temperature .................................................................... +150°C
ESD damage can range from subtle performance degradation
tocompletedevicefailure. Precisionintegratedcircuitsmaybe
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
LINEARITY DIFFERENTIAL
SPECIFIED
ERROR
(LSB)
NONLINEARITY
(LSB)
PACKAGE
PACKAGE-LEAD DESIGNATOR(1)
TEMPERATURE
RANGE
ORDERING
NUMBER
PACKAGE
MARKING
TRANSPORT
MEDIA, QUANTITY
PRODUCT
DAC7741Y
±6
"
±4
"
LQFP-48
PT
"
–40°C to +85°C
DAC7741Y/250
DAC7741Y/2K
DAC7741Y
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
DAC7741YB
±4
"
±2
"
LQFP-48
PT
"
–40°C to +85°C
DAC7741YB/250
DAC7741YB/2K
DAC7741YB
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
DAC7741YC
±3
"
±1
"
LQFP-48
PT
"
–40°C to +85°C
DAC7741YC/250
DAC7741YC/2K
DAC7741YC
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
DAC7741YL
±2
"
±1
"
LQFP-48
PT
"
0°C to +70°C
DAC7741YL/250
DAC7741YL/2K
DAC7741YL
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, internal reference enabled, unless otherwise noted.
DAC7741Y
TYP
DAC7741YB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error (INL)
±6
±5
±4
±4
±3
±2
LSB
LSB
LSB
TA = 25°C
Differential Linearity Error (DNL)
Monotonicity
14
15
Bits
Offset Error
Offset Error Drift
Gain Error
±0.1
ꢀ
% of FSR
ppm/°C
% of FSR
% of FSR
ppm/°C
ppm/V
±2
ꢀ
With Internal REF
With External REF
With Internal REF
At Full-Scale
±0.4
±0.25
±0.25
±0.1
Gain Error Drift
PSRR (VCC or VSS
±15
50
±10
ꢀ
)
200
ꢀ
ANALOG OUTPUT(1)
Voltage Output(2)
+11.4/–4.75(1)
+11.4/–11.4(1)
+11.4/–6.4(1)
0 to 10
±10
±5
ꢀ
ꢀ
ꢀ
V
V
V
Output Current
Output Impedance
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
±5
ꢀ
mA
Ω
pF
mA
0.1
200
±15
ꢀ
ꢀ
ꢀ
ꢀ
AGND
Indefinite
REFERENCE
Reference Output
9.96
10
400
±15
10.04
9.975
ꢀ
ꢀ
±10
10.025
V
Ω
REFOUT Impedance
REFOUT Voltage Drift
REFOUT Voltage Adjustment(3)
REFIN Input Range(4)
ppm/°C
mV
V
±25
4.75
ꢀ
ꢀ
VCC – 1.4
ꢀ
ꢀ
ꢀ
REFIN Input Current
REFADJ Input Range
10
ꢀ
nA
V
Absolute Max Value that
can be applied is VCC
0
10
+2
ꢀ
ꢀ
REFADJ Input Impedance
50
1
ꢀ
ꢀ
kΩ
mA
Ω
V
V
REF Output Current
REF Impedance
–2
DAC7741
2
SBAS248B
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, internal reference enabled, unless otherwise noted.
DAC7741Y
TYP
DAC7741YB
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Settling Time to ±0.003%
20V Output Step
3
5
ꢀ
ꢀ
µs
RL = 5kΩ, CL = 200pF,
with external REFOUT
to REFIN filter(5)
Digital Feedthrough
Output Noise Voltage
2
100
ꢀ
ꢀ
nV-s
nV/√Hz
at 10kHz
DIGITAL INPUT
VIH
VIL
|IH| < 10µA
|IL| < 10µA
0.7 • VDD
ꢀ
ꢀ
V
V
0.3 • VDD
ꢀ
ꢀ
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.6mA
3.6
V
V
0.4
POWER SUPPLY
VDD
VCC
VSS
+4.75
+11.4
–15.75
–15.75
+5.0
+5.25
+15.75
–11.4
–4.75
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Bipolar Operation
Unipolar Operation
V
IDD
ICC
ISS
Power
100
4
–2.5
85
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
µA
mA
mA
mW
mW
Unloaded
Unloaded
No Load, Ext. Reference
No Load, Int. Reference
6
ꢀ
–4
ꢀ
ꢀ
100
150
+85
ꢀ
ꢀ
TEMPERATURE RANGE
Specified Performance
–40
°C
ꢀ Specifications same as grade to the left.
NOTES: (1) With minimum VCC /VSS requirements, internal reference enabled.
(2) Please refer to the “Theory of Operation” section for more information with respect to output voltage configurations.
(3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference.
(4) The minimum value for REFIN must be equal to the greater of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed.
(5) Reference low-pass filter values: 100kΩ, 1.0µF (See Figure 10).
DAC7741
SBAS248B
3
www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, internal reference enabled, unless otherwise noted.
DAC7741YL
TYP
DAC7741YC
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error (INL)
±2
±1
±3
±2
±1
LSB
LSB
LSB
T
A = 25°C
±1
±2
Differential Linearity Error (DNL)
Monotonicity
Offset Error
Offset Error Drift
Gain Error
16
16
Bits
±0.1
ꢀ
% of FSR
ppm/°C
% of FSR
% of FSR
ppm/°C
ppm/V
ꢀ
With Internal REF
With External REF
With Internal REF
At Full-Scale
±0.4
±0.25
±0.2
±0.1
Gain Error Drift
±15
50
±7
ꢀ
PSRR (VCC or VSS
)
200
ꢀ
ANALOG OUTPUT(1)
Voltage Output(2)
+11.4/–4.75(1)
+11.4/–11.4(1)
+11.4/–6.4(1)
0 to 10
±10
±5
ꢀ
ꢀ
ꢀ
V
V
V
Output Current
Output Impedance
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
±5
ꢀ
mA
Ω
pF
mA
0.1
200
±15
ꢀ
ꢀ
ꢀ
ꢀ
AGND
Indefinite
REFERENCE
Reference Output
9.96
10
400
±15
10.04
9.975
ꢀ
ꢀ
±7
10.025
V
Ω
REFOUT Impedance
REFOUT Voltage Drift
REFOUT Voltage Adjustment(3)
REFIN Input Range(4)
ppm/°C
mV
V
±25
4.75
ꢀ
ꢀ
VCC – 1.4
ꢀ
ꢀ
ꢀ
REFIN Input Current
REFADJ Input Range
10
ꢀ
nA
V
Absolute Max Value that
can be applied is VCC
0
10
+2
ꢀ
ꢀ
REFADJ Input Impedance
50
1
ꢀ
ꢀ
kΩ
mA
Ω
V
V
REF Output Current
REF Impedance
–2
DYNAMIC PERFORMANCE
Settling Time to ±0.003%
20V Output Step
3
5
ꢀ
ꢀ
µs
RL = 5kΩ, CL = 200pF,
with external REFOUT
to REFIN filter(5)
Digital Feedthrough
Output Noise Voltage
2
100
ꢀ
ꢀ
nV-s
nV/√Hz
at 10kHz
DIGITAL INPUT
VIH
VIL
|IH| < 10µA
|IL| < 10µA
0.7 • VDD
ꢀ
ꢀ
V
V
0.3 • VDD
ꢀ
ꢀ
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.6mA
3.6
V
V
0.4
POWER SUPPLY
VDD
VCC
VSS
+4.00
+11.4
–15.75
–15.75
+5.0
+5.25
+15.75
–11.4
–4.75
+4.75
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Bipolar Operation
Unipolar Operation
ꢀ
V
IDD
ICC
ISS
Power
100
4
–2.5
85
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
µA
mA
mA
mW
mW
Unloaded
Unloaded
No Load, Ext. Reference
No Load, Int. Reference
6
ꢀ
–4
ꢀ
100
150
70
ꢀ
TEMPERATURE RANGE
Specified Performance
0
–40
+85
°C
ꢀ Specifications same as grade to the left.
NOTES: (1) With minimum VCC /VSS requirements, internal reference enabled.
(2) Please refer to the “Theory of Operation” section for more information with respect to output voltage configurations.
(3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference.
(4) The minimum value for REFIN must be equal to the greater of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed.
(5) Reference low-pass filter values: 100kΩ, 1.0µF (See Figure 10).
DAC7741
4
SBAS248B
www.ti.com
PIN CONFIGURATION
Top View
LQFP
48 47 46 45 44 43 42 41 40 39 38 37
NC
VSS
1
2
3
4
5
6
7
8
9
36 NC
35 DB15
34 DB14
33 DB13
32 DB12
31 DB11
30 DB10
29 DB9
28 DB8
27 DB7
26 TEST
25 NC
VCC
VREF
ROFFSET
AGND
AGND
RFB2
RFB1
DAC7741
SJ 10
VOUT 11
NC 12
13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
28
29
30
31
32
33
34
35
36
37
38
39
DB8
DB9
Data Bit 8
1
2
3
4
NC
VSS
No Connection
Data Bit 9
Negative Analog Power Supply.
Positive Analog Power Supply.
DB10
DB11
DB12
DB13
DB14
DB15
NC
Data Bit 10
VCC
VREF
Data Bit 11
Buffered Output from REFIN, can be used to
drive external devices. Internally, this pin
directly drives the DAC circuitry.
Data Bit 12
Data Bit 13
5
6
7
8
ROFFSET
AGND
AGND
RFB2
Offsetting Resistor
Data Bit 14
Analog ground (Must be tied to analog ground)
Analog ground (Must be tied to analog ground)
Data Bit 15 (MSB)
No Connection
Digital Ground
Digital Power Supply
Feedback Resistor 2, used to configure DAC
output range.
DGND
VDD
9
RFB1
Feedback Resistor 1, used to configure DAC
output range.
RST
VOUT reset; active LOW, depending on the state of
RSTSEL, the DAC register is either reset to mid-
scale or min-scale.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SJ
VOUT
NC
Summing Junction of the Output Amplifier
DAC Voltage Output
No Connection
No Connection
No Connection
No Connection
Data Bit 0 (LSB)
Data Bit 1
40
LDAC
DAC register load control, rising edge triggered.
Data is loaded from the input register to the DAC
register.
NC
41
42
CS
Chip Select, active LOW
NC
R/W
Enabled by CS, controls data read (HIGH) and
write (LOW) from or to the input register.
NC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
NC
43
RSTSEL
REFEN
Reset Select; determines the action of RST. If
HIGH, RST will reset the DAC register to mid-
scale. If LOW, RST will reset the DAC register to
min-scale.
Data Bit 2
Data Bit 3
44
Enables internal +10V reference (REFOUT), active
LOW.
Data Bit 4
Data Bit 5
45
46
REFOUT
Internal Reference Output
Data Bit 6
REFADJ
Internal Reference Trim. (Acts as a gain
adjustment input when the internal reference is
used.)
No Connection
No Connection
No Connection
Reserved, Connect to DGND
Data Bit 7
NC
NC
47
48
REFIN
NC
Reference Input
No Connection
TEST
DB7
DAC7741
SBAS248B
5
www.ti.com
TIMING CHARACTERISTICS
DAC7741Y
TYP
PARAMETER
DESCRIPTION
MIN
MAX
UNITS
tRCS
tRDS
tRDH
tDZ
CS LOW for Read
100
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
10
10
70
tCSD
tWCS
tWS
tWH
tLS
85
100
30
10
10
40
0
R/W LOW to CS LOW
R/W LOW after CS HIGH
CS LOW to LDAC HIGH
CS LOW after LDAC HIGH
LDAC HIGH
tLH
tLX
30
0
tDS
Data Valid to CS LOW
Data Valid after CS HIGH
LDAC LOW
tDH
20
40
0
tLWD
tSS
RSTSEL Valid Before RST LOW
RSTSEL Valid After RST HIGH
RST LOW
tSH
10
30
tRSS
tS
Voltage Output Settling Time
5
TIMING DIAGRAMS
tWCS
CS
tWS
tWH
R/W
tRCS
CS
tRDS
tDH
tRDH
Data In
DB15-DB0
Data Valid
R/W
tDS
tLH
tDZ
tLS
tLWD
Data Valid
Data Out
DB15-DB0
LDAC
VOUT
tCSD
tLX
tS
READ CYCLE
±0.003% of FSR
Error Bands
WRITE CYCLE
RESET TIMING
tSS
RSTSEL
tSH
tRSS
RST
+FS
tS
(RSTSEL = LOW)
VOUT
Min-Scale
Mid-Scale
–FS
+FS
(RSTSEL = HIGH)
VOUT
–FS
DAC7741
6
SBAS248B
www.ti.com
TYPICAL CHARACTERISTICS
TA = +25°C (unless otherwise noted)
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
6
4
2
0
LINEARITY ERROR vs DIGITAL INPUT CODE
6
4
2
0
–2
–2
–4
–6
–4
–6
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
6
4
2
0
OFFSET ERROR vs TEMPERATURE
5
4
3
–2
–4
–6
2
VOUT = –10 to +10V
1
0
VOUT = 0 to +10V
2.0
1.5
–1
–2
–3
–4
–5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
–40
–15
10
35
60
85
Temperature (°C)
Digital Input Code
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE
GAIN ERROR vs TEMPERATURE
0.125
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
Bipolar Configuration: VOUT = –10V to +10V
Internal Reference Enabled, TA = 25°C
Int. Ref, Unipolar Mode: VOUT = 0 to +10V
Int. Ref, Bipolar Mode:
0.100
0.075
0.050
0.025
0.000
–0.025
VOUT = –10 to +10V
Ext. Ref, Unipolar Mode:
OUT = 0 to +10V
V
Ext. Ref, Bipolar Mode:
VOUT = –10 to +10V
–40
–15
10
35
60
85
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Temperature (°C)
Digital Input Code
DAC7741
SBAS248B
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted)
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE
VSS SUPPLY CURRENT vs DIGITAL INPUT CODE
3.4
–1.50
–1.75
–2.00
–2.25
–2.50
–2.75
Bipolar Configuration: VOUT = –10V to +10V
External Reference, REFEN = 5V, TA = 25°C
3.3
3.2
3.1
3.0
2.9
2.8
Bipolar Configuration: VOUT = –10V to +10V
A = 25°C
T
2.7
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
6
1000
TA = 25°C, Transition
Shown for One Data
Input (CS = 5V, R/W = 0)
5
4
800
600
400
200
0
3
ICC
2
Load Current Excluded, VCC = +15V, VSS = –15V
1
0
Bipolar VOUT Configuration: –10V to +10V
–1
–2
–3
–4
ISS
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
–40
–15
10
35
60
85
VLOGIC (V)
Temperature (°C)
HISTOGRAM OF VSS CURRENT CONSUMPTION
HISTOGRAM OF VCC CURRENT CONSUMPTION
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Bipolar Output Configuration
Internal Reference Enabled
Code = 5555H
Bipolar Output Configuration
Internal Reference Enabled
Code = 5555H
–3.50
–3.00
–2.50
–2.00
–1.50
3.000
3.500
4.000
4.500
5.000
ISS (mA)
ICC (mA)
DAC7741
8
SBAS248B
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted)
POWER SUPPY REJECTION RATIO vs FREQUENCY
(Measured at VOUT
POWER SUPPY REJECTION RATIO vs FREQUENCY
)
(Measured at VOUT
)
10
0
10
0
Bipolar Configuration: ±10V VOUT, Code FFFFH
–VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p
Bipolar Configuration: ±10V VOUT
Code 8000H
–10
–20
–30
–40
–50
–60
–70
–80
–VSS, VCC = 15V + 1Vp-p
–10
–20
–30
–40
–50
–60
–70
–80
V
DD = 5V + 0.5Vp-p
VSS
VCC
VSS
VDD
VCC
VDD
0.01K
0.1K
1K
10K
100K
1M
10M
0.1K
1K
10K
100K
1M
10M
Frequency (Hz)
Frequency (Hz)
INTERNAL REFERENCE OUTPUT vs TEMPERATURE
INTERNAL REFERENCE START-UP
10.015
10.010
10.005
10.000
9.995
15V
0V
10V
0V
9.990
9.985
–40
–15
10
35
60
85
Time (2ms/div)
Temperature (°C)
REFOUT VOLTAGE vs LOAD
OUTPUT VOLTAGE vs RLOAD
Source
11.0
10.5
10.0
9.5
12
8
Loaded to VCC
VCC = +15V
4
0
–4
–8
–12
Sink
9.0
Loaded to AGND
10
8.5
1
100
1K
0.0
0.1
1.0
10.0
100.0
REFOUT LOAD(kΩ)
RLOAD (kΩ)
DAC7741
SBAS248B
9
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted)
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at REFOUT
)
OUTPUT NOISE vs FREQUENCY
10
0
900
800
700
600
500
400
300
200
100
0
Internal Reference Enabled
Unipolar Configuration, Internal Reference Enabled
–VSS, VCC = 15V + 1Vp-p,
DD = 5V + 0.5Vp-p
V
–10
–20
–30
–40
–50
–60
–70
–80
VCC
Code FFFFH
VDD
VSS
Code 0000H
1
10
100
1k
10k
100k
1M
10M
0.01K
0.1K
1K
10K
100K
1M
10M
Frequency (Hz)
Frequency (Hz)
OUTPUT NOISE vs FREQUENCY
BROADBAND NOISE
800
700
600
500
400
300
200
100
0
Bipolar Configuration: ±10V, Internal Reference Enabled
Code 0000H
Code FFFFH
Internal Reference Enabled
Code 8000H
Filtered with 1.6Hz Low-Pass
Code FFFFH, Bipolar ±10V Configuration
10kHz Measurement BW
0.01K
0.1K
1K
10K
100K
1M
10M
Time (100µs/div)
Frequency (Hz)
UNIPOLAR FULL-SCALE SETTLING TIME
BIPOLAR FULL-SCALE SETTLING TIME
Large-Signal Output (5V/div)
Large-Signal Output (5V/div)
Small-Signal Error (300µV/div)
Small-Signal Error (300µV/div)
Unipolar Configuration: VOUT = 0V to +10V
Zero-Scale to + Full-Scale Change
5kΩ, 200pF Load
Bipolar Configuration: VOUT = –10V to +10V
–Full-Scale to + Full-Scale Change
5kΩ, 200pF Load
Time (2µs/div)
Time (2µs/div)
DAC7741
10
SBAS248B
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted)
UNIPOLAR FULL-SCALE SETTLING TIME
BIPOLAR FULL-SCALE SETTLING TIME
Small-Signal Error (300µV/div)
Large-Signal Output (5V/div)
Bipolar Configuration: VOUT = –10 to +10V
+Full-Scale to –Full-Scale
5kΩ, 200pF Load
Time (2µs/div)
Time (2µs/div)
MID-SCALE GLITCH
MID-SCALE GLITCH
Time (1µs/div)
Time (1µs/div)
DIGITAL FEEDTHROUGH
All Data Bits Toggling (5V/div)
VOUT = 8000H (100mV/div)
CS = 5V
Time (200ns/div)
DAC7741
SBAS248B
11
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The digital input is a parallel word made up of the 16-bit DAC
code, which is then loaded into the DAC register using the
LDAC input pin. The converter can be powered from ±12V
to ±15V dual analog supplies and a +5V logic supply. The
device offers a reset function, which immediately sets the
DAC output voltage and DAC register to min-scale (code
0000H) or mid-scale (code 8000H). The data I/O and reset
functions are discussed in more detail in the following sec-
tions.
THEORY OF OPERATION
The DAC7741 is a voltage output, 16-bit DAC with a +10V
built-in internal reference. The architecture is an R-2R ladder
configuration with the three MSBs segmented, followed by
an operational amplifier that serves as a buffer. The output
buffer is designed to allow user-configurable output adjust-
ments, giving the DAC7741 output voltage ranges of 0V to
+10V, –5V to +5V, or –10V to +10V. Please refer to
Figures 2, 3, and 4 for pin configuration information.
ROFFSET
RFB2
REFIN
VREF
REFADJ
REFOUT
R/4
R/4
Buffer
RFB1
+10V Internal
Reference
R/2
R/2
R/4
SJ
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREF
AGND
FIGURE 1. DAC7741 Architecture.
Data Bus
VDD
0.1µF
1µF
DGND
VDD
NC
NC
RST
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
LDAC
CS
Control Bus
R/W
Data Bus
DAC7741
RSTSEL
REFEN
REFOUT
REFADJ
REFIN
NC
NC
NC
VSS
(0V to +10V)
0.1µF
1µF
VCC
0.1µF
1µF
FIGURE 2. Basic Operation: VOUT = 0 to +10V.
12
DAC7741
SBAS248B
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Data Bus
VDD
0.1µF
1µF
DGND
VDD
NC
NC
RST
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
LDAC
CS
Control Bus
R/W
Data Bus
DAC7741
RSTSEL
REFEN
REFOUT
REFADJ
REFIN
NC
NC
NC
VSS
(–5V to +5V)
0.1µF
1µF
VCC
0.1µF
1µF
FIGURE 3. Basic Operation: VOUT = –5V to +5V.
Data Bus
VDD
0.1µF
1µF
DGND
VDD
NC
NC
RST
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
LDAC
CS
Control Bus
R/W
Data Bus
DAC7741
RSTSEL
REFEN
REFOUT
REFADJ
REFIN
NC
NC
NC
VSS
(–10V to +10V)
0.1µF
1µF
VCC
0.1µF
1µF
FIGURE 4. Basic Operation: VOUT = –10V to +10V.
DAC7741
SBAS248B
13
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the VREF pin. In this configuration, VREF is used to setup the
DAC7741 output amplifier into one of three voltage output
modes as discussed earlier. VREF can also be used to drive
other system components requiring an external reference.
ANALOG OUTPUTS
The output amplifier can swing to within 1.4V of the supply
rails, specified over the –40°C to +85°C temperature range.
This allows for a ±10V DAC voltage output operation from
±12V supplies with a typical 5% tolerance.
The internal reference of the DAC7741 can be disabled when
use of an external reference is desired. When using an
external reference, the reference input, REFIN , can be any
voltage between 4.75V (or VSS + 14V, whichever is greater)
and VCC – 1.4V.
When the DAC7741 is configured for a unipolar, 0V to 10V
output, a negative voltage supply is required. This is due to
internal biasing of the output stage. Please refer to the
“Electrical Characteristics” table for more information.
The minimum and maximum voltage output values are de-
pendent upon the output configuration implemented and
reference voltage applied to the DAC7741. Please note that
VSS (the negative power supply) must be in the range of
–4.75V to –15.75V for unipolar operation. The voltage on VSS
sets several bias points within the converter and is required
in all modes of operation. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not ensured.
DIGITAL INTERFACE
Table III shows the data format for the DAC7741 and
Table II illustrates the basic control logic of the device. The
interface consists of a chip select input (CS), read/write
control input (R/W), data inputs (DB0-DB15) and a load DAC
input (LDAC). An asynchronous reset input (RST) which is
active low, is provided to simplify start-up conditions, periodic
resets, or emergency resets to a known state, depending on
the status of the reset select (RSTSEL) signal. The DAC
code is provided via a 16-bit parallel interface, as shown in
Table II. The input word makes up the DAC code to be
loaded into the data input register of the device. The data is
latched into the input register on rising CS and is loaded into
the DAC register upon reception of a rising edge on the
LDAC input. This action updates the analog output, VOUT, to
the desired value. LDAC inputs of multiple DAC7741 devices
can be connected when a synchronized update of numerous
DAC outputs is desired. Please refer to the timing section for
more detailed data I/O information.
Supply sequence is important in establishing the correct
startup of the DAC. The digital supply (VDD) needs to estab-
lish correct bias conditions before the analog supplies (VCC
SS) are brought up. If the digital supply cannot be brought
up first, it must come up before either analog supply (VCC or
SS), with the preferred sequence of: VSS (device substrate),
VDD then VCC
,
V
V
.
REFERENCE INPUTS
The DAC7741 provides a built-in +10V voltage reference and
on-chip buffer to allow external component reference drive. To
use the internal reference, REFEN must be LOW, enabling the
reference circuitry of the DAC7741 (see Table I) and the
REFOUT pin must be connected to REFIN. This is the input to
the on-chip reference buffer. The buffers output is provided at
ANALOG OUTPUT
DIGITAL INPUT
Unipolar Configuration
Bipolar Configuration
Unipolar Straight Binary
Bipolar Offset Binary
0x0000
0x0001
:
Zero (0V)
–Full-Scale (–VREF or –VREF/2)
Zero + 1LSB
–Full-Scale + 1LSB
:
1/2 Full-Scale
1/2 Full-Scale + 1LSB
:
:
Bipolar Zero
Bipolar Zero + 1LSB
:
REFEN
ACTION
0x8000
0x8001
:
1
Internal Reference disabled;
REFOUT = HIGH Impedance
0
Internal Reference enabled;
REFOUT = +10V
0xFFFF
Full-Scale (VREF – 1LSB) +Full-Scale (+VREF – 1LSB
or +VREF/2 – 1LSB)
TABLE I. REFEN Action.
TABLE III. DAC7741 Data Format.
CONTROL STATUS
R/W CS RST RSTSEL LDAC
COMMAND
Input Register
DAC Register
Mode
L
L
H
X
H, L, ↓
Write
Hold
Write Data to Input Register
X
H
H
X
↑
Hold
Write
Update DAC register with data from input
register.
L
H
X
X
L
L
H
H
H
L
X
X
X
L
↑
Transparent
Read
Write
Hold
Hold
Write DAC register directly from data bus
Read data in input register.
No Change
H, L, ↓
H, L, ↓
X
H
X
Hold
Reset to Min-Scale Reset to Min-Scale Reset to Input and DAC Register (0000H)
Min-Scale
X
X
L
H
X
Reset to Mid-Scale Reset to Mid-Scale Reset to Input and DAC Register (8000H)
Mid-Scale
TABLE II. DAC7741 Logic Truth Table.
14
DAC7741
SBAS248B
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DAC RESET
(+VREF
)
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a low signal on
RST. Once RST is LOW, the DAC output will begin settling to
the mid-scale or min-scale code depending on the state of the
RSTSEL input. A HIGH value on RSTSEL will cause VOUT to
reset to the mid-scale code (8000H) and a LOW value will reset
VOUT to min-scale (0000H). A change in the state of the
RSTSEL input while RST is LOW will cause a corresponding
change in the reset command selected internally and conse-
quently change the output value of VOUT of the DAC. Note that
a valid reset signal also resets the input register of the DAC to
the value specified by the state of RSTSEL.
+ Full Scale
Gain Adjust
Rotates
the Line
1LSB
Input =
0000H
Input =
FFFFH
Zero Scale
(AGND)
Digital Input
Offset Adjust Translates the Line
FIGURE 5. Relationship of Offset and Gain Adjustments for
GAIN AND OFFSET CALIBRATION
VOUT = 0V to +10V Output Configuration.
The architecture of the DAC7741 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7741
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 5 and 6 illustrate the
relationship of offset and gain adjustments for the DAC7741
in a unipolar configuration and in a bipolar configuration,
(+VREF or +VREF/2)
+ Full
Scale
1LSB
Input =
0000H
Gain
Adjust
Rotates
the Line
respectively.
Offset
Adjust
Translates
the Line
When calibrating the DAC output, offset should be adjusted
first to avoid first order interaction of adjustments. In unipolar
mode, the DAC7741 offset is adjusted from code 0000H and
for either bipolar mode, offset adjustments are made at code
8000H. Gain adjustment can then be made at code FFFFH for
each configuration, where the output of the DAC should be
at +10V for the 0V to +10V – 1LSB or ±10V output range and
+5V – 1LSB for the ±5V output range. Figure 7 shows the
generalized external offset and gain adjustment circuitry
Input =
FFFFH
Input = 8000H
– Full-Scale
(–VREF OR –VREF/2)
Digital Input
FIGURE 6. Relationship of Offset and Gain Adjustments
for VOUT = –10V to +10V Output Configuration.
(Same theory applies for VOUT = –5V to +5V).
using potentiometers.
15 REFOUT
16 REFADJ
Optional Gain
17 REFIN
Adjust
18 NC
RPOT1
ISJ
R1
(Other Connections Omitted
for Clarity)
RS
RPOT2
+
VOADJ
–
Optional Offset
Adjust
FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.
DAC7741
SBAS248B
15
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than 100kΩ) as shown in Figure 7. Since the input imped-
ance of REFADJ is typically 50kΩ, the smaller the resistance
of the potentiometer, the more linear the adjustment will be.
A 10kΩ potentiometer is suggested if linearity of the refer-
ence adjustment is of concern.
OFFSET ADJUSTMENT
Offset adjustment is accomplished by introducing a small
current into the summing junction (SJ) of the DAC7741. The
voltage at SJ, or VSJ, is dependent on the output configura-
tion of the DAC7741. See Table IV for the required pin
strapping for a given configuration and the nominal values of
VSJ for each output range.
OFFSET ADJUST RANGE
50
–10V to +10V VOUT
Configuration
(1)
typ
REFERENCE
OUTPUT
PIN STRAPPING
VSJ
CONFIGURATION CONFIGURATION ROFFSET RFB1 RFB2
min (75% of typ)
25
Internal
Reference
0V to +10V
–10V to +10V
–5V to +5V
to VREF to VOUT to VOUT
NC
to AGND to VOUT to VOUT +1.666V
+5V
NC to VOUT +3.333V
typ
External
Reference
0V to VREF
–VREF to VREF
to VREF to VOUT to VOUT VREF/2
0
NC
NC to VOUT VREF/3
min (75% of typ)
–VREF/2 to VREF/2 to AGND to VOUT to VOUT VREF/6
0V to 10V and –5V to +5V
NOTE: (1) Voltage measured at VSJ for a given configuration.
–25
–50
VOUT Configuration
TABLE IV. Nominal VSJ vs. VOUT and Reference Configuration.
The current level required to adjust the DAC7741 offset can
be created by using a potentiometer divider as shown in
Figure 7. Another alternative is to use a unipolar DAC in
order to apply a voltage, VOADJ, to the resistor RS. A ±2uA
current range applied to SJ will ensure offset adjustment
coverage of the ±0.1% maximum offset specification of the
DAC7741.
–2
–1
0
1
2
ISJ (µA)
FIGURE 8. Offset Adjustment Transfer Characteristic.
When the DAC7741 internal reference is not used, gain
adjustments can be made via trimming the external refer-
ence applied to the DAC at REFIN. This can be accomplished
through using a potentiometer, unipolar DAC, or other means
of precision voltage adjustment to control the voltage pre-
sented to the DAC7741 by the external reference. Figure 9
and Table VI summarize the range of adjustment of the
internal reference via REFADJ.
When in a unipolar configuration (VSJ = 5V), only a single
resistor, RS, is needed for symmetrical offset adjustment with
a 0V to 10V VOADJ range. When in one of the two bipolar
configurations, VSJ is either +3.333v (±10V range) or +1.666V
(±5V range), and circuit values chosen to match those given
in Table V will provide symmetrical offset adjust. Please refer
to Figure 7 for component configuration.
OUTPUT
CONFIGURATION
RPOT2
R1
RS
ISJ
RANGE
NOMINAL
OFFSET
REFOUT ADJUST RANGE
40
ADJUSTMENT
0V to +10V
–10V to +10V
–5V to +5V
10K
10K
10K
0
5K
20K
2.5M
1.5M
1M
±2µA
±2.2µA
±1.7µA
±25mV
±55mV
±21mV
Typical REFOUT
Adjustment Range
30
20
10
TABLE V. Recommended External Component Values for
Symmetrical Offset Adjustment (VREF = 10V).
Minimum REFOUT
0
Adjustment Range
Figure 8 illustrates the typical and minimum offset adjustment
ranges provided by forcing a current at SJ for a given output
voltage configuration.
–10
–20
–30
–40
GAIN ADJUSTMENT
0
2
4
6
8
10
When using the internal reference of the DAC7741, gain
adjustment is performed by adjusting the internal refer-
ence voltage via the reference adjust pin, REFADJ. The
effect of a reference voltage change on the gain of the
DAC output can be seen in the generic equation (for
unipolar configuration):
REFADJ (V)
FIGURE 9. Internal Reference Adjustment Transfer Charac-
teristic.
VOLTAGE AT REFADJ
REFOUT VOLTAGE
VOUT = VREFIN • (N/65536)
REFADJ = 0V
REFADJ = 5V or NC(1)
REFADJ = 10V
10V + 25mV (min)
10V
10V – 25mV (max)
where N is represented in decimal format and ranges from 0
to 65535.
NOTE: "NC" is "Not Connected"
REFADJ can be driven by a low impedance voltage source
such as a unipolar, 0V to +10V DAC or a potentiometer (less
TABLE VI. Minimum Internal Reference Adjustment Range.
DAC7741
16
SBAS248B
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NOISE PERFORMANCE
LAYOUT
Increased noise performance of the DAC output can be
achieved by filtering the voltage reference input to the
DAC7741. Figure 10 shows a typical internal reference filter
schematic. A low-pass filter applied between the REFOUT and
REFIN pins can increase noise immunity at the DAC and
output amplifier. The REFOUT pin can source a maximum of
50µA so care should be taken in order to avoid overloading
A precision analog component requires careful layout, adequate
bypassing, and clean, well-regulated power supplies. The
DAC7741 offers separate digital and analog supplies, as it will
often be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more digital
logic present in the design and the higher the switching speed,
the more important it will become to separate the analog and
digital ground and supply planes at the device.
the internal reference output.
Since the DAC7741 has both analog and digital ground pins,
return currents can be better controlled and have less effect
on the DAC output error. Ideally, AGND would be connected
directly to an analog ground plane and DGND to the digital
ground plane. The analog ground plane would be separate
from the ground connection for the digital components until
they were connected at the power entry point of the system.
43 RSTSEL
44 REFEN
The voltages applied to VCC and VSS should be well regulated
and low noise. Switching power supplies and dc/dc convert-
ers will often have high-frequency glitches or spikes riding on
the output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connec-
tions and analog output.
100kΩ
45 REFOUT
1µF
46 REFADJ
47 REFIN
48 NC
(Other Connections
Omitted for Clarity)
In addition, a 1µF to 10µF bypass capacitor in parallel with a
0.1µF bypass capacitor is strongly recommended for each
supply input. In some situations, additional bypassing may
be required, such as a 100µF electrolytic capacitor or even
a "Pi" filter made up of inductors and capacitors–all designed
to essentially low-pass filter the analog supplies, removing
any high frequency noise components.
FIGURE 10. Internal Reference Filter.
DAC7741
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
250
250
(1)
(2)
(3)
(4/5)
(6)
DAC7741YB/250
DAC7741YC/250
DAC7741YL/250
ACTIVE
LQFP
LQFP
LQFP
PT
48
48
48
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
0 to 70
DAC7741Y
Samples
Samples
Samples
B
ACTIVE
ACTIVE
PT
Call TI
Call TI
DAC7741Y
C
PT
DAC7741Y
L
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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14-Oct-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
PT0048A
LQFP - 1.6 mm max height
S
C
A
L
E
2
.
0
0
0
LOW PROFILE QUAD FLATPACK
9.2
8.8
7.2
6.8
B
A
9.2
8.8
7.2
6.8
0.27
48X
0.17
0.08
C A B
44X 0.5
4X 5.5
SEE DETAIL A
1.6 MAX
C
SEATING PLANE
0.1 C
1.45
1.35
0.25
GAGE PLANE
0.75
0.45
0.5 MIN
0 -7
A15.000
DETAIL A
4215159/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
4. This may also be a thermally enhanced plastic package with leads conected to the die pads.
www.ti.com
EXAMPLE BOARD LAYOUT
PT0048A
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK
PKG
SYMM
48
37
SEE SOLDER MASK
DETAILS
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM
(8.2)
(R0.05) TYP
12
25
13
24
(8.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE 10.000
0.05 MAX
ALLAROUND
0.05 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL EDGE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215159/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PT0048A
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK
PKG
SYMM
48
37
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM
(8.2)
(R0.05) TYP
12
25
13
24
(8.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 10X
4215159/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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