DAC7742 [TI]

具有内部基准电压的 16 位、单通道、并行接口;


型号：	DAC7742
厂家：	TEXAS INSTRUMENTS
描述：	具有内部基准电压的 16 位、单通道、并行接口
文件：	总22页 (文件大小：705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC7742

SBAS256A – DECEMBER 2002 – AUGUST 2007

16-Bit, Single Channel

DIGITAL-TO-ANALOG CONVERTER

With Internal Reference and Parallel Interface

DESCRIPTION

FEATURES

ꢀ LOW POWER: 150mW Maximum

The DAC7742 is a 16-bit Digital-to-Analog Converter (DAC)

that provides 16 bits of monotonic performance over the

specified operating temperature range and offers a +10V,

low-drift internal reference. Designed for automatic test equip-

ment and industrial process control applications, the DAC7742

output swing can be configured in a ±10V, ±5V, or +10V

range. The flexibility of the output configuration allows the

DAC7742 to provide both unipolar and bipolar operation by

pin strapping. The DAC7742 includes a high-speed output

amplifier with a maximum settling time of 5µs to ±0.003%

FSR for a 20V full-scale change and only consumes 100mW

(typical) of power.

ꢀ +10V INTERNAL REFERENCE

ꢀ UNIPOLAR OR BIPOLAR OPERATION

ꢀ SETTLING TIME: 5µs to ±0.003% FSR

ꢀ 16-BIT MONOTINICITY, –40°C TO +85°C

ꢀ ±10V, ±5V OR +10V CONFIGURABLE VOLTAGE

OUTPUT

ꢀ RESET TO MIN-SCALE OR MID-SCALE

ꢀ DOUBLE-BUFFERED DATA INPUT

ꢀ INPUT REGISTER DATA READBACK

ꢀ SMALL LQFP-48 PACKAGE

The DAC7742 features a standard 16-bit parallel interface with

double buffering to allow asynchronous updates of the analog

output, and data read-back to support data integrity verification

prior to an update. A user-programmable reset control allows

the DAC output to reset to min-scale (FFFF_H) or mid-scale

(7FFF_H) overriding the DAC register values. The DAC7742 is

available in an LQFP-48 package and three performance

grades specified to operate from –40°C to +85°C.

ꢀ SUPPORTS TRANSPARENT DATA INPUT

OPERATION

APPLICATIONS

ꢀ PROCESS CONTROL

ꢀ ATE PIN ELECTRONICS

ꢀ CLOSED-LOOP SERVO CONTROL

ꢀꢀMOTOR CONTROL

ꢀꢀDATA ACQUISITION SYSTEMS

REF_OUTREF_IN

V_DDV_SSV_CC

REFADJ

V_REF

R_OFFSET

Buffer

RFB2

REFEN

+10V

Reference

R/W

Control

Logic

RFB1

RST

RSTSEL

Input

DAC

I/O

Buffer

Data I/O

DAC

V_OUT

AGND

DGND

LDAC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

V_CCto V_SS........................................................................... –0.3V to +32V

_CCto AGND ...................................................................... –0.3V to +16V

_SSto AGND ...................................................................... –16V to +0.3V

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

AGND to DGND ................................................................. –0.3V to +0.3V

REF_INto AGND ............................................................. 0V to V_CC– 1.4V

_DDto DGND ........................................................................ –0.3V to +6V

Digital Input Voltage to DGND ................................. –0.3V to V_DD+ 0.3V

Digital Output Voltage to DGND .............................. –0.3V to V_DD+ 0.3V

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range .........................................–65°C to +150°C

Junction Temperature .................................................................... +150°C

ESD damage can range from subtle performance degradation

tocompletedevicefailure. Precisionintegratedcircuitsmaybe

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION

LINEARITY DIFFERENTIAL

SPECIFIED

ERROR

(LSB)

NONLINEARITY

(LSB)

PACKAGE

PACKAGE-LEAD DESIGNATOR⁽¹⁾

TEMPERATURE

RANGE

ORDERING

NUMBER

PACKAGE

MARKING

TRANSPORT

MEDIA, QUANTITY

PRODUCT

DAC7742

±6

±4

LQFP-48

–40°C to +85°C

DAC7742Y/250

DAC7742Y/2K

DAC7742Y

Tape and Reel, 250

Tape and Reel, 2000

DAC7742

±4

±2

LQFP-48

–40°C to +85°C

DAC7742YB/250

DAC7742YB/2K

DAC7742YB

Tape and Reel, 250

Tape and Reel, 2000

DAC7742

±3

±1

LQFP-48

–40°C to +85°C

DAC7742YC/250

DAC7742YC/2K

DAC7742YC

Tape and Reel, 250

Tape and Reel, 2000

NOTE: (1) For the most current packageand ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.

ELECTRICAL CHARACTERISTICS

All specifications at T_A= T_MINto T_MAX, V_CC= +15V, V_SS= –15V, V_DD= +5V, Internal reference enabled, unless otherwise noted.

DAC7742Y

TYP

DAC7742YB

TYP

DAC7742YC

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

ACCURACY

Linearity Error (INL)

±6

±5

±4

±3

±2

±3

±2

±1

LSB

T_A= 25°C

Differential Linearity Error (DNL)

Monotonicity

Bits

Offset Error

Offset Error Drift

Gain Error

±0.1

ꢀ

% of FSR

ppm/°C

% of FSR

ppm/°C

ppm/V

±2

ꢀ

With Internal REF

With External REF

With Internal REF

At Full-Scale

±0.4

±0.25

±0.1

±0.2

ꢀ

Gain Error Drift

PSRR (V_CCor V_SS

±15

±10

ꢀ

±7

ꢀ

)

200

ꢀ

ANALOG OUTPUT⁽¹⁾

Voltage Output⁽²⁾

+11.4/–4.75

+11.4/–11.4

+11.4/–6.4

0 to 10

±10

±5

ꢀ

Output Current

Output Impedance

Maximum Load Capacitance

Short-Circuit Current

Short-Circuit Duration

±5

ꢀ

Ω

0.1

200

±15

ꢀ

AGND

Indefinite

REFERENCE

Reference Output

9.96

400

±15

10.04

9.975

ꢀ

±10

10.025

ꢀ

±7

ꢀ

Ω

REF_OUTImpedance

REF_OUTVoltage Drift

REF_OUTVoltage Adjustment⁽³⁾

REF_INInput Range⁽⁴⁾

REF_INInput Current

REFADJ Input Range

ppm/°C

±25

4.75

ꢀ

V_CC– 1.4

ꢀ

Absolute Max Value that

can be applied is V_CC

ꢀ

REFADJ Input Impedance

ꢀ

kΩ

Ω

_REFOutput Current

_REFImpedance

–2

ꢀ

DAC7742

SBAS256A

www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)

All specifications at T_A= T_MINto T_MAX, V_CC= +15V, V_SS= –15V, V_DD= +5V, Internal reference enabled, unless otherwise noted.

DAC7742Y

TYP

DAC7742YB

TYP

DAC7742YC

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

DYNAMIC PERFORMANCE

Settling Time to ±0.003%

20V Output Step

R_L= 5kΩ, C_L= 200pF,

with external REF_OUT

to REF_INfilter⁽⁵⁾

ꢀ

µs

Digital Feedthrough

Output Noise Voltage

100

ꢀ

nV-s

nV/√Hz

at 10kHz

DIGITAL INPUT

V_IH

V_IL

|I_H| < 10µA

|I_L| < 10µA

0.7 • V_DD

ꢀ

0.3 • V_DD

ꢀ

Input Coding

See Table III

ꢀ

DIGITAL OUTPUT

V_OH

V_OL

I_OH= –0.8mA

I_OL= 1.6mA

3.6

0.4

POWER SUPPLY

V_DD

V_CC

V_SS

+4.75

+11.4

–15.75

+5.0

+5.25

+15.75

–11.4

–4.75

ꢀ

Bipolar Operation

Unipolar Operation

I_DD

I_CC

I_SS

Power

100

–2.5

ꢀ

µA

Unloaded

No Load, Ext. Reference

No Load, Int. Reference

ꢀ

–4

ꢀ

100

150

+85

ꢀ

TEMPERATURE RANGE

Specified Performance

–40

°C

ꢀ Specifications same as DAC7742Y.

NOTES: (1) With minimum V_CC/V_SSrequirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output

voltage configurations. (3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REF_INmust be equal

to the greater of V_SS+14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100kΩ, 1.0µF (See Figure 10).

DAC7742

SBAS256A

www.ti.com

PIN CONFIGURATION

Top View

LQFP

48 47 46 45 44 43 42 41 40 39 38 37

V_SS

36 NC

35 DB15

34 DB14

33 DB13

32 DB12

31 DB11

30 DB10

29 DB9

28 DB8

27 DB7

26 TEST

25 NC

V_CC

V_REF

R_OFFSET

AGND

RFB2

RFB1

DAC7742

SJ 10

V_OUT11

NC 12

13 14 15 16 17 18 19 20 21 22 23 24

PIN DESCRIPTIONS

NAME

DESCRIPTION

NAME

DESCRIPTION

DB8

DB9

Data Bit 8

V_SS

No Connection

Data Bit 9

Negative Analog Power Supply

Positive Analog Power Supply

DB10

DB11

DB12

DB13

DB14

DB15

Data Bit 10

V_CC

V_REF

Data Bit 11

Buffered Output from REF_IN; can be used to

drive external devices. Internally, this pin

directly drives the DAC's circuitry.

Data Bit 12

Data Bit 13

R_OFFSET

AGND

RFB2

Offsetting Resistor

Data Bit 14

Analog Ground (Must be tied to analog ground.)

Data Bit 15 (MSB)

No Connection

Digital Ground

Digital Power Supply

Feedback Resistor 2, used to configure DAC

output range.

DGND

V_DD

RFB1

Feedback Resistor 1, used to configure DAC

output range.

RST

V_OUTreset; active LOW, depending on the state of

RSTSEL, the DAC register is either reset to mid-

scale or min-scale.

V_OUT

Summing Junction of the Output Amplifier

DAC Voltage Output

No Connection

Data Bit 0 (LSB)

Data Bit 1

LDAC

DAC register load control, active LOW. Data is

loaded from the input register to the DAC register.

Chip Select, Active LOW

R/W

Enabled by CS, controls data read (HIGH) and

write (LOW) from or to the input register.

RSTSEL

REFEN

Reset Select; determines the action of RST. If

HIGH, RST will reset the DAC register to mid-

scale. If LOW, RST will reset the DAC register to

min-scale.

DB0

DB1

DB2

DB3

DB4

DB5

DB6

Data Bit 2

Data Bit 3

Enables internal +10V reference (REF_OUT), active

LOW.

Data Bit 4

REF_OUT

Internal Reference Output

Data Bit 5

REFADJ

Internal Reference Trim. (Acts as a gain

adjustment input when the internal reference is

used.)

Data Bit 6

No Connection

Reserved, Connect to DGND

Data Bit 7

REF_IN

Reference Input

No Connection

TEST

DB7

DAC7742

SBAS256A

www.ti.com

TIMING DIAGRAMS

DATA WRITE CYCLE

t_WCS

t_LH

t_WS

t_WH

t_LS

R/W

t_DS

t_DH

t_DS

t_DH

Data In

Data Valid

DB15-DB0

LDAC

V_OUT

t_LWD

t_S

READ CYCLE

RESET TIMING

t_SS

RSTSEL

t_SH

t_RCS

t_RDS

t_RSS

RST

+FS

t_RDH

R/W

t_S

(RSTSEL = LOW)

t_DZ

V_OUT

Min-Scale

Data Valid

Data Out

DB15-DB0

–FS

t_CSD

+FS

Mid-Scale

(RSTSEL = HIGH)

V_OUT

–FS

TIMING CHARACTERISTICS

DAC7742Y

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

READ

t_RCS

t_RDS

t_RDH

t_DZ

CS LOW for Read

R/W HIGH to CS LOW

R/W HIGH After CS HIGH

CS HIGH to Data Bus High Impedance

CS LOW to Data Bus Valid

100

t_CSD

WRITE

t_WS

R/W LOW to CS LOW

R/W LOW After CS HIGH

CS LOW for Write

t_WH

t_WCS

t_LWD

t_LS

t_LH

t_DS

LDAC LOW for Write

CS LOW to LDAC HIGH for Direct Update

CS LOW After LDAC HIGH

Data Valid to CS LOW

t_DH

Data Valid After CS HIGH

RESET

t_RSS

t_SS

RST LOW

RSTSEL Valid Before RST LOW

RSTSEL Valid After RST HIGH

t_SH

ANALOG

t_S

Voltage Output Settling Time

µs

DAC7742

SBAS256A

www.ti.com

TYPICAL CHARACTERISTICS

T_A= +25°C (unless otherwise noted).

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

–2

–4

–6

Bipolar Configuration: V_OUT= –10V to +10V

–4

Bipolar Configuration: V_OUT= –10V to +10V

T_A= 25°C, Internal Reference Enabled

_A= 85°C, Internal Reference Enabled

–6

2.0

1.5

2.0

1.5

1.0

0.5

0.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

FFFF_HDFFF_HBFFF_H9FFF_H7FFF_H5FFF_H3FFF_H1FFF_H0000_H

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

OFFSET ERROR vs TEMPERATURE

–2

–4

–6

Bipolar Configuration: V_OUT= –10V to +10V

_A= –40°C, Internal Reference Enabled

V_OUT= –10V to +10V

V_OUT= 0V to +10V

2.0

1.5

–1

1.0

–2

–3

–4

–5

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–40

–15

FFFF_HDFFF_HBFFF_H9FFF_H7FFF_H5FFF_H3FFF_H1FFF_H0000_H

Temperature (°C)

Digital Input Code

V_CCSUPPLY CURRENT vs DIGITAL INPUT CODE

GAIN ERROR vs TEMPERATURE

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

0.15

Bipolar Configuration: V_OUT= –10V to +10V

Internal Reference Enabled, T_A= 25°C

Ext. Ref, Bipolar Mode:

_OUT= –10V to +10V

0.10

0.05

Int. Ref, Bipolar Mode:

V_OUT= –10V to +10V

Ext. Ref, Unipolar Mode:

Int. Ref, Unipolar Mode:

_OUT= 0V to +10V

V_OUT= 0V to +10V

–0.05

–40

–15

FFFF_HDFFF_HBFFF_H9FFF_H7FFF_H5FFF_H3FFF_H1FFF_H0000_H

Temperature (°C)

Digital Input Code

DAC7742

SBAS256A

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

_SSSUPPLY CURRENT vs DIGITAL INPUT CODE

V_CCSUPPLY CURRENT vs DIGITAL INPUT CODE

–1.50

–1.75

–2.00

–2.25

–2.50

–2.75

3.4

Bipolar Configuration: V_OUT= –10V to +10V

External Reference, REFEN = 5V, T_A= 25°C

3.3

3.2

3.1

3.0

2.9

2.8

Bipolar Configuration: V_OUT= –10V to +10V

_A= 25°C

2.7

FFFF_HDFFF_HBFFF_H9FFF_H7FFF_H5FFF_H3FFF_H1FFF_H0000_H

Digital Input Code

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

SUPPLY CURRENT vs TEMPERATURE

1000

T_A= 25°C, Transition

Shown for One Data

Input (CS = 5V, R/W = 0)

800

600

400

200

I_CC

Load Current Excluded, V_CC= +15V, V_SS= –15V

Bipolar V_OUTConfiguration: –10V to +10V

–1

–2

–3

–4

I_SS

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

–40

–15

V_LOGIC(V)

Temperature (°C)

HISTOGRAM OF V_SSCURRENT CONSUMPTION

HISTOGRAM OF V_CCCURRENT CONSUMPTION

100

Bipolar Output Configuration

Internal Reference Enabled

Code = AAAA_H

Bipolar Output Configuration

Internal Reference Enabled

Code = AAAA_H

3.000

3.500

4.000

I_CC(mA)

4.500

5.000

–3.50

–3.00

–2.50

–2.00

–1.50

_SS(mA)

DAC7742

SBAS256A

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY

(Measured at V_OUT

)

Bipolar Configuration: ±10V V_OUT

Code 7FFF_H

Bipolar Configuration: ±10V V_OUT, Code 0000_H

–V_SS, V_CC= 15V + 1Vp-p, V_DD= 5V + 0.5Vp-p

–V_SS, V_CC= 15V + 1Vp-p

–10

–20

–30

–40

–50

–60

–70

–80

–10

–20

–30

–40

–50

–60

–70

–80

_DD= 5V + 0.5Vp-p

V_SS

V_CC

V_SS

V_CC

V_DD

0.1k

10k

100k

10M

0.01k

0.1k

10k

100k

10M

Frequency (Hz)

INTERNAL REFERENCE OUTPUT vs TEMPERATURE

INTERNAL REFERENCE START-UP

10.015

10.010

10.005

10.000

9.995

15V

10V

9.990

9.985

–40

–15

Time (2ms/div)

Temperature (°C)

OUTPUT VOLTAGE vs R_LOAD

Source

REF_OUTVOLTAGE vs LOAD

11.0

10.5

10.0

9.5

Loaded to V_CC

V_CC= +15V

–4

–8

–12

Sink

9.0

Loaded to AGND

8.5

0.0

0.1

1.0

10.0

100.0

100

R_LOAD(kΩ)

REF_OUTLOAD (kΩ)

DAC7742

SBAS256A

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY

OUTPUT NOISE vs FREQUENCY

(Measured at REF_OUT

)

900

800

700

600

500

400

300

200

100

Unipolar Configuration, Internal Reference Enabled

Internal Reference Enabled

–V_SS, V_CC= 15V + 1Vp-p,

V_DD= 5V + 0.5Vp-p

–10

–20

–30

–40

–50

–60

–70

–80

V_CC

Code 0000_H

V_DD

V_SS

Code FFFF_H

0.01k

0.1k

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

OUTPUT NOISE vs FREQUENCY

BROADBAND NOISE

800

700

600

500

400

300

200

100

Bipolar Configuration: ±10V, Internal Reference Enabled

Code FFFF_H

Code 0000_H

Internal Reference Enabled

Filtered with 1.6Hz Low-Pass

Code 0000_H, Bipolar ±10V Configuration

10kHz Measurement BW

Code 7FFF_H

0.01k

0.1k

10k

100k

10M

Time (100µs/div)

Frequency (Hz)

UNIPOLAR FULL-SCALE SETTLING TIME

BIPOLAR FULL-SCALE SETTLING TIME

Small-Signal Error (150µV/div)

Small-Signal Error (300µV/div)

Large-Signal Output (5V/div)

Unipolar Configurtaion: V_OUT= 0V to +10V

+ Full-Scale to Zero-Scale

5kΩ, 200pF Load

Bipolar Configurtaion: V_OUT= –10V to +10V

+Full-Scale to –Full-Scale

5kΩ, 200pF Load

Time (2µs/div)

DAC7742

SBAS256A

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

BIPOLAR FULL-SCALE SETTLING TIME

UNIPOLAR FULL-SCALE SETTLING TIME

Large-Signal Output (5V/div)

Small-Signal Error (150µV/div)

Small-Signal Error (300µV/div)

Unipolar Configuration: V_OUT= 0V to +10V

Zero-Scale to +Full-Scale

Bipolar Configuration: V_OUT= –10 to +10V

–Full-Scale to +Full-Scale

5kΩ, 200pF Load

Time (2µs/div)

MID-SCALE GLITCH

Code 8000_Hto 7FFF_H

Code 7FFF_Hto 8000_H

Bipolar Configuration: ±10V V_OUT

Time (1µs/div)

DIGITAL FEEDTHROUGH

All Data Bits Toggling (5V/div)

V_OUT= 7FFF_H(100mV/div)

CS = 5V

Time (200ns/div)

DAC7742

SBAS256A

www.ti.com

The digital input is a parallel word made up of the 16-bit DAC

code and is loaded into the DAC register using the LDAC

input pin. The converter can be powered from ±12V to ±15V

dual analog supplies and a +5V logic supply. The device

offers a reset function, which immediately sets the DAC

output voltage and DAC register to min-scale (code FFFF_H)

or mid-scale (code 7FFF_H). The data I/O and reset functions

are discussed in more detail in the following sections.

THEORY OF OPERATION

The DAC7742 is a voltage output, 16-bit DAC with a +10V built-

in internal reference. The architecture is an R-2R ladder con-

figuration with the three MSBs segmented, followed by an

operational amplifier that serves as a buffer, as shown in Figure

1. The output buffer is designed to allow user-configurable

output adjustments giving the DAC7742 output voltage ranges

of 0V to +10V, –5V to +5V, or –10V to +10V. Please refer to

Figures 2, 3, and 4 for pin configuration information.

R_OFFSET

RFB2

REF_IN

V_REF

REF_ADJ

REF_OUT

R/4

Buffer

RFB1

+10V Internal

Reference

R/2

R/4

V_OUT

V_REF

AGND

FIGURE 1. DAC7742 Architecture.

Data Bus

V_DD

0.1µF

1µF

DGND

V_DD

RST

DB6

DB5

DB4

DB3

DB2

DB1

DB0

LDAC

Control Bus

R/W

Data Bus

DAC7742

RSTSEL

REFEN

REF_OUT

REFADJ

REF_IN

V_SS

(0V to +10V)

0.1µF

1µF

V_CC

0.1µF

1µF

FIGURE 2. Basic Operation: V_OUT= 0V to +10V.

DAC7742

SBAS256A

www.ti.com

Data Bus

V_DD

0.1µF

1µF

DGND

V_DD

RST

DB6

DB5

DB4

DB3

DB2

DB1

DB0

LDAC

Control Bus

R/W

Data Bus

DAC7742

RSTSEL

REFEN

REF_OUT

REFADJ

REF_IN

V_SS

(–5V to +5V)

0.1µF

1µF

V_CC

0.1µF

1µF

FIGURE 3. Basic Operation: V_OUT= –5V to +5V.

Data Bus

V_DD

0.1µF

1µF

DGND

V_DD

RST

DB6

DB5

DB4

DB3

DB2

DB1

DB0

LDAC

Control Bus

R/W

Data Bus

DAC7742

RSTSEL

REFEN

REF_OUT

REFADJ

REF_IN

V_SS

(–10V to +10V)

0.1µF

1µF

V_CC

0.1µF

1µF

FIGURE 4. Basic Operation: V_OUT= –10V to +10V.

DAC7742

SBAS256A

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ANALOG OUTPUTS

at the V_REFpin. In this configuration, V_REFis used to setup the

DAC7742 output amplifier into one of three voltage output

modes as discussed earlier. V_REFcan also be used to drive

other system components requiring an external reference.

The output amplifier can swing to within 1.4V of the supply

rails, specified over the –40°C to +85°C temperature range.

This allows for a ±10V DAC voltage output operation from

±12V supplies with a typical 5% tolerance.

The internal reference of the DAC7742 can be disabled when

use of an external reference is desired. When using an

external reference, the reference input, REF_IN, can be any

voltage between 4.75V (or V_SS+ 14V, whichever is greater)

and V_CC– 1.4V.

When the DAC7742 is configured for a unipolar, 0V to 10V

output, a negative voltage supply is required. This is due to

internal biasing of the output stage. Please refer to the

“Electrical Characteristics” table for more information.

The minimum and maximum voltage output values are de-

pendent upon the output configuration implemented and

reference voltage applied to the DAC7742. Please note that

V_SS(the negative power supply) must be in the range of

–4.75V to –15.75V for unipolar operation. The voltage on V_SS

sets several bias points within the converter and is required

in all modes of operation. If V_SSis not in one of these two

configurations, the bias values may be in error and proper

operation of the device is not ensured.

DIGITAL INTERFACE

Table III shows the data format for the DAC7742 and

Table II illustrates the basic control logic of the device. The

interface consists of a chip select input (CS), read/write

control input (R/W), data inputs (DB0-DB15), and a load DAC

input (LDAC). An asynchronous reset input (RST) which is

active LOW, is provided to simplify start-up conditions, peri-

odic resets, or emergency resets to a known state, depend-

ing on the status of the reset select (RSTSEL) signal. The

DAC code is provided via a 16-bit parallel interface, as

shown in Table II. The input word makes up the DAC code

to be loaded into the data input register of the device. The

data is latched into the input register on rising CS and is

loaded into the DAC register upon reception of a LOW level

on the LDAC input. This action updates the analog output,

Supply sequence is important in establishing correct startup

of the DAC.

The digital supply (V_DD) needs to establish correct bias

conditions before the analog supplies (V_CC, V_SS) are brought

up. If the digital supply cannot be brought up first, it must

come up before either analog supply (V_CCor V_SS), with the

preferred sequence of: V_SS(device substrate), V_DD, and then

V_OUT, to the desired value. LDAC inputs of multiple DAC7742s

V_CC

can be connected when a synchronized update of numerous

DAC outputs is desired. Please refer to the timing section for

more detailed data I/O information.

REFERENCE INPUTS

The DAC7742 provides a built-in +10V voltage reference and

on-chip buffer to allow external component reference drive. To

use the internal reference, REFEN must be LOW, enabling the

reference circuitry of the DAC7742 (as shown in Table I) and

the REF_OUTpin must be connected to REF_IN. This is the input

to the on-chip reference buffer. The buffer’s output is provided

ANALOG OUTPUT

DIGITAL INPUT

Unipolar Configuration

Bipolar Configuration

Complementary Straight Binary Complementary Offset Binary

0xFFFF

0xFFFE

Zero (0V)

–Full-Scale (–V_REFor –V_REF/2)

Zero + 1LSB

–Full-Scale + 1LSB

1/2 Full-Scale

1/2 Full-Scale + 1LSB

Bipolar Zero

Bipolar Zero + 1LSB

0x7FFF

0x7FFE

REFEN

ACTION

Internal Reference disabled;

REF_OUT= High Impedance

0x0000

Full-Scale (V_REF– 1LSB) +Full-Scale (+V_REF– 1LSB

or +V_REF/2 – 1LSB)

Internal Reference enabled;

REF_OUT= +10V

TABLE III. DAC7742 Data Format.

TABLE I. REFEN Action.

CONTROL STATUS

COMMAND

R/W

RST

RSTSEL

LDAC

Input Register

DAC Register

Mode

Write Data to Input Register

Write

Hold

Write

Update DAC Register with Data from Input

H, L

Transparent

Read

Write

Hold

Write DAC Register Directly from Data Bus

Read Data in Input Register

No Change

Hold

Reset to Min-Scale

Reset to Input and DAC Register (FFFF_H)

Min-Scale

Reset to Mid-Scale

Reset to Input and DAC Register (7FFF_H)

Mid-Scale

TABLE II. DAC7742 Logic Truth Table.

DAC7742

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DAC RESET

(+V_REF

)

The RST and RSTSEL inputs control the reset of the analog

output. The reset command is level triggered by a LOW signal

on RST. Once RST is LOW, the DAC output will begin settling

to the mid-scale or min-scale code depending on the state of

the RSTSEL input. A HIGH value on RSTSEL will cause V_OUT

to reset to the mid-scale code (7FFF_H) and a LOW value will

reset V_OUTto min-scale (FFFF_H). A change in the state of the

RSTSEL input while RST is LOW will cause a corresponding

change in the reset command selected internally and conse-

quently change the output value of V_OUTof the DAC. Note that

a valid reset signal also resets the input register of the DAC to

the value specified by the state of RSTSEL.

+ Full-Scale

Gain Adjust

Rotates

the Line

1LSB

Input =

FFFF_H

Input =

0000 _H

Zero Scale

(AGND)

Digital Input

Offset Adjust Translates the Line

FIGURE 5. Relationship of Offset and Gain Adjustments for

GAIN AND OFFSET CALIBRATION

V_OUT= 0V to +10V Output Configuration.

The architecture of the DAC7742 is designed in such a way

as to allow for easily configurable offset and gain calibration

using a minimum of external components. The DAC7742

has built-in feedback resistors and output amplifier summing

points brought out of the package in order to make the

absolute calibration possible. Figures 5 and 6 illustrate the

relationship of offset and gain adjustments for the DAC7742

in a unipolar configuration and in a bipolar configuration,

(+V_REFor +V_REF/2)

+ Full-

Scale

1LSB

Input =

FFFF_H

Gain

Adjust

Rotates

the Line

respectively.

Offset

Adjust

Translates

the Line

When calibrating the DAC’s output, offset should be adjusted

first to avoid 1st-order interaction of adjustments. In unipolar

mode, the DAC7742’s offset is adjusted from code FFFF_H

and for either bipolar mode, offset adjustments are made at

code 7FFF_H. Gain adjustment can then be made at code

0000_Hfor each configuration, where the output of the DAC

should be at +10V for the 0V to +10V – 1LSB or ±10V output

range and +5V – 1LSB for the ±5V output range. Figure 7

shows the generalized external offset and gain adjustment

Input =

0000 _H

Input = 7FFF_H

– Full-Scale

(–V_REFOR –V_REF/2)

Digital Input

FIGURE 6. Relationship of Offset and Gain Adjustments for

_OUT=–10Vto+10VOutputConfiguration.(Same

circuitry using potentiometers.

Theory Applies for V_OUT= –5V to +5V.)

15 REF_OUT

16 REFADJ

Optional Gain

17 REF_IN

Adjust

18 NC

R_POT1

I_SJ

R₁

(Other Connections Omitted

for Clarity)

R_S

R_POT2

V_OADJ

–

Optional Offset

Adjust

FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.

DAC7742

SBAS256A

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REFADJ can be driven by a low impedance voltage source

such as a unipolar, 0V to +10V DAC or a potentiometer (less

than 100kΩ), see Figure 7. Since the input impedance of

REFADJ is typically 50kΩ, the smaller the resistance of the

potentiometer, the more linear the adjustment will be. A 10kΩ

potentiometer is suggested if linearity of the reference adjust-

ment is of concern.

OFFSET ADJUSTMENT

Offset adjustment is accomplished by introducing a small

current into the summing junction (SJ) of the DAC7742. The

voltage at SJ, or V_SJ, is dependent on the output configura-

tion of the DAC7742. Table IV shows the required pin

strapping for a given configuration and the nominal values of

V_SJfor each output range.

(1)

REFERENCE

OUTPUT

PIN STRAPPING

V_SJ

OFFSET ADJUST RANGE

CONFIGURATION CONFIGURATION R_OFFSETRFB1 RFB2

–10V to +10V V_OUT

typ

Internal

Reference

0V to +10V

–10V to +10V

–5V to +5V

to V_REFto V_OUTto V_OUT

NC NC

+5V

Configuration

to V_OUT+3.333V

to AGND to V_OUTto V_OUT+2.5V

min (75% of typ)

External

0V to V_REF

to V_REFto V_OUTto V_OUTV_REF/2

Reference

–V_REFto V_REF

to V_OUTV_REF/3

typ

–V_REF/2 to V_REF/2 to AGND to V_OUTto V_OUTV_REF/4

NOTE: (1) Voltage measured at V_SJfor a given configuration.

min (75% of typ)

0V to 10V and –5V to +5V

TABLE IV. Nominal V_SJvs V_OUTand Reference Configuration.

–25

–50

V_OUTConfiguration

The current level required to adjust the DAC7742’s offset can

be created by using a potentiometer divider, see Figure 7.

Another alternative is to use a unipolar DAC in order to apply

a voltage, V_OADJ, to the resistor R_S. A ±1.2µA current range

applied to SJ will ensure offset adjustment coverage of the

±0.1% maximum offset specification of the DAC7742.

–2

–1

I_SJ(µA)

FIGURE 8. Offset Adjustment Transfer Characteristic.

When in a unipolar configuration (V_SJ= 5V), only a single

resistor, R_S, is needed for symmetrical offset adjustment with

a 0V to 10V V_OADJrange. When in one of the two bipolar

configurations, V_SJis either +3.333v (±10V range) or +2.5V

(±5V range), and circuit values chosen to match those given

in Table V will provide symmetrical offset adjust. Please refer

When the DAC7742’s internal reference is not used, gain

adjustments can be made via trimming the external refer-

ence applied to the DAC at REF_IN. This can be accomplished

through using a potentiometer, unipolar DAC, or other means

of precision voltage adjustment to control the voltage pre-

sented to the DAC7742 by the external reference. Figure 9

and Table VI summarize the range of adjustment of the

internal reference via REFADJ.

to Figure 7 for component configuration.

OUTPUT

CONFIGURATION

R_POT2

R₁

R_S

I_SJ

RANGE

NOMINAL

OFFSET

ADJUSTMENT

REF_OUTADJUST RANGE

0V to +10V

–10V to +10V

–5V to +5V

10k

2.5M

1.5M

±2µA

±2.2µA

±1.7µA

±25mV

±55mV

±21mV

Typical REF_OUT

Adjustment Range

TABLE V. Recommended External Component Values for

Symmetrical Offset Adjustment (V_REF= 10V).

Minimum REF_OUT

Adjustment Range

Figure 8 illustrates the typical and minimum offset adjustment

ranges provided by forcing a current at SJ for a given output

voltage configuration.

–10

–20

–30

–40

GAIN ADJUSTMENT

When using the internal reference of the DAC7742, gain

adjustment is performed by adjusting the device’s internal

reference voltage via the reference adjust pin, REFADJ.

The effect of a reference voltage change on the gain of the

DAC output can be seen in the generic equation (for

unipolar configuration):

REFADJ (V)

FIGURE 9. Internal Reference Adjustment Transfer Charac-

teristic.

VOLTAGE AT REFADJ

REF_OUTVOLTAGE

65535 – N

(

•

)

REFADJ = 0V

REFADJ = 5V or NC⁽¹⁾

REFADJ = 10V

10V + 25mV (min)

10V

10V – 25mV (max)

V_OUT= V_REFIN

65536

Where N is represented in decimal format and ranges from

0 to 65535.

NOTE: "NC" is "Not Connected".

TABLE VI. Minimum Internal Reference Adjustment Range.

DAC7742

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NOISE PERFORMANCE

LAYOUT

Increased noise performance of the DAC output can be

achieved by filtering the voltage reference input to the

DAC7742. Figure 10 shows a typical internal reference filter

schematic. A low-pass filter applied between the REF_OUTand

REF_INpins can increase noise immunity at the DAC and

output amplifier. The REF_OUTpin can source a maximum of

50µA so care should be taken in order to avoid overloading

A precision analog component requires careful layout, adequate

bypassing, and clean, well-regulated power supplies. The

DAC7742 offers separate digital and analog supplies, as it will

often be used in close proximity with digital logic, microcontrollers,

microprocessors, and digital signal processors. The more digital

logic present in the design and the higher the switching speed,

the more important it will become to separate the analog and

digital ground and supply planes at the device.

the internal reference output.

Since the DAC7742 has both analog and digital ground pins,

return currents can be better controlled and have less effect

on the DAC output error. Ideally, AGND would be connected

directly to an analog ground plane and DGND to the digital

ground plane. The analog ground plane would be separate

from the ground connection for the digital components until

they were connected at the power entry point of the system.

43 RSTSEL

44 REFEN

The voltages applied to V_CCand V_SSshould be well regulated

and low noise. Switching power supplies and DC/DC con-

verters will often have high-frequency glitches or spikes

riding on the output voltage. In addition, digital components

can create similar high-frequency spikes as their internal

logic switches states. This noise can easily couple into the

DAC output voltage through various paths between the

power connections and analog output.

100kΩ

45 REF_OUT

1µF

46 REFADJ

47 REF_IN

48 NC

(Other Connections

Omitted for Clarity)

In addition, a 1µF to 10µF bypass capacitor in parallel with a

0.1µF bypass capacitor is strongly recommended for each

supply input. In some situations, additional bypassing may

be required, such as a 100µF electrolytic capacitor or even

a "Pi" filter made up of inductors and capacitors–all designed

to essentially low-pass filter the analog supplies, removing

any high frequency noise components.

FIGURE 10. Internal Reference Filter.

DAC7742

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PACKAGE OPTION ADDENDUM

www.ti.com

1-Jun-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

DAC7742Y/250

DAC7742Y/250G4

DAC7742YB/250

DAC7742YB/250G4

DAC7742YC/250

DAC7742YC/250G4

ACTIVE

LQFP

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jun-2011

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC7742Y/250

DAC7742YB/250

DAC7742YC/250

LQFP

250

330.0

16.4

9.6

1.9

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC7742Y/250

DAC7742YB/250

DAC7742YC/250

LQFP

250

367.0

38.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

PT (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,08

0,50

0,13 NOM

5,50 TYP

7,20

6,80

Gage Plane

9,20

8,80

0,25

0,05 MIN

0°–7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4040052/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

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DAC7742 [TI]

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