DAC7750IPWP [TI]
适用于 4mA 至 20mA 电流环路应用的 12 位、单通道、可编程电流输出 DAC | PWP | 24 | -40 to 125;
| 型号： | DAC7750IPWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 4mA 至 20mA 电流环路应用的 12 位、单通道、可编程电流输出 DAC | PWP | 24 | -40 to 125 |
| 文件： | 总58页 (文件大小：5382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC7750, DAC8750
ZHCSC70D –DECEMBER 2013 –REVISED DECEMBER 2021
DACx750 适用于4-20mA 电流环路应用的单通道、
12 位和16 位可编程电流输出数模转换器
1 特性
3 说明
• 电流输出选项：
DAC7750 和 DAC8750 (DACx750) 是完全集成的低成
本、精密 12 位和 16 位数模转换器 (DAC)，旨在满足
工业过程控制应用的要求。这些器件经编程可提供范围
介于 4-20mA、0-20mA 或 0-24mA 的电流输出。
DACx750 包括可靠性功能，例如 SPI 帧上的 CRC 错
误校验、看门狗计时器、开路、合规电压和热警报。此
外，可通过访问一个内部高精度电阻器来监控输出电
流。
– 0mA 至24mA
– 4mA 至20mA
– 0mA 至20mA
• ±0.1% FSR 典型总体未调误差(TUE)
• DNL：±1LSB 最大值
• 最大环路合规性电压：AVDD –2V
• 内部5V 基准：10ppm/°C（最大值）
• 4.6V 内部电源输出
• CRC 帧错误校验
• 看门狗计时器
• 热警报
• 开路警报
• 用于监控输出电流的引脚
• 片上故障警报
• 针对偏移和增益的用户校准
• 宽温度范围：–40°C 至125°C
• 封装：6mm × 6mm 40 引脚VQFN 和24 引脚
HTSSOP
这些器件包括一个上电复位功能，以确保器件在某个已
知状态（IOUT 被禁用并且处于高阻抗状态）上电。如
果输出被启用，CLR 引脚将电流输出设定为低电平。
对零和增益寄存器进行编程，以便对终端系统内的器件
进行数字校准。输出转换率也可通过寄存器进行编程。
这些器件可以在电流输出上叠加外部 HART® 信号，并
采用10V 至36V 电源供电。
器件信息
封装(1)
HTSSOP (24)
VQFN (40)
封装尺寸（标称值）
7.80mm × 4.40mm
6.00mm × 6.00mm
器件型号
DACx750
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 模拟输出模块
• CPU（PLC 控制器）
• 流量变送器
• 其他传感器变送器
• 传动器
• 过程分析（pH、气体、浓度、力和湿度）
DVDD
DVDD-EN
REFOUT
REFIN
HART-IN
AVDD
DACx750
Internal
Reference
LATCH
SCLK
DIN
DAC Input
Register
R3-SENSE
Current Output Stage
Thermal
Alarm
SDO
BOOST
IOUT
Pre-
Conditioning
DAC
User Calibration
Gain/Offset
Register
Current
Source
ALARM
ISET-R
IGAIN
IENABLE
CLR
Slew Rate
Control
Watchdog
Timer
GND
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS538
DAC7750, DAC8750
ZHCSC70D –DECEMBER 2013 –REVISED DECEMBER 2021
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................28
8.5 Programming............................................................ 32
8.6 Register Maps...........................................................34
9 Application and Implementation..................................37
9.1 Application Information............................................. 37
9.2 Typical Application.................................................... 39
10 Power Supply Recommendations..............................42
11 Layout...........................................................................42
11.1 Layout Guidelines................................................... 42
11.2 Layout Example...................................................... 43
12 Device and Documentation Support..........................44
12.1 Documentation Support.......................................... 44
12.2 接收文档更新通知................................................... 44
12.3 支持资源..................................................................44
12.4 Trademarks.............................................................44
12.5 Electrostatic Discharge Caution..............................44
12.6 术语表..................................................................... 44
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Electrical Characteristics: AC....................................10
7.7 Timing Requirements: Write Mode............................10
7.8 Timing Requirements: Readback Mode....................10
7.9 Timing Diagrams ...................................................... 11
7.10 Typical Characteristics............................................12
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
Information.................................................................... 44
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (January 2018) to Revision D (December 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Changed Loop compliance voltage to Reference input voltage, and Reference input voltage to External
reference current in Recommended Operating Conditions ............................................................................... 6
• Changed Digital input low voltage test condition upper limit from 2.6 V to 3.6 V in Recommended Operating
Conditions ..........................................................................................................................................................6
• Deleted Timing Requirements: Daisy-Chain Mode section and Daisy-Chain Mode Timing figure................... 11
• Deleted Power-Supply Sequence section; content moved to Power Supply Recommendations section........ 22
• Deleted daisy-chain operation content from Watchdog Timer section..............................................................24
• Deleted The DACx750 Shares the SPI Bus With Other Devices subsection from Watchdog Timer section... 24
• Deleted daisy-chain operation from Frame Error Checking section................................................................. 24
• Added CRC fault reset command of 0x96 to Frame Error Checking section................................................... 24
• Deleted The DACx750 Shares the SPI Bus With Other Devices subsection................................................... 24
• Changed duplicated 010 step-size from 0.125 to 0.25 in Table 8-3, Slew Rate Step-Size Options ................ 26
• Added CRC fault reset command to Table 8-8, Write Address Functions .......................................................32
• Deleted Daisy-Chain Operation section............................................................................................................33
• Added Multiple Devices on the Bus section......................................................................................................33
• Changed Table 8-11 to delete daisy-chain operation and add CRC fault reset................................................34
• Changed DCEN to Reserved for DB3 in Control Register table.......................................................................34
• Deleted text stating CAP2 pin is only available for the 40-pin VQFN package.................................................37
• Added series resistance for supply and corrected HART-IN capacitance for Figure 9-3..................................39
• Added content from deleted Power-Supply Sequence section to Power Supply Recommendations section.. 42
• Added fast supply ramp and series resistance content to Power-Supply Recommendations .........................42
• Added power supply series resistance to Figure 11-1, Layout Example ......................................................... 43
Changes from Revision B (June 2016) to Revision C (January 2018)
Page
• Added last paragraph to User Calibration section............................................................................................ 25
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• Added last paragraph to Programmable Slew Rate section.............................................................................26
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5 Device Comparison Table
DIFFERENTIAL
NONLINEARITY (LSB)
PRODUCT
RESOLUTION
TUE (FSR)
DAC8750
DAC7750
16
12
0.2%
0.2%
±1
±1
6 Pin Configuration and Functions
NC
ALARM
GND
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
NC
CAP2
CAP1
GND
BOOST
IOUT
CLR
ThermalPad
LATCH
SCLK
DIN
R3-SENSE
HART-IN
DVDD-EN
NC
SDO
NC
NC
Not to scale
图6-1. RHA Package, 40-Pin VQFN, Top View
GND
1
24
23
22
21
20
19
18
17
16
15
14
13
AVDD
DVDD
ALARM
GND
2
NC
3
CAP2
4
CAP1
GND
5
BOOST
IOUT
CLR
6
ThermalPad
LATCH
SCLK
DIN
7
R3-SENSE
HART-IN
DVDD-EN
REFIN
8
9
SDO
10
11
12
GND
REFOUT
ISET-R
GND
Not to scale
图6-2. PWP Package, 24-Pin HTSSOP, Top View
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表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
RHA
(VQFN)
PWP
(HTSSOP)
NAME
Alarm pin. Open drain output. External pullup resistor required (10 kΩ). The
pin goes low (active) when the ALARM condition is detected (open circuit,
over temperature, timeout, and so on).
ALARM
2
3
Digital output
AVDD
BOOST
CAP1
CAP2
36
27
28
29
24
20
21
22
Supply input
Analog output
Analog input
Analog input
Positive analog power supply.
Boost pin. External transistor connection (optional).
Connection for output filtering capacitor (optional).
Connection for output filtering capacitor (optional).
Clear input. Logic high on this pin causes the part to enter CLEAR state.
Active high.
CLR
DIN
5
8
6
9
2
Digital input
Digital input
Serial data input. Data are clocked into the 24-bit input shift register on the
rising edge of the serial clock input. Schmitt-Trigger logic input.
Supply input
or output
DVDD
39
Digital power supply. Can be input or output, depending on DVDD-EN pin.
Internal power-supply enable pin. Connect this pin to GND to disable the
internal supply, or leave this pin unconnected to enable the internal supply.
When this pin is connected to GND, an external supply must be connected
to the DVDD pin.
DVDD-EN
GND
23
16
Digital input
12, 13, 14,
15, 37
1, 11, 12
Supply input
Ground reference point for all analog circuitry of the device.
GND
3, 4
24
4, 5
17
Supply input
Analog input
Analog output
Ground reference point for all digital circuitry of the device.
Input pin for HART modulation.
HART-IN
IOUT
26
19
Current output pin
Connection pin for external precision resistor (15 kΩ). See 节8 of this data
sheet.
ISET-R
LATCH
16
6
13
7
Analog input
Digital input
Load DAC registers input. A rising edge on this pin loads the input shift
register data into the DAC data and control registers and updates the DAC
output.
1, 10, 11,
19, 20, 21,
22, 30, 31,
32, 33, 34,
35, 38, 40
NC
23
18
No connection.
—
This pin is used as a monitoring feature for the output current. The voltage
measured between the R3-SENSE pin and the BOOST pin is directly
proportional to the output current.
R3-SENSE
25
Analog output
Internal reference output. Connects to REFIN when using internal
reference.
REFOUT
REFIN
SCLK
17
18
7
14
15
8
Analog output
Analog input
Digital input
Digital output
Reference input
Serial clock input of the SPI. Data can be transferred at rates up to 30 MHz.
Schmitt-Trigger logic input.
SDO
9
10
Serial data output. Data are valid on the rising edge of SCLK.
The thermal pad is internally connected to GND. For enhanced thermal
performance, thermally connect the pad to a copper plane. The pad can be
electrically connected to the same potential as the GND pin or left
electrically unconnected provided a supply connection is made at the GND
pin.
Thermal Pad
Supply input
—
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
AVDD to GND
40
DVDD to GND
6
V
IOUT to GND
AVDD
V
REFIN to GND
6
V
REFOUT to GND
ALARM to GND
6
V
6
DVDD + 0.3
DVDD + 0.3
10
V
Digital input voltage to GND
SDO to GND
V
V
Current into REFOUT
Operating temperature
mA
°C
°C
°C
125
–40
–65
TJ
Junction temperature
Storage temperature
150
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human body model (HBM) ESD stress voltage(2)
Charged device model (CDM) ESD stress voltage(3)
VESD
Electrostatic discharge(1)
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
MIN
10
NOM
MAX
36
UNIT
V
AVDD
DVDD
Analog supply voltage
Digital supply voltage
2.7
5.5
V
Reference input voltage
4.95
5.05
V
External reference current
Loop compliance voltage (output = 24 mA)(1)
Digital input high voltage
30
µA
V
AVDD –2
VIH
VIL
2
V
3.6 V < AVDD < 5.5 V
2.7 V < AVDD < 3.6 V
0.8
0.6
Digital Input low voltage
V
Specified performance temperature
125
°C
–40
(1) Loop compliance voltage is defined as the voltage at the IOUT pin
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7.4 Thermal Information
DAC7750, DAC8750
THERMAL METRIC(1)
RHA (VQFN)
40 PINS
32.9
PWP (HTSSOP)
UNIT
24 PINS
32.3
14.1
12.2
0.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
17.2
7.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
7.5
12
ψJB
RθJC(bot)
1.4
0.63
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
at AVDD = 10 V to 36 V, GND = 0 V, REFIN = 5 V external, DVDD = 2.7 V to 5.5 V, and all specifications are from –40°C to
+125°C (unless otherwise noted); for IOUT, RL = 300 Ω; typical specifications are at 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT OUTPUT
RANGE bits = 111
RANGE bits = 110
RANGE bits = 101
DAC8750
0
0
24
20
20
Current output
Resolution
mA
4
16
12
Bits
DAC7750
CURRENT OUTPUT ACCURACY (0 mA TO 20 mA AND 0 mA TO 24 mA)(1)
0.2%
0.16%
0.08%
±1
TA = –40°C to +125°C
–0.2%
–0.16%
–0.08%
Total unadjusted error, TUE
FSR
TA = –40°C to +85°C
TA = 25°C
±0.02%
Differential nonlinearity, DNL
Relative accuracy, INL(3)
Monotonic
LSB
FSR
±0.08%
±0.024%
0.17%
0.1%
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.17%
–0.1%
Offset error
FSR
ppm FSR/°C
FSR
±0.01%
±5
0.07%
–0.07%
Offset error temperature coefficient
Full-scale error
0.2%
0.16%
0.08%
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.2%
–0.16%
–0.08%
±0.015%
±5
Internal RSET
Full-scale error temperature coefficient
ppm FSR/°C
External RSET
±10
0.2%
0.15%
0.08%
0.17%
0.12%
0.05%
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.2%
–0.15%
–0.08%
–0.17%
–0.12%
–0.05%
Internal RSET
External RSET
±0.01%
Gain error
FSR
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
±0.01%
±3
Internal RSET
External RSET
Gain error temperature coefficient
Output current drift vs time
ppm FSR/°C
ppm FSR
±8
Internal RSET
External RSET
±50
±25
TA = 125°C, 1000 hrs
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7.5 Electrical Characteristics (continued)
at AVDD = 10 V to 36 V, GND = 0 V, REFIN = 5 V external, DVDD = 2.7 V to 5.5 V, and all specifications are from –40°C to
+125°C (unless otherwise noted); for IOUT, RL = 300 Ω; typical specifications are at 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT OUTPUT ACCURACY (4 mA TO 20 mA)(1)
0.25%
0.08%
0.29%
0.25%
0.1%
TA = –40°C to +125°C
–0.25%
–0.08%
–0.29%
–0.25%
–0.1%
Internal RSET
TA = 25°C
±0.02%
Total unadjusted error, TUE
External RSET
FSR
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
±0.02%
Differential nonlinearity, DNL
Relative accuracy, INL(3)
Monotonic
±1
LSB
FSR
±0.08%
±0.024%
0.22%
0.2%
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +85°C
–0.22%
–0.2%
Internal RSET
External RSET
Offset error
0.2%
FSR
ppm FSR/°C
FSR
–0.2%
0.18%
0.07%
–0.18%
–0.07%
Internal and external RSET, TA = 25°C
±0.01%
±3
Offset error temperature coefficient
Full-scale error
0.25%
0.08%
0.29%
0.25%
0.1%
TA = –40°C to +125°C
–0.25%
–0 .08%
–0.29%
–0.25%
–0 .1%
Internal RSET
External RSET
TA = 25°C
±0.015%
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
±0.015%
±5
Internal RSET
External RSET
Full-scale error temperature coefficient
ppm FSR/°C
±10
0.2%
0.15%
0.08%
0.16%
0.12%
0.05%
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.2%
–0.15%
–0.08%
–0.16%
–0.12%
–0.05%
Internal RSET
External RSET
±0.01%
Gain error
FSR
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
±0.01%
±3
Internal RSET
External RSET
Gain error temperature coefficient
Output current drift vs time
ppm FSR/°C
ppm FSR
±8
Internal RSET
External RSET
±50
±75
TA = 125°C, 1000 hrs
CURRENT OUTPUT STAGE(2)
Loop compliance voltage(4)
Inductive load(5)
Output = 24 mA
V
AVDD –2
50
50
mH
DC PSRR
1
μA/V
MΩ
Output impedance
Code = 0x8000
R3 RESISTOR
R3 resistor value
36
40
40
44
Ω
R3 resistor temperature coefficient
EXTERNAL REFERENCE INPUT
Reference input voltage
External reference current
Reference input capacitance
ppm/°C
4.95
5
30
10
5.05
V
REFIN = 5.0 V
μA
pF
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7.5 Electrical Characteristics (continued)
at AVDD = 10 V to 36 V, GND = 0 V, REFIN = 5 V external, DVDD = 2.7 V to 5.5 V, and all specifications are from –40°C to
+125°C (unless otherwise noted); for IOUT, RL = 300 Ω; typical specifications are at 25°C
PARAMETER
INTERNAL REFERENCE OUTPUT
Reference output
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
4.995
5.005
±10
V
Reference temperature coefficient(2)
Output noise (0.1 Hz to 10 Hz)
Noise spectral density
Capacitive load
ppm/°C
TA = –40°C to +85°C
TA = 25°C
14
185
600
±5
μVPP
nV/√Hz
nF
TA = 25°C, 10 kHz
Load current
mA
Short-circuit current
REFOUT shorted to GND
25
mA
AVDD = 24 V, TA = 25°C, sourcing
AVDD = 24 V, TA = 25°C, sinking
55
Load regulation
μV/mA
μV/V
120
±1.2
Line regulation
DVDD INTERNAL REGULATOR
Output voltage
AVDD = 24 V
4.6
V
mA
Output load current(2)
Load regulation
10
3.5
1
mV/mA
mV/V
mA
Line regulation
Short-circuit current
Capacitive load stability(2)
DIGITAL INPUTS
AVDD = 24 V, to GND
35
2.5
μF
High-level input voltage, VIH
2
V
V
3.6 V < AVDD < 5.5 V
2.7 V < AVDD < 3.6 V
0.8
0.6
Low-level input voltage, VIL
Hysteresis voltage
Input current
0.4
10
V
DVDD-EN, VIN ≤5 V
All pins other than DVDD-EN
Per pin
–2.7
μA
pF
±1
Pin capacitance
DIGITAL OUTPUTS
0.4
Low-level output voltage, VOL, sinking 200 μA
HIigh-level output voltage, VOH, sourcing 200 μA
High-impedance leakage
V
SDO
DVDD –0.5
±1
μA
10-kΩpullup resistor to
0.4
Low-level output voltage,
DVDD
V
VOL
ALARM
2.5 mA
0.6
±1
High-impedance leakage
μA
High-impedance output capacitance
10
pF
POWER SUPPLY
AVDD
10
36
5.5
3
V
V
DVDD
Internal regulator disabled
2.7
Outputs disabled, external DVDD
Outputs disabled, internal DVDD
Code = 0x0000, IOUT enabled
VIH = DVDD, VIL = GND, interface idle
AVDD = 36 V, IOUT = 0 mA, DVDD = 5 V
AIDD
4
mA
3
DIDD
1
mA
Power dissipation
TEMPERATURE
Thermal alarm
95
115
mW
142
18
°C
°C
Thermal alarm hysteresis
(1) DAC8750 and DAC7750 current output range is set by writing to RANGE bits in control register at address 0x55.
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(2) Specified by design and characterization; not production tested.
(3) For 0-mA to 20-mA and 0-mA to 24-mA ranges, INL is calculated beginning from code 0x0100 for DAC8750 and from code 0x0010 for
DAC7750.
(4) Loop compliance voltage is defined as the voltage at the IOUT pin.
(5) For stability, use slew rate limit feature or add a capacitor between IOUT and GND
7.6 Electrical Characteristics: AC
At AVDD = 10 V to 36 V, GND = 0 V, REFIN= 5 V external and DVDD = 2.7 V to 5.5 V. For IOUT, RL = 300 Ω. All
specifications –40°C to 125°C (unless otherwise noted). Typical specifications are at 25°C.
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
16-mA step, to 0.1% FSR, no L (inductance)
16-mA step, to 0.1% FSR, L < 1 mH
10
25
μs
μs
Output current settling time
AC PSRR
200-mV, 50-Hz or 60-Hz sine wave superimposed
on power-supply voltage
dB
–75
(1) Specified by characterization, not production tested.
7.7 Timing Requirements: Write Mode
at TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN
33
13
13
13
40
5
MAX
UNIT
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
SCLK cycle time
SCLK low time
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK high time
LATCH delay time
LATCH high time(2)
Data setup time
Data hold time
7
LATCH low time
CLR pulse duration
CLR activation time
40
20
5
(1) Specified by design, not production tested.
(2) Based on digital interface circuitry only. When writing to DAC control and configuration registers, consider the analog output
specifications in 节7.6.
7.8 Timing Requirements: Readback Mode
at TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN
60
25
25
13
40
5
MAX
UNIT
ns
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
SCLK cycle time
SCLK low time
ns
SCLK high time
ns
LATCH delay time
ns
LATCH high time
ns
Data setup time
ns
Data hold time
7
ns
LATCH low time
40
ns
Serial output delay time (CL, SDO = 15 pF)
LATCH rising edge to SDO 3-state (CL, SDO = 15 pF)
35
35
ns
ns
(1) Specified by design, not production tested.
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7.9 Timing Diagrams
t1
1
2
24
SCLK
t3
t4
t2
t5
LATCH
t8
t7
t6
DB23
DIN
DB0
t9
CLR
t10
IOUT
图7-1. Write Mode Timing
t11
t13
SCLK
LATCH
DIN
1
2
24
t14
1
2
8
9
22
23
24
t12
t15
t18
t17
t16
DB23
NOP condition
DB0
DB23
X
DB0
t19
DB0
t20
Input word specifies
register to be read
SDO
X
X
X
DB16
Undefined data
First eight bits are
don’t care bits
Selected register
data clocked out
图7-2. Readback Mode Timing
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7.10 Typical Characteristics
at TA = 25°C (unless otherwise noted)
5.005
5.004
5.003
5.002
5.001
5.000
4.999
4.998
4.997
4.996
4.995
25
20
15
10
5
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (oC)
C003
Temperature Drift (ppm/oC)
30 units shown
AVDD = 24 V
C002
图7-4. Internal Reference Temperature Drift Histogram
图7-3. REFOUT vs Temperature
5.004
5.003
5.002
5.001
5.000
4.999
4.998
4.997
4.996
5.0050
5.0025
5.0000
4.9975
4.9950
-10
-8
-6
-4
-2
0
2
4
6
8
10
10
14
18
22
26
30
34
38
Load Current (mA)
AVDD (V)
C001
C002
AVDD = 24 V
图7-5. REFOUT vs Load Current
TA = 25°C
图7-6. REFOUT vs AVDD
1000
900
800
700
600
500
400
300
200
100
0
Time (2 s/div)
10
100
1k
10k
100k
Frequency (Hz)
C006
C001
AVDD = 24 V
图7-7. REFOUT Noise PSD vs Frequency
AVDD = 24 V
图7-8. Internal Reference, Peak-to-Peak Noise (0.1 Hz to 10 Hz)
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7.10 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
AVDD (4 V/div)
REFOUT (2 V/div)
Time (200 µs/div)
10
13
16
19
22
25
28
31
34
37
AVDD (V)
C002
C004
AVDD = 10 V
External DVDD
IOUT = 0 mA
图7-9. REFOUT Transient vs Time
图7-10. AIDD vs AVDD
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
8
7
6
5
4
3
2
1
0
-1
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40
-35
-30
-25
-20
-15
-10
-5
0
5
External DVDD (V)
Load Current (mA)
C001
C002
TA = 25°C
External DVDD
TA = 25°C
Internal DVDD
图7-11. DIDD vs External DVDD
图7-12. Internal DVDD vs Load Current
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
0 mA to 24 mA Internal RSET
0 mA to 24 mA Internal RSET, BOOST
0 mA to 24 mA External RSET
0 mA to 24 mA External RSET, BOOST
10
100
1k
10k
100k
1M
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Frequency (Hz)
C001
C009
AVDD = 18 V
CLOAD = 100 nF
AVDD = 24 V
图7-14. IOUT TUE vs Code (0 mA to 24 mA)
RLOAD = 300 Ω
图7-13. Internal DVDD PSRR vs Frequency
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7.10 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
0.05
0.05
0.00
0.00
-0.05
-0.05
-0.10
-0.15
-0.20
-0.25
-0.10
0 mA to 20 mA Internal RSET
0 mA to 20 mA Internal RSET, BOOST
-0.15
0 mA to 20 mA External RSET
4 mA to 20 mA Internal RSET
0 mA to 20 mA External RSET, BOOST
-0.20
4 mA to 20 mA Internal RSET, BOOST
4 mA to 20 mA External RSET
4 mA to 20 mA External RSET, BOOST
-0.25
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
C006
C003
AVDD = 24 V
图7-15. IOUT TUE vs Code (0 mA to 20 mA)
AVDD = 24 V
图7-16. IOUT TUE vs Code (4 mA to 20 mA)
RLOAD = 300 Ω
RLOAD = 300 Ω
0.08
0.12
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.10
0.08
0.06
0.04
0.02
0.00
0 mA to 20 mA
0 mA to 24 mA
4 mA to 20 mA
0 mA to 20 mA
0 mA to 24 mA
4 mA to 20 mA
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (oC)
Temperature (oC)
C008
C009
AVDD = 10 V
AVDD = 10 V
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-17. IOUT TUE vs Temperature (Internal RSET
)
图7-18. IOUT TUE vs Temperature (External RSET)
0.05
0.05
Max Total Unadjusted Error
0.04
Max Total Unadjusted Error
0.04
0.03
0.02
0.03
0.02
0.01
0.01
Min Total Unadjusted Error
0.00
Min Total Unadjusted Error
-0.01
0
10
14
18
22
26
30
34
38
10
14
18
22
26
30
34
38
AVDD (V)
AVDD (V)
C006
C005
0-mA to 24-mA range
0-mA to 24-mA range
图7-20. IOUT TUE vs Supply (External RSET
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-19. IOUT TUE vs Supply (Internal RSET
)
)
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7.10 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
0.016
0.016
0.012
0.008
0.004
0.000
-0.004
-0.008
-0.012
-0.016
0 mA to 20 mA Internal RSET
0 mA to 24 mA Internal RSET
0 mA to 20 mA Internal RSET, BOOST
0 mA to 20 mA External RSET
0.012
0.008
0.004
0.000
-0.004
-0.008
-0.012
-0.016
0 mA to 24 mA Internal RSET, BOOST
0 mA to 24 mA External RSET
0 mA to 20 mA External RSET, BOOST
0 mA to 24 mA External RSET, BOOST
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
C007
C004
AVDD = 24 V
AVDD = 24 V
图7-22. IOUT INL vs Code (0 mA to 20 mA)
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-21. IOUT INL vs Code (0 mA to 24 mA)
0.016
0.012
0.008
0.004
0.000
-0.004
-0.008
-0.012
-0.016
0.004
0.002
0.000
-0.002
-0.004
-0.006
-0.008
Max INL
4 mA to 20 mA Internal RSET
4 mA to 20 mA Internal RSET, BOOST
4 mA to 20 mA External RSET
4 mA to 20 mA External RSET, BOOST
Min INL
0
8192 16384 24576 32768 40960 49152 57344 65536
-40 -25 -10
5
20
35
50
65
80
95 110 125
Code
Temperature (oC)
C001
C002
AVDD = 24 V
AVDD = 10 V
All IOUT ranges
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-23. IOUT INL vs Code (4 mA to 20 mA)
图7-24. IOUT INL vs Temperature (Internal RSET)
0.004
0.002
0.000
-0.002
-0.004
-0.006
-0.008
0.015
Max INL
Max INL
0.010
0.005
0.000
-0.005
Min INL
-0.010
-0.015
Min INL
-40 -25 -10
5
20
35
50
65
80
95 110 125
10
14
18
22
26
30
34
38
Temperature (oC)
AVDD (V)
C004
C001
AVDD = 10 V
All IOUT ranges
0-mA to 24-mA range
图7-26. IOUT INL vs Supply (Internal RSET
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-25. IOUT INL vs Temperature (External RSET
)
)
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7.10 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
0.015
1.0
0.8
0.010
0.6
Max INL
0.4
0.005
0.2
0.000
-0.005
-0.010
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Min INL
-0.015
10
14
18
22
26
30
34
38
0
8192 16384 24576 32768 40960 49152 57344 65536
AVDD (V)
Code
C003
C008
0-mA to 24-mA range
AVDD = 24 V
0-mA to 24-mA range
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-28. IOUT DNL vs Code (0 mA to 24 mA)
图7-27. IOUT INL vs Supply (External RSET
)
1.0
1.0
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
C005
C002
AVDD = 24 V
RLOAD = 300 Ω
图7-29. IOUT DNL vs Code (0 mA to 20 mA)
0-mA to 24-mA range
AVDD = 24 V
RLOAD = 300 Ω
图7-30. IOUT DNL vs Code (4 mA to 20 mA)
4-mA to 24-mA range
1.0
1.0
0.8
0.6
0.8
0.6
Max DNL
Max DNL
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
Min DNL
Min DNL
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (oC)
Temperature (oC)
C010
C011
AVDD = 10 V
All IOUT ranges
AVDD = 10 V
All IOUT ranges
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-31. IOUT DNL vs Temperature (Internal RSET
)
图7-32. IOUT DNL vs Temperature (External RSET)
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7.10 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
1.0
0.8
1.0
0.8
Max DNL
Max DNL
0.6
0.4
0.6
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
Min DNL
34
Min DNL
10
14
18
22
26
30
38
10
14
18
22
26
30
34
38
AVDD (V)
AVDD (V)
C008
C007
0-mA to 24-mA range
0-mA to 24-mA range
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-33. IOUT DNL vs Supply (Internal RSET
)
图7-34. IOUT DNL vs Supply (External RSET
)
0.18
0.12
0.09
0.06
0.12
0.06
0.03
0.00
0.00
0 mA to 20 mA Internal RSET
0 mA to 24 mA Internal RSET
4 mA to 20 mA Internal RSET
0 mA to 20 mA External RSET
0 mA to 24 mA External RSET
4 mA to 20 mA External RSET
0 mA to 20 mA Internal RSET
0 mA to 24 mA Internal RSET
4 mA to 20 mA Internal RSET
0 mA to 20 mA External RSET
0 mA to 24 mA External RSET
4 mA to 20 mA External RSET
-0.03
-0.06
-0.09
-0.12
-0.06
-0.12
-0.18
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (oC)
Temperature (oC)
C006
C003
AVDD = 10 V
AVDD = 10 V
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-35. IOUT Full-Scale Error vs Temperature
图7-36. IOUT Offset Error vs Temperature
0.12
44
43
42
41
40
39
38
37
36
0 mA to 20 mA Internal RSET
0 mA to 24 mA Internal RSET
4 mA to 20 mA Internal RSET
0 mA to 20 mA External RSET
0 mA to 24 mA External RSET
4 mA to 20 mA External RSET
0.09
0.06
0.03
0.00
-0.03
-0.06
-0.09
-0.12
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (oC)
Temperature (oC)
C007
C001
AVDD = 10 V
33 units shown
图7-38. R3 Resistance vs Temperature
RLOAD = 300 Ω
图7-37. IOUT Gain Error vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
30
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
25
20
15
10
5
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (oC)
R3 Temperature Drift (ppm/ oC)
C004
C002
AVDD = 36 V
IOUT = 24 mA
RLOAD = 300 Ω
NOTE: Compliance voltage headroom is defined as the drop
from the AVDD pin to the IOUT pin.
图7-39. R3 Resistance Temperature Drift Histogram
图7-40. Compliance Headroom Voltage vs Temperature
30
25
20
15
10
5
IOUT (4 mA/div)
LATCH (5 V/div)
0
Time (5 µs/div)
0
1
2
3
4
5
6
Headroom Voltage (V)
C005
C001
AVDD = 36 V
DAC configured to deliver 24 mA
AVDD = 24 V
4-mA to 20-mA range
RLOAD = 300 Ω
From code: 0x0000
To code: 0xFFFF
RLOAD = 300 Ω
NOTE: Compliance voltage headroom is defined as the drop
from the AVDD pin to the IOUT pin.
图7-41. IOUT vs Compliance Headroom Voltage
图7-42. 4-mA to 20-mA Rising
IOUT (4 mA/div)
LATCH (5 V/div)
Time (5 µs/div)
Time (60 µs/div)
C001
C001
AVDD = 24 V
4-mA to 20-mA range
From code: 0x0000 To code: 0xFFFF
AVDD = 24 V
RLOAD = 300 Ω
RLOAD = 300 Ω
图7-43. 4-mA to 20-mA Falling
图7-44. IOUT Power-On Glitch
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7.10 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
1.0
8000h to 7FFFh
7FFFh to 8000h
0.8
0.6
0.4
0.2
0.0
-0.2
Time (2 µs/div)
Time (2 µs/div)
C002
C001
AVDD = 24 V
图7-45. IOUT Output Enable Glitch
AVDD = 24 V
RLOAD = 300 Ω
RLOAD = 250 Ω
图7-46. IOUT Digital-to-Analog Glitch
1200
1000
800
600
400
200
0
Time (4 s/div)
10
100
1k
10k
100k
Frequency (Hz)
C003
C002
AVDD = 24 V
All IOUT ranges
AVDD = 24 V
0-mA to 20-mA range
RLOAD = 300 Ω
DAC = midscale
图7-48. IOUT Peak-to-Peak Noise vs Time (0.1 Hz to 10 Hz)
图7-47. IOUT Noise PSD vs Frequency
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
4
8
12
16
20
24
28
32
36
10
100
1k
10k
100k
1M
IOUT Terminal Voltage (V)
Frequency (Hz)
C002
C001
AVDD = 36 V
Output disabled
AVDD = 24 V
All IOUT ranges
RLOAD = 250 Ω
图7-49. IOUT Hi-Z Leakage Current vs Voltage
图7-50. IOUT PSRR vs Frequency
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8 Detailed Description
8.1 Overview
The DAC8750 and DAC7750 are low-cost, precision, fully-integrated, 16-bit and 12-bit digital-to-analog
converters (DACs) designed to meet the requirements of industrial process control applications. These devices
can be programmed as a current output with a range of 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA. The
DAC8750 and DAC7750 include reliability features such as CRC error checking on the serial peripheral interface
(SPI) frame, a watchdog timer, an open circuit, compliance voltage, and thermal alarm. In addition the output
current can be monitored by accessing an internal precision resistor.
These devices include a power-on-reset function to ensure powering up in a known state (both IOUT is disabled
and in a high-impedance state). The CLR pin sets the current output to the low-end of the range if the output is
enabled. Zero code error and gain error calibration registers can be programmed to digitally calibrate the device
in the end system. The output slew rate is also programmable. These devices can AC couple an external HART
signal on the current output and can operate with either a 10-V to 36-V supply.
8.2 Functional Block Diagram
DVDD
DVDD-EN
REFOUT
REFIN
HART-IN
AVDD
DACx750
Internal
Reference
LATCH
SCLK
DIN
DAC Input
Register
R3-SENSE
Current Output Stage
Thermal
Alarm
SDO
BOOST
IOUT
Pre-
Conditioning
DAC
User Calibration
Gain/Offset
Register
Current
Source
ALARM
ISET-R
IGAIN
IENABLE
CLR
Slew Rate
Control
Watchdog
Timer
GND
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8.3 Feature Description
8.3.1 DAC Architecture
The resistor-string section is simply a string of resistors, each with the same value, from REFIN to GND, as 图
8-1 shows. This type of architecture makes sure the DAC is monotonic. The 16-bit (DAC8750) or 12-bit
(DAC7750) binary digital code loaded to the DAC register determines at which node on the string the voltage is
tapped off before it is fed into the voltage-to-current conversion stage. The current-output stage converts the
voltage output from the string to current. When the output is disabled, it is in a high-impedance (Hi-Z) state. After
power-on, the output is disabled.
To Current Output
图8-1. DAC Structure: Resistor String
8.3.2 Current Output Stage
The current output stage consists of a preconditioner and a current source, as shown in 图 8-2. This stage
provides a current output according to the DAC code. The output range can be programmed as 0 mA to 20 mA,
0 mA to 24 mA, or 4 mA to 20 mA. Use an external transistor to reduce the power dissipation of the device. The
maximum compliance voltage on IOUT equals (AVDD – 2 V). In single power-supply mode, the maximum
AVDD is 36 V, and the maximum compliance voltage is 34 V. After power on, the IOUT pin is in a Hi-Z state.
AVDD
R3-SENSE
R2
R3
BOOST
T2
Þ
A2
+
T1
IOUT
12-/16-BitBa_
DACBa_
+
A1
Þ
RSET
图8-2. Current Output
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For a 5-V reference, the output can be expressed as shown in 方程式1 through 方程式3.
For a 0-mA to 20-mA output range, use 方程式1.
CODE
IOUT = 20mA •
2N
(1)
(2)
(3)
For a 0-mA to 24-mA output range, use 方程式2.
CODE
IOUT = 24mA •
2N
For a 4-mA to 20-mA output range, use 方程式3.
CODE
IOUT = 16mA •
+ 4mA
2N
where
• CODE is the decimal equivalent of the code loaded to the DAC
• N is the bits of resolution; 16 for DAC8750, and 12 for DAC7750
The current-output range is normally set according to the value of the RANGE bits in the Control Register (see
节8.4.1 for more details).
8.3.3 Internal Reference
The DACx750 includes an integrated 5-V reference with a buffered output (REFOUT) capable of driving up to
5 mA (source or sink) with an initial accuracy of ±5 mV maximum and a temperature drift coefficient of 10
ppm/°C maximum.
8.3.4 Digital Power Supply
An internally generated 4.6-V supply capable of driving up to 10 mA can be output on DVDD by leaving the
DVDD-EN pin unconnected. This configuration simplifies the system power-supply design when an isolation
barrier is required to generate the digital supply. The internally generated supply can be used to drive isolation
components used for the digital data lines and other miscellaneous components, such as references and
temperature sensors; see 图9-3 for an example application.
If an external supply is preferred, the DVDD pin (which can be driven up to 5.5 V in this case) can become an
input by tying DVDD-EN to GND. See 节7.5 for detailed specifications.
8.3.5 DAC Clear
The DAC has an asynchronous clear function through the CLR pin that is active-high and allows the current
output to be cleared to zero-scale code. When the CLR signal returns to low, the output remains at the cleared
value. The preclear value can be restored by pulsing the LATCH signal without clocking any data. A new value
cannot be programmed until the CLR pin returns to low. To avoid glitches on the output, disable the output by
writing a 0 to the OUTEN bit of the Control Register before changing the current range.
8.3.6 Power-On Reset
The DACx750 incorporates two internal POR circuits for the DVDD and AVDD supplies. The DVDD and AVDD
POR signals are ANDed together so that both supplies must be at their minimal specified values for the device to
not be in a reset condition. These POR circuits initialize internal logic and registers, as well as set the analog
outputs to a known state while the device supplies are ramping. All registers are reset to their default values.
Typically the POR function can be ignored, as long as the device supplies power-up and maintains the specified
minimum voltage levels. However, in the case of a supply drop or brownout, the DACx750 can have an internal
POR reset event or lose digital memory integrity. 图 8-3 represents the threshold levels for the internal POR for
both the DVDD and AVDD supplies.
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Supply (V)
Supply Max.
Specified Supply
Voltage Range
No Power-On Reset
Supply Min.
Undefined Operation Threshold
Undefined
POR Threshold
0.00
Power-On Reset
图8-3. Relevant Voltage Levels for POR Circuit
For the DVDD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply min) to 5.5 V
(supply max). For the DVDD supply region between 2.4 V (undefined operation threshold) and 0.8 V (POR
threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For the
DVDD supply below 0.8 V (POR threshold), the internal POR resets if the supply voltage remains less than 0.8 V
for approximately 1 ms.
For the AVDD supply, no internal POR occurs for nominal supply operation from 10 V (supply min) to 36 V
(supply max). For AVDD supply voltages between 8 V (undefined operation threshold) and 1 V (POR threshold),
the internal POR circuit may or may not provide a reset over all temperature conditions. For the AVDD supply
below 1 V (POR threshold), the internal POR resets if the supply voltage remains less than 1 V for approximately
1 ms. In case the DVDD or AVDD supply drops to a level where the internal POR signal is indeterminate, either
power cycle the device, or toggle the LATCH pin and then perform a software reset. Both options initialize the
internal circuitry to a known state and provide proper operation.
8.3.7 Alarm Detection
These devices also provide an alarm detection feature. When one or more of following events occur, the ALARM
pin goes low:
• The current output load is in open circuit,
• The voltage at IOUT reaches a level where accuracy of the output current is compromised. This condition is
detected by monitoring internal voltage levels of the IOUT circuitry and is typically below the specified
compliance voltage headroom (defined as the voltage drop between the AVDD and IOUT pins) minimum of 2
V,
• The die temperature exceeds 142°C,
• The SPI watchdog timer exceeds the timeout period (if enabled), or
• The SPI frame error CRC check encounters an error (if enabled).
When the ALARM pins of multiple DACx750 devices are connected together to form a wired-AND function, the
host processor must read the status register of each device to know all the fault conditions that are present. Note
that the thermal alarm has hysteresis of approximately 18°C. After being set, the alarm only resets when the die
temperature drops below 124°C.
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8.3.8 Watchdog Timer
This feature is useful to make sure that communication between the host processor and the DACx750 has not
been lost. The feature can be enabled by setting the WDEN bit of the Configuration Register to 1. The watchdog
timeout period can be set using the WDPD bits of the configuration register, as shown in 表8-1. The timer period
is based off an internal oscillator with a typical value of 8 MHz.
表8-1. Watchdog Timeout Period
WDPD BITS
WATCHDOG TIMEOUT PERIOD (Typical)
00
01
10
11
10 ms
51 ms
102 ms
204 ms
If the watchdog timer is enabled, these devices must have an SPI frame with 0x95 as the write address byte
written to the device within the programmed timeout period. Otherwise, the ALARM pin asserts low and the WD-
FLT bit of the status register is set to 1. The ALARM pin can be asserted low for any of the different conditions
explained in 节 8.3.7. To reset the WD-FLT bit to 0, use a software reset, disable the watchdog timer, or power
down the device.
8.3.9 Frame Error Checking
In noisy environments, error checking can be used to check the integrity of SPI data communication between the
DACx750 and the host processor. To enable this feature, set the CRCEN bit of the Configuration Register to 1.
The frame error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is,
100000111). When error checking is enabled, the SPI frame width is 32 bits, as shown in 表 8-2. Start with the
default 24-bit frame, enable frame error checking, and then switch to the 32-bit frame. The normal 24-bit SPI
data are appended with an 8-bit CRC polynomial by the host processor before feeding to the device. For a
register readback, the CRC polynomial is output on the SDO pins by the device as part of the 32-bit frame.
表8-2. SPI Frame with Frame Error Checking
Enabled
BIT 31:BIT 8
BIT 7:BIT 0
Normal SPI frame data
8-bit CRC polynomial
When in CRC mode, the DACx750 calculates CRC words every 32 clocks, unconditional of when the LATCH pin
toggles. The DACx750 decodes the 32-bit input frame data to compute the CRC remainder. If no error exists in
the frame, the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has single- or
multiple-bit errors), the ALARM pin asserts low and the CRC-FLT bit of the status register is set to 1. The
ALARM pin can be asserted low for any of the different conditions explained in 节 8.3.7. To reset the CRC-FLT
bit to 0, either issue software reset command of 0x96, disable the frame error checking, or power down the
device. In the case of a CRC error, the specific SPI frame is blocked from writing to the device.
If CRC mode is enabled on the first frame issued to the device after power up, issue a no operation, or NOOP,
command to the device in order to reset the SPI clock and SPI frame alignment in the event that any transients
on the SCLK line are interpreted as SCLK periods. A NOOP command can be issued to the device by simply
toggling the LATCH pin without any SCLK periods.
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8.3.10 User Calibration
The device implements a user-calibration function (enabled by the CALEN bit in the Configuration Register) to
trim system gain and zero errors. The DAC output is calibrated according to the value of the gain calibration and
zero calibration registers. The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The
gain register must be programmed to 0x8000 to achieve the default gain of 1 because the power-on value of the
register is 0x0000, equivalent to a gain of 0.5. The zero code adjustment is typically ±32,768 LSBs with 1 LSB
per step. The input data format of the gain register is unsigned straight binary, and the input data format of the
zero register is 2's complement. The gain and offset calibration is described by 方程式4.
User _GAIN + 215
CODE _OUT = CODE •
+ User _ ZERO
216
(4)
where
• CODE is the decimal equivalent of the code loaded to the DAC data register at address 0x01
• N is the bits of resolution (16 for DAC8750 and 12 for DAC7750)
• User_ZERO is the signed 16-bit code in the zero register
• User_GAIN is the unsigned 16-bit code in the gain register
• CODE_OUT is the decimal equivalent of the code loaded to the DAC (limited between 0x0000 to 0xFFFF for
DAC8750 and 0x000 to 0xFFF for DAC7750)
This is a purely digital implementation and the output is still limited by the programmed value at both ends of the
current output range (set by the RANGE bits, as described in 节 8.4.1). In addition, the correction only makes
sense for endpoints inside of the true device end points. To correct more than just the actual device error (for
example, a system offset), the valid range for the adjustment changes accordingly and must be taken into
account.
New calibration codes are only applied to subsequent writes to the DAC data register. Updating the calibration
codes does not automatically update the DAC output. Additionally, before applying new DAC data, configure the
calibration codes along with the slew rate control.
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8.3.11 Programmable Slew Rate
The slew rate control feature controls the rate at which the output current changes. With the slew rate control
feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached
load.
To reduce the slew rate, enable the slew rate control feature through bit 4 of the Control Register. With this
feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a
rate defined by bits [7:5] (SRSTEP) and bits [11:8] (SRCLK) of the Control Register. SRCLK defines the rate at
which the digital slew updates, and SRSTEP defines the amount by which the output value changes at each
update. If the DAC data register is read while the DAC output is still changing, the instantaneous value is read.
表8-3 lists the slew rate step-size options. 表8-4 summarizes the slew rate update clock options.
表8-3. Slew Rate Step-Size (SRSTEP) Options
STEP SIZE (LSB)
SRSTEP
000
DAC7750
DAC8750
0.0625
1
2
001
0.125
010
0.25
0.5
1
4
011
8
100
16
32
64
128
101
2
110
4
111
8
表8-4. Slew Rate Update Clock (SRCLK) Options
SRCLK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DAC UPDATE FREQUENCY (Hz)
258,065
200,000
153,845
131,145
115,940
69,565
37,560
25,805
20,150
16,030
10,295
8,280
6,900
5,530
4,240
3,300
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The time required for the output to slew over a given range is expressed as 方程式5.
Output Change
Step Size · Update Clock Frequency · LSB Size
Slew Time =
(5)
where
• Slew Time is expressed in seconds
• Output Change is expressed in amps (A) for IOUT or volts (V) for VOUT
When the slew rate control feature is enabled, all output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output. If the CLR pin is asserted, the output slews to the
zero-scale value at the programmed slew rate. Read bit 1 (SR-ON) of the Status Register to verify that the slew
operation has completed. The update clock frequency for any given value is the same for all output ranges. The
step size, however, varies across output ranges for a given value of step size because the LSB size is different
for each output range. 图 8-4 shows an example of IOUT slewing at a rate set by the previously described
parameters. In this example for the DAC8750 (LSB size of 305 nA for the 0-mA to 20-mA range), the settings
correspond to an update clock frequency of 6.9 kHz and a step size of 128 LSB. As shown in the case with no
capacitors on CAP1 or CAP2, the steps occur at the update clock frequency (6.9 kHz corresponds to a period
close to 150 µs), and the size of each step is approximately 38 µA (128 × 305 nA). Calculate the slew time for a
specific code change by using 方程式5.
no cap
3 nF CAP1
3 nF CAP2
10 nF CAP1
10 nF CAP2
SRCLK=1100h
SRSTEP = 111h
0 mA to 20 mA range
Time (150 µs/ div)
C001
图8-4. IOUT vs Time With Digital Slew Rate Control
Apply the desired programmable slew rate control setting before updating the DAC data register because
updates to the DAC data register in tandem with updates to the slew rate control registers can create race
conditions that may result in unexpected DAC data.
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8.4 Device Functional Modes
8.4.1 Setting Current-Output Ranges
The current output range is set according to 表8-5.
表8-5. RANGE Bits vs Output Range
RANGE
OUTPUT RANGE
4 mA to 20 mA
0 mA to 20 mA
0 mA to 24 mA
101
110
111
Note that changing the RANGE bits at any time causes the DAC data register to be cleared.
8.4.2 Current-Setting Resistor
Resistor RSET (used to convert the DAC voltage to current) illustrated in 图 8-2 determines the stability of the
output current over temperature. If desired, an external, low-drift, precision 15-kΩ resistor can be connected to
the ISET-R pin and used instead of the internal RSET resistor.
8.4.3 BOOST Configuration for IOUT
图8-5 illustrates an external NPN transistor used to reduce power dissipation on the die. Most of the load current
flows through the NPN transistor with a small amount flowing through the on-chip PMOS transistor based on the
gain of the NPN transistor. This configuration reduces the temperature induced drift on the die and internal
reference and is an option for use cases at the extreme end of the supply, load current, and ambient temperature
ranges.
The inclusion of the bipolar junction transistor (BJT) adds an additional open loop gain to internal amplifier A2
(see 图 8-2) and thus, can cause possible instability. Adding series emitter resistor R2 decreases the gain of the
stage created by the BJT and internal R3 resistor (see 图 8-2) especially for cases where RLOAD is a short or a
very small load, such as a multimeter. Recommended values for R1, R2, and C1 in this circuit are 1 kΩ, 30 Ω
and 22 nF, respectively. An equivalent solution is to place R2 (with a recommended value of 3 kΩ instead of
30 Ω) in series with the base of the transistor instead of the configuration provided in 图 8-5. Note that there is
some gain error introduced by this configuration; see 图 7-14, 图 7-15 and 图 7-16. Use the internal transistor in
most cases because the values in 节 7.5 are based on the configuration with the internal on-chip PMOS
transistor.
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BOOST
IOUT
R2
DACx750
R1
C1
RLOAD
GND
Copyright © 2016, Texas Instruments Incorporated
图8-5. Boost Mode Configuration
8.4.4 Filtering The Current Output
The DACx750 provides access to internal nodes of the circuit; see 图 9-2. Place capacitors on these pins and
AVDD to form a filter on the output current, reducing bandwidth and the slew rate of the output, especially useful
for driving inductive loads. However, to achieve large reductions in slew rate, use the programmable slew rate to
avoid having to use large capacitors. Even in that case, use the capacitors on CAP1 and CAP2 to smooth out
the stairsteps caused by the digital code changes as shown in 图 8-6. However, note that power supply ripple
also couples into the devices through these capacitors.
25
22
19
no cap
16
3 nF CAP1
3 nF CAP2
10 nF CAP1
10 nF CAP2
13
10
7
TA = 25ºC
AVDD = 24 V
RLOAD = 250 Ω
4
1
Time (200 µs/div)
C001
图8-6. IOUT vs Time for Different Cap Values on CAP1 and CAP2
8.4.5 Output Current Monitoring
Many applications, especially for functional safety, require monitoring to make sure that the output current stays
close to the programmed value. To monitor the output current, place a sense resistor in series with the output
and measure the voltage across the resistor. However, this resistor reduces the compliance voltage available for
the load. The DACx750 provide access to an internal precision resistor (R3 in 图 8-2) through the R3-SENSE
and BOOST pins to perform analog readback for monitoring the output current. Measure the voltage between
the R3-SENSE and BOOST pins and divide by the value of the R3 resistor to determine the magnitude of the
output current. The R3 resistor has a typical value of 40 Ω (see 图 7-38 for a plot of resistance vs temperature)
with a temperature drift coefficient of 40 ppm/°C (see 图7-39 for a histogram of R3 resistance temperature drift).
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The R3 resistor is tested to stay within the minimum (36 Ω) and maximum (44 Ω) resistance values shown in
the R3 Resistor portion of 节 7.5. To remove the tolerance error, perform a simple calibration by programming a
certain value of output current, measuring the voltage across R3-SENSE and BOOST, and calculating the exact
value of R3.
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8.4.6 HART Interface
For the DACx750, HART digital communication can be modulated onto the input signal by the methods shown in
the following subsections. For more detail, see Implementing HART Communication with the DAC8760 Family.
8.4.6.1 Implementing HART in 4-mA to 20-mA Mode
This method is limited to the case where the RANGE bits of the Control Register are programmed to the 4-mA to
20-mA range. Some applications require going beyond the 4-mA to 20-mA range. In those cases, see the
methods described in the next subsection.
The external HART signal (ac voltage; 500 mVPP, 1200 Hz, and 2200 Hz) can be capacitively coupled in through
the HART-IN pin and transferred to a current that is superimposed on the 4-mA to 20-mA current output. The
HART-IN pin has a typical input impedance of 35 kΩ that together with the input capacitor used to couple the
external HART signal, forms a filter to attenuate frequencies beyond the HART band-pass region. In addition to
this filter, an external passive filter is recommended to complete the filtering requirements of the HART
specifications. 图 8-7 shows the output current versus time operation for a typical HART signal. 表 8-6 specifies
the performance of the HART-IN pin.
1200 Hz
(mark)
Phase
Continuous
2200 Hz
(space)
Bit
Boundary
6.5 mA
6.0 mA
5.5 mA
Bit Cell Time = 833 ms
Time
DC current = 6 mA.
图8-7. Output Current vs Time
表8-6. HART-IN Pin Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
kΩ
mA
Input impedance
Output current (peak-to-peak)
HART signal ac-coupled into pin
Input signal of 500 mV (peak-to-peak)
35
1
0.9
1.1
8.4.6.2 Implementing HART in All Current Output Modes
The use of the HART-IN pin to implement HART modulation is limited to the case where the RANGE bits of the
节 8.6.1.1 are set to the 4-mA to 20-mA range. If it is desirable to implement HART in all current-output modes,
see 节9.1.1.
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8.5 Programming
表8-11 describes the available commands and registers on the DACx750 devices. No operation, read operation,
and watchdog timer refer to commands and are not explicit registers. For more information on these commands,
see 节8.5.1.3 and 节8.3.8.
8.5.1 Serial Peripheral Interface (SPI)
The device is controlled over a versatile four-wire serial interface (SDI, SDO, SCLK, and LATCH) that operates
at clock rates of up to 30 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP)
standards. The SPI communication command consists of a write address byte and a data word for a total of 24
bits. The timing for the digital interface is illustrated in 图7-1 and 图7-2.
8.5.1.1 SPI Shift Register
The default frame is 24 bits wide (see 节 8.3.9 for 32-bit frame mode) and begins with the rising edge of SCLK
that clocks in the MSB. The subsequent bits are latched on successive rising edges of SCLK. The default 24-bit
input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in 表8-7.
表8-7. Default SPI Frame
BIT 23:BIT 16
BIT 15:BIT 0
Address byte
Data word
The host processor must issue 24 bits before it issues a rising edge on the LATCH pin. Input data bits are
clocked in regardless of the LATCH pin and are unconditionally latched on the rising edge of LATCH. By default,
the SPI shift register resets to 0x000000 at power on or after a reset.
8.5.1.2 Write Operation
A write operation is accomplished when the address byte is set according to 表 8-8. For more information on the
DACx750 registers, see 节8.6.
表8-8. Write Address Functions
ADDRESS
BYTE
(HEX)
FUNCTION
00
01
02
55
56
57
58
59
95
96
No operation (NOP)
Write DAC Data register
Register read
Write control register
Write reset register
Write configuration register
Write DAC gain calibration register
Write DAC zero calibration register
Watchdog timer reset
CRC error reset
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8.5.1.3 Read Operation
A read operation is accomplished when the address byte is 0x02. Follow the read operation with a no-operation
(NOP) command to clock out an addressed register; see 图 7-2. To read from a register, the address byte and
data word is as shown in 表 8-9. The read register value is output MSB first on SDO on successive falling edges
of SCLK.
表8-9. Default SPI Frame for Register Read
DATA WORD
ADDRESS BYTE
(HEX)
BIT 15:BIT 6
BIT 5:BIT 0
Register read address (see 表8-10)
02
X (don't care)
表8-10 shows the register read addresses available on the DACx750 devices.
表8-10. Register Read Address Functions
READ ADDRESS(1)
FUNCTION
XX XX00
Read status register
XX XX01
Read DAC data register
XX XX10
Read control register
00 1011
Read configuration register
Read DAC gain calibration register
Read DAC zero calibration register
01 0011
01 0111
(1) X denotes don't care bits.
8.5.1.4 Stand-Alone Operation
SCLK can operate in either continuous or burst mode, as long as the LATCH rising edge occurs after the
appropriate number of SCLK cycles. Providing more than or less than 24 SCLK cycles before the rising edge of
LATCH results in incorrect data being programmed into the device registers, and incorrect data sent out on SDO.
The rising edge of SCLK that clocks in the MSB of the 24-bit input frame marks the beginning of the write cycle,
and data are written to the addressed registers on the rising edge of LATCH.
8.5.1.5 Multiple Devices on the Bus
Communication with the device is not directly gated by LATCH; therefore, do not connect multiple devices in
parallel without gating SCLK. 图8-8 shows two devices with SCLK gated for each device.
CS1
SCLK
DIN
LATCH1
SCLK
SDO
DIN
DOUT
CS2
Device 1
Microcontroller
LATCH2
SCLK
SDO
DIN
Device 2
图8-8. Multiple Devices on the Bus Using Gated SCLK
The microcontroller uses two chip select lines, one for each LATCH pin. Each line is used to gate the SCLK for
communication for each device.
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8.6 Register Maps
表 8-11 shows the available registers on the DACx750 devices. See 节 8.6.1 for descriptions of all DACx750
registers.
表8-11. Command and Register Map
READ AND
WRITE
DATA BITS (DB15:DB0)
REGISTER OR
COMMAND
ACCESS
15:14
13
12
11
10:9
8
7
6
5
4
3
2
1
0
Control
RW
RW
RW
X
REXT
OUTEN
SRCLK
SRSTEP
SREN
Reserved
CRCEN
RANGE
Configuration
DAC Data(2)
No operation(3)
Read Operation (3)
Reset
X(1)
CALEN HARTEN
WDEN
WDPD
D15:D0
X
—
—
W
R
X
READ ADDRESS
RESET
T-FLT
Status
Reserved
CRC-FLT
WD-FLT
I-FLT
SR-ON
DAC Gain Calibration
RW
RW
G15:G0, unsigned
Z15:Z0, signed
(2)
DAC Zero Calibration
(2)
Watchdog Timer
Reset (3)
X
X
—
—
CRC Fault Reset (3)
(1) X denotes don't care bits.
(2) DAC8750 (16-bit version) shown. DAC7750 (12-bit version) contents are located in DB15:DB4.
For DAC7750, DB3:DB0 are don't care bits when writing and zeros when reading.
(3) No operation, read operation, watchdog timer reset, and CRC fault reset are commands and not registers.
8.6.1 DACx750 Register Descriptions
8.6.1.1 Control Register
The DACx750 control register is written to at address 0x55. 表8-12 shows the description for the control register
bits.
表8-12. Control Register
DATA BIT(S)
DB15:DB14
DB13
NAME
Reserved
REXT
DEFAULT
DESCRIPTION
Reserved. Do not write any value other than zero to these bits.
External current setting resistor enable.
00
0
Output enable.
DB12
OUTEN
0
Bit = 1: Output is determined by RANGE bits.
Bit = 0: Output is disabled. IOUT is Hi-Z.
DB11:DB8
DB7:DB5
SRCLK[3:0]
0000
000
Slew rate clock control. Ignored when bit SREN = 0.
Slew rate step size control. Ignored when bit SREN = 0.
SRSTEP[2:0]
Slew Rate Enable.
Bit = 1: Slew rate control is enabled, and the ramp speed of the output change is determined
by SRCLK and SRSTEP.
DB4
SREN
0
Bit = 0: Slew rate control is disabled. Bits SRCLK and SRSTEP are ignored. The output
changes to the new level immediately.
DB3
Reserved
0
Reserved. Must be set to 0.
Output range bits.
DB2:DB0
RANGE[2:0]
000
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8.6.1.2 Configuration Register
The DACx750 configuration register is written to at address 0x57. 表 8-13 summarizes the description for the
configuration register bits.
表8-13. Configuration Register
DATA BIT(S)
NAME
DEFAULT
DESCRIPTION
DB15:DB6
Reserved
00 0000 0000
Reserved. Do not write any value other than zero to these bits.
User calibration enable. When user calibration is enabled, the DAC data are
adjusted according to the contents of the gain and zero calibration registers. See
the 节8.3.10 section.
DB5
DB4
CALEN
0
0
Enable interface through HART-IN pin (only valid for IOUT set to 4-mA to 20-mA
range through RANGE bits).
Bit = 1: HART signal is connected through internal resistor and modulates output
current.
HARTEN
Bit = 0: HART interface is disabled.
DB3
DB2
CRCEN
WDEN
0
0
Enable frame error checking.
Watchdog timer enable.
Watchdog timeout period.
DB1:DB0
WDPD[1:0]
00
8.6.1.3 DAC Registers
The DAC registers consist of a DAC data register (表8-14), a DAC gain calibration register (表8-15), and a DAC
zero calibration register (表 8-16). User calibration as described in 节 8.3.10 is a feature that allows for trimming
the system gain and zero errors. 表 8-14 through 表 8-16 show the DAC8750, 16-bit version of these registers.
The DAC7750 (12-bit version) register contents are located in DB15:DB4. For DAC7750, DB3:DB0 are don't
care bits when writing and zeros when reading.
表8-14. DAC Data Register
DATA BITS
NAME
DEFAULT
DESCRIPTION
DB15:DB0
D15:D0
0x0000
DAC data register. Format is unsigned straight binary.
表8-15. DAC Gain Calibration Register
DATA BITS
NAME
DEFAULT
DESCRIPTION
DB15:DB0
G15:G0
0x0000
Gain calibration register for user calibration. Format is unsigned straight binary.
表8-16. DAC Zero Calibration Register
DATA BITS
NAME
DEFAULT
DESCRIPTION
DB15:DB0
Z15:Z0
0x0000
Zero calibration register for user calibration. Format is twos complement.
8.6.1.4 Reset Register
The DACx750 reset register is written to at address 0x56. 表8-17 provides the description.
表8-17. Reset Register
DATA BIT(S)
NAME
DEFAULT
DESCRIPTION
DB15:DB1
Reserved
000 0000 0000 0000 Reserved. Writing to these bits does not cause any change.
Software reset bit. Writing 1 to the bit performs a software reset that resets all
DB0
RESET
0
registers and the ALARM status to the respective power-on reset default value.
After reset completes, the RESET bit clears itself.
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8.6.1.5 Status Register
This read-only register consists of four ALARM status bits (CRC-FLT, WD-FLT, I-FLT, and T-FLT) and the SR-ON
bit that shows the slew rate status, as shown in 表8-18.
表8-18. Status Register
DATA BIT(S)
NAME
DEFAULT
DESCRIPTION
DB15:DB5
Reserved
000 0000 0000
Reserved. Reading these bits returns 0.
Bit = 1 indicates CRC error on SPI frame.
Bit = 0 indicates normal operation.
DB4
DB3
CRC-FLT
WD-FLT
0
0
Bit = 1 indicates watchdog timer timeout.
Bit = 0 indicates normal operation.
Bit = 1 indicates an open circuit or a compliance voltage violation in IOUT
loading.
DB2
I-FLT
0
Bit = 0 indicates IOUT load is at normal condition.
Bit = 1 when DAC code is slewing as determined by SRCLK and SRSTEP.
Bit = 0 when DAC code is not slewing.
DB1
DB0
SR-ON
T-FLT
0
0
Bit = 1 indicates die temperature is over 142°C.
Bit = 0 indicates die temperature is not over 142°C.
These devices continuously monitor the current output and die temperature. When an alarm occurs, the
corresponding ALARM status bit is set (1). Whenever an ALARM status bit is set, it remains set until the event
that caused it is resolved. The ALARM bit can only be cleared by performing a software reset, a power-on reset
(by cycling power), or by having the error condition resolved. These bits are reasserted if the alarm condition
continues to exist in the next monitoring cycle.
The ALARM bit goes to 0 when the error condition is resolved.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 HART Implementation
If desirable, the following subsections show two methods to implement HART, irrespective of the RANGE bit
settings.
9.1.1.1 Using the CAP2 Pin
The first method to implement HART is to couple the signal through the CAP2 pin, as shown in 图9-1.
C1
C2
HART FSK Input
CAP1
CAP2
AVDD
R3-SENSE
BOOST
R2
R3
T2
Þ
A2
+
12.5 kꢀ
T1
IOUT
12-/16-Bita__
DAC__a
+
A1
Þ
RSET
GND
图9-1. Implementing HART on IOUT Using the CAP2 Pin
In 图9-1, R3 is nominally 40 Ω, and R2 depends on the current output range (set by the RANGE bits), described
as follows:
• 4-mA to 20-mA range: R2 = 2.4 kΩ(typical)
• 0-mA to 20-mA range: R2 = 3 kΩ(typical)
• 0-mA to 24-mA range: R2 = 3.6 kΩ(typical)
The purpose of the 12.5-kΩresistor is to create a filter when CAP1 and CAP2 are used.
To insert the external HART signal on the CAP2 pin, an external ac-coupling capacitor is typically connected to
CAP2. The high-pass filter 3-dB frequency is determined by the resistive impedance looking into
CAP2 (R2 + 12.5 kΩ) and the coupling-capacitor value. The 3-dB frequency is 1 / (2 × π × [R2 + 12.5 kΩ] ×
[Coupling Capacitor Value]).
When the input HART frequency is greater than the 3-dB frequency, the ac signal is seen at the plus input of
amplifier A2, and is therefore seen across the 40-Ω resistor. To generate a 1-mA signal on the output therefore
requires a 40-mV peak-to-peak signal on CAP2. Most HART modems do not output a 40-mV signal; therefore, a
capacitive divider is used in 图 9-1 to attenuate the FSK signal from the modem. In 图 9-1, the high-pass cutoff
frequency is 1 / (2 × π × [R2+ 12.5 kΩ] × [C1 + C2]). There is one disadvantage to this approach: if the AVDD
supply is not clean, any ripple on the supply could couple into the device.
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9.1.1.2 Using the ISET-R Pin
The second method to implement HART is to couple the HART signal through the ISET-R pin when IOUT is
operated using an external RSET resistor. The FSK signal from the modem is ac-coupled into the pin through a
series combination of Rin and Cin as shown in 图9-2.
HART-IN
CAP2
CAP1
AVDD
(ON Only in 4-mA
to 20-mA Range)
S1
R3-SENSE
BOOST
R3
HART
Signal
Conditioning
R2
R1
A2
+
T2
IOUT
DAC
+
A1
T1
ISET-R
Cin
Rin
HART SIGNAL
RSET
15 kΩ
图9-2. Implementing HART with the ISET-R pin
The magnitude of the ac-current output is calculated with 方程式6.
(VHART × k) / Rin
(6)
where
• VHART is the amplitude of the HART FSK signal from the modem
• k is a constant that represents the gain transfer function from the ISET-R pin to the IOUT pin and depends on
the selected current output range as follows:
– k = 60 for the 4-mA to 20-mA range
– k = 75 for the 0-mA to 20-mA range
– k = 90 for the 0-mA to 24-mA range
The series input resistor and capacitor form a high-pass filter at the ISET-R pin. Select Cin to make sure that all
signals in the HART extended-frequency band pass through unattenuated.
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9.2 Typical Application
Isolation
Field
Barrier
Connections
+24V
+24V Field Supply Input
+24V
10 Ω
Field GND
100pF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
10k
DVDD-EN
DVDD
AVDD
VCC2
VDD
VCC1
OUTC
GPIO
GPIO
CS
ALARM
CLR
INC
INA
OUTA
ISO7631
+24V
INB
OUTB
LATCH
GND1
GND2
Unidirectional
TVS Diode Pair
15
Current Output
0-20mA, 4-20mA, 0-24mA
100nF
IOUT
Digital Controller
DACX750
0.1µF
0.1µF
VCC2
INC
VCC1
OUTC
SDO
DIN
MISO
OUTA
INA
ISO7631
MOSI
SCLK
SCLK
OUTB
INB
GND2
GND
GND1
HART-IN
22nF
GND
REFIN
REFOUT
HART Signal
FSK 1200-
2200Hz
0.1µF
图9-3. DACx750 in a Voltage and Current Output Driver for Factory Automation and Control, EMC and
EMI Protected - DACx750 in an Analog Output (AO) Module
9.2.1 Design Requirements
Analog I/O modules are used by programmable logic controllers (PLCs) and distributed control systems (DCSs)
to interface to sensors, actuators, and other field instruments. These modules must meet stringent electrical
specifications for both performance as well as protection. These outputs are typically current loops based on the
4-mA to 20-mA range. Common error budgets accommodate 0.1% full-scale range total unadjusted error
(%FSR TUE) at room temperature. Designs which desire stronger accuracy over temperature frequently
implement calibration. Often times the PLC back-plane provides access to a 12-V to 36-V analog supply, from
which a majority of supply voltages are derived.
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9.2.2 Detailed Design Procedure
图9-4 illustrates a common generic solution for realizing these desired voltage and current output spans.
15V
RA
RB
5V
15V
AVDD
A2
CS
DIN
+
15V
A1
Q2
-15V
Q1
+
SCLK
LDAC
IOUT
-15V
GND VREFIN/VREFOUT
RSET
GND
图9-4. Generic Design for Typical PLC Current and Voltage Outputs
The current output circuit is comprised of amplifiers A1 and A2, MOSFETs Q1 and Q1, and the three resistors
RSET, RA, and RB. This two-stage current source enables the ground-referenced DAC output voltage to drive the
high-side amplifier required for the current-source.
The high-level of integration of the DACx750 family lends itself very well to the design of analog output modules,
offering simplicity of design and reducing solution size. The DACx750 integrates all of the components shown in
图9-4 allowing a software configurable current output driver. 图9-3 illustrates an example circuit design for such
an application using the DACx750 for the current output driver.
The design uses two triple channel isolators (ISO7631FC) to provide galvanic isolation for the digital lines to
communicate to the main controller. Note that these isolators can be driven by the internally-generated supply
(DVDD) from the DACx750 to save components and cost. The DACx750 supplies up to 10 mA that meets the
supply requirements of the two isolators running at up to 10 Mbps. Note that additional cost savings are possible
if noncritical digital signals such as CLR and ALARM are tied to GND or left unconnected. Finally, a protection
scheme with transient voltage suppressors and other components is placed on all pins which connect to the
field.
The protection circuitry is designed to provide immunity to the IEC61000-4 test suite which includes system-level
industrial transient tests. The protection circuit includes transient voltage suppressor (TVS) diodes, clamp-to-rail
steering diodes, and pass elements in the form of resistors and ferrite beads. For more detail about selecting
these components, see the Single-Channel Industrial Voltage and Current Output Driver, Isolated, EMC/EMI
Tested Reference Design.
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9.2.3 Application Curve
The current output circuit was measured in 0-mA to 24-mA mode using an 8.5 digit digital multimeter to measure
the output while driving a 300-Ω load at 25°C. The measured results are illustrated in 图 9-5. The current output
remains within the data sheet specified performance.
The design was also exposed to IEC61000-4 electrostatic discharge, electrically fast transient, conducted
immunity, and radiated immunity tests on both the current and voltage outputs. During each of these tests a 6.5
digit digital multimeter, set in fast 5.5 digit acquisition mode, was used to monitor the output. Complete data sets
for the voltage and current outputs during these tests are available in the Single-Channel Industrial Voltage and
Current Output Driver, Isolated, EMC/EMI Tested Reference Design.
0
-0.005
-0.01
-0.015
-0.02
-0.025
-0.03
-0.035
-0.04
-0.045
0
16384
32768
DAC Input Code
49152
65536
D002
图9-5. Current Output TUE vs Code
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10 Power Supply Recommendations
The DACx750 family operates within the specified single-supply range of 10 V to 36 V applied to the AVDD pin.
The digital supply, DVDD, operates within the specified supply range of 2.7 V to 5.5 V or powered by the internal
4.6-V LDO, as described in 节8.3.4.
Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create similar high-frequency spikes. This noise can be easily
coupled into the DAC output voltage or current through various paths between the power connections and
analog output. To further reduce noise, include bulk and local decoupling capacitors.
CAUTION
Do not ramp the supplies for the DACx750 faster than 1 V/ns or damage may result to the device. A
10-Ωseries resistor from the analog supply to the device AVDD connection helps reduce the supply
ramp.
The DACx750 has internal power on reset (POR) circuitry for both the digital DVDD and analog AVDD supplies.
This circuitry makes sure that the internal logic and power-on state of the DAC power up to the proper state
independent of the supply sequence. The recommended power-supply sequence is to first have the analog
AVDD supply come up, followed by the digital DVDD supply. DVDD can come up first as long as AVDD ramps to
at least 5 V within 50 μs. If neither condition can be satisfied, issue a software reset command using the SPI
bus after both AVDD and DVDD are stable.
The current consumption on the AVDD pin and current ranges for the current output are listed in 节 7.5. The
power supply must meet the requirements listed in 节7.5.
11 Layout
11.1 Layout Guidelines
To maximize the performance of the DACx750 in any application, good layout practices and proper circuit design
must be followed. A few recommendations specific to the DACx750 are:
• As illustrated in 图9-1, CAP2 is directly connected to the input of the final IOUT amplifier. Any noise or
unwanted ac signal routed near the CAP1 and CAP2 pins could capacitively couple onto internal nodes and
affect IOUT. Therefore, make sure to avoid routing any digital or HART signal traces over the CAP1 and
CAP2 traces.
• Connect the thermal PAD to the lowest potential in the system.
• Make sure that AVDD has decoupling capacitors local to the respective pins.
• Place the reference capacitor close to the reference input pin.
• Avoid routing switching signals near the reference input.
• For designs that include protection circuits:
– Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure
that return current from high-energy transients does not cause damage to sensitive devices.
– Use large, wide traces to provide a low-impedance path to divert high-energy transients away from I/O
pins.
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11.1.1 Thermal Considerations
The DACx750 is designed for a maximum junction temperature of 150°C. In cases where the maximum AVDD is
driving maximum current into ground, this junction temperature can be exceeded. Use 方程式 7 to determine the
maximum junction temperature that can be reached.
Power dissipation = (TJ max –TA) / θJA
(7)
where
• TJ max = 150°C
• TA is the ambient temperature
• θJA is the package-dependent, junction-to-ambient thermal resistance, found in 节7.4.
The power dissipation is calculated by multiplying all the supply voltages with the currents supplied, which are
found in the Power Requirements subsection of 节7.5.
Consider an example: IOUT is enabled, supplying 24 mA into GND with a 25°C ambient temperature, AVDD of
24 V, and DVDD is generated internally. From the 节 7.5, the max value of AIDD = 3 mA when IOUT is enabled
and DAC code = 0x0000. Also, the max value of DIDD = 1 mA. Accordingly, the worst-case power dissipation is
24 V × (24 mA + 3 mA + 1 mA) = 672 mW. Using the θJA value for the TSSOP package, we get TJ max = 25°C
+ (32.3 × 0.672)°C = 46.7°C. At 85°C ambient temperature, the corresponding value of TJ max is 106.7°C. Using
this type of analysis, the system designer can both specify and design for the equipment operating conditions.
Note that for enhanced thermal performance, connect the thermal pad in both packages to a copper plane.
11.2 Layout Example
图 11-1 shows an example layout for the DACx750 device based on a similar layout for the DACx760 from
TIPD153.
GND
AVDD
DVDD
Analog Supply
Series Resistance
Digital
Supply
Analog
Supply
Decoupling
Decoupling
External
Boost Transistor
(Optional)
ALARM
Pull-up
Resistance
CAP1 / CAP2
Capacitance
(Optional)
Q1
Digital I/O
IOUT
0
R3-SENSE
Reference
Capacitance
External RSET
(Optional)
HART
Input
图11-1. Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Single-Channel Industrial Voltage & Current Output Driver, Isolated, EMC/EMI Tested
Reference Design
• Texas Instruments, Implementing HART™ Communication with the DAC8760 Family
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
HART® is a registered trademark of HART Communication Foundation.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DAC7750 DAC8750
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC7750IPWP
DAC7750IPWPR
DAC7750IRHAR
DAC7750IRHAT
DAC8750IPWP
DAC8750IPWPR
DAC8750IRHAR
DAC8750IRHAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
VQFN
PWP
PWP
RHA
RHA
PWP
PWP
RHA
RHA
24
24
40
40
24
24
40
40
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DAC7750
2000 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
DAC7750
DAC7750
DAC7750
DAC8750
DAC8750
DAC8750
DAC8750
VQFN
250
60
RoHS & Green
RoHS & Green
HTSSOP
HTSSOP
VQFN
2000 RoHS & Green
2500 RoHS & Green
VQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC7750IPWPR
DAC7750IRHAT
DAC8750IPWPR
HTSSOP PWP
VQFN RHA
HTSSOP PWP
24
40
24
2000
250
330.0
180.0
330.0
16.4
16.4
16.4
6.95
6.3
8.3
6.3
8.3
1.6
1.1
1.6
8.0
12.0
8.0
16.0
16.0
16.0
Q1
Q2
Q1
2000
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC7750IPWPR
DAC7750IRHAT
DAC8750IPWPR
HTSSOP
VQFN
PWP
RHA
PWP
24
40
24
2000
250
350.0
210.0
350.0
350.0
185.0
350.0
43.0
35.0
43.0
HTSSOP
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DAC7750IPWP
DAC8750IPWP
PWP
PWP
HTSSOP
HTSSOP
24
24
60
60
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
GENERIC PACKAGE VIEW
PWP 24
4.4 x 7.6, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024J
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
22X 0.65
PLANE
24
1
2X
7.9
7.7
7.15
NOTE 3
12
B
13
0.30
24X
4.5
4.3
0.19
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 2.08 MAX
NOTE 5
4X 0.3 MAX
13
4X 0.1 MAX
NOTE 5
12
0.25
GAGE PLANE
1.2 MAX
5.26
5.11
25
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
24
3.20
3.05
4225860/A 04/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0024J
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.2)
METAL COVERED
BY SOLDER MASK
SYMM
24X (1.5)
1
24
24X (0.45)
SEE DETAILS
(R0.05) TYP
(5.26)
22X (0.65)
SYMM
25
(7.8)
NOTE 9
(1.2) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
13
12
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4225860/A 04/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024J
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.2)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
24X (1.5)
1
24
24X (0.45)
(R0.05) TYP
22X (0.65)
SYMM
(5.26)
25
BASED ON
0.125 THICK
STENCIL
12
13
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.58 X 5.88
3.20 X 5.26 (SHOWN)
2.92 X 4.80
0.125
0.15
0.175
2.70 X 4.45
4225860/A 04/2020
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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