DAC81416 [TI]
具有集成内部基准电压的 16 通道 16 位高电压输出 DAC;
| 型号： | DAC81416 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成内部基准电压的 16 通道 16 位高电压输出 DAC |
| 文件： | 总59页 (文件大小：3240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC81416, DAC71416, DAC61416
ZHCSIG7B –JULY 2018 –REVISED JUNE 2021
具有内部基准电压的DACx1416 16 通道16 位、14 位和12 位
高电压输出DAC
1 特性
3 说明
• 高性能
DAC81416、DAC71416 和 DAC61416 (DACx1416)
是具有引脚兼容性和16 位、14 位、12 位分辨率的 16
通道缓冲高电压输出数模转换器 (DAC) 系列产品。
DACx1416 包括一个低漂移 2.5V 内部电压基准，因此
在大多数应用中无需使用外部精密基准。这些器件具有
单调性，并能提供±1LSB INL 的高线性度。
– 在16 位分辨率下具有单调性
– INL：16 位分辨率下为±1LSB（最大值）
– TUE：FSR 最大值的±0.1%
• 集成2.5V 精密内部基准
– 初始精度：±2.5 mV（最大值）
– 低漂移：5ppm/°C（典型值）
• 灵活的输出配置
用户可自行选择输出配置，包括满量程双极输出电压
±20V、±10V、±5V 或 ±2.5V，以及满量程单极输出电
压 40V、20V、10V 和 5V。而且，每个 DAC 通道的
满量程输出范围都是独立可编程的。集成的 DAC 输出
缓冲器可实现高达 25 mA 的灌电流或拉电流，从而减
少了对额外的运算放大器的需求。每个通道对都可进行
相应配置，从而提供经过失调校准的差分输出。通过三
个专用 A-B 切换引脚，可以生成最多具有三种频率的
抖动信号。
– 输出范围：±2.5V、±5V、±10V、±20V
0 至5V、0 至10V、0 至20V、0 至40V
– 差分输出模式
• 高驱动能力：±25mA，相对于电源轨的摆幅为1.5V
• 三个专用A-B 切换引脚可用于生成抖动信号
• 模拟温度输出
– -4 mV/°C 的传感器增益
• 50MHz SPI 兼容型串行接口
DACx1416 包含的上电复位电路可在上电时将 DAC 输
出端连接至接地端。输出端会保持该状态，直至器件寄
存器得到适当的运行配置。
– 4 线制模式，工作电压为1.7V 至5.5V
– 菊花链运行方式
– CRC 误差校验
与 DACx1416 之间的通信通过一个支持 1.7V 至 5.5V
工作电压的4 线制串行接口进行。
• 温度范围：–40°C 至+125°C
• 小封装
– 6mm × 6mm，40 引脚VQFN
器件信息
封装(1)
封装尺寸（标称值）
器件型号
DAC81416
2 应用
• 数据中心内部互联（长距离、水下）
• 数据中心间互联（地铁）
• 光学模块
DAC71416
DAC61416
VQFN (40)
6.00mm × 6.00mm
• 半导体测试
• 实验室和现场仪表
• 数据采集(DAQ)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
REF
REFCMP REFGND
VIO
VAA
VDD
VCC
Internal
Reference
DAC
Buffer
DAC
Register
SCLK
SDI
Range Config
SDO
DAC
BUF
OUT0
CS
LDAC
Channel 0
Channel 1
RESET
OUT1
CLR
TOGGLE0
TOGGLE1
TOGGLE2
Channel 15
OUT15
Power Down Logic
Resistive Network
ALMOUT
Power On Reset
Temperature Sensor
TEMPOUT
DACx1416
GND
VSS
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEO0
DAC81416, DAC71416, DAC61416
ZHCSIG7B –JULY 2018 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
8.5 Programming............................................................ 29
8.6 Register Maps...........................................................32
9 Application and Implementation..................................47
9.1 Application Information............................................. 47
9.2 Typical Application.................................................... 47
10 Power Supply Recommendations..............................51
11 Layout...........................................................................52
11.1 Layout Guidelines................................................... 52
11.2 Layout Example...................................................... 52
12 Device and Documentation Support..........................53
12.1 Device Support....................................................... 53
12.2 Documentation Support.......................................... 53
12.3 接收文档更新通知................................................... 53
12.4 支持资源..................................................................53
12.5 Trademarks.............................................................53
12.6 Electrostatic Discharge Caution..............................53
12.7 术语表..................................................................... 53
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Timing Requirements ............................................... 11
7.7 Timing Diagrams.......................................................13
7.8 Typical Characteristics..............................................14
8 Detailed Description......................................................23
8.1 Overview...................................................................23
8.2 Functional Block Diagram.........................................23
8.3 Feature Description...................................................24
8.4 Device Functional Modes..........................................27
Information.................................................................... 53
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (November 2018) to Revision B (June 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 为清晰起见，更改了格式和小的编辑问题...........................................................................................................1
Changes from Revision * (July 2018) to Revision A (November 2018)
Page
• 将DAC81416 从“预告信息”更改为“量产数据”...........................................................................................1
• 将DAC71416 和DAC61416 从“产品预发布”更改为“量产数据”................................................................ 1
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5 Device Comparison Table
DEVICE
RESOLUTION
16-bit
DAC81416
DAC71416
DAC61416
14-bit
12-bit
6 Pin Configuration and Functions
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VIO
1
30
29
28
27
26
25
24
23
22
21
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
2
3
4
5
6
Thermal Pad
7
8
OUT8
9
TEMPOUT
ALMOUT
GND
10
Not to scale
图6-1. RHA Package, 40-Pin VQFN, Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VIO
Output
Output
Output
Output
Output
Output
Output
Output
Power
Ground
Channel 0 analog DAC output voltage.
Channel 1 analog DAC output voltage.
Channel 2 analog DAC output voltage.
Channel 3 analog DAC output voltage.
Channel 4 analog DAC output voltage.
Channel 5 analog DAC output voltage.
Channel 6 analog DAC output voltage.
Channel 7 analog DAC output voltage.
2
3
4
5
6
7
8
9
IO supply voltage. (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the device.
Ground reference point for all circuitry on the device.
10, 36
GND
Serial interface data output. The SDO pin must be enabled before operation by setting the SDO-EN bit.
Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified
by the FSDO bit (rising edge by default).
11
SDO
Output
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表6-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
12
SCLK
Input
Input
Serial interface clock.
Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK
pin.
13
14
SDI
CS
Active low serial data enable. This input is the frame synchronization signal for the serial data. When the
signal goes low, it enables the serial interface input shift register.
Input
Input
Toggle pin 0. Control signal for those DAC outputs configured for toggle operation to switch between the
two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set
by Register A. A logic high updates the DAC output to the value set by Register B. Connect the
TOGGLE0 pin to ground if unused.
15
16
17
TOGGLE0
TOGGLE1
TOGGLE2
Toggle pin 1. Control signal for those DAC outputs configured for toggle operation to switch between the
two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set
by Register A. A logic high updates the DAC output to the value set by Register B. Connect the
TOGGLE1 pin to ground if unused.
Input
Input
Toggle pin 2. Control signal for those DAC outputs configured for toggle operation to switch between the
two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set
by Register A. A logic high updates the DAC output to the value set by Register B. Connect the
TOGGLE2 pin to ground if unused.
Active low synchronization signal. When the LDAC pin is low, the DAC outputs of those channels
configured in synchronous mode are updated simultaneously. Connect to VIO if unused.
18
19
20
LDAC
RESET
CLR
Input
Input
Input
Active low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
Active low clear input. Logic low on this pin clears all DAC outputs to their clear code. Connect to VIO if
unused.
ALMOUT is an open drain alarm output. An external 10-kΩ pull-up resistor to a voltage no higher than VIO
is required.
21
ALMOUT
Output
22
TEMPOUT
OUT8
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Analog temperature monitor output.
23
Channel 8 analog DAC output voltage.
Channel 9 analog DAC output voltage.
Channel 10 analog DAC output voltage.
Channel 11 analog DAC output voltage.
Channel 12 analog DAC output voltage.
Channel 13 analog DAC output voltage.
Channel 14 analog DAC output voltage.
Channel 15 analog DAC output voltage.
Output positive analog power supply (9 V to 41.5 V).
Output negative analog power supply (–21.5 V to 0 V).
24
OUT9
25
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
VCC
26
27
28
29
30
31, 40
32, 39
VSS
Reference input to the device when operating with external reference. When using internal reference, this
is the reference output voltage pin. Connect a 150-nF capacitor to ground.
33
34
REF
Input/Output
Input/Output
Reference compensation capacitor connection. Connect a 330-pF capacitor between REFCMP and
REFGND.
REFCMP
35
37
38
REFGND
VAA
Ground
Power
Power
Ground reference point for the internal reference.
Analog supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VDD pin.
Digital supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VAA pin.
VDD
The thermal pad is located on the package underside. Connect the thermal pad to any internal PCB
ground plane through multiple vias for good thermal performance.
Thermal Pad
Thermal Pad
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–22
MAX
UNIT
V
VDD to GND
VIO to GND
VCC to GND
6
6
V
44
V
Supply voltage
VSS to GND
0.3
V
REFGND to GND
VDD to VAA
0.9
V
–0.3
–0.3
–0.3
VSS –0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
0.3
V
VCC to VSS
44
V
DAC outputs to GND
TEMPOUT to GND
REF and REFCMP to GND
Digital inputs to GND
SDO to GND
VCC + 0.3
VDD + 0.3
VDD + 0.3
VIO + 0.3
VIO + 0.3
6
V
V
V
Pin voltage
V
V
ALARMOUT to GND
Operating junction temperature
Storage temperature
V
TJ
150
°C
°C
Tstg
150
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4.5
1.7
9
NOM
MAX
5.5
5.5
5.5
41.5
0
UNIT
V
(1)
(1)
VAA
VDD
VIO
Analog supply voltage
Digital supply voltage
V
IO supply voltage
V
VCC
VSS
Output buffer positive supply voltage
Output buffer negative supply voltage
Output buffer supply voltage range
Digital input voltage
V
(2)
V
–21.5
9
43
V
VCC –VSS
0
VIO
2.51
0.6
125
V
VREFIN
Reference input voltage to VREFGND
REFGND pin voltage
2.49
0
2.5
0
V
(3)
VREFGND
V
TA
Operating ambient temperature
°C
–40
(1) VAA and VDD must be at the same potential.
(2) VSS is only connected to GND when all DAC outputs are unipolar.
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(3) If VREFGND is not connected to GND, a buffered source must be used to drive it.
7.4 Thermal Information
DACx1416
RHA (VQFN)
40 PINS
26.8
THERMAL METRIC(1)
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
RΘJC(top)
RΘJB
14.1
3.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJT
3.4
ΨJB
RΘJC(bot)
0.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
all minimum/maximum specifications at TA = –40℃to +125℃and all typical specifications at TA = 25℃, VCC = 9 V to 41.5
V, VSS = –21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, digital
inputs at VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC PERFORMANCE(1)
DAC81416
16
14
12
Resolution
DAC71416
DAC61416
Bits
DAC81416, all ranges, except 0 V to 40
V and ±2.5 V
±0.5
±1
1
–1
–2
DAC81416, 0 V to 40 V and ±2.5-V
ranges
2
INL
Integral nonlinearity
LSB
DAC71416, all ranges
DAC61416, all ranges
DAC81416, specified 16-bit monotonic
DAC71416, specified 14-bit monotonic
DAC61416, specified 12-bit monotonic
All ranges, except ±2.5 V
±2.5-V range
±0.5
±0.5
1
1
1
–1
–1
±0.5
–1
DNL
TUE
Differential nonlinearity
Total unadjusted error
±0.5
1
1
LSB
–1
±0.5
–1
±0.01
±0.02
±0.015
0.04
0.1
0.2
–0.1
–0.2
–0.03
0
%FSR
Unipolar offset error
Unipolar zero-code error
Bipolar zero error
All unipolar ranges
0.03 %FSR
0.1 %FSR
0.2 %FSR
0.2 %FSR
All unipolar ranges
All bipolar ranges
±0.02
±0.075
±0.02
±0.02
–0.2
–0.2
–0.1
–0.2
Full-scale error
All ranges
All ranges, except ±2.5 V
±2.5-V range
0.1
%FSR
0.2
Gain error
ppm of
FSR/°C
Unipolar offset error drift
Bipolar zero error drift
Gain error drift
All unipolar ranges
All bipolar ranges
All ranges
±2
±2
±2
ppm of
FSR/°C
ppm of
FSR/°C
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7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40℃to +125℃and all typical specifications at TA = 25℃, VCC = 9 V to 41.5
V, VSS = –21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, digital
inputs at VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ppm of
FSR
Output voltage drift over time TA = 40°C, full-scale code, 1900 hours
5
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7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40℃to +125℃and all typical specifications at TA = 25℃, VCC = 9 V to 41.5
V, VSS = –21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, digital
inputs at VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIFFERENTIAL MODE PERFORMANCE(1)
All ranges
±0.01
±0.02
±0.01
0.1
–0.1
–0.2
–0.1
TUE
Total unadjusted error
%FSR
0.2
±2.5-V range
Common-mode error
All bipolar ranges, midscale code
0.1 %FSR
OUTPUT CHARACTERISTICS
To VSS and VCC
(–10 mA ≤IOUT ≤10 mA)
1
Output voltage headroom
V
To VSS and VCC
(–15 mA ≤IOUT ≤15 mA)
1.5
Full-scale output shorted to VSS
Zero-scale output shorted to VCC
40
40
Short-circuit current(2)
mA
Midscale code, –15 mA ≤IOUT ≤15
mA
Load regulation
70
μV/mA
Maximum capacitive load(3)
RLOAD = open
Midscale code
Full-scale code
0
1
nF
0.05
40
DC output impedance
Ω
DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale settling
time to ±1 LSB, ±10-V range,
RL = 5 kΩ, CL = 200 pF
Output voltage settling time
Slew rate
12
µs
V/µs
V
0-V to 5-V range
1
4
All other output ranges
Power-down to active DAC output,
±20 V range, midscale code,
RL = 5 kΩ, CL = 200 pF
Power-on glitch magnitude
0.3
0.1 Hz to 10 Hz, midscale code,
0-V to 5-V range
Output noise
15
78
µVpp
Output noise density
1 kHz, midscale code, 0-V to 5-V range
nV/Hz
Midscale code, frequency = 60 Hz,
amplitude = 200 mVpp superimposed
on VDD, VCC or VSS
Power supply ac rejection
ratio
PSRR-AC
PSRR-DC
1
LSB/V
LSB/V
Midscale code, VDD = 5 V ± 5%,
VCC = 20 V, VSS = –20 V
1
1
1
4
Midscale code, VDD = 5 V,
VCC = 20 V ± 5%, VSS = –20 V
Power supply dc rejection
ratio
Midscale code, VDD = 5 V,
VCC = 20 V, VSS = –20 V ± 5%
1-LSB change around major carrier,
0-V to 5-V range
Code change glitch impulse
nV-s
nV-s
0-V to 5-V range, measured channel at
midscale, full-scale swing on all other
channels
Channel-to-channel ac
crosstalk
4
Channel-to-channel dc
crosstalk
0-V to 5-V range, measured channel at
midscale, all other channels at full-scale
0.25
1
LSB
nV-s
0-V to 5-V range, midscale code,
fSCLK = 1 MHz
Digital feedthrough
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7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40℃to +125℃and all typical specifications at TA = 25℃, VCC = 9 V to 41.5
V, VSS = –21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, digital
inputs at VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EXTERNAL REFERENCE INPUT
Reference input voltage
VREFIN
range
To VREFGND
2.49
2.5
2.51
V
Reference input current
Reference input impedance
Reference input capacitance
INTERNAL REFERENCE
50
50
20
µA
kΩ
pF
Reference output voltage
VREFOUT
range
TA = 25°C
2.4975
2.5025
V
Reference output drift
5
0.1
12
15 ppm/°C
Reference output impedance
Reference output noise
Ω
0.1 Hz to 10 Hz
µVpp
Reference output noise
density
10 kHz, REFLOAD = 10 nF
150
nV/Hz
Reference load current
Reference load regulation
Reference line regulation
5
80
20
mA
Source
µV/mA
µV/V
Reference output drift over
time
TA = 25°C, 1900 hours
250
µV
µV
First cycle
±700
±50
Reference thermal hysteresis
Additional cycle
DIGITAL INPUTS AND OUTPUTS
VIH
VIL
High-level input voltage
Low-level input voltage
Input current
0.7 × VIO
V
0.3 × VIO
V
µA
pF
V
±2
2
Input pin capacitance
High-level output voltage
Low-level output voltage
Output pin capacitance
VOH
VOL
IOH = 0.2 mA
IOL = 0.2 mA
VIO –0.2
0.4
0.4
V
5
5
pF
ALARM OUTPUT
Output pin capacitance
Low-level output voltage
TEMPERATURE OUTPUT
pF
V
VOL
ILOAD = –0.2 mA
VTEMPOUT,0C
1.34
V
Output voltage offset at 0℃
Sensor gain
mV/°C
–4
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7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40℃to +125℃and all typical specifications at TA = 25℃, VCC = 9 V to 41.5
V, VSS = –21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, digital
inputs at VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER REQUIREMENTS
Active mode, internal reference
enabled, full-scale code, ±20 V output
range, SPI static
0.05
0.5
mA
IDD
IAA
ICC
VDD supply current
VAA supply current
VCC supply current
Active mode, internal reference
disabled, full-scale code, ±20 V output
range, SPI static
0.05
0.05
20
0.5
0.5
30
mA
mA
mA
Power-down mode
Active mode, internal reference
enabled, full-scale code, ±20 V output
range, SPI static
Active mode, internal reference
disabled, full-scale code, ±20 V output
range, SPI static
18
2
28
85
25
mA
µA
Power-down mode
Active mode, internal reference
enabled, full-scale code, ±20 V output
range, SPI static
10
mA
Active mode, internal reference
disabled, full-scale code, ±20 V output
range, SPI static
10
10
25
30
mA
µA
Power-down mode
Active mode, internal reference
enabled, full-scale code, ±20 V output
range, SPI static
mA
–15
–10
Active mode, internal reference
disabled, full-scale code, ±20 V output
range, SPI static
ISS
VSS supply current
VIO supply current
mA
–15
–30
–10
Power-down mode
µA
µA
–10
IIO
SCLK and SDI toggling at 50 MHz
350
500
(1) End point fit between codes. 16-bit: Code 256 to 65280, 14-bit: Code 128 to 16256, 12-bit: Code 32 to 4064.
(2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified
maximum junction temperature may impair device reliability.
(3) Specified by design and characterization, not production tested.
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7.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
SERIAL INTERFACE - WRITE OPERATION
VIO = 1.7 V to 2.7 V
25
f(SCLK)
Serial clock frequency
SCLK high time
SCLK low time
SDI setup time
SDI hold time
MHz
50
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
20
10
20
10
10
5
tSCLKHIGH
tSCLKLOW
tSDIS
ns
ns
ns
ns
ns
ns
ns
µs
µs
10
5
tSDIH
30
15
10
5
CS to SCLK falling edge
setup time
tCSS
SCLK falling edge to CS
rising edge
tCSH
50
25
2.4
2.4
4
tCSHIGH
tDACWAIT
tBCASTWAIT
CS hight time
Sequential DAC update wait
time
Broadcast DAC update wait
time
4
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 0
VIO = 1.7 V to 2.7 V
15
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
Serial clock frequency
SCLK high time
SCLK low time
SDI setup time
SDI hold time
MHz
20
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
33
25
33
25
10
5
ns
ns
ns
ns
ns
ns
ns
10
5
tSDIH
30
20
8
CS to SCLK falling edge
setup time
tCSS
SCLK falling edge to CS
rising edge
tCSH
5
50
25
0
tCSHIGH
tSDOZD
tSDODLY
CS high time
20
ns
20
SDO tri-state to driven
SDO output delay
0
0
35
ns
20
0
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MAX UNIT
7.6 Timing Requirements (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 1
VIO = 1.7 V to 2.7 V
25
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
Serial clock frequency
SCLK high time
SCLK low time
SDI setup time
SDI hold time
MHz
35
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
20
14
20
14
10
5
ns
ns
ns
ns
ns
ns
ns
10
5
tSDIH
30
20
8
CS to SCLK falling edge
setup time
tCSS
SCLK falling edge to CS
rising edge
tCSH
5
50
25
0
tCSHIGH
tSDOZD
tSDODLY
CS high time
20
ns
20
SDO tri-state to driven
SDO output delay
0
0
35
ns
20
0
DIGITAL LOGIC
CS rising edge to LDAC or
tLOGDLY
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
40
20
CLR falling edge delay time
ns
CS rising edge to LDAC or
CLR falling edge delay time
tLOGDLY
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
20
10
20
10
tLDAC
LDAC low time
CLR low time
ns
ns
tCLR
1
tRESET
POR reset delay
TOGGLE frequency
ms
1
100
kHz
100
fTOGGLE
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7.7 Timing Diagrams
tCSHIGH
tCSS
tCSH
CS
SCLK
SDI
tSCLKLOW
tSCLKHIGH
Bit 23
Bit 1
Bit 0
tSDIH
tSDIS
图7-1. Serial Interface Write Timing Diagram
tCSHIGH
tCSS
tCSH
CS
tSCLKLOW tSCLKHIGH
SCLK
FIRST READ COMMAND
ANY COMMAND
Bit 1
SDI
Bit 23
Bit 22
Bit 0
Bit 23
Bit 0
tSDIS tSDIH
SDO
Bit 23
Bit 1
Bit 0
FSDO = 0
tSDODLY
tSDODZ
DATA FROM FIRST READ COMMAND
SDO
Bit 23
Bit 1 Bit 0
FSDO = 1
tSDODLY
DATA FROM FIRST READ COMMAND
图7-2. Serial Interface Read Timing Diagram
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7.8 Typical Characteristics
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
1.0
0.8
1.0
0.8
2.5V
5V
10V
20V
0-5V
0-10 V
0-20 V
0-40 V
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D002
D001
图7-4. Integral Linearity Error vs Digital Input Code (Unipolar
图7-3. Integral Linearity Error vs Digital Input Code (Bipolar
Outputs)
Outputs)
1.0
1.0
2.5V
5V
10V
20V
0-5V
0-10 V
0-20 V
0-40 V
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D003
D004
图7-5. Differential Linearity Error vs Digital Input Code (Bipolar
图7-6. Differential Linearity Error vs Digital Input Code
Outputs)
(Unipolar Outputs)
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
0.100
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
0.100
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
2.5V
5V
10V
20V
0-5V
0-10 V
0-20 V
0-40 V
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D005
D006
图7-7. Total Unadjusted Error vs Digital Input Code (Bipolar
图7-8. Total Unadjusted Error vs Digital Input Code (Unipolar
Outputs)
Outputs)
0.0500
0.0500
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
2.5V
5V
10V
20V
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
-0.0375
-0.0500
-0.0375
-0.0500
0-5 V
0-10 V
0-20 V
0-40 V
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D007
D008
图7-9. Common Mode Error vs Digital Input Code (Differential
图7-10. Common Mode Error vs Digital Input Code (Differential
Bipolar Outputs)
Unipolar Outputs)
1.0
1.0
INL MAX
INL MIN
DNL MAX
DNL MIN
0.8
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D009
D010
±20-V output range
±20-V output range
图7-11. Integral Linearity Error vs Temperature
图7-12. Differential Linearity Error vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
0.100
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
0-5 V
2.5 V
5 V
10 V
20 V
0-5 V
0-10 V
0-20 V
0-40 V
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D011
D012
图7-13. Total Unadjusted Error vs Temperature
图7-14. Unipolar Offset Error vs Temperature
0.10
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
0-5 V
2.5 V
5 V
10 V
20 V
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D014
D013
图7-16. Bipolar Zero Error vs Temperature
图7-15. Unipolar Zero Code Error vs Temperature
0.100
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
2.5 V
5 V
10 V
20 V
0-5 V
2.5 V
5 V
10 V
20 V
0-5 V
0-10 V
0-20 V
0-40 V
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D015
D016
图7-17. Gain Error vs Temperature
图7-18. Full-Scale Error vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
0.0500
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
-0.0375
-0.0500
0.0500
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
-0.0375
-0.0500
2.5 V
5 V
10 V
20 V
0-5 V
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D017
D018
图7-19. Common Mode Error vs Temperature
图7-20. Common Mode Error vs Temperature
(Differential Bipolar Outputs)
(Differential Unipolar Outputs)
30
25
20
15
10
5
30
25
20
15
10
5
25
20
15
10
5
IDD
IAA
ICC
ISS
0
-5
-10
-15
-20
-25
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D019
D020
±20-V output range
±20-V output range
图7-21. Supply Current (IDD, IAA) vs Digital Input Code
图7-22. Supply Current (ICC, ISS) vs Digital Input Code
500
450
400
350
300
250
200
150
100
50
25
20
15
10
5
0
-5
-10
-15
IDD
IAA
ICC
ISS
-20
-25
0
1.7
2.65
3.6
VIO (V)
4.55
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D021
D022
±20-V output range
图7-23. Supply Current (IIO) vs Supply Voltage
±20-V output range
图7-24. Supply Current vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
90
75
60
45
30
15
0
40
30
IDD
IAA
ICC
ISS
20
10
0
-10
-20
-30
-40
-15
-30
Code 0x0000
Code 0x8000
Code 0xFFFF
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-50 -40 -30 -20 -10
0
10
Load Current (mA)
20
30
40
50
D023
D024
±20-V output range
图7-25. Power-Down Current vs Temperature
±20-V output range
图7-26. Source and Sink Capability
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
20 V
10 V
20 V
10 V
0
3
6
9
12
Sourcing Current (mA)
15
18
21
24
27
30
0
3
6
9
12
Sinking Current (mA)
15
18
21
24
27
30
D025
D026
Full-scale code
图7-27. VCC Headroom vs Sourcing Current
Zero code
图7-28. VSS Footroom vs Sinking Current
LDAC (5V/div)
VOUT (5V/div)
LDAC (5V/div)
VOUT (5V/div)
Time (5 msec/div)
Time (5 msec/div)
D027
D028
±20-V output range
±20-V output range
图7-30. Full-Scale Settling Time, Falling Edge
图7-29. Full-Scale Settling Time, Rising Edge
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
LDAC (5V/div)
VOUT (5mV/div)
-0.8
-1.0
Time (5 msec/div)
Time (0.5msec/div)
D029
D030
Power-down to active DAC mode
±20-V output range
图7-31. DAC Output Enable Glitch
0-V to 5-V output range
图7-32. Glitch Impulse, 1 LSB Step
20
15
10
5
20
15
10
5
0
0
-5
-5
Time (25 msec/div)
Time (25 msec/div)
D031
D032
±20-V output range
Toggle signal: 1 VPP
±20-V output range
Toggle signal: 1 VPP
DC value: 3/4 full-scale
DC change: midscale to 3/4 full-scale
图7-33. Toggle Output Change Response
图7-34. Toggle Enable Response
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
VOUT
VCC
VOUT
VCC
VSS
VDD = VAA = VIO
VSS
VDD = VAA = VIO
Time (50 msec/div)
Time (50 msec/div)
D033
D034
图7-35. Power-Up Response
图7-36. Power-Down Response
CLR (5 V/div)
VOUT (5 V/div)
CLR (5 V/div)
VOUT (5 V/div)
Time (1 msec/div)
Time (0.5 msec/div)
D035
D036
±20-V output range
Full-scale code to 0 V
±20-V output range
Toggle signal: 1 VPP
DC value at 20 V
图7-37. Clear Command Response
图7-38. Clear Command Response in Toggle Mode
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
1500
1350
1200
1050
900
750
600
450
300
150
0
100
1000
10000
100000
Time (1 sec/div)
Frequency (Hz)
D037
D038
0 to 5-V output range
Midscale code
0 to 5-V output range
Midscale code
图7-39. DAC Output Noise Density vs Frequency
图7-40. DAC Output Noise
2.505
2.5005
2.5004
2.5003
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
4.5 4.6 4.7 4.8 4.9
5
VDD, VAA (V)
5.1 5.2 5.3 5.4 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D040
D039
图7-42. Internal Reference Voltage vs Supply Voltage
图7-41. Internal Reference Voltage vs Temperature
2.5005
2.5004
2.5003
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
1500
1350
1200
1050
900
750
600
450
300
150
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Hours
100
1000
10000
100000
Frequency (Hz)
D041
D042
图7-43. Internal Reference Voltage vs Time
图7-44. Internal Reference Noise Density vs Frequency
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7.8 Typical Characteristics (continued)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥VMAX + 1.5 V for the DAC range,
bipolar ranges: VSS ≤VMIN –1.5 V and VCC ≥VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless
otherwise noted)
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0
Time (1 sec/div)
0
1
2
3
4
5
6
7
8
9
10
Temperature Drift (ppm/oC)
D043
D044
图7-45. Internal Reference Noise
图7-46. Internal Reference Temperature Drift Histogram
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8 Detailed Description
8.1 Overview
The DACx1416 are a pin-compatible family of 16-channel, buffered, high-voltage output digital-to-analog
converters (DACs) with 16‑bit, 14‑bit, and 12‑bit resolution. The DACx1416 include a 2.5-V internal reference. A
user-selectable output configuration enables full-scale bipolar output voltages of ±20 V, ±10 V, ±5 V or ±2.5 V,
and full-scale unipolar output voltages of 40 V, 20 V, 10 V or 5 V. The full-scale output range for each DAC
channel is independently programmable. In addition, each pair of DAC channels can be configured to provide a
differential output. Three dedicated A-B toggle pins enable dither signal generation with up to three possible
frequencies.
The DACx1416 operate from five supply voltages: VDD, VAA, VCC, VSS and VIO.
• VDD and VAA are the digital and analog supplies for the DACs, internal reference and other low voltage
components and must be set at the same potential.
• VCC and VSS are the positive and analog supplies for the DAC output amplifiers.
• VIO sets the logic levels for the digital inputs and outputs.
Communication with the DACx1416 is performed through a 4-wire serial interface that supports stand-alone and
daisy-chain operation. The optional frame-error checking provides added robustness to the DACx1416 serial
interface.
The DACx1416 incorporate a power-on-reset circuit that connects the DAC outputs to ground at power up. The
outputs remain in this state until the device registers are properly configured for operation.
8.2 Functional Block Diagram
REF
REFCMP REFGND
VIO
VAA
VDD
VCC
Internal
Reference
DAC
Buffer
DAC
Register
SCLK
SDI
Range Config
SDO
DAC
BUF
OUT0
CS
LDAC
Channel 0
Channel 1
RESET
OUT1
CLR
TOGGLE0
TOGGLE1
TOGGLE2
Channel 15
OUT15
Power Down Logic
Resistive Network
ALMOUT
Power On Reset
Temperature Sensor
TEMPOUT
DACx1416
GND
VSS
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8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
Each output channel in the DACx1416 consists of an R-2R ladder architecture followed by an output buffer
amplifier capable of rail-to-rail operation. The output amplifiers can drive 25 mA with 1.5-V headroom from either
VCC or VSS while maintaining the specified TUE specification for the device. The full-scale output voltage for
each channel can be individually configured to the following ranges:
• –20 V to +20 V
• –10 V to +10 V
• –5 V to +5 V
• –2.5 V to +2.5 V
• 0 V to 40 V
• 0 V to 20 V
• 0 V to 10 V
• 0 V to 5 V
图8-1 shows a block diagram of the DAC architecture.
REF
VCC
2.5-V
Reference
DAC Range
Select
Register
DAC Buffer
Register
(Toggle Reg B)
DAC Active
Serial Interface
WRITE
Asynchronous Mode
Register
Synchronous Mode
(LDAC(A) Trigger)
(Toggle Reg A)
DAC
Output
VOUT
DAC
GND
TOGGLE
VSS
A. The DAC trigger is generated by either by writing 1 to the LDAC bit or by the LDAC pin in synchronous mode. In asynchronous mode,
the DAC latch is transparent.
图8-1. DACx1416 DAC Block Diagram
8.3.1.1 DAC Transfer Function
The input data are written to the individual DAC Data registers in straight binary format for all output ranges. The
DAC transfer function is given by 方程式1.
≈ CODE
’
V
=
× FSR + V
÷
∆
OUT
MIN
n
«
2
◊
(1)
where:
• CODE is the decimal equivalent of the binary code that is loaded to the DAC register. CODE range is from 0
to 2n –1.
• n is the DAC resolution in bits. Either 12 (DAC61416), 14 (DAC71416) or 16 (DAC81416).
• FSR is the DAC full-scale range. Equal to VMAX –VMIN for the selected DAC output range.
• VMIN is the lowest voltage for the selected DAC output range.
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8.3.1.2 DAC Register Structure
Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active DAC registers can be configured to happen immediately (asynchronous mode)
or initiated by a DAC trigger signal (synchronous mode). Once the DAC active registers are updated, the DAC
outputs change to the new values.
After a power-on or reset event, all DAC registers are set to zero code, the DAC output amplifiers are powered
down, and the DAC outputs are clamped to ground.
8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In
asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register
and DAC output on a CS rising edge. In synchronous mode, writing to the DAC data register does not
automatically update the DAC output. Instead the update occurs only after a trigger event. A DAC trigger signal
is generated either through the LDAC bit or by the LDAC pin. The synchronous update mode enables
simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required
between DAC output updates.
8.3.1.2.2 Broadcast DAC Register
The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a
single register write. Broadcast operation is only possible when all DAC channels are in single-ended mode
operation. If one or more outputs are configured in differential mode the broadcast command is ignored.
Each DAC channel can be configured to update or remain unaffected by a broadcast command by setting the
corresponding DAC-BRDCAST-EN bit. A register write to the BRDCAST-DATA register forces those DAC
channels that have been configured for broadcast operation to update their DAC buffer registers to this value.
The DAC outputs update to the broadcast value according to their synchronous mode configuration.
8.3.1.2.3 Clear DAC Operation
The DAC outputs are set in clear mode through the CLR pin. In clear mode each DAC data channel is set to the
clear code associated with its configuration as shown in 表 8-1. A CLR pin logic low forces all DAC channels to
clear the contents of their buffer and active registers to the clear code, and sets the analog outputs accordingly
regardless of their synchronization setting.
表8-1. Clear DAC Value
UNIPOLAR / BIPOLAR RANGE
DIFFERENTIAL MODE
CLEAR CODE
Zero code
Unipolar
Unipolar
Bipolar
Bipolar
No
Yes
No
Midscale code
Midscale code
Midscale code
Yes
When a DAC is operating in toggle mode, a clear command sets both toggle registers to the clear value.
8.3.2 Internal Reference
The DAx1416 includes a precision 2.5-V bandgap reference with a typical temperature drift of 5 ppm/°C. The
internal reference is externally available at the REF pin. An external buffer amplifier with a high impedance input
is required to drive any external load.
A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering. A
compensation capacitor (330 pF, typical) should be connected between the REFCMP pin and REFGND.
Operation from an external reference is also supported by powering down the internal reference. The external
reference is applied to the REF pin.
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8.3.3 Device Reset Options
8.3.3.1 Power-on-Reset (POR)
The DACx1416 includes a power-on reset function. After the supplies have been established, a POR event is
issued. The POR causes all registers to initialize to their default values and communication with the device is
valid only after a 1-ms power-on-reset delay. After a POR event, the device is set in power-down mode where all
DAC channels and internal reference are powered down and the DAC output pins are connected to ground
through a 10-kΩinternal resistor.
8.3.3.2 Hardware Reset
A device hardware reset event is initiated by a minimum 500 ns logic low on the RESET pin. A hardware reset
initiates a POR event.
8.3.3.3 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to SOFT-RESET in the TRIGGER
register. The software reset command is triggered on the CS rising edge of the instruction. A software reset
initiates a POR event.
8.3.4 Thermal Protection
Because of the device DAC channel density and high drive capability, make sure that the effects of power
dissipation on the device temperature are understood and that the device temperature does not exceed the
maximum junction temperature.
8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
The DACx1416 includes an analog temperature monitor with an unbuffered output voltage that is inversely
proportional to the device junction temperature. The TEMPOUT pin output voltage has a temperature slope of –
4 mV/°C and a 1.34-V offset as described by 方程式2.
-4 mV
≈
’
V
=
× T + 1.34 V
÷
TEMPOUT
∆
«
°C
◊
(2)
where:
• T is the device junction temperature in °C.
• VTEMPOUT is the temperature monitor output voltage.
8.3.4.2 Thermal Shutdown
The DACx1416 incorporates a thermal shutdown that is triggered when the die temperature exceeds 140°C. A
thermal shutdown sets the TEMP-ALM bit and causes all DAC outputs to power-down, however the internal
reference remains powered on. The ALMOUT pin can be configured to monitor a thermal shutdown condition by
setting the TEMPALM-EN bit. Once a thermal shutdown is triggered, the device stays in shutdown even after the
device temperature lowers.
The die temperature must fall below 140°C before the device can be returned to normal operation. To resume
normal operation, the thermal alarm must be cleared through the ALM-RESET bit while the DAC channels are in
power-down mode.
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8.4 Device Functional Modes
8.4.1 Toggle Mode
Each DAC in the device can be independently configured to operate in toggle mode. A DAC channel in toggle
mode incorporates two DAC registers (Register A and Register B) and can be set to switch repetitively between
these two values. The DACx1416 toggle mode operation can be configured to introduce a dither signal to the
DAC output, to generate a periodic signal or to implement ON/OFF signaling, among some examples.
To update the toggle registers the following sequence should be followed:
1. Set DAC channel in synchronous mode and disable toggle mode for that channel
2. Write the desired Register A value to the DAC data register
3. Issue a DAC trigger signal to load Register A
4. Write the desired Register B value to the DAC data register
5. Enable toggle mode to load Register B
Once both registers are loaded with data, any of the three TOGGLE[2:0] pins can be used to switch those DACs
configured for toggle operation back and forth between the contents of their two DAC specific registers by using
an external clock or logic signal. A TOGGLE pin logic low updates the DAC output to the value set by Register A.
A logic high updates the DAC output to the value set by Register B. The three TOGGLE[2:0] pins give the
DACx1416 the option to operate with up to three toggle rates.
Additionally, the device can be configured for software controlled toggle operation by setting the SOFTTOGGLE-
EN bit. In this mode, any of the three AB-TOG[2:0] bits can be used as a toggle control signal. Setting the AB-
TOG bit to 1 enables Register B and clearing it to 0 enables Register A.
8.4.2 Differential Mode
Each DAC pair in the device, can be independently configured to operate as a differential output pair. The
differential output of a DACx-y pair is updated by writing to the DACx channel. For proper operation, the two
DAC pairs must be configured to the same output range prior to enabling differential mode. 图 8-2 and 图 8-3
show the ideal differential output voltages (VDIFF) and common mode voltages (VCM) for a DAC differential pair
configured for ±20-V and 0 to 40-V operation, respectively.
After being configured as a differential output, the DACx-y pair can be set for toggle operation by updating the
DACx toggle registers as described in 节8.4.1.
Imbalances between the two differential signals result in common-mode and amplitude errors. The device
incorporates an offset register that enables the user to introduce a voltage offset to the DACy channel of the
DACx-y differential pair to compensate for a DC offset error between the two channels. The offset compensation
gives approximately a ±0.2%FSR adjustment window. The differential DAC data register must be rewritten after
an update to the offset register.
40
30
40
30
20
20
10
10
0
0
-10
-20
-30
-40
-10
-20
-30
-40
DACx
DACy
VCM
VDIFF
DACx
DACy
VCM
VDIFF
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D045
D046
图8-2. Differential Bipolar Output (16-Bit):
图8-3. Differential Unipolar Output (16-Bit):
±20-V Output Range
0-V to 40-V Output Range
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8.4.3 Power-Down Mode
The DACx1416 DAC output amplifiers and internal reference power-down status can be individually configured
and monitored though the PWDWN registers. Setting a DAC channel in power-down mode disables the output
amplifier and clamps the output pin to ground through an internal 10-kΩresistor.
The DAC data registers are not cleared when the DAC goes into power-down which makes it possible to return
to the same output voltage upon return to normal operation. The DAC data registers can also be updated while
in power-down mode.
After a power-on or reset event all the DAC channels and the internal reference are in power-down mode. The
entire device can be configured into power-down or active modes through the DEV-PWDWN bit.
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8.5 Programming
The DACx1416 family of devices is controlled through a flexible four-wire serial interface that is compatible with
SPI type interfaces used on many microcontrollers and DSP controllers. The interface provides access to the
DACx1416 registers and can be configured to daisy-chain multiple devices for write operations. The DACx1416
incorporates an optional error checking mode to validate SPI data communication integrity in noisy
environments.
8.5.1 Stand-Alone Operation
A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is
24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay
low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the
access cycle contains less than then minimum clock edges, the communication is ignored. If the access cycle
contains more than the minimum clock edges, only the first 24 or 32 bits are used by the device. When CS is
high, the SCLK and SDI signals are blocked and the SDO is in a Hi-Z state.
In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which
identifies the request as a read or write command and the 6-bit address to be accessed. The last 16 bits in the
cycle form the data cycle.
表8-2. Serial Interface Access Cycle
BIT
23
FIELD
DESCRIPTION
Identifies the communication as a read or write command to the address
register. R/W = 0 sets a write operation. R/W = 1 sets a read operation.
RW
22
x
Don't care bit.
Register address. Specifies the register to be accessed during the read or
write operation.
21-16
A[5:0]
Data cycle bits. If a write command, the data cycle bits are the values to be
written to the register with address A[5:0]. If a read command, the data cycle
bits are don't care values.
15-0
DI[15:0]
Read operations require that the SDO pin is first enabled by setting the SDO-EN bit. A read operation is initiated
by issuing a read command access cycle. After the read command, a second access cycle must be issued to get
the requested data. Data are clocked out on SDO pin either on the falling edge or rising edge of SCLK according
to the FSDO bit.
表8-3. SDO Output Access Cycle
BIT
23
FIELD
DESCRIPTION
RW
Echo RW from previous access cycle.
22
x
Echo bit 22 from previous access cycle.
21-16
15-0
A[5:0]
DO[15:0]
Echo address from previous access cycle.
Readback data requested on previous access cycle.
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8.5.1.1 Streaming Mode Operation
Since updating the sixteen channels data registers requires a large amount of data to be passed to the device,
the device supports streaming mode. In streaming mode the DAC data registers can be written to the device
without providing an instruction command for each data register. Streaming mode is enabled by setting the STR-
EN bit. Once enabled the streaming operation is implemented by holding the CS active and continuing to shift
new data into the device.
The instruction cycle includes the starting address. The device starts writing to this address and automatically
increments the address as long as CS is asserted. If the last DAC data register address has been reached and
CS is still asserted, the data for this address is overwritten with the new data.
/CS
1
2
X
3
4
5
6
7
8
9
23
24
25
39
40
41
55
56
57
71
72
SCLK
SDI
STREAM WRITE COMMAND
A5 A4 A3 A2
ADDRESS N
ADDRESS N+1
ADDRESS N+2
ADDRESS N+3
W
A1
A0
D15 œ D0
D15 œ D0
D15 œ D0
D15 œ D0
SDO
图8-4. Serial Interface Streaming Cycle
8.5.2 Daisy-Chain Operation
For systems that contain more than one DACx1416 devices, the SDO pin can be used to daisy-chain them
together. The SDO pin must be enabled by setting the SDO-EN bit before initiating the daisy-chain operation.
Daisy-chain operation is useful in reducing the number of serial interface lines.
The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the
CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling
edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the
SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system
requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the
total number of DACx1416 devices in the daisy chain. When the serial transfer to all devices is complete the CS
signal is taken high. This action transfers the data from the SPI shift registers to the internal registers of each
device in the daisy chain and prevents any further data from being clocked into the input shift register. Daisy-
chain operation is not supported while in streaming mode.
C
B
A
DACx1416
DACx1416
DACx1416
SDO
SDO
SDO
SDI
SDI
SDI
SCLK
SCLK
SCLK
CS
CS
CS
图8-5. Daisy-Chain Layout
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8.5.3 Frame Error Checking
If the DACx1416 is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature is enabled by setting the CRC-EN bit.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111).
When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data is
appended with an 8-bit CRC polynomial by the host processor before feeding it to the device. In all serial
interface readback operations the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.
表8-4. Error Checking Serial Interface Access Cycle
BIT
31
FIELD
DESCRIPTION
Identifies the communication as a read or write command to the address
register. R/W = 0 sets a write operation. R/W = 1 sets a read operation.
RW
30
CRC-ERROR
A[5:0]
Reserved bit. Set to zero.
Register address. Specifies the register to be accessed during the read or
write operation.
29-24
Data cycle bits. If a write command, the data cycle bits are the values to be
written to the register with address A[5:0]. If a read command, the data cycle
bits are don't care values.
23-8
7-0
DI[15:0]
CRC
8-bit CRC polynomial.
The DACx1416 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error
exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a
second access cycle can be issued to determine the error checking results (CRC-ERROR bit) on the SDO pin.
If there is a CRC error, the CRC-ALM bit of the status register is set to 1. The ALMOUT pin can be configured to
monitor a CRC error by setting the CRCALM-EN bit.
表8-5. Write Operation Error Checking Cycle
BIT
31
FIELD
DESCRIPTION
Echo RW from previous access cycle (RW = 0).
Returns a 1 when a CRC error is detected, 0 otherwise.
Echo address from previous access cycle.
Echo data from previous access cycle.
RW
30
CRC-ERROR
A[5:0]
29-24
23-8
7-0
DO[15:0]
CRC
Calculated CRC value of bits 31:8.
A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The
error check result (CRC-ERROR bit) from the read command is output on the SDO pin.
As in the case of a write operation failing the CRC check, the CRC-ALM bit of the status register is set to 1 and
the ALMOUT pin, if configured for CRC alerts, is set low.
表8-6. Read Operation Error Checking Cycle
BIT
31
FIELD
DESCRIPTION
Echo RW from previous access cycle (RW = 1).
Returns a 1 when a CRC error is detected, 0 otherwise.
Echo address from previous access cycle.
Readback data requested on previous access cycle.
Calculated CRC value of bits 31:8.
RW
30
CRC-ERROR
A[5:0]
29-24
23-8
7-0
DO[15:0]
CRC
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8.6 Register Maps
表 8-7 lists the memory-mapped registers for the device. All register offset addresses not listed in 表 8-7 should
be considered as reserved locations and the register contents should not be modified.
表8-7. DACx1416 Registers
Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
Acronym
NOP
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
NOP Register
DEVICEID
STATUS
Device ID Register
Status Register
SPICONFIG
GENCONFIG
BRDCONFIG
SYNCCONFIG
TOGGCONFIG0
TOGGCONFIG1
DACPWDWN
DACRANGE0
DACRANGE1
DACRANGE2
DACRANGE3
TRIGGER
BRDCAST
DAC0
SPI Configuration Register
General Configuration Register
Broadcast Configuration Register
Sync Configuration Register
DAC[15:8] Toggle Configuration Register
DAC[7:0] Toggle Configuration Register
DAC Power-Down Register
DAC[15:12] Range Register
DAC[11:8] Range Register
DAC[7:4] Range Register
DAC[3:0] Range Register
Trigger Register
Broadcast Data Register
DAC0 Data Register
DAC1
DAC1 Data Register
DAC2
DAC2 Data Register
DAC3
DAC3 Data Register
DAC4
DAC4 Data Register
DAC5
DAC5 Data Register
DAC6
DAC6 Data Register
DAC7
DAC7 Data Register
DAC8
DAC8 Data Register
DAC9
DAC9 Data Register
DAC10
DAC10 Data Register
DAC11
DAC11 Data Register
DAC12
DAC12 Data Register
DAC13
DAC13 Data Register
DAC14
DAC14 Data Register
DAC15
DAC15 Data Register
OFFSET0
OFFSET1
OFFSET2
OFFSET3
DAC[14-15;12-13] Differential Offset Register
DAC[10-11;8-9] Differential Offset Register
DAC[6-7;4-5] Differential Offset Register
DAC[2-3;0-1] Differential Offset Register
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Complex bit access types are encoded to fit into small table cells. 表 8-8 shows the codes that are used for
access types in this section.
表8-8. Access Type Codes
Access Type
Code
R
Description
Read Type
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
Register Array Variables
When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
i,j,k,l,m,n
When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.
y
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8.6.1 NOP Register (Offset = 00h) [reset = 0000h]
NOP is shown in 图8-6 and described in 表8-9.
Return to Summary Table.
图8-6. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
W-0h
表8-9. NOP Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
NOP
W
0h
No operation. Write 0000h for proper no-operation command.
8.6.2 DEVICEID Register (Offset = 01h) [reset = ----h]
DEVICEID is shown in 图8-7 and described in 表8-10.
Return to Summary Table.
图8-7. DEVICEID Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
DEVICEID
R----h
4
3
DEVICEID
R----h
VERSIONID
R-0h
表8-10. DEVICEID Register Field Descriptions
Bit
Field
Type
Reset
Description
Device ID
DAC81416: 29Ch
DAC71416: 28Ch
DAC61416: 24Ch
15-2
1-0
DEVICEID
R
---h
VERSIONID
R
0h
Version ID. Subject to change.
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8.6.3 STATUS Register (Offset = 02h) [reset = 0000h]
STATUS is shown in 图8-8 and described in 表8-11.
Return to Summary Table.
图8-8. STATUS Register
15
7
14
6
13
12
11
10
9
8
RESERVED
R-0h
5
4
3
2
1
0
RESERVED
R-0h
CRC-ALM
R-0h
DAC-BUSY
R-0h
TEMP-ALM
R-0h
表8-11. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-3
RESERVED
CRC-ALM
R
0h
This bit is reserved.
2
1
R
0h
CRC-ALM = 1 indicates a CRC error.
DAC-BUSY
R
0h
DAC-BUSY = 1 indicates DAC registers are not ready for updates.
TEMP-ALM = 1 indicates die temperature is over +140°C. A thermal
alarm event forces the DAC outputs to go into power-down mode.
0
TEMP-ALM
R
0h
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8.6.4 SPICONFIG Register (Offset = 03h) [reset = 0AA4h]
SPICONFIG is shown in 图8-9 and described in 表8-12.
Return to Summary Table.
图8-9. SPICONFIG Register
15
7
14
6
13
5
12
11
10
9
CRCALM-EN
R/W-1h
1
8
RESERVED
R-0h
TEMPALM-EN DACBUSY-EN
RESERVED
R-0h
R/W-1h
3
R/W-0h
2
4
0
RESERVED SOFTTOGGLE- DEV-PWDWN
EN
CRC-EN
STR-EN
SDO-EN
FSDO
RESERVED
R-1h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R-0h
表8-12. SPICONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11
RESERVED
R
0h
This bit is reserved.
TEMPALM-EN
R/W
1h
When set to 1 a thermal alarm triggers the ALMOUT pin.
When set to 1 the ALMOUT pin is set between DAC output updates.
Contrary to other alarm events, this alarm resets automatically.
10
DACBUSY-EN
R/W
0h
9
8
7
6
CRCALM-EN
RESERVED
R/W
R
1h
0h
1h
0h
When set to 1 a CRC error triggers the ALMOUT pin.
This bit is reserved.
RESERVED
R
This bit is reserved.
SOFTTOGGLE-EN
R/W
When set to 1 enables soft toggle operation.
DEV-PWDWN = 1 sets the device in power-down mode
DEV-PWDWN = 0 sets the device in active mode
5
DEV-PWDWN
R/W
1h
4
3
2
CRC-EN
STR-EN
SDO-EN
R/W
R/W
R/W
0h
0h
1h
When set to 1 frame error checking is enabled.
When set to 1 streaming mode operation is enabled.
When set to 1 the SDO pin is operational.
Fast SDO bit (half-cycle speedup). When 0, SDO updates during
SCLK rising edges. When 1, SDO updates during SCLK falling
edges.
1
0
FSDO
R/W
R
0h
0h
RESERVED
This bit is reserved.
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8.6.5 GENCONFIG Register (Offset = 04h) [reset = 7F00h]
GENCONFIG is shown in 图8-10 and described in 表8-13.
Return to Summary Table.
图8-10. GENCONFIG Register
15
RESERVED
R-0h
14
REF-PWDWN
R/W-1h
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R-1h
7
4
3
DAC-14-15-
DIFF-EN
DAC-12-13-
DIFF-EN
DAC-10-11-
DIFF-EN
DAC-8-9-DIFF- DAC-6-7-DIFF- DAC-4-5-DIFF- DAC-2-3-DIFF- DAC-0-1-DIFF-
EN
EN
EN
EN
EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表8-13. GENCONFIG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15
R
0h
This bit is reserved.
REF-PWDWN = 1 powers down the internal reference
REF-PWDWN = 0 activates the internal reference
14
REF-PWDWN
RESERVED
R/W
R
1h
1h
13-8
This bit is reserved.
7
6
5
4
3
2
1
0
DAC-14-15-DIFF-EN
DAC-12-13-DIFF-EN
DAC-10-11-DIFF-EN
DAC-8-9-DIFF-EN
DAC-6-7-DIFF-EN
DAC-4-5-DIFF-EN
DAC-2-3-DIFF-EN
DAC-0-1-DIFF-EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
When set to 1 the corresponding DAC pair is set to operate in
differential mode. The DAC data registers must be rewritten after
enabling or disabling differential operation.
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8.6.6 BRDCONFIG Register (Offset = 05h) [reset = FFFFh]
BRDCONFIG is shown in 图8-11 and described in 表8-14.
Return to Summary Table.
图8-11. BRDCONFIG Register
15
14
13
12
11
10
9
8
DAC15-
DAC14-
DAC13-
DAC12-
DAC11-
DAC10-
DAC9-
DAC8-
BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN
R/W-1h
7
R/W-1h
6
R/W-1h
5
R/W-1h
4
R/W-1h
3
R/W-1h
2
R/W-1h
1
R/W-1h
0
DAC7-
DAC6-
DAC5-
DAC4-
DAC3-
DAC2-
DAC1-
DAC0-
BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
表8-14. BRDCONFIG Register Field Descriptions
Bit
15
14
13
12
11
10
9
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
Description
DAC15-BRDCAST-EN
DAC14-BRDCAST-EN
DAC13-BRDCAST-EN
DAC12-BRDCAST-EN
DAC11-BRDCAST-EN
DAC10-BRDCAST-EN
DAC9-BRDCAST-EN
DAC8-BRDCAST-EN
DAC7-BRDCAST-EN
DAC6-BRDCAST-EN
DAC5-BRDCAST-EN
DAC4-BRDCAST-EN
DAC3-BRDCAST-EN
DAC2-BRDCAST-EN
DAC1-BRDCAST-EN
DAC0-BRDCAST-EN
When set to 1 the corresponding DAC is set to update its output to
the value set in the BRDCAST register. All DAC channels must be
configured in single-ended mode for broadcast operation. If one or
more outputs are configured in differential mode the broadcast mode
is ignored.
8
7
6
When cleared to 0 the corresponding DAC output remains unaffected
by a BRDCAST command.
5
4
3
2
1
0
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8.6.7 SYNCCONFIG Register (Offset = 06h) [reset = 0000h]
SYNCCONFIG is shown in 图8-12 and described in 表8-15.
Return to Summary Table.
图8-12. SYNCCONFIG Register
15
14
13
12
11
10
9
8
DAC15-SYNC- DAC14-SYNC- DAC13-SYNC- DAC12-SYNC- DAC11-SYNC- DAC10-SYNC- DAC9-SYNC-
DAC8-SYNC-
EN
EN
R/W-0h
7
EN
R/W-0h
6
EN
R/W-0h
5
EN
R/W-0h
4
EN
R/W-0h
3
EN
R/W-0h
2
EN
R/W-0h
1
R/W-0h
0
DAC7-SYNC-
EN
DAC6-SYNC-
EN
DAC5-SYNC-
EN
DAC4-SYNC-
EN
DAC3-SYNC-
EN
DAC2-SYNC-
EN
DAC1-SYNC-
EN
DAC0-SYNC-
EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表8-15. SYNCCONFIG Register Field Descriptions
Bit
15
14
13
12
11
10
9
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Description
DAC15-SYNC-EN
DAC14-SYNC-EN
DAC13-SYNC-EN
DAC12-SYNC-EN
DAC11-SYNC-EN
DAC10-SYNC-EN
DAC9-SYNC-EN
DAC8-SYNC-EN
DAC7-SYNC-EN
DAC6-SYNC-EN
DAC5-SYNC-EN
DAC4-SYNC-EN
DAC3-SYNC-EN
DAC2-SYNC-EN
DAC1-SYNC-EN
DAC0-SYNC-EN
When set to 1 the corresponding DAC output is set to update in
response to an LDAC trigger (synchronous mode).
When cleared to 0 the corresponding DAC output is set to update
immediately (asynchronous mode).
8
7
6
5
4
3
2
1
0
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8.6.8 TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]
TOGGCONFIG0 is shown in 图8-13 and described in 表8-16.
Return to Summary Table.
图8-13. TOGGCONFIG0 Register
15
14
13
12
11
10
9
8
DAC15-AB-TOGG-EN
R/W-0h
DAC14-AB-TOGG-EN
R/W-0h
DAC13-AB-TOGG-EN
R/W-0h
DAC12-AB-TOGG-EN
R/W-0h
7
6
5
4
3
2
1
0
DAC11-AB-TOGG-EN
R/W-0h
DAC10-AB-TOGG-EN
R/W-0h
DAC9-AB-TOGG-EN
R/W-0h
DAC8-AB-TOGG-EN
R/W-0h
表8-16. TOGGCONFIG0 Register Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
15-14
13-12
11-10
9-8
DAC15-AB-TOGG-EN
DAC14-AB-TOGG-EN
DAC13-AB-TOGG-EN
DAC12-AB-TOGG-EN
DAC11-AB-TOGG-EN
DAC10-AB-TOGG-EN
DAC9-AB-TOGG-EN
DAC8-AB-TOGG-EN
0h
0h
Enables toggle mode operation and configures the toggle pin or soft
toggle bit:
0h
0h
00 = Toggle mode disabled
01 = Toggle mode enabled: TOGGLE0
10 = Toggle mode enabled: TOGGLE1
11 = Toggle mode enabled: TOGGLE2
7-6
0h
5-4
0h
3-2
0h
1-0
0h
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8.6.9 TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]
TOGGCONFIG1 is shown in 图8-14 and described in 表8-17.
Return to Summary Table.
图8-14. TOGGCONFIG1 Register
15
14
13
12
11
10
9
8
DAC7-AB-TOGG-EN
R/W-0h
DAC6-AB-TOGG-EN
R/W-0h
DAC5-AB-TOGG-EN
R/W-0h
DAC4-AB-TOGG-EN
R/W-0h
7
6
5
4
3
2
1
0
DAC3-AB-TOGG-EN
R/W-0h
DAC2-AB-TOGG-EN
R/W-0h
DAC1-AB-TOGG-EN
R/W-0h
DAC0-AB-TOGG-EN
R/W-0h
表8-17. TOGGCONFIG1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
15-14
13-12
11-10
9-8
DAC7-AB-TOGG-EN
DAC6-AB-TOGG-EN
DAC5-AB-TOGG-EN
DAC4-AB-TOGG-EN
DAC3-AB-TOGG-EN
DAC2-AB-TOGG-EN
DAC1-AB-TOGG-EN
DAC0-AB-TOGG-EN
0h
0h
Enables toggle mode operation and configures the toggle pin or soft
toggle bit:
0h
0h
00 = Toggle mode disabled
01 = Toggle mode enabled: TOGGLE0
10 = Toggle mode enabled: TOGGLE1
11 = Toggle mode enabled: TOGGLE2
7-6
0h
5-4
0h
3-2
0h
1-0
0h
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8.6.10 DACPWDWN Register (Offset = 09h) [reset = FFFFh]
DACPWDWN is shown in 图8-15 and described in 表8-18.
Return to Summary Table.
图8-15. DACPWDWN Register
15
14
13
12
11
10
9
8
DAC15-
DAC14-
DAC13-
DAC12-
DAC11-
DAC10-
DAC9-PWDWN DAC8-PWDWN
PWDWN
PWDWN
PWDWN
PWDWN
PWDWN
PWDWN
R/W-1h
7
R/W-1h
6
R/W-1h
5
R/W-1h
4
R/W-1h
3
R/W-1h
2
R/W-1h
1
R/W-1h
0
DAC7-PWDWN DAC6-PWDWN DAC5-PWDWN DAC4-PWDWN DAC3-PWDWN DAC2-PWDWN DAC1-PWDWN DAC0-PWDWN
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
表8-18. DACPWDWN Register Field Descriptions
Bit
15
14
13
12
11
10
9
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
Description
DAC15-PWDWN
DAC14-PWDWN
DAC13-PWDWN
DAC12-PWDWN
DAC11-PWDWN
DAC10-PWDWN
DAC9-PWDWN
DAC8-PWDWN
DAC7-PWDWN
DAC6-PWDWN
DAC5-PWDWN
DAC4-PWDWN
DAC3-PWDWN
DAC2-PWDWN
DAC1-PWDWN
DAC0-PWDWN
8
When set to 1 the corresponding DAC is in power-down mode and
its output is connected to GND through a 10-kΩinternal resistor.
7
6
5
4
3
2
1
0
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8.6.11 DACRANGEn Register (Offset = 0Ah - 0Dh) [reset = 0000h]
DACRANGEn is shown in 图8-16 and described in 表8-19.
Return to Summary Table.
图8-16. DACRANGEn Register
15
7
14
13
12
11
10
9
8
0
DACa-RANGE[3:0]
W-0h
DACb-RANGE[3:0]
W-0h
6
5
4
3
2
1
DACc-RANGE[3:0]
W-0h
DACd-RANGE[3:0]
W-0h
表8-19. DACRANGEn Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-8
7-4
DACa-RANGE[3:0]
DACb-RANGE[3:0]
DACc-RANGE[3:0]
W
0h
Sets the output range for the corresponding DAC.
0000 = 0 to 5 V
W
0h
0001 = 0 to 10 V
W
0h
0010 = 0 to 20 V
0100 = 0 to 40 V
1001 = -5 V to +5 V
1010 = -10 V to +10 V
1100 = -20 V to +20 V
1110 = -2.5 V to +2.5 V
All others: invalid
3-0
DACd-RANGE[3:0]
W
0h
The two outputs of a differential DAC pair must be configured to the
same output range prior to setting them up as a differential pair.
a: 15, 11, 7 or 3; b: 14, 10, 6 or 2; c: 13, 9, 5 or 1; d: 12, 8, 4 or 0
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8.6.12 TRIGGER Register (Offset = 0Eh) [reset = 0000h]
TRIGGER is shown in 图8-17 and described in 表8-20.
Return to Summary Table.
图8-17. TRIGGER Register
15
14
13
12
RESERVED
W-0h
11
10
2
9
1
8
ALM-RESET
W-0h
7
6
5
4
3
0
AB-TOG2
W-0h
AB-TOG1
W-0h
AB-TOG0
W-0h
LDAC
W-0h
SOFT-RESET[3:0]
W-0h
表8-20. TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
15-9
RESERVED
W
0h
This bit is reserved
Set this bit to 1 to clear an alarm event. Not applicable for a DAC-
BUSY alarm event.
8
7
ALM-RESET
W
W
0h
0h
If soft toggle is enabled set, this bit controls the toggle between
values for those DACs that have been set in toggle mode 2 in the
TOGGCONFIG register. Set to 1 to update to Register B and clear to
0 for Register A.
AB-TOG2
AB-TOG1
AB-TOG0
If soft toggle is enabled set, this bit controls the toggle between
values for those DACs that have been set in toggle mode 1 in the
TOGGCONFIG register. Set to 1 to updated to Register B and clear
to 0 for Register A.
6
5
W
W
0h
0h
If soft toggle is enabled set, this bit controls the toggle between
values for those DACs that have been set in toggle mode 0 in the
TOGGCONFIG register. Set to 1 to update to Register B and clear to
0 for Register A.
Set this bit to 1 to synchronously load those DACs who have been
set in synchronous mode in the SYNCCONFIG register.
4
LDAC
W
W
0h
0h
When set to the reserved code 1010 resets the device to its default
state.
3-0
SOFT-RESET[3:0]
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8.6.13 BRDCAST Register (Offset = 0Fh) [reset = 0000h]
BRDCAST is shown in 图8-18 and described in 表8-21.
Return to Summary Table.
图8-18. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BRDCAST-DATA[15:0]
R/W-0h
表8-21. BRDCAST Register Field Descriptions
Bit
Field
Type
Reset
Description
Writing to the BRDCAST register forces those DAC channels that
have been set to broadcast in the BRDCONFIG register to update its
data register data to the BRDCAST-DATA one.
Data is MSB aligned in straight binary format and follows the format
below:
15-0
BRDCAST-DATA[15:0]
R/W
0h
DAC81416: { DATA[15:0] }
DAC71416: { DATA[13:0], x, x }
DAC61416: { DATA[11:0], x, x, x, x}
x –Don 't care bits
8.6.14 DACn Register (Offset = 10h - 1Fh) [reset = 0000h]
DACn is shown in 图8-19 and described in 表8-22.
Return to Summary Table.
图8-19. DACn Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACn-DATA[15:0]
R/W-0h
表8-22. DACn Register Field Descriptions
Bit
Field
Type
Reset
Description
Stores the 16-, 14- or 12-bit data to be loaded to DACn in MSB
aligned straight binary format. In differential DAC mode data is
loaded into the lowest-valued DAC in the DAC pair (in pair DACxy,
data is loaded into DACx and writes to DACy are ignored).
Data follows the format below:
15-0
DACn-DATA[15:0]
R/W
0h
DAC81416: { DATA[15:0] }
DAC71416: { DATA[13:0], x, x }
DAC61416: { DATA[11:0], x, x, x, x}
x –Don 't care bits
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8.6.15 OFFSETn Register (Offset = 20h - 23h) [reset = 0000h]
OFFSETn is shown in 图8-20 and described in 表8-23.
Return to Summary Table.
图8-20. OFFSETn Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
OFFSETab[7:0]
R/W-0h
4
3
OFFSETcd[7:0]
R/W-0h
表8-23. OFFSETn Register Field Descriptions
Bit
15-8
Field
OFFSETab[7:0]
Type
Reset
Description
R/W
0h
Provides offset adjustment to DACy in the differential DACx-y pair in
two 's complement format.
Data follows the format below:
•
•
•
DAC81416:
– Format: { OFFSET[7:0] }
– Range: -128 LSB to +127 LSB
DAC71416:
– Format: { OFFSET[5:0], x, x }
– Range: -32 LSB to +31 LSB
DAC61416:
7-0
OFFSETcd[7:0]
R/W
0h
– Format: { OFFSET[3:0], x, x, x, x}
– Range: -8 LSB to +7 LSB
x –Don 't care bits
The differential DAC data register must be rewritten after updating
the offset register.
ab: 14-15, 10-11, 6-7 or 2-3; cd: 12-13, 8-9, 4-5 or 0-1
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
One of the primary applications of the DACx1416 family is Mach Zehnder Modulator (MZM) biasing, employed in
Optical Line Cards and Optical Modules. With high-voltage, high-current and differential output features, the
DACx1416 family can be used for biasing both LiNbO3 and InP type modulators. With the help of the toggle
mode and multiple corresponding input pins, the required dither waveform for such applications can be
generated without involving SPI programming. The small package size and integrated reference minimize the
total footprint of such applications.
9.2 Typical Application
MZM
PR
Transmitted
π/2
MZM
Signal
LASER
BS
BC
MZM
MZM
π/2
IQ Modulator
R1
R2
Bias+
Bias-
Dither - I
TOGGLE0
TOGGLE1
OUT0
OUT1
C
DACx1416
Dither - Q
MZM: Mach-Zehnder Modulator
BS: Beam Splitter
PR: Polarization Rotator
BC: Beam Combiner
图9-1. Biasing a Mach Zehnder Modulator
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9.2.1 Design Requirements
Designing biasing circuits that are made to match both types of MZM technologies (LiNbO3 and InP) requires
high voltage and current ranges as shown in 表 9-1. The Optical Internetworking Forum (OIF) recommends four
differential IQ bias and two differential phase bias inputs, as shown in 图 9-1. This differential signaling scheme
helps in minimizing the crosstalk and noise between channels, which may otherwise result in a complicated bias
control algorithm. While an ideal dither tone should be a sine wave, generating a sine wave can be cumbersome
in a largely digital circuit domain. A square wave is relatively easier to generate through digital circuits, and can
also be used, provided that the bandwidth of this dither signal is lower than the low cutoff frequency of the
receiver (that is, 100 kHz or 1 MHz as per OIF). Passive RC filters with cutoff frequency lower than 100 kHz can
be used at the DAC output for LiNbO3 modulators, which have very small bias current requirement. For InP
modulators that are mainly used with optical modules, typically requiring a receiver low cutoff frequency of MHz,
choose RC values so that the power dissipation across the resistors is small.
For smooth detection of the dither signal at the MZM output, use two orthogonal dither frequency sources for the
I and Q arms. The amplitude of the dither waveform is typically 0.5% to 2.5% of the dc bias voltage, which is
mainly governed by the design implementation.
表9-1. Requirements of MZM Biasing Circuit
PARAMETER
VALUE
DC range
Up to ±18 V
Dither amplitude
Dither frequency
Dither shape
40 mV to 500 mV
100 Hz to 100 kHz
Sine or square
Up to 25 mA (for InP MZM)
2
Bias current
Number of dither frequencies
Output type
Differential (6 pairs)
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9.2.2 Detailed Design Procedure
图 9-1 provides the simplified circuit diagram for biasing a MZM for a Dither-type Bias Control circuit. As shown,
this cicuit requires four differential input pairs for IQ biasing, and two differential input pairs for phase biasing. To
bias a LiNbO3 MZM, the voltage can be as high as ±18 V, whereas the current requirement is of the order of few
micro amperes. The low cutoff frequency of the receiver is typically 100 kHz, and hence, the bandwidth of the
dither signals should be well below this frequency. Be aware that only the IQ bias inputs require the dither signal,
and not the phase bias. The DACx1416 featuresa toggle mode wherein the outputs can be configured to provide
a square wave imposed on a dc bias. This mode requires setting the HIGH and LOW codes for the square wave
and the transition happens in sync with the selected toggle input pin. The pseudocode to achieve the dither
output using the toggle function is provided below.
//SYNTAX: WRITE <REGISTER NAME>,<DATA>
//Power-on Device, Disable Soft-toggle
WRITE SPICONFIG,0x0A84
//Select Range for all 12 channels as ±10V
WRITE DACRANGE2, 0xAAAA
WRITE DACRANGE3, 0xAAAA
WRITE DACRANGE4, 0xAAAA
//Power-on DAC Channels 0 - 11
WRITE DACPWDWN,0xF000
//Write HIGH code to Register A of all IQ Bias Differential Pairs
WRITE DAC0,0xXXXX
WRITE DAC2,0xXXXX
WRITE DAC4,0xXXXX
WRITE DAC6,0xXXXX
//Write Data to Phase Bias Channels
WRITE DAC8,0xXXXX
WRITE DAC10,0xXXXX
//Enable Sync for All Differential Pairs
WRITE SYNCCONFIG,0x0FFF
//Enable Software LDAC
WRITE TRIGGER,0x0002
//Write LOW code to Register B of all IQ Bias Differential Pairs
WRITE DAC_DATA0,0xXXXX
WRITE DAC_DATA0,0xXXXX
WRITE DAC_DATA0,0xXXXX
WRITE DAC_DATA0,0xXXXX
//Turn Toggle Mode ON for All IQ Differential Pairs
//DAC11-10:Y/Phase Bias , DAC9-8:Y/I Bias - TOGG0, DAC7-6:Y/Q Bias - TOGG 1
//DAC5-4:Y/Phase Bias , DAC3-2:Y/I Bias - TOGG0, DAC1-0:Y/Q Bias - TOGG 1
WRITE TOGGCONFIG0,0x0005
WRITE TOGGCONFIG1,0xA05A
//Method to Modify the DC Value of Any IQ Differential Pair
//Turn Off Toggle Mode for that Channel (e.g. DAC0-1)
WRITE TOGGCONFIG1,0xA050
//Turn Off Sync for the Channel
WRITE SYNCCONFIG,0x0FFC
//Write HIGH code to Register A of the Channel Pair
WRITE DAC0,0xXXXX
//Turn On Sync for the Channel Pair
WRITE SYNCCONFIG,0x0FFF
//Turn On Toggle for the Channel Pair
WRITE TOGGCONFIG1,0xA05A
The dither frequencies can be set at 1 kHz and 2 kHz so that a single-pole RC low-pass filter can provide
sufficient attenuation at 100 kHz. For example, when R1 = R2 = 10 kΩ and C = 0.01 µF, an attenuation of
approximately 40 dB is obtained at 100 kHz.
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9.2.3 Application Curves
0.6
0.4
0.2
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-0.2
-0.4
-0.6
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
0
20
40
60
80 100 120 140 160 180 200
Frequency (kHz)
dac8
dac8
Toggle frequency = 10 kHz
Toggle frequency = 10 kHz, no filter at output
图9-2. Toggle AC Amplitude Transition
图9-3. Frequency Spectrum of Toggle Output
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10 Power Supply Recommendations
The DACx1416 require five power supply inputs: VIO, VDD, VAA, VCC and VSS. VDD and VAA should be at
same level. Assuming VIO and VDD/VAA to be different, there are four separate power-supply sources required.
Place a 0.1-µF ceramic capacitor close to each power-supply pin. Be aware that VCC and VSS have two pins
each. In addition, a 4.7-µF or 10-µF bulk capacitor is recommended for each power supply; tantalum or
aluminum types can be chosen for the bulk capacitors.
There is no sequencing requirement for the power supplies. As the DAC output range is configurable, make sure
that the power-supplies have enough headroom to achieve linearity at codes close to the power supply rails.
When sourcing or sinking current from or to the DAC output, the heat dissipation must be considered. For
example, a typical application of MZM bias with 25-mA load current from or to 12 channels with 2.5-V power-
supply headroom can create a power dissipation across the DAC of (12 × 2.5 × 25 mA) = 0.75 W. The thermal
design to dissipate the power in this example may involve inclusion of heat sinks in order to avoid thermal
shutdown of the device.
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11 Layout
11.1 Layout Guidelines
The pin configuration of the DACx1416 has been designed in such a way that the analog, digital, and power pins
are spatially separated from each other, which makes the PCB layout simple. An example layout is shown in 图
11-1. As evident, every power supply pin has a 0.1-µF capacitor close to the pin. Make sure to lay out the analog
and digital signals away from each other, or on different PCB layers. Make sure to provide an unbroken
reference plane (either ground or VIO) for the digital signals. The higher frequency signals, such as SCLK and
SDI, must have appropriate impedance termination in order to address signal integrity.
11.2 Layout Example
Power
Supplies
External
Reference
Analog
Outputs
Analog
Outputs
Digital IO
图11-1. Example Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, see the following: DAC81416 Evaluation Module
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, DAC81416EVM User's Guide
• Texas Instruments, DACx1416 Delivers Optimized Solution to Mach Zehnder Modulator Biasing application
note
• Texas Instruments, Programmable Voltage Output With Sense Connections Circuit application note
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
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提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC61416RHAR
DAC61416RHAT
DAC71416RHAR
DAC71416RHAT
DAC81416RHAR
DAC81416RHAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
RHA
RHA
40
40
40
40
40
40
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DAC61416
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
DAC61416
DAC71416
DAC71416
DAC81416
DAC81416
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC61416RHAR
DAC61416RHAT
DAC71416RHAR
DAC71416RHAT
DAC81416RHAR
DAC81416RHAT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
RHA
RHA
40
40
40
40
40
40
2500
250
330.0
180.0
330.0
180.0
330.0
180.0
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
1.1
1.1
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
2500
250
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jun-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC61416RHAR
DAC61416RHAT
DAC71416RHAR
DAC71416RHAT
DAC81416RHAR
DAC81416RHAT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
RHA
RHA
40
40
40
40
40
40
2500
250
367.0
213.0
367.0
213.0
367.0
213.0
367.0
191.0
367.0
191.0
367.0
191.0
38.0
35.0
38.0
35.0
38.0
35.0
2500
250
2500
250
Pack Materials-Page 2
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