DAC8164ICPW [TI]
14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/∑C Internal Reference; 14位，四通道，超低短时脉冲波形干扰，电压输出数位类比转换器具有2.5V ， 2ppm的/ ΣC内部参考
| 型号： | DAC8164ICPW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/∑C Internal Reference |
| 文件： | 总47页 (文件大小：1459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC8164
www.ti.com ......................................................................................................................................... SBAS410A–FEBRUARY 2008–REVISED FEBRUARY 2008
14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output
DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference
1
FEATURES
DESCRIPTION
234
•
Relative Accuracy: 1LSB
Glitch Energy: 0.15nV-s
Internal Reference:
The DAC8164 is
a
low-power, voltage-output,
four-channel, 14-bit digital-to-analog converter (DAC).
The device includes 2.5V, 2ppm/°C internal
•
•
a
reference (enabled by default), giving a full-scale
output voltage range of 2.5V. The internal reference
has an initial accuracy of 0.004% and can source up
to 20mA at the VREFH/VREFOUT pin. The device is
monotonic, provides very good linearity, and
minimizes undesired code-to-code transient voltages
(glitch). The DAC8164 uses a versatile 3-wire serial
interface that operates at clock rates up to 50MHz.
The interface is compatible with standard SPI™,
QSPI™, Microwire™, and digital signal processor
(DSP) interfaces.
–
–
–
–
–
2.5V Reference Voltage (enabled by default)
0.004% Initial Accuracy (typ)
2ppm/°C Temperature Drift (typ)
5ppm/°C Temperature Drift (max)
20mA Sink/Source Capability
•
•
•
•
•
Power-On Reset to Zero-Scale
Ultra-Low Power Operation: 1mA at 5V
Wide Power Supply Range: +2.7V to +5.5V
14-Bit Monotonic Over Temperature Range
The DAC8164 incorporates a power-on-reset circuit
that ensures the DAC output powers up at zero-scale
and remains there until a valid code is written to the
device. The device contains a power-down feature,
accessed over the serial interface, that reduces the
current consumption of the device to 1.3µA at 5V.
Power consumption is 2.6mW at 3V, reducing to
1.4µW in power-down mode. The low power
consumption, internal reference, and small footprint
make this device ideal for portable, battery-operated
equipment.
Settling Time: 10µs to ±0.006% Full-Scale
Range (FSR)
•
•
Low-Power Serial Interface with
Schmitt-Triggered Inputs: Up to 50MHz
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
•
•
1.8V to 5.5V Logic Compatibility
Temperature Range: –40°C to +105°C
The DAC8164 is drop-in and functionally compatible
with the DAC7564 and DAC8564, and functionally
compatible with the DAC7565, DAC8165 and
DAC8565. All these devices are available in a
TSSOP-16 package.
APPLICATIONS
•
•
•
•
•
•
Portable Instrumentation
Closed-Loop Servo-Control
Process Control, PLCs
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
IOVDD
AVDD
VREFL
DAC8164
DAC Register A
VOUTA
VOUTB
VOUTC
VOUTD
Data Buffer A
14-Bit DAC
DAC Register B
DAC Register C
DAC Register D
Data Buffer B
Data Buffer C
Data Buffer D
14-Bit DAC
14-Bit DAC
14-Bit DAC
RELATED
DEVICES
16-BIT
14-BIT
12-BIT
Pin and
Functionally
Compatible
DAC8564
DAC8164
DAC7564
SYNC
SCLK
DIN
Functionally
Compatible
Register
Control
Buffer
Control
DAC8565
DAC8165
DAC7565
24-Bit Shift Register
Power-Down
Control Logic
2.5V
Reference
Control Logic
GND
A0
A1
LDAC
ENABLE
VREFH/VREFOUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
DAC8164
SBAS410A–FEBRUARY 2008–REVISED FEBRUARY 2008......................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
REFERENCE
DRIFT
(ppm/°C)
SPECIFIED
TEMPERATURE PACKAGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PRODUCT
DAC8164A
DAC8164B
DAC8164C
DAC8164D
RANGE
MARKING
DAC8164
DAC8164B
DAC8164
±4
±2
±4
±2
±1
±1
±1
±1
25
25
5
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
PW
PW
PW
PW
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
5
–40°C to +105°C DAC8164D
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
DAC8164
–0.3 to +6
UNIT
V
AVDD to GND
Digital input voltage to GND
VOUT to GND
–0.3 to +VDD + 0.3
–0.3 to +VDD + 0.3
–0.3 to +VDD + 0.3
–40 to +125
–65 to +150
+150
V
V
VREF to GND
V
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
Power dissipation
°C
°C
°C
W
(TJ max – TA)/θJA
+118
Thermal impedance, θJA
Thermal impedance, θJC
°C/W
°C/W
V
+29
Human body model (HBM)
Charged device model (CDM)
4000
ESD rating
1500
V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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DAC8164
www.ti.com ......................................................................................................................................... SBAS410A–FEBRUARY 2008–REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8164
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
14
Bits
Measured by the line
passing through
codes 120 and 16200
DAC8164A, DAC8164C
DAC8164B, DAC8164D
±1
±1
±4
±2
LSB
Relative accuracy
LSB
Differential nonlinearity
Offset error
14-bit monotonic
±0.3
±5
±1
±8
LSB
mV
Offset error drift
Full-scale error
Gain error
±1
µV/°C
Measured by the line passing through codes 120 and
16200.
±0.2
±0.05
±1
±0.5
±0.2
% of FSR
% of FSR
AVDD = 5V
ppm of
FSR/°C
Gain temperature coefficient
AVDD = 2.7V
Output unloaded
±2
PSRR
Power-supply rejection ratio
1
mV/V
OUTPUT CHARACTERISTICS(2)
Output voltage range
0
VREF
10
V
To ±0.006% FSR, 0080h to 3F40h, RL = 2kΩ,
0pF < CL < 200pF
8
Output voltage settling time
µs
RL = 2kΩ, CL = 500pF
12
2.2
Slew rate
V/µs
RL = ∞
470
1000
0.15
0.15
0.25
–100
1
Capacitive load stability
pF
RL = 2kΩ
Code change glitch impulse
Digital feedthrough
1LSB change around major carry
SCLK toggling, SYNC high
Full-scale swing on adjacent channel
1kHz full-scale sine wave, outputs unloaded
At mid-code input
nV-s
nV-s
LSB
dB
Channel-to-channel dc crosstalk
Channel-to-channel ac crosstalk
DC output impedance
Ω
Short-circuit current
50
mA
Coming out of power-down mode, AVDD = 5V
Coming out of power-down mode, AVDD = 3V
2.5
Power-up time
µs
5
AC PERFORMANCE(2)
SNR
87
–78
79
dB
dB
THD
TA = +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz.
First 19 harmonics removed for SNR calculation.
SFDR
dB
SINAD
77
dB
DAC output noise density
DAC output noise
REFERENCE
TA = +25°C, at mid-code input, fOUT = 1kHz
TA = +25°C, at mid-code input, 0.1Hz to 10Hz
120
6
nV/√Hz
µVPP
AVDD = 5.5V
AVDD = 3.6V
360
348
µA
µA
Internal reference current consumption
External reference current
External VREF = 2.5V, if internal reference is disabled,
all four channels active
80
µA
Reference input range VREFH voltage
Reference input range VREFL voltage
Reference input impedance
VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V
VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V
0
0
AVDD
V
V
AVDD/2
31
kΩ
(1) Linearity calculated using a reduced code range of 120 to 16200; output unloaded.
(2) Ensured by design or characterization; not production tested.
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SBAS410A–FEBRUARY 2008–REVISED FEBRUARY 2008......................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8164
PARAMETER
REFERENCE OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
Initial accuracy
TA = +25°C
TA = +25°C
DAC8164A, DAC8164B(3)
DAC8164C, DAC8164D(4)
f = 0.1Hz to 10Hz
2.4995
–0.02
2.5
±0.004
5
2.5005
0.02
25
V
%
Output voltage temperature drift
Output voltage noise
ppm/°C
µVPP
2
5
12
TA = +25°C, f = 1MHz, CL = 0µF
TA = +25°C, f = 1MHz, CL = 1µF
TA = +25°C, f = 1MHz, CL = 4µF
TA = +25°C
50
Output voltage noise density
(high-frequency noise)
20
nV/√Hz
16
Load regulation, sourcing(5)
Load regulation, sinking(5)
Output current load capability(6)
Line regulation
30
µV/mA
µV/mA
mA
TA = +25°C
15
±20
10
TA = +25°C
µV/V
ppm
Long-term stability/drift (aging)(5)
TA = +25°C, time = 0 to 1900 hours
First cycle
50
100
25
Thermal hysteresis(5)
ppm
Additional cycles
LOGIC INPUTS(6)
Input current
±1
µA
2.7V ≤ IOVDD ≤ 5.5V
1.8V ≤ IOVDD ≤ 2.7V
2.7V ≤ IOVDD ≤ 5.5V
1.8V ≤ IOVDD ≤ 2.7V
0.3 × IOVDD
0.1 × IOVDD
VIN
L
Logic input LOW voltage
Logic input HIGH voltage
V
0.7 × IOVDD
VINH
V
0.95 × IOVDD
Pin capacitance
3
pF
POWER REQUIREMENTS
AVDD
2.7
1.8
5.5
5.5
20
V
V
IOVDD
(6)
IOIDD
10
1
µA
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
1.6
1.5
3.5
2.5
8.8
5.4
19
Normal mode
mA
µA
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
0.95
1.3
0.5
3.6
2.6
4.7
1.4
(7)
IDD
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
All power-down modes
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
Normal mode
mW
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
Power
Dissipation
(7)
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
All power-down modes
µW
°C
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
9
TEMPERATURE RANGE
Specified performance
–40
+105
(3) Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
(4) Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +120°C.
(5) Explained in more detail in the Application Information section of this data sheet.
(6) Ensured by design or characterization; not production tested.
(7) Input code = 8192, reference current included, no load.
4
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PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(Top View)
VOUT
A
1
2
3
4
5
6
7
8
16 LDAC
15
VOUT
B
ENABLE
VREFH/VREFOUT
AVDD
14 A1
13 A0
DAC8164
IOVDD
VREF
L
12
11
10
9
DIN
GND
VOUT
C
D
SCLK
SYNC
VOUT
PIN DESCRIPTIONS
PIN
1
NAME
DESCRIPTION
VOUT
VOUT
A
B
Analog output voltage from DAC A
Analog output voltage from DAC B
2
VREFH/
VREFOUT
3
Positive reference input / reference output 2.5V if internal reference used.
4
5
6
7
8
AVDD
Power-supply input, 2.7V to 5.5V
Negative reference input
VREF
L
GND
Ground reference point for all circuitry on the part
Analog output voltage from DAC C
Analog output voltage from DAC D
VOUT
VOUT
C
D
Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC8164. Schmitt-Trigger logic input.
9
SYNC
10
11
SCLK
DIN
Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-Trigger logic input.
12
13
14
15
16
IOVDD
A0
Digital input-output power supply
Address 0—sets device address; see Table 5.
A1
Address 1—sets device address; see Table 5.
ENABLE
LDAC
The enable pin (active low) connects the SPI interface to the serial port
Load DACs; rising edge triggered, loads all DAC registers
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SERIAL WRITE OPERATION
6
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www.ti.com ......................................................................................................................................... SBAS410A–FEBRUARY 2008–REVISED FEBRUARY 2008
TIMING REQUIREMENTS(1)(2)
At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8164
PARAMETER
TEST CONDITIONS
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
MIN TYP MAX UNIT
40
ns
20
(3)
t1
t2
t3
t4
t5
t6
t7
t8
t9
SCLK cycle time
SCLK HIGH time
SCLK LOW time
10
ns
20
20
ns
10
0
SYNC to SCLK rising edge setup time
Data setup time
ns
0
5
ns
5
4.5
Data hold time
ns
4.5
0
SCLK falling edge to SYNC rising edge
Minimum SYNC HIGH time
ns
0
40
ns
20
130
24th SCLK falling edge to SYNC falling edge
ns
130
15
ns
15
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
t10
t11
t12
t13
t14
t15
15
ns
15
ENABLE falling edge to SYNC falling edge
24th SCLK falling edge to ENABLE rising edge
24th SCLK falling edge to LDAC rising edge
LDAC rising edge to ENABLE rising edge
LDAC HIGH time
10
ns
10
50
ns
50
10
ns
10
10
ns
10
(1) All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.
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TYPICAL CHARACTERISTICS: Internal Reference
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades A and B)
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.503
2.502
2.501
2.500
2.499
2.498
2.497
10 Units Shown
80 100
13 Units Shown
80 100 120
-40
-20
0
20
40
60
120
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
Figure 1.
Figure 2.
REFERENCE OUTPUT TEMPERATURE DRIFT
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°C, Grades C and D)
(–40°C to +120°, Grades A and B)
40
30
20
10
0
30
20
10
0
Typ: 5ppm/°C
Typ: 2ppm/°C
Max: 5ppm/°C
Max: 25ppm/°C
0.5
1
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Temperature Drift (ppm/°C)
Figure 3.
3
5
7
9
11
13
15
17
19
Temperature Drift (ppm/°C)
Figure 4.
LONG-TERM
REFERENCE OUTPUT TEMPERATURE DRIFT
(0°C to +120°C, Grades C and D)
STABILITY/DRIFT(1)
200
150
100
50
40
30
20
10
0
Typ: 1.2ppm/°C
Max: 3ppm/°C
0
-50
-100
-150
-200
Average
20 Units Shown
1200 1500 1800
0
300
600
900
0.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Temperature Drift (ppm/°C)
Figure 5.
Time (Hours)
Figure 6.
(1) Explained in more detail in the Application Information section of this data sheet.
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TYPICAL CHARACTERISTICS: Internal Reference (continued)
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE NOISE DENSITY
vs FREQUENCY
INTERNAL REFERENCE NOISE
0.1Hz TO 10Hz
300
250
200
150
100
50
12mV (peak-to-peak)
Reference Unbuffered
CREF = 0mF
CREF = 4.8mF
0
Time (2s/div)
10
100
1k
10k
100k
1M
20 25
5.5
Frequency (Hz)
Figure 7.
Figure 8.
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades A and B)
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
+120°C
+120°C
+25°C
+25°C
-40°C
-40°C
-25 -20 -15 -10 -5
0
5
10
15
-25 -20 -15 -10 -5
0
5
10
15
20 25
ILOAD (mA)
ILOAD (mA)
Figure 9.
Figure 10.
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades A and B)
2.503
2.502
2.501
2.500
2.499
2.498
2.503
2.502
2.501
2.500
2.499
2.498
+120°C
-40°C
+120°C
+25°C
+25°C
-40°C
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
AVDD (V)
AVDD (V)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
2
1
2
1
Channel A, AVDD = 5V, External VREF = 4.99V
Channel B, AVDD = 5V, External VREF = 4.99V
0
0
-1
-2
-1
-2
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
2
1
2
1
Channel D, AVDD = 5V, External VREF = 4.99V
0
0
-1
-2
-1
-2
Channel C, AVDD = 5V, External VREF = 4.99V
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 15.
Figure 16.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
2
1
2
1
Channel A, AVDD = 5V, External VREF = 4.99V
Channel B, AVDD = 5V, External VREF = 4.99V
0
0
-1
-2
-1
-2
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 17.
Figure 18.
10
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
2
1
2
1
Channel D, AVDD = 5V, External VREF = 4.99V
0
0
-1
-2
-1
-2
Channel C, AVDD = 5V, External VREF = 4.99V
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 19.
Figure 20.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
2
1
2
1
Channel A, AVDD = 5V, External VREF = 4.99V
Channel B, AVDD = 5V, External VREF = 4.99V
0
0
-1
-2
-1
-2
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 21.
Figure 22.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
2
1
2
1
Channel D, AVDD = 5V, External VREF = 4.99V
0
0
-1
-2
-1
-2
Channel C, AVDD = 5V, External VREF = 4.99V
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
OFFSET ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
4
3
0.50
0.25
0
AVDD = 5V
Internal VREF Enabled
AVDD = 5V
Internal VREF Enabled
Ch C
Ch C
Ch D
2
1
Ch D
Ch A
Ch B
Ch A
-0.25
0
Ch B
-1
-0.50
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 25.
Figure 26.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
5.5
5.5
4.5
DAC Loaded with 3FFFh
DAC Loaded with 3FFFh
4.5
3.5
3.5
AVDD = 5V, Ch A
AVDD = 5V, Ch B
Internal Reference Disabled
Internal Reference DIsabled
2.5
2.5
1.5
1.5
0.5
0.5
DAC Loaded with 0000h
15
DAC Loaded with 0000h
15
-0.5
-0.5
0
5
10
20
0
5
10
20
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 27.
Figure 28.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
5.5
4.5
5.5
4.5
DAC Loaded with 3FFFh
DAC Loaded with 3FFFh
3.5
3.5
AVDD = 5V, Ch C
Internal Reference Disabled
AVDD = 5V, Ch D
Internal Reference Disabled
2.5
2.5
1.5
1.5
0.5
0.5
DAC Loaded with 0000h
15
DAC Loaded with 0000h
15
-0.5
-0.5
0
5
10
20
0
5
10
20
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1400
1300
1200
1100
1000
900
1300
1200
1100
1000
900
AVDD = 5.5V
Internal VREF Included
AVDD = 5.5V
Internal VREF Included
DAC Loaded with 2000h
800
800
0
6144 8192 10240 12288 14336 16384
-40
-20
0
20
40
60
80
100
120
5.5
6
2048 4096
Digital Input Code
Temperature (°C)
Figure 31.
Figure 32.
POWER-SUPPLY CURRENT
vs POWER-SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE
1100
1.2
AVDD = 2.7V to 5.5V
Internal VREF Included
AVDD = 2.7V to 5.5V
Internal VREF Included
1090
1080
1070
1060
1050
1.0
0.8
0.6
0.4
0.2
DAC Loaded with 2000h
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
AVDD (V)
AVDD (V)
Figure 33.
Figure 34.
POWER-DOWN CURRENT
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
3200
2800
2400
2000
1600
1200
800
3.0
2.5
2.0
1.5
1.0
0.5
0
AVDD = IOVDD = 5.5V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
AVDD = 5.5V
Sweep from
0V to 5.5V
Sweep from
5.5V to 0V
0
1
2
3
4
5
-40
-20
0
20
40
60
80
100
120
VLOGIC (V)
Temperature (°C)
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
-50
-60
-70
-80
-90
-100
-40
-50
-60
-70
-80
-90
-100
Channel A, AVDD = 5V, External VREF = 4.99V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
Channel B, AVDD = 5V, External VREF = 4.99V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
THD
THD
3rd Harmonic
3rd Harmonic
2nd Harmonic
2nd Harmonic
0
1
2
3
4
5
0
1
2
3
4
5
fOUT (kHz)
fOUT (kHz)
Figure 37.
Figure 38.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
-50
-60
-70
-80
-90
-100
-40
-50
-60
-70
-80
-90
-100
Channel C, AVDD = 5V, External VREF = 4.99V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
Channel D, AVDD = 5V, External VREF = 4.99V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
THD
THD
3rd Harmonic
2nd Harmonic
3rd Harmonic
2nd Harmonic
0
1
2
3
4
5
0
1
2
3
4
5
fOUT (kHz)
fOUT (kHz)
Figure 39.
Figure 40.
POWER-SUPPLY CURRENT
HISTOGRAM
60
AVDD = 5.5V
Internal VREF Included
50
40
30
20
10
0
950
1000
1050
1100
1150
1200
Power-Supply Current (mA)
Figure 41.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
POWER SPECTRAL DENSITY
96
94
92
90
88
86
84
0
-20
All Channels, AVDD = 5V, External VREF = 4.99V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
AVDD = 5V, External VREF = 4.99V
fOUT = 1kHz, fS = 225kSPS
Measurement Bandwidth = 20kHz
Channel B
-40
Channel C
-60
Channel A
-80
-100
-120
-140
Channel D
0
1
2
3
4
5
0
5
10
15
20
fOUT (kHz)
Frequency (Hz)
Figure 42.
Figure 43.
FULL-SCALE SETTLING TIME:
5V RISING EDGE
FULL-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
AVDD = 5V
Ext VREF = 4.096V
From Code: 3FFFh
To Code: 0000h
AVDD = 5V
Ext VREF = 4.096V
From Code: 0000h
To Code: 3FFFh
Falling
Edge
1V/div
Rising Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 44.
Figure 45.
HALF-SCALE SETTLING TIME:
5V RISING EDGE
HALF-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
AVDD = 5V
Ext VREF = 4.096V
From Code: 3000h
To Code: 1000h
AVDD = 5V
Ext VREF = 4.096V
From Code: 1000h
To Code: 3000h
Rising
Edge
1V/div
Falling
Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 46.
Figure 47.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
GLITCH ENERGY:
5V, 1LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 1LSB STEP, FALLING EDGE
AVDD = 5V
AVDD = 5V
Int VREF = 2.5V
From Code: 07FFh
To Code: 0800h
Glitch: 0.09nV-s
Int VREF = 2.5V
From Code: 0800h
To Code: 07FFh
Glitch: 0.1nV-s
Time (2ms/div)
Time (2ms/div)
Figure 48.
Figure 49.
GLITCH ENERGY:
5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 16LSB STEP, FALLING EDGE
AVDD = 5V
AVDD = 5V
Int VREF = 2.5V
From Code: 0800h
To Code: 0810h
Glitch: 0.3nV-s
Int VREF = 2.5V
From Code: 0810h
To Code: 0800h
Glitch: 0.2nV-s
Time (5ms/div)
Time (5ms/div)
Figure 50.
Figure 51.
GLITCH ENERGY:
5V, 64LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 64LSB STEP, FALLING EDGE
AVDD = 5V
AVDD = 5V
Int VREF = 2.5V
From Code: 2040h
To Code: 2000h
Glitch: 0.1nV-s
Int VREF = 2.5V
From Code: 2000h
To Code: 2040h
Glitch: 0.1nV-s
Time (2ms/div)
Time (2ms/div)
Figure 52.
Figure 53.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
DAC OUTPUT NOISE DENSITY
vs FREQUENCY(1)
DAC OUTPUT NOISE DENSITY
vs FREQUENCY(2)
1200
1000
800
600
400
200
0
400
350
300
250
200
150
100
50
Internal Reference Enabled
No Load at VREFH/VREFOUT Pin
DAC = Full-Scale
Internal Reference Enabled
4.8mF versus No Load at VREFH/VREFOUT Pin
No Load on Reference
Mid-Scale
Full Scale
Zero Scale
4.8mF Capacitor
On Reference
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 54.
Figure 55.
DAC OUTPUT NOISE
0.1Hz TO 10Hz
6mV (peak-to-peak)
DAC = Mid-Scale
Internal Reference Enabled
Time (2s/div)
Figure 56.
(1) Explained in more detail in the Application Information section of this data sheet.
(2) See the Application Information section for more information.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1400
1300
1200
1100
1000
900
2400
2000
1600
1200
800
AVDD = IOVDD = 3.6V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
AVDD = 3.6V
Internal VREF Included
DAC Loaded with 2000h
Sweep from 0V to 3.6V
Sweep from
3.6V to 0V
800
-40
-20
0
20
40
60
80
100
120
0
0.5
1.0
1.5
2.0
VLOGIC (V)
Figure 57.
2.5
3.0
3.5
4.0
Temperature (°C)
Figure 58.
POWER-SUPPLY CURRENT
HISTOGRAM
80
AVDD = 3.6V
Internal VREF Included
60
40
20
0
900
950
1000
1050
1100
1150
1200
Power-Supply Current (mA)
Figure 59.
18
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
2
1
2
1
Channel A, AVDD = 2.7V, Internal VREF = 2.5V
Channel B, AVDD = 2.7V, Internal VREF = 2.5V
0
0
-1
-2
-1
-2
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 60.
Figure 61.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
2
1
2
1
Channel D, AVDD = 2.7V, Internal VREF = 2.5V
0
0
-1
-2
-1
-2
Channel C, AVDD = 2.7V, Internal VREF = 2.5V
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 62.
Figure 63.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
2
1
2
1
Channel A, AVDD = 2.7V, Internal VREF = 2.5V
Channel B, AVDD = 2.7V, Internal VREF = 2.5V
0
0
-1
-2
-1
-2
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 64.
Figure 65.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
2
1
2
1
Channel D, AVDD = 2.7V, Internal VREF = 2.5V
0
0
-1
-2
-1
-2
Channel C, AVDD = 2.7V, Internal VREF = 2.5V
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
0
0
0
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 66.
Figure 67.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
2
1
2
1
Channel A, AVDD = 2.7V, Internal VREF = 2.5V
Channel B, AVDD = 2.7V, Internal VREF = 2.5V
0
0
-1
-2
-1
-2
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 68.
Figure 69.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
2
1
2
1
Channel D, AVDD = 2.7V, Internal VREF = 2.5V
0
0
-1
-2
-1
-2
Channel C, AVDD = 2.7V, Internal VREF = 2.5V
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
2048 4096
6144 8192 10240 12288 14336 16384
2048 4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 70.
Figure 71.
20
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
OFFSET ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
4
3
0.50
0.25
0
AVDD = 2.7V
Internal VREF Enabled
AVDD = 2.7V
Internal VREF Enabled
Ch C
Ch C
Ch D
2
1
Ch D
Ch B
Ch B
Ch A
-0.25
0
Ch A
-40 -20
-1
-0.50
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 72.
Figure 73.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
3.0
3.0
2.5
2.0
1.5
1.0
0.5
0
DAC Loaded with 3FFFh
DAC Loaded with 3FFFh
2.5
2.0
1.5
1.0
0.5
0
AVDD = 2.7V, Ch A
AVDD = 2.7V, Ch B
Internal Reference Enabled
Internal Reference Enabled
DAC Loaded with 0000h
5
DAC Loaded with 0000h
5
0
10
15
20
0
10
15
20
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 74.
Figure 75.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
DAC Loaded with 3FFFh
DAC Loaded with 3FFFh
AVDD = 2.7V, Ch C
AVDD = 2.7V, Ch D
Internal Reference Enabled
Internal Reference Enabled
DAC Loaded with 0000h
5
DAC Loaded with 0000h
5
0
10
15
20
0
10
15
20
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 76.
Figure 77.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
1300
1200
1100
1000
900
1600
1400
1200
1000
800
AVDD = 2.7V
Internal VREF Included
AVDD = 2.7V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
Sweep from
2.7V to 0V
Sweep from 0V to 2.7V
800
0
6144 8192 10240 12288 14336 16384
2048 4096
0
0.5
1.0
1.5
2.0
2.5
3.0
Digital Input Code
VLOGIC (V)
Figure 79.
Figure 78.
FULL-SCALE SETTLING TIME:
2.7V RISING EDGE
FULL-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
AVDD = 2.7V
Int VREF = 2.5V
From Code: 3FFFh
To Code: 0000h
Rising
Edge
0.5V/div
AVDD = 2.7V
Int VREF = 2.5V
From Code: 0000h
To Code: 3FFFh
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 80.
Figure 81.
HALF-SCALE SETTLING TIME:
2.7V RISING EDGE
HALF-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
AVDD = 2.7V
Int VREF = 2.5V
From Code: 3000h
To Code: 1000h
AVDD = 2.7V
Int VREF = 2.5V
From Code: 1000h
To Code: 3000h
Rising
Edge
0.5V/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 82.
Figure 83.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
GLITCH ENERGY:
2.7V, 1LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 1LSB STEP, FALLING EDGE
AVDD = 2.7V
AVDD = 2.7V
Int VREF = 2.5V
From Code: 07FFh
To Code: 0800h
Glitch: 0.02nV-s
Int VREF = 2.5V
From Code: 0800h
To Code: 07FFh
Glitch: 0.02nV-s
Time (2ms/div)
Time (2ms/div)
Figure 84.
Figure 85.
GLITCH ENERGY:
2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 16LSB STEP, FALLING EDGE
AVDD = 2.7V
AVDD = 2.7V
Int VREF = 2.5V
From Code: 0800h
To Code: 0810h
Glitch: 0.01nV-s
Int VREF = 2.5V
From Code: 0810h
To Code: 0800h
Glitch: 0.01nV-s
Time (5ms/div)
Time (5ms/div)
Figure 86.
Figure 87.
GLITCH ENERGY:
2.7V, 64LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 64LSB STEP, FALLING EDGE
AVDD = 2.7V
AVDD = 2.7V
Int VREF = 2.5V
From Code: 2040h
To Code: 2000h
Glitch: 0.1nV-s
Int VREF = 2.5V
From Code: 2000h
To Code: 2040h
Glitch: 0.1nV-s
Time (2ms/div)
Time (2ms/div)
Figure 88.
Figure 89.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs TEMPERATURE
POWER-DOWN CURRENT
vs TEMPERATURE
1400
1300
1200
1100
1000
900
2.0
1.5
1.0
0.5
0
AVDD = 2.7V
Internal VREF Included
DAC Loaded with 2000h
AVDD = 2.7V
800
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 90.
Figure 91.
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THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
VREF
The DAC8164 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 92
shows a block diagram of the DAC architecture.
RDIVIDER
VREF
2
VREFH
50kW
50kW
R
62kW
VOUTX
REF(+)
Resistor String
REF(-)
DAC
Register
To Output Amplifier
(2x Gain)
R
VREFL
Figure 92. DAC8164 Architecture
The input coding to the DAC8164 is straight binary,
so the ideal output voltage is given by Equation 1.
DIN
VOUTX = 2 ´ VREFL + (VREFH - VREFL) ´
16384
(1)
R
R
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 16383. X represents channel A, B, C, or D.
RESISTOR STRING
The resistor string section is shown in Figure 93. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
Figure 93. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to AVDD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 2.2V/µs,
with a full-scale settling time of 8µs with the output
unloaded.
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INTERNAL REFERENCE
VREF
The DAC8164 includes a 2.5V internal reference that
is enabled by default. The internal reference is
externally available at the VREFH/VREFOUT pin. A
minimum 100nF capacitor is recommended between
the reference output and GND for noise filtering.
Reference
The internal reference of the DAC8164 is a bipolar
Disable
transistor-based,
precision
bandgap
voltage
reference. Figure 94 shows the basic bandgap
topology. Transistors Q1 and Q2 are biased such that
the current density of Q1 is greater than that of Q2.
The difference of the two base-emitter voltages
(VBE1 – VBE2) has a positive temperature coefficient
and is forced across resistor R1. This voltage is
gained up and added to the base-emitter voltage of
Q2, which has a negative temperature coefficient. The
resulting output voltage is virtually independent of
temperature. The short-circuit current is limited by
design to approximately 100mA.
Q1
1
N
Q2
R1
R2
Figure 94. Simplified Schematic of the Bandgap
Reference
Enable/Disable Internal Reference
To then enable the internal reference, either perform
a power-cycle to reset the device, or write the 24-bit
serial command shown in Table 2. These actions put
the internal reference back into the default mode. In
the default mode, the internal reference powers down
automatically when all DACs power down in any of
the power-down modes (see the Power-Down Modes
section); the internal reference powers up
automatically when any DAC is powered up.
The internal reference in the DAC8164 is enabled by
default and operates in automatic mode; however, the
reference can be disabled for debugging, evaluation
purposes, or when using an external reference. A
serial command that requires a 24-bit write sequence
(see the Serial Interface section) must be used to
disable the internal reference, as shown in Table 1.
During the time that the internal reference is disabled,
the DAC functions normally using an external
reference. At this point, the internal reference is
disconnected from the VREFH/VREFOUT pin (3-state
output). Do not attempt to drive the VREFH/VREFOUT
pin externally and internally at the same time
indefinitely.
The DAC8164 also provides the option of keeping the
internal reference powered on all the time, regardless
of the DAC(s) state (powered up or down). To keep
the internal reference powered on, regardless of the
DAC(s) state, write the 24-bit serial command shown
in Table 3.
Table 1. Write Sequence for Disabling Internal Reference
(internal reference always powered down—012000h)
DB23
0
DB16
DB13
DB0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
X
X
X
|———————————————– Data Bits –———————————————|
Table 2. Write Sequence for Enabling Internal Reference
(internal reference powered up to default mode—010000h)
DB23
0
DB16
DB0
X
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
|———————————————– Data Bits –———————————————|
Table 3. Write Sequence for Enabling Internal Reference
(internal reference always powered up—011000h)
DB23
0
DB16
DB12
DB0
X
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
|———————————————– Data Bits –———————————————|
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SERIAL INTERFACE
be kept LOW or brought HIGH. In either case, the
minimum delay time from the 24th falling SCLK edge
to the next falling SYNC edge must be met in order to
properly begin the next cycle. To assure the lowest
power consumption of the device, care should be
taken that the levels are as close to each rail as
possible. Refer to the Typical Characteristics section
for Figure 36, Figure 57, and Figure 79 (Supply
Current vs Logic Input Voltage).
The DAC8164 has a 3-wire serial interface (SYNC,
SCLK, and DIN) compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs.
See the Serial Write Operation timing diagram for an
example of a typical write sequence.
The DAC8164 input shift register is 24 bits wide,
consisting of eight control bits (DB23 to DB16) and 14
data bits (DB15 to DB2). Bits DB0 and DB1 are
ignored by the DAC and should be treated as don't
care bits. All 24 bits of data are loaded into the DAC
under the control of the serial clock input, SCLK.
DB23 (MSB) is the first bit that is loaded into the DAC
shift register, and is followed by the rest of the 24-bit
word pattern, left-aligned. This configuration means
that the first 24 bits of data are latched into the shift
register and any further clocking of data is ignored.
The DAC8164 receives all 24 bits of data and
decodes the first eight bits to determine the DAC
operating/control mode. The 14 bits of data that
follow are decoded by the DAC to determine the
equivalent analog output, while the last two bits (DB1
and DB0) are ignored. The data format is straight
binary with all '0's corresponding to 0V output and all
IOVDD AND VOLTAGE TRANSLATORS
The IOVDD pin powers the the digital input structures
of the DAC8164. For single-supply operation, it can
be tied to AVDD. For dual-supply operation, the IOVDD
pin provides interface flexibility with various CMOS
logic families and should be connected to the logic
supply of the system. Analog circuits and internal
logic of the DAC8164 use AVDD as the supply
voltage. The external logic high inputs translate to
AVDD by level shifters. These level shifters use the
IOVDD voltage as a reference to shift the incoming
logic HIGH levels to AVDD. IOVDD is ensured to
operate from 2.7V to 5.5V regardless of the AVDD
voltage, assuring compatibility with various logic
families. Although specified down to 2.7V, IOVDD
operates at as low as 1.8V with degraded timing and
temperature performance. For lowest power
consumption, logic VIH levels should be as close as
possible to IOVDD, and logic VIL levels should be as
close as possible to GND voltages.
'1's corresponding to full-scale output (that is, VREF
–
1 LSB). For all documentation purposes, the data
format and representation here is a true 14-bit pattern
(that is, 3FFFh for full-scale), even if the usable 14
bits of data are extracted from a left-justified 16-bit
data format that the DAC8164 requires.
The write sequence begins by bringing the SYNC line
low. Data from the DIN line are clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 50MHz, making
the DAC8164 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked into the shift register and the shift
register locks. Further clocking does not change the
shift register data. After 24 bits are locked into the
shift register, the eight MSBs are used as control bits
and the following 14 LSBs are used as data. After
receiving the 24th falling clock edge, the DAC8164
decodes the eight control bits and 14 data bits to
perform the required function, without waiting for a
SYNC rising edge. A new write sequence starts at the
next falling edge of SYNC. A rising edge of SYNC
before the 24-bit sequence is complete resets the SPI
interface; no data transfer occurs. After the 24th
falling edge of SCLK is received, the SYNC line may
INPUT SHIFT REGISTER
The input shift register (SR) of the DAC8164 is 24
bits wide, as shown in Table 4, and consists of eight
control bits (DB23 to DB16), 14 data bits (DB15 to
DB2), and two don't care bits. The first two control
bits (DB23 and DB22) are the address match bits.
The DAC8164 offers hardware-enabled addressing
capability, allowing a single host to talk to up to four
DAC8164s through a single SPI bus without any glue
logic, enabling up to 16-channel operation. The state
of DB23 should match the state of pin A1; similarly,
the state of DB22 should match the state of pin A0. If
there is no match, the control command and the data
(DB21...DB0) are ignored by the DAC8164. That is, if
there is no match, the DAC8164 is not addressed.
Address matching can be overridden by the
broadcast update.
Table 4. Data Input Register Format
DB23
DB12
D10
A1
A0
D8
LD1
D7
LD0
D6
0
DAC Select 1
D4
DAC Select 0
D3
PD0
D2
D13
D1
D12
D0
D11
X
DB11
DB0
D9
D5
X
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LD1 (DB21) and LD0 (DB20) control the loading of
each analog output with the specified 14-bit data
value or power-down command. Bit DB19 must
always be '0'. The DAC channel select bits (DB18,
DB17) control the destination of the data (or
power-down command) from DAC A through DAC D.
The final control bit, PD0 (DB16), selects the
power-down mode of the DAC8164 channels as well
as the power-down mode of the internal reference.
DB21 = 0 and DB20 = 1: Single-channel update.
The data buffer and DAC register corresponding to a
DAC selected by DB18 and DB17 update with the
contents of SR data (or power-down).
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 updates with
the SR data; simultaneously, all the other channels
update with previously stored data (or power-down)
from data buffers.
The DAC8164 supports a number of different load
commands. The load commands include broadcast
commands to address all the DAC8164s on an SPI
bus. The load commands are summarized as follows:
DB21 = 1 and DB20 = 1: Broadcast update. All the
DAC8164s on the SPI bus respond, regardless of
address matching. If DB18 = 0, SR data are ignored
and any channels from all DAC8164s update with
previously stored data (or power-down). If DB18 = 1,
SR data (or power-down) update any channels of all
DAC8164s in the system. This broadcast update
feature allows the simultaneous update of up to 16
channels.
DB21 = 0 and DB20 = 0: Single-channel store. The
data buffer corresponding to a DAC selected by
DB18 and DB17 updates with the contents of SR
data (or power-down).
Refer to Table 5 for more information.
Table 5. Control Matrix for the DAC8164
DB23
A1
DB22
A0
DB21
LD 1
DB20
LD 0
DB19
0
DB18
DB17
DB16
DB15
DB14
DB13-DB2
DB1-DB0
Don't
Care
DAC Sel 1
DAC Sel 0
PD0
MSB
MSB-1
MSB-2...LSB
(Address Select)
DESCRIPTION
This address selects one of four possible
devices on a single SPI data bus based on the
address pin(s) state of each device.
0/1 0/1
See Below
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
Data
X
X
X
X
Write to buffer A with data
Write to buffer B with data
Write to buffer C with data
Write to buffer D with data
Data
Data
Data
Write to buffer (selected by DB17 and DB18)
with power-down command
0
0
0
0
1
1
0
0
0
(00, 01, 10, or 11)
(00, 01, 10, or 11)
(00, 01, 10, or 11)
1
0
1
See Table 6
0
0
X
X
X
A0 and A1 should
correspond to the
package address
set via pins 13
and 14
Write to buffer with data and load DAC
(selected by DB17 and DB18)
Data
Data
Write to buffer with power-down command and
load DAC (selected by DB17 and DB18)
See Table 6
See Table 6
Write to buffer with data (selected by DB17 and
DB18) and then load all DACs simultaneously
from their corresponding buffers
1
1
0
0
0
0
(00, 01, 10, or 11)
(00, 01, 10, or 11)
0
1
X
X
Write to buffer with power-down command
(selected by DB17 and DB18) and then load all
DACs simultaneously from their corresponding
buffers
0
Broadcast Modes
Simultaneously update all channels of all
DAC8164 devices in the system with data
stored in each channels data buffer
X
X
1
1
0
0
X
X
X
X
Write to all devices and load all DACs with SR
data
X
X
X
X
1
1
1
1
0
0
1
1
X
X
0
1
Data
X
X
Write to all devices and load all DACs with
power-down command in SR
See Table 6
0
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SYNC INTERRUPT
LDAC FUNCTIONALITY
In a normal write sequence, the SYNC line stays low
for at least 24 falling edges of SCLK and the
addressed DAC register updates on the 24th falling
edge. However, if SYNC is brought high before the
24th falling edge, it acts as an interrupt to the write
sequence; the shift register resets and the write
sequence is discarded. Neither an update of the data
buffer contents, DAC register contents, nor a change
in the operating mode occurs (as shown in
Figure 95).
The DAC8164 offers both a software and hardware
simultaneous
update
function.
The
DAC
double-buffered architecture has been designed so
that new data can be entered for each DAC without
disturbing the analog outputs.
DAC8164 data updates are synchronized with the
falling edge of the 24th SCLK cycle, which follows a
falling edge of SYNC. For such synchronous updates,
the LDAC pin is not required and it must be
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
asynchronous DAC updates. To do an LDAC
operation, single-channel store(s) should be done
(loading DAC buffers) by setting LD0 and LD1 to '0'.
Multiple single-channel updates can be done in order
to set different channel buffers to desired values and
then make a rising edge on LDAC. Data buffers of all
channels must be loaded with desired data before an
POWER-ON RESET TO ZERO-SCALE
The DAC8164 contains a power-on reset circuit that
controls the output voltage during power-up. On
power-up, the DAC registers are filled with zeros and
the output voltages are set to zero-scale; they remain
that way until a valid write sequence and load
command are made to the respective DAC channel.
The power-on reset is useful in applications where it
is important to know the state of the output of each
DAC while the device is in the process of powering
up.
LDAC rising edge. After
a
low-to-high LDAC
transition, all DACs are simultaneously updated with
the contents of the corresponding data buffers. If the
contents of a data buffer are not changed by the
serial interface, the corresponding DAC output
remains unchanged after the LDAC trigger.
No device pin should be brought high before power is
applied to the device. The internal reference is
powered on by default and remains that way until a
valid reference-change command is executed.
ENABLE PIN
For normal operation, the enable pin must be driven
to a logic low. If the enable pin is driven high, the
DAC8164 stops listening to the serial port. However,
SCLK, SYNC, and DIN must not be kept floating, but
must be at some logic level. This feature can be
useful for applications that share the same serial port.
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB0
DB23
DB0
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 24th Falling Edge
Valid Write Sequence:
Output/Mode Updates on the 24th Falling Edge
Figure 95. SYNC Interrupt Facility
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POWER-DOWN MODES
DACs. However, for the three power-down modes,
the supply current falls to 1.3µA at 5.5V (0.5µA at
3.6V). Not only does the supply current fall, but the
output stage also switches internally from the output
of the amplifier to a resistor network of known values.
The DAC8164 has two separate sets of power-down
commands. One set is for the DAC channels and the
other set is for the internal reference. For more
information on powering down the reference, see the
Enable/Disable Internal Reference section.
The advantage of this switching is that the output
impedance of the device is known while it is in
power-down mode. As described in Table 6, there are
three different power-down options. VOUT can be
connected internally to GND through a 1kΩ resistor, a
100kΩ resistor, or open circuited (High-Z). The output
stage is shown in Figure 96. In other words, DB16,
DB15, and DB14 = '111' represent a power-down
condition with Hi-Z output impedance for a selected
channel. '101' represents a power-down condition
with 1kΩ output impedance, and '110' represents a
power-down condition with 100kΩ output impedance.
DAC Power-Down Commands
The DAC8164 uses four modes of operation. These
modes are accessed by setting three bits (PD2, PD1,
and PD0) in the shift register. Table 6 shows how to
control the operating mode with data bits PD0
(DB16), PD1 (DB15), and PD2 (DB14).
Table 6. DAC Operating Modes
PD0
PD1
PD2
(DB16)
(DB15)
(DB14)
DAC OPERATING MODES
Normal operation
0
1
1
1
X
0
1
1
X
1
0
1
Output typically 1kΩ to GND
Output typically 100kΩ to GND
Output high-impedance
Resistor
Amplifier
VOUTX
String
DAC
The DAC8164 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast a power-down
condition to all the DAC8164s in a system; it is also
possible to simultaneously power-down a channel
while updating data on other channels.
Power-Down
Circuitry
Resistor
Network
Figure 96. Output Stage During Power-Down
When the PD0 bit is set to '0', the device works
normally with its typical current consumption of 1mA
at 5.5V with an input code = 8192. The reference
current is included with the operation of all four
All analog channel circuitries are shut down when the
power-down mode is exercised. However, the
contents of the DAC register are unaffected when in
power down. The time required to exit power-down is
typically 2.5µs for VDD = 5V, and 5µs for VDD = 3V.
See the Typical Characteristics for more information.
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OPERATING EXAMPLES: DAC8164
For the following examples, ensure that DAC pins A0 and A1 are both connected to ground. Pins A0 and A1
must always match data bits DB22 and DB23 within the SPI write sequence/protocol. X = don't care; value can
be either '0' or '1'.
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
•
•
•
•
1st: Write to data buffer A:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
0
DB18
DB17
DB16
DB15
D13
DB14
D12
DB13 DB12-DB2 DB1-DB0
D11 D10-D0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
0
X
2nd: Write to data buffer B:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
0
DB18
DB17
DB16
DB15
D13
DB14
D12
DB13 DB12-DB2 DB1-DB0
D11 D10-D0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
1
0
X
3rd: Write to data buffer C:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
0
DB18
DB17
DB16
DB15
D13
DB14
D12
DB13 DB12-DB2 DB1-DB0
D11 D10-D0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
1
0
0
X
4th: Write to data buffer D and simultaneously update all DACs:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
D13
DB14
D12
DB13 DB12-DB2 DB1-DB0
D11 D10-D0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
1
0
0
1
1
0
X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge
of the fourth write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
•
•
•
•
1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
0
0
D13
D12
D11 D10-D0
X
2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
1
0
D13
D12
D11 D10-D0
X
3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
0
0
D13
D12
D11 D10-D0
X
4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
1
0
D13
D12
D11 D10-D0
X
After completion of each write cycle, DAC analog output settles to the voltage specified.
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Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ
Simultaneously
•
•
•
•
1st: Write power-down command to data buffer A: DAC A to 1kΩ.
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
0
DB14
1
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
0
1
X
X
X
2nd: Write power-down command to data buffer B: DAC B to 1kΩ.
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
0
DB14
1
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
1
1
X
X
X
3rd: Write power-down command to data buffer C: DAC C to 100kΩ.
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
0
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
1
0
1
1
X
X
X
4th: Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs.
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
1
0
0
1
1
1
1
0
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified
mode upon completion of the fourth write sequence.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially
•
•
•
•
1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
0
1
1
1
X
X
X
2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
1
1
1
1
X
X
X
3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
0
1
1
1
X
X
X
4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
DB23
(A1)
DB22
(A0)
DB21
(LD1)
DB20
(LD0)
DB19
DB18
DB17
DB16
DB15
DB14
DB13 DB12-DB2 DB1-DB0
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
1
1
1
1
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first, second, third, and fourth write sequences, respectively.
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Example 5: Power-Down All Channels Simultaneously while Reference is Always Powered Up
•
1st: Write sequence for enabling the DAC8164 internal reference all the time:
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11-DB2
DB1-DB0
X
(A1)
(A0)
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
0
1
0
0
0
1
X
•
2nd: Write sequence to power-down all DACs to high-impedance:
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11-DB2
DB1-DB0
X
(A1)
(A0)
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
1
1
0
1
0
1
1
1
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first and second write sequences, respectively.
Example 6: Write a Specific Value to All DACs while Reference is Always Powered Down
•
1st: Write sequence for disabling the DAC8164 internal reference all the time (after this sequence, the
DAC8164 requires an external reference source to function):
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11-DB2
DB1-DB0
(A1)
(A0)
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
0
1
0
0
1
0
X
X
•
2nd: Write sequence to write specified data to all DACs:
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11-DB2
DB1-DB0
X
(A1)
(A0)
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
1
1
0
1
0
0
D13
D12
D11
D10
D9–D0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the fourth write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling
edge of the fourth write cycle). Reference is always powered-down.
Example 7: Write a Specific Value to DAC A, while Reference is Placed in Default Mode and All Other
DACs are Powered Down to High-Impedance
•
•
•
1st: Write sequence for placing the DAC8164 internal reference into default mode. Alternately, this step can
be replaced by performing a power-on reset (see the Power-On Reset section):
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11-DB2
DB1-DB0
X
(A1)
(A0)
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
0
1
0
0
0
0
X
2nd: Write sequence to power-down all DACs to high-impedance (after this sequence, the DAC8164 internal
reference powers down automatically):
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11-DB2
DB1-DB0
(A1)
(A0)
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
1
1
0
1
0
1
1
1
X
X
X
X
3rd: Write sequence to power-up DAC A to a specified value (after this sequence, the DAC8164 internal
reference powers up automatically):
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11-DB2
DB1-DB0
(A1)
(A0)
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
0
0
D13
D12
D11
D10
D9–D0
X
The DAC B, DAC C, and DAC D analog outputs simultaneously power-down to high-impedance, and DAC A
settles to the specified value upon completion.
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APPLICATION INFORMATION
INTERNAL REFERENCE
Temperature Drift
The internal reference of the DAC8164 does not
The internal reference is designed to exhibit minimal
require an external load capacitor for stability
drift error, defined as the change in reference output
because it is stable with any capacitive load.
voltage over varying temperature. The drift is
However, for improved noise performance, an
calculated using the box method described by
Equation 2:
external load capacitor of 150nF or larger connected
to the VREFH/VREFOUT output is recommended.
Figure 97 shows the typical connections required for
V
REF_MAX - VREF_MIN
´ 106 (ppm/°C)
operation of the DAC8164 internal reference. A
supply bypass capacitor at the AVDD input is also
recommended.
Drift Error =
VREF ´ TRANGE
(2)
Where:
DAC8164
VREF_MAX = maximum reference voltage observed
within temperature range TRANGE
VREF_MIN = minimum reference voltage observed
within temperature range TRANGE
VREF = 2.5V, target value for reference output
voltage.
.
LDAC
ENABLE
A1
1
2
3
4
5
6
7
8
VOUT
A
B
16
15
14
13
12
11
10
9
VOUT
.
150nF
VREFH/VREFOUT
AVDD
A0
AVDD
0.1mF
The internal reference (grades C and D) features an
exceptional typical drift coefficient of 2ppm/°C from
–40°C to +120°C. Characterizing a large number of
units, a maximum drift coefficient of 5ppm/°C (grades
C and D) is observed. Temperature drift results are
summarized in the Typical Characteristics.
IOVDD
DIN
VREF
GND
VOUT
VOUT
L
SCLK
SYNC
C
D
Noise Performance
Figure 97. Typical Connections for Operating the
DAC8164 Internal Reference
Typical 0.1Hz to 10Hz voltage noise can be seen in
Figure 8, Internal Reference Noise. Additional filtering
can be used to improve output noise levels, although
care should be taken to ensure the output impedance
does not degrade the ac performance. The output
noise spectrum at VREFH/VREFOUT without any
external components is depicted in Figure 7, Internal
Reference Noise Density vs Frequency. Another
noise density spectrum is also shown in Figure 7.
This spectrum was obtained using a 4.8µF load
capacitor at VREFH/VREFOUT for noise filtering.
Internal reference noise impacts the DAC output
noise; see the DAC Noise Performance section for
more details.
Supply Voltage
The internal reference features an extremely low
dropout voltage. It can be operated with a supply of
only 5mV above the reference output voltage in an
unloaded condition. For loaded conditions, refer to
the Load Regulation section. The stability of the
internal reference with variations in supply voltage
(line regulation, dc PSRR) is also exceptional. Within
the specified supply voltage range of 2.7V to 5.5V,
the variation at VREFH/VREFOUT is less than 10µV/V;
see the Typical Characteristics.
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Load Regulation
Thermal Hysteresis
Load regulation is defined as the change in reference
output voltage as a result of changes in load current.
The load regulation of the internal reference is
measured using force and sense contacts as shown
in Figure 98. The force and sense lines reduce the
impact of contact and trace resistance, resulting in
accurate measurement of the load regulation
contributed solely by the internal reference.
Measurement results are summarized in the Typical
Characteristics. Force and sense lines should be
used for applications that require improved load
regulation.
Thermal hysteresis for a reference is defined as the
change in output voltage after operating the device at
+25°C, cycling the device through the operating
temperature range, and returning to +25°C.
Hysteresis is expressed by Equation 3:
|VREF_PRE - VREF_POST
|
´ 106 (ppm/°C)
VHYST
=
VREF_NOM
(3)
Where:
VHYST = thermal hysteresis.
VREF_PRE = output voltage measured at +25°C
pre-temperature cycling.
Output Pin
Contact and
VREF_POST = output voltage measured after the
device cycles through the temperature range of
–40°C to +120°C, and returns to +25°C.
Trace Resistance
VOUT
Force Line
IL
DAC NOISE PERFORMANCE
Sense Line
Typical noise performance for the DAC8164 with the
internal reference enabled is shown in Figure 54 to
Figure 56. Output noise spectral density at the VOUT
pin versus frequency is depicted in Figure 54 for
full-scale, midscale, and zero-scale input codes. The
typical noise density for midscale code is 120nV/√Hz
at 1kHz and 100nV/√Hz at 1MHz. High-frequency
noise can be improved by filtering the reference noise
as shown in Figure 55, where a 4.8µF load capacitor
is connected to the VREFH/VREFOUT pin and
compared to the no-load condition. Integrated output
noise between 0.1Hz and 10Hz is close to 6µVPP
(midscale), as shown in Figure 56.
Load
Meter
Figure 98. Accurate Load Regulation of the
DAC8164 Internal Reference
Long-Term Stability
Long-term stability/aging refers to the change of the
output voltage of a reference over a period of months
or years. This effect lessens as time progresses (see
Figure 6, the typical long-term stability curve). The
typical drift value for the internal reference is 50ppm
from 0 hours to 1900 hours. This parameter is
characterized by powering-up and measuring 20 units
at regular intervals for a period of 1900 hours.
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BIPOLAR OPERATION USING THE DAC8164
R2
10kW
V
REF
H
AV
DD
The DAC8164 is designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in either Figure 99 or Figure 100.
The circuit shown gives an output voltage range of
±VREF. Rail-to-rail operation at the amplifier output is
achievable using an OPA703 as the output amplifier.
+6V
R1
10kW
±5V
OPA703
AVDD
VREF
VOUT
H
DAC8164
-6V
10mF
0.1mF
VREF
L
GND
The output voltage for any input code can be
calculated with Equation 4:
3-Wire
Serial Interface
R1 + R2
R1
R2
R1
D
VO = VREF
´
´
- VREF
´
16384
Figure 99. Bipolar Output Range Using External
Reference at 5V
(4)
where D represents the input code in decimal
(0–16383).
R2
10kW
AV
DD
With VREFH = 5V, R1 = R2 = 10kΩ.
+6V
R1
10 ´ D
10kW
VO =
- 5V
16384
(5)
±2.5V
OPA703
AVDD
VREF
VOUT
This result has an output voltage range of ±5V with
0000h corresponding to a –5V output and 3FFFh
H
DAC8164
VREF
-6V
corresponding to
a +5V output, as shown in
150nF
L
GND
Figure 99. Similarly, using the internal reference, a
±2.5V output voltage range can be achieved, as
Figure 100 shows.
3-Wire
Serial Interface
Figure 100. Bipolar Output Range Using Internal
Reference
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MICROPROCESSOR INTERFACING
DAC8164(1)
Microwireä
CS
SK
SYNC
SCLK
DAC8164 to an 8051 Interface
Figure 101 shows a serial interface between the
DAC8164 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8164, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051; in this case, port line P3.3 is used. When
data are to be transmitted to the DAC8164, P3.3 is
taken low. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted; then, a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken high following the
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC8164 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore
take this requirement into account, and mirror the
data as needed.
DIN
SO
NOTE: (1) Additional pins omitted for clarity.
Figure 102. DAC8164 to Microwire Interface
DAC8164 to 68HC11 Interface
Figure 103 shows a serial interface between the
DAC8164 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8164, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal derives from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
PC7
DAC8164(1)
SYNC
SCK
SCLK
DIN
MOSI
80C51/80L51(1)
P3.3
DAC8164(1)
SYNC
NOTE: (1) Additional pins omitted for clarity.
TXD
SCLK
DIN
Figure 103. DAC8164 to 68HC11 Interface
RXD
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8164, PC7 is left low after the first eight bits are
transferred; then, a second and third serial write
operation are performed to the DAC. PC7 is taken
high at the end of this procedure.
NOTE: (1) Additional pins omitted for clarity.
Figure 101. DAC8164 to 80C51/80L51 Interface
DAC8164 to Microwire Interface
Figure 102 shows an interface between the DAC8164
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
are clocked into the DAC8164 on the rising edge of
the SK signal.
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LAYOUT
The power applied to VDD should be well-regulated
and low noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8164 offers single-supply operation, and is
often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
As with the GND connection, VDD should be
connected to a power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1µF to 10µF capacitor and 0.1µF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors—all
designed to essentially low-pass filter the supply and
remove the high-frequency noise.
As a result of the single ground pin of the DAC8164,
all return currents (including digital and analog return
currents for the DAC) must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
38
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DAC8164
www.ti.com ......................................................................................................................................... SBAS410A–FEBRUARY 2008–REVISED FEBRUARY 2008
PARAMETER DEFINITIONS
With the increased complexity of many different
specifications listed in product data sheets, this
section summarizes selected specifications related to
digital-to-analog converters.
Full-Scale Error
Full-scale error is defined as the deviation of the real
full-scale output voltage from the ideal output voltage
while the DAC register is loaded with the full-scale
code. Ideally, the output should be VDD – 1 LSB. The
full-scale error is expressed in percent of full-scale
range (%FSR).
STATIC PERFORMANCE
Static performance parameters are specifications
such as differential nonlinearity (DNL) or integral
nonlinearity (INL). These are dc specifications and
provide information on the accuracy of the DAC. They
are most important in applications where the signal
changes slowly and accuracy is required.
Offset Error
The offset error is defined as the difference between
actual output voltage and the ideal output voltage in
the linear region of the transfer function. This
difference is calculated by using a straight line
defined by two codes. Since the offset error is defined
by a straight line, it can have a negative or positve
value. Offset error is measured in mV.
Resolution
Generally, the DAC resolution can be expressed in
different forms. Specifications such as IEC 60748-4
recognize the numerical, analog, and relative
resolution. The numerical resolution is defined as the
number of digits in the chosen numbering system
necessary to express the total number of steps of the
transfer characteristic, where a step represents both
a digital input code and the corresponding discrete
analogue output value. The most commonly-used
definition of resolution provided in data sheets is the
numerical resolution expressed in bits.
Zero-Code Error
The zero-code error is defined as the DAC output
voltage, when all '0's are loaded into the DAC
register. Zero-scale error is
difference between actual output voltage and ideal
output voltage (0V). It is expressed in mV. It is
primarily caused by offsets in the output amplifier.
a measure of the
Gain Error
Least Significant Bit (LSB)
Gain error is defined as the deviation in the slope of
the real DAC transfer characteristic from the ideal
transfer function. Gain error is expressed as a
percentage of full-scale range (%FSR).
The least significant bit (LSB) is defined as the
smallest value in a binary coded system. The value of
the LSB can be calculated by dividing the full-scale
output voltage by 2n, where n is the resolution of the
converter.
Full-Scale Error Drift
Most Significant Bit (MSB)
Full-scale error drift is defined as the change in
full-scale error with
Full-scale error drift is expressed in units of
%FSR/°C.
a change in temperature.
The most significant bit (MSB) is defined as the
largest value in a binary coded system. The value of
the MSB can be calculated by dividing the full-scale
output voltage by 2. Its value is one-half of full-scale.
Offset Error Drift
Relative Accuracy or Integral Nonlinearity (INL)
Offset error drift is defined as the change in offset
error with a change in temperature. Offset error drift
is expressed in µV/°C.
Relative accuracy or integral nonlinearity (INL) is
defined as the maximum deviation between the real
transfer function and a straight line passing through
the endpoints of the ideal DAC transfer function. DNL
is measured in LSBs.
Zero-Code Error Drift
Zero-code error drift is defined as the change in
zero-code error with
Zero-code error drift is expressed in µV/°C.
a change in temperature.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is defined as the
maximum deviation of the real LSB step from the
ideal 1LSB step. Ideally, any two adjacent digital
codes correspond to output analog voltages that are
exactly one LSB apart. If the DNL is less than 1LSB,
the DAC is said to be monotonic.
Gain Temperature Coefficient
The gain temperature coefficient is defined as the
change in gain error with changes in temperature.
The gain temperature coefficient is expressed in ppm
of FSR/°C.
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Power-Supply Rejection Ratio (PSRR)
Channel-to-Channel DC Crosstalk
Power-supply rejection ratio (PSRR) is defined as the
ratio of change in output voltage to a change in
supply voltage for a full-scale output of the DAC. The
PSRR of a device indicates how the output of the
DAC is affected by changes in the supply voltage.
PSRR is measured in decibels (dB).
Channel-to-channel dc crosstalk is defined as the dc
change in the output level of one DAC channel in
response to a change in the output of another DAC
channel. It is measured with a full-scale output
change on one DAC channel while monitoring
another DAC channel remains at midscale; it is
expressed in LSB.
Monotonicity
Channel-to-Channel AC Crosstalk
Monotonicity is defined as a slope whose sign does
not change. If a DAC is monotonic, the output
changes in the same direction or remains at least
constant for each step increase (or decrease) in the
input code.
AC crosstalk in a multi-channel DAC is defined as the
amount of ac interference experienced on the output
of a channel at a frequency (f) (and its harmonics),
when the output of an adjacent channel changes its
value at the rate of frequency (f). It is measured with
one channel output oscillating with a sine wave
frequency of 1kHz, while monitoring the amplitude of
1kHz harmonics on an adjacent DAC channel output
(kept at zero scale); it is expressed in dB.
DYNAMIC PERFORMANCE
Dynamic performance parameters are specifications
such as settling time or slew rate, which are important
in applications where the signal rapidly changes
and/or high frequency signals are present.
Signal-to-Noise Ratio (SNR)
Signal-to-noise ratio (SNR) is defined as the ratio of
the root mean-squared (RMS) value of the output
signal divided by the RMS values of the sum of all
other spectral components below one-half the output
frequency, not including harmonics or dc. SNR is
measured in dB.
Slew Rate
The output slew rate (SR) of an amplifier or other
electronic circuit is defined as the maximum rate of
change of the output voltage for all possible input
signals.
DV
(t)
OUT
SR = max
Total Harmonic Distortion (THD)
Dt
Total harmonic distortion + noise is defined as the
ratio of the RMS values of the harmonics and noise
to the value of the fundamental frequency. It is
Where ΔVOUT(t) is the output produced by the
amplifier as a function of time t.
expressed in
frequency amplitude at sampling rate fS.
a percentage of the fundamental
Output Voltage Settling Time
Settling time is the total time (including slew time) for
the DAC output to settle within an error band around
its final value after a change in input. Settling times
are specified to within ±0.003% (or whatever value is
specified) of full-scale range (FSR).
Spurious-Free Dynamic Range (SFDR)
Spurious-free dynamic range (SFDR) is the usable
dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is
the measure of the difference in amplitude between
the fundamental and the largest harmonically or
non-harmonically related spur from dc to the full
Nyquist bandwidth (half the DAC sampling rate, or
fS/2). A spur is any frequency bin on a spectrum
analyzer, or from a Fourier transform, of the analog
output of the DAC. SFDR is specified in decibels
relative to the carrier (dBc).
Code Change/Digital-to-Analog Glitch Energy
Digital-to-analog glitch impulse is the impulse injected
into the analog output when the input code in the
DAC register changes state. It is normally specified
as the area of the glitch in nanovolts-second (nV-s),
and is measured when the digital input code changes
by 1LSB at the major carry transition.
Signal-to-Noise plus Distortion (SINAD)
Digital Feedthrough
SINAD includes all the harmonic and outstanding
spurious components in the definition of output noise
power in addition to quantizing any internal random
noise power. SINAD is expressed in dB at a specified
input frequency and sampling rate, fS.
Digital feedthrough is defined as impulse seen at the
output of the DAC from the digital inputs of the DAC.
It is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale
code change on the data bus; that is, from all '0's to
all '1's and vice versa.
40
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DAC8164
www.ti.com ......................................................................................................................................... SBAS410A–FEBRUARY 2008–REVISED FEBRUARY 2008
DAC Output Noise Density
Output noise density
internally-generated random noise. Random noise is
characterized as a spectral density (nV/√Hz). It is
measured by loading the DAC to midscale and
measuring noise at the output.
Full-Scale Range (FSR)
is
defined
as
Full-scale range (FSR) is the difference between the
maximum and minimum analog output values that the
DAC is specified to provide; typically, the maximum
and minimum values are also specified. For an n-bit
DAC, these values are usually given as the values
matching with code 0 and 2n.
DAC Output Noise
DAC output noise is defined as any voltage deviation
of DAC output from the desired value (within a
particular frequency band). It is measured with a DAC
channel kept at midscale while filtering the output
voltage within
a band of 0.1Hz to 10Hz and
measuring its amplitude peaks. It is expressed in
terms of peak-to-peak voltage (Vpp).
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PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2008
PACKAGING INFORMATION
Orderable Device
DAC8164IAPW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DAC8164IAPWG4
DAC8164IAPWR
DAC8164IAPWRG4
DAC8164IBPW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DAC8164IBPWG4
DAC8164IBPWR
DAC8164IBPWRG4
DAC8164ICPW
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DAC8164ICPWG4
DAC8164ICPWR
DAC8164ICPWRG4
DAC8164IDPW
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DAC8164IDPWG4
DAC8164IDPWR
DAC8164IDPWRG4
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2008
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
DAC8164IAPWR
DAC8164IBPWR
DAC8164ICPWR
DAC8164IDPWR
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
16
16
2000
2000
2000
2000
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
7.0
7.0
7.0
7.0
5.6
5.6
5.6
5.6
1.6
1.6
1.6
1.6
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC8164IAPWR
DAC8164IBPWR
DAC8164ICPWR
DAC8164IDPWR
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
16
16
2000
2000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
29.0
29.0
29.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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14-Bit, quad channel, ultra-low glitch, vout DAC with 2.5V, 2ppm/°C int. ref. and reset to mi 16-TSSOP -40 to 105
TI
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