DAC8550 [TI]
16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter;
| 型号： | DAC8550 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter |
| 文件： | 总28页 (文件大小：1059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC855
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC8550
1
FEATURES
DESCRIPTION
234
•
Relative Accuracy: 3LSB
The DAC8550 is a small, low-power, voltage output,
16-bit digital-to-analog converter (DAC). It is
monotonic, provides good linearity, and minimizes
undesired code-to-code transient voltages. The
DAC8550 uses a versatile, 3-wire serial interface that
operates at clock rates of up to 30MHz and is
•
Glitch Energy: 0.1nV-s
•
MicroPower Operation:
140μA at 2.7V
•
•
•
•
•
Power-On Reset to Midscale
Power Supply: +2.7V to +5.5V
16-Bit Monotonic Over Temperature
Settling Time: 10μs to ±0.003% FSR
compatible
with
standard
SPI™,
QSPI™,
Microwire™, and digital signal processor (DSP)
interfaces.
Low-Power Serial Interface with Schmitt-
Triggered Inputs
The DAC8550 requires an external reference voltage
to set its output range. The DAC8550 incorporates a
power-on reset circuit that ensures that the DAC
output powers up at midscale and remains there until
a valid write takes place to the device. The DAC8550
contains a power-down feature, accessed over the
serial interface, that reduces the current consumption
of the device to 200nA at 5V.
•
On-Chip Output Buffer Amplifier with Rail-to-
Rail Output Amplifier
•
•
•
•
Power-Down Capability
2's Complement Input
SYNC Interrupt Facility
The low-power consumption of this device in normal
operation makes it ideal for portable, battery-operated
equipment. Power consumption is 0.38mW at 2.7V,
reducing to less than 1μW in power-down mode.
Drop-In Compatible with DAC8531/01 and
DAC8551 (Binary Input)
•
Available in a Tiny MSOP-8 Package
The DAC8550 is available in an MSOP-8 package.
APPLICATIONS
For additional flexibilty, see the DAC8551, a binary-
coded counterpart to the DAC8550.
•
•
•
•
•
•
Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
FUNCTIONAL BLOCK DIAGRAM
VDD
Portable Instrumentation
Programmable Attenuation
VFB
VREF
REF (+)
16-Bit DAC
VOUT
16
DAC Register
16
SYNC
SCLK
DIN
PWB
Control
Resistor
Network
Shift Register
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
PACKAGE
LEAD
PACKAGE
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
DESIGNATOR(1)
DAC8550IDGKT
DAC8550IDGKR
DAC8550IBDGKT
DAC8550IBDGKR
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
DAC8550
±12
±8
±1
±1
MSOP-8
MSOP-8
DGK
DGK
–40°C to +105°C
–40°C to +105°C
D80
D80
DAC8550B
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
Supply voltage, VDD to GND
–0.3V to 6V
–0.3V to +VDD + 0.3V
–0.3V to +VDD + 0.3V
–40°C to +105°C
–65°C to +150°C
150°C
Digital input voltage range, VI to GND
Output voltage, VOUT to GND
Operating free-air temperature range, TA
Storage temperature range, TSTG
Junction temperature range, TJ (max)
Power dissipation (DGK package)
Thermal impedance, θJA
(TJmax – TA)/θJA
206°C/W
Thermal impedance, θJC
44°C/W
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V, –40°C to +105°C range (unless otherwise noted).
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
LSB
DAC8550
±3
±3
±12
±8
Measured by line passing through codes
–32283 and +32063
EL
Relative accuracy
DAC8550B
LSB
ED
Differential nonlinearity
Zero-code error
16-bit Monotonic
±0.25
±2
±1
LSB
EO
EFS
EG
±12
±0.5
±0.2
mV
Full-scale error
Measured by line passing through codes –32283 and +32063.
±0.05
±0.02
±5
% of FSR
% of FSR
μV/°C
Gain error
Zero-code error drift
Gain temperature coefficient
±1
ppm of FSR/°C
mV/V
PSRR Power-supply rejection ratio
RL = 2kΩ, CL = 200pF
0.75
(1) Linearity calculated using a reduced code range of –32283 to +32063; output unloaded.
2
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V, –40°C to +105°C range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS(2)
VO
tSD
SR
Output voltage range
Output voltage settling time
Slew rate
0
VREF
10
V
μs
To ±0.003% FSR, 1200h to 8D00h, RL = 2kΩ, 0pF < CL < 200pF
RL = 2kΩ, CL = 500pF
8
12
μs
1.8
470
1000
0.1
0.1
1
V/μs
pF
RL = ∞
Capacitive load stability
RL = 2kΩ
pF
Code change glitch impulse
Digital feedthrough
1LSB change around major carry
SCLK toggling, FSYNC high
At mid-code input
nV-s
Ω
zO
DC output impedance
VDD = 5V
50
IOS
Short-circuit current
Power-up time
mA
VDD = 3V
20
Coming out of power-down mode, VDD = 5V
Coming out of power-down mode, VDD = 3V
2.5
5
tON
μs
AC PERFORMANCE
SNR
THD
Signal-to-noise ratio
95
–85
87
Total harmonic distortion
BW = 20kHz, VDD = 5V, fOUT = 1kHz,
1st 19 harmonics removed for SNR calculation
dB
SFDR
Spurious-free dynamic range
SINAD Signal-to-noise and distortion
84
REFERENCE INPUT
VREF
Reference voltage
0
VDD
75
V
VREF = VDD = 5V
40
30
μA
μA
kΩ
II(REF)
Reference current input range
VREF = VDD = 3.6V
45
zI(REF)
Reference input impedance
125
(3)
LOGIC INPUTS
Input current
±1
μA
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
0.3VDD
0.1VDD
VIL
VIH
Low-level input voltage
V
0.7VDD
0.9VDD
High-level input voltage
Pin capacitance
V
3
pF
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (normal mode)
Input code equals mid-scale, no load, does not include reference
current
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
160
140
250
240
VIH = VDD and VIL = GND
μA
μA
IDD (all power-down modes)
VDD = 3.6V to 5.5V
VIH = VDD and VIL = GND
0.2
2
2
VDD = 2.7V to 3.6V
0.05
POWER EFFICIENCY
IOUT/IDD
ILOAD = 2mA, VDD = 5V
89
%
TEMPERATURE RANGE
Specified performance
–40
+105
°C
(2) Specified by design and characterization, not production tested.
(3) Specified by design and characterization, not production tested.
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
PIN CONFIGURATION
MSOP-8
(Top View)
VDD
VREF
VFB
GND
DIN
1
2
3
4
8
7
6
5
DAC8550
SCLK
SYNC
VOUT
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
1
2
3
4
VDD
VREF
VFB
Power-supply input, 2.7V to 5.5V.
Reference voltage input.
Feedback connection for the output amplifier.
VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
updated following the 24th clock (unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC8550). Schmitt-Trigger logic input.
5
SYNC
6
7
8
SCLK Serial clock input. Data can be transferred at rates up to 30MHz. Schmitt-Trigger logic input.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-
Trigger logic input.
DIN
GND Ground reference point for all circuitry on the part.
4
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
SERIAL WRITE OPERATION
t9
t1
SCLK
1
24
t8
t2
t3
t7
t4
SYNC
t6
t5
DB23
DIN
DB0
DB23
TIMING CHARACTERISTICS(1) (2)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VDD = 2.7V to 3.6V
MIN
50
33
13
13
22.5
13
0
TYP
MAX
UNIT
(3)
t1
t2
t3
t4
t5
t6
t7
SCLK cycle time
SCLK HIGH time
SCLK LOW time
ns
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 5.5V
ns
ns
ns
ns
ns
ns
SYNC to SCLK rising edge setup time
Data setup time
0
5
5
4.5
4.5
0
Data hold time
24th SCLK falling edge to SYNC rising edge
0
50
33
100
t8
t9
Minimum SYNC HIGH time
ns
ns
24th SCLK falling edge to SYNC falling edge
(1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation Timing Diagram.
(3) Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS: VDD = 5 V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (-40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
6
4
6
4
VDD = 5V, VREF = 4.99V
VDD = 5V, VREF = 4.99V
2
2
0
0
-2
-4
-6
-2
-4
-6
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
ZERO-SCALE ERROR
vs TEMPERATURE
6
4
10
5
VDD = 5V
VREF = 4.99V
VDD = 5V, VREF = 4.99V
2
0
-2
-4
-6
1.0
0.5
0
0
-0.5
-1.0
-5
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
-40
0
40
80
120
Temperature (°C)
Figure 3.
Figure 4.
6
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
FULL-SCALE ERROR
vs TEMPERATURE
SOURCE AND SINK CURRENT CAPABILITY
0
6
5
4
3
2
1
0
VDD = 5V
VREF = 4.99V
DAC Loaded with FFFFh
-5
VDD = 5.5V
VREF = VDD - 10mV
DAC Loaded with 0000h
-10
-40
0
40
80
120
0
2
4
6
8
10
110
5.5
Temperature (°C)
I(SOURCE/SINK) (mA)
Figure 5.
Figure 6.
SUPPLY CURRENT
POWER-SUPPLY CURRENT
vs TEMPERATURE
vs DIGITAL INPUT CODE
300
250
200
150
100
50
250
200
150
100
50
VREF = VDD = 5V
VDD = VREF = 5V
Reference Current Included
0
0
-40
-10
20
50
80
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Temperature (°C)
Figure 7.
Figure 8.
SUPPLY CURRENT
vs SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs SUPPLY VOLTAGE
300
1.0
VREF = VDD
VREF = VDD
280
260
240
220
200
180
160
140
120
100
Reference Current Included, No Load
0.8
0.6
0.4
0.2
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
4.3
4.7
5.1
VDD (V)
VDD (V)
Figure 9.
Figure 10.
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME: 5V RISING EDGE
1800
TA = 25°C, SCL Input (all other inputs = GND)
Trigger Pulse 5V/div
1600
VDD = VREF = 5.5V
1400
1200
1000
800
600
400
200
0
VDD = 5V
VREF = 4.096V
From Code: D000
To Code: FFFF
Rising Edge
1V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
0
1
2
3
4
5
VLOGIC (V)
Figure 11.
Figure 12.
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
HALF-SCALE SETTLING TIME: 5V RISING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
VDD = 5V
VREF = 4.096V
Rising
Edge
1V/div
From Code: 4000
To Code: CFFF
Falling
Edge
1V/div
Zoomed Falling Edge
1mV/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 13.
Figure 14.
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
VDD = 5V
VREF = 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Falling
Edge
1V/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (400ns/div)
Figure 15.
Figure 16.
8
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
VDD = 5V
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
VREF = 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 17.
Figure 18.
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
VDD = 5V
VREF = 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 19.
Figure 20.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
-40
VDD = 5V
VDD = 5V
VREF = 4.096V
From Code: 80FF
To Code: 8000
VREF = 4.9V
-50
-60
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
Glitch: Not Detected
Theoretical Worst Case
-70
THD
-80
-90
2nd Harmonic
1
3rd Harmonic
-100
Time (400ns/div)
0
2
3
4
5
fOUT (kHz)
Figure 21.
Figure 22.
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
POWER SPECTRAL DENSITY
98
96
94
92
90
88
86
84
VREF = VDD = 5V
VDD = 5V
-10
-30
-1dB FSR Digital Input
fS = 1MSPS
VREF = 4.096V
fOUT = 1kHz
Measurement Bandwidth = 20kHz
f
= 1MSPS
CLK
-50
-70
-90
-110
-130
0
5
10
15
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.5
fOUT (kHz)
Frequency (kHz)
Figure 23.
Figure 24.
OUTPUT NOISE DENSITY
350
300
250
200
150
100
VDD = 5V
VREF = 4.99V
Code = 7FFFh
No Load
100
1k
10k
100k
Frequency (Hz)
Figure 25.
10
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
TYPICAL CHARACTERISTICS: VDD = 2.7 V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (-40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
6
4
6
4
VDD = 2.7V, VREF = 2.69V
VDD = 2.7V, VREF = 2.69V
2
2
0
0
-2
-4
-6
-2
-4
-6
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 26.
Figure 27.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
ZERO-SCALE ERROR
vs TEMPERATURE
6
4
10
5
VDD = 2.7V
VREF = 2.69V
VDD = 2.7V, VREF = 2.69V
2
0
-2
-4
-6
1.0
0.5
0
0
-0.5
-1.0
-5
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
-40
0
40
80
120
Temperature (°C)
Figure 28.
Figure 29.
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = +25°C, unless otherwise noted.
FULL-SCALE ERROR
vs TEMPERATURE
SOURCE AND SINK CURRENT CAPABILITY
5
3.0
2.5
2.0
1.5
1.0
0.5
0
VDD = 2.7V
VREF = 2.69V
DAC Loaded with FFFFh
0
VDD = 2.7V
VREF = VDD - 10mV
-5
DAC Loaded with 0000h
-10
-40
0
40
80
120
0
2
4
6
8
10
Temperature (°C)
I(SOURCE/SINK) (mA)
Figure 30.
Figure 31.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs TEMPERATURE
180
160
140
120
100
80
250
200
150
100
50
VREF = VDD = 2.7V
VDD = VREF = 2.7V
Reference Current Included
60
40
20
0
0
-40
-10
20
50
80
110
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Temperature (°C)
Figure 32.
Figure 33.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME: 2.7V RISING EDGE
800
TA = 25°C, SCL Input (all other inputs = GND)
Trigger Pulse 2.7V/div
700
600
500
400
300
200
100
0
VDD = VREF = 2.7V
Rising
Edge
0.5V/div
VDD = 2.7V
VREF = 2.5V
From Code: 0000
To Code: FFFF
Zoomed Rising Edge
1mV/div
Time (2ms/div)
0
0.5
1.0
1.5
2.0
2.5 2.7
VLOGIC (V)
Figure 34.
Figure 35.
12
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = +25°C, unless otherwise noted.
FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE
HALF-SCALE SETTLING TIME: 2.7V RISING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: FFFF
To Code: 0000
VDD = 2.7V
VREF = 2.5V
From Code: 4000
To Code: CFFF
Rising
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Edge
0.5V/div
Time (2ms/div)
Time (2ms/div)
Figure 36.
Figure 37.
HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE
GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: CFFF
To Code: 4000
VDD = 2.7V
VREF = 2.5V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Falling
Edge
0.5V/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (400ns/div)
Figure 38.
Figure 39.
GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE
GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 40.
Figure 41.
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE
GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 42.
Figure 43.
GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Figure 44.
14
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
THEORY OF OPERATION
DAC SECTION
The architecture of the DAC8850 consists of a string
DAC followed by an output buffer amplifier. Figure 45
shows the block diagram of the DAC architecture.
R
R
VREF
50kW
50kW
VFB
62kW
VOUT
REF(+)
Resistor String
REF(-)
DAC
Register
To Output
Amplifier
R
GND
Figure 45. DAC8550 Architecture
The input coding to the DAC8550 is 2's complement,
so the ideal output voltage is given by:
VREF VREF D
VOUT
+
)
2
65536
(1)
R
R
where D = decimal equivalent of the 2's complement
code that is loaded to the DAC register; D ranges
from –32768 to +32767 where D = 0 is centered at
VREF/2.
RESISTOR STRING
The resistor string section is shown in Figure 46. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier.
Monotonicity is ensured because of the string resistor
architecture.
Figure 46. Resistor String
SERIAL INTERFACE
The DAC8550 has a 3-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI, QSPI,
and Microwire interface standards, as well as most
DSP interfaces. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail output voltages with a range of 0V to VDD. It
is capable of driving a load of 2kΩ in parallel with
1000pF to GND. The source and sink capabilities of
the output amplifier can be seen in the Typical
Characteristics. The slew rate is 1.8V/μs with a full-
scale setting time of 8μs with the output unloaded.
The write sequence begins by bringing the SYNC line
LOW. Data from the DIN line are clocked into the 24-
bit shift register on each falling edge of SCLK. The
serial clock frequency can be as high as 30MHz,
making the DAC8550 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock, the
last data bit is clocked in and the programmed
function is excuted (that is, a change in DAC register
contents and/or a change in the mode of operation).
The inverting input of the output amplifier is brought
out to the VFB pin. This architecture allows for better
accuracy in critical applications by tying the VFB point
and the amplifier output together directly at the load.
Other signal conditioning circuitry may also be
connected between these points for specific
applications.
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. Since the SYNC buffer
draws more current when the SYNC signal is HIGH
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
than it does when it is LOW, SYNC should be idled
LOW between write sequences for lowest power
operation of the part. As mentioned above, it must be
brought HIGH again just before the next write
sequence.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs,
as shown in Figure 48.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in
Figure 47. The first six bits are don't care bits. The
next two bits (PD1 and PD0) are control bits that
control which mode of operation the part is in (normal
mode or any one of three power-down modes). For a
more complete description of the various modes see
the Power-Down Modes section. The next 16 bits are
the data bits. These bits are transferred to the DAC
register on the 24th falling edge of SCLK.
POWER-ON RESET
The DAC8550 contains a power-on reset circuit that
controls the output voltage during power-up. On
power-up, the output voltages are set to midscale;
they remain that way until a valid write sequence is
made to the DAC. The power-on reset is useful in
applications where it is important to know the state of
the output of the DAC while it is in the process of
powering up.
DB23
DB0
X
X
X
X
X
X
PD PD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1
0
Figure 47. DAC8550 Data Input Register Format
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 48. SYNC Interrupt Facility
16
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
POWER-DOWN MODES
impedance of the device is known while in power-
down mode. There are three different options. The
output is connected internally to GND through a 1kΩ
resistor, a 100kΩ resistor, or it is left open-circuited
(High-Z). The output stage is illustrated in Figure 49.
The DAC8550 supports four separate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in the control register.
Table 1 shows how the state of the bits corresponds
to the mode of operation of the device.
VFB
Table 1. Operating Modes
Amplifier
VOUT
Resistor
String
DAC
PD1
(DB17)
PD0
(DB16)
OPERATING MODE
Normal operation
0
—
0
0
—
1
Power-down modes
Output typically 1kΩ to GND
Output typically 100kΩ to GND
High-Z
Power-Down
Circuitry
Resistor
Network
1
0
1
1
Figure 49. Output Stage During Power-Down
When both bits are set to '0', the device works
normally with a typical current consumption of 200μA
at 5V. However, for the three power-down modes, the
supply current falls to 200nA at 5V (50nA at 3V). Not
only does the supply current fall, but the output stage
is also internally switched from the output of the
amplifier to a resistor network of known values. The
advantage with this configuration is that the output
All analog circuitry is shut down when the power-
down mode is activated. However, the contents of the
DAC register are unaffected when in power-down.
The time to exit power-down is typically 2.5μs for VDD
= 5V, and 5μs for VDD = 3V. See the Typical
Characteristics for more information.
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
MICROPROCESSOR INTERFACING
DAC8550 to 8051 Interface
www.ti.com
MicrowireTM
CS
DAC8550(1)
SYNC
SCLK
DIN
SK
SO
See Figure 50 for a serial interface between the
DAC8550 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8550, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data are to be transmitted to the DAC8550, P3.3 is
taken LOW. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC8550 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore
take this into account, and mirror the data as needed.
NOTE: (1) Additional pins omitted for clarity.
Figure 51. DAC8550 to Microwire Interface
DAC8550 to 68HC11 Interface
Figure 52 shows a serial interface between the
DAC8550 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8550, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
PC7
DAC8550(1)
SYNC
SCK
SCLK
DIN
MOSI
80C51/80L51(1)
P3.3
DAC8550(1)
SYNC
NOTE: (1) Additional pins omitted for clarity.
TXD
RXD
SCLK
DIN
Figure 52. DAC8550 to 68HC11 Interface
NOTE: (1) Additional pins omitted for clarity.
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8550, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
Figure 50. DAC8550 to 80C51/80L51 Interface
DAC8550 to Microwire Interface
Figure 51 shows an interface between the DAC8550
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
clocked into the DAC8550 on the rising edge of the
SK signal.
18
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
APPLICATION INFORMATION
5 V
5 kW
200 mA )
+ 1.2 mA
(2)
USING THE REF02 AS A POWER SUPPLY
FOR THE DAC8550
The load regulation of the REF02 is typically
0.005%/mA, resulting in an error of 299μV for the
1.2mA current drawn from it. This value corresponds
to an 8.9LSB error.
Due to the extremely low supply current required by
the DAC8550, an alternative option is to use a REF02
+5V precision voltage reference to supply the
required voltage to the device, as shown in Figure 53.
BIPOLAR OPERATION USING THE DAC8550
+15V
The DAC8550 has been designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in Figure 54. The circuit shown gives
+5V
an output voltage range of ±VREF
.
Rail-to-rail
REF02
operation at the amplifier output is achievable using
an OPA703 as the output amplifier.
285mA
The output voltage for any input code can be
calculated as follows:
SYNC
Three-Wire
Serial
Interface
V
R1 ) R2
R2
ǒ Ǔ
R1
D
65536
REF ) VREF
* VREF
ƫ
VOUT = 0V to 5V
ǒ
Ǔ ǒ Ǔ
VO
+
ƪ
SCLK
DIN
DAC8550
2
R1
(3)
where D represents the input code in 2's complement
(–32768 to +32767).
With VREF = 5V, R1 = R2 = 10kΩ.
Figure 53. REF02 as a Power Supply to the
DAC8550
D
VO + 10
65536
(4)
This configuration is especially useful if the power
supply is quite noisy or if the system supply voltages
are at some value other than 5V. The REF02 outputs
a steady supply voltage for the DAC8550. If the
REF02 is used, the current it needs to supply to the
DAC8550 is 250μA. This configuration is with no load
on the output of the DAC. When a DAC output is
loaded, the REF02 also needs to supply the current
to the load. The total typical current required (with a
5kΩ load on the DAC output) is:
Using this example, an output voltage range of ±5V
with 8000h corresponding to a –5V output and 8FFFh
corresponding to a 5V output can be achieved.
Similarly, using VREF = 2.5V, a ±2.5V output voltage
range can be achieved.
R2
10kW
V
REF
+6V
R1
10kW
5V
OPA703
VFB
VOUT
VREF
DAC8550
-6V
10mF
0.1mF
Three-Wire
Serial Interface
Figure 54. Bipolar Output Range
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): DAC8550
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
www.ti.com
LAYOUT
The power applied to VDD should be well-regulated
and low-noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes.
This noise can easily couple into the DAC output
voltage through various paths between the power
connections and analog output.
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8550 offers single-supply operation and is
used often in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
As with the GND connection, VDD should be
connected to a 5V power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1μF to 10μF capacitor and 0.1μF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100μF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors, all
designed to essentially low-pass filter the 5V supply,
removing the high-frequency noise.
Due to the single ground pin of the DAC8550, all
return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the power-
entry point of the system.
20
Submit Documentation Feedback
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
DAC8550
www.ti.com
SLAS476E –MARCH 2006–REVISED MARCH 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2006) to Revision E
Page
•
•
Changed low-level input voltage values in Electrcial Characteristics ................................................................................... 3
Changed high-level input voltage values in Electrcial Characteristics .................................................................................. 3
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): DAC8550
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
DAC8550IBDGKR
DAC8550IBDGKRG4
DAC8550IBDGKT
DAC8550IBDGKTG4
DAC8550IDGKR
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGK
8
8
8
8
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
D80
D80
D80
D80
D80
D80
D80
D80
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGK
DGK
DGK
DGK
DGK
DGK
DGK
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
2500
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
DAC8550IDGKRG4
DAC8550IDGKT
Green (RoHS
& no Sb/Br)
CU NIPDAU
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
DAC8550IDGKTG4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC8550IBDGKR
DAC8550IBDGKT
DAC8550IDGKR
DAC8550IDGKT
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
2500
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC8550IBDGKR
DAC8550IBDGKT
DAC8550IDGKR
DAC8550IDGKT
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
2500
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
2500
250
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明