DAC8552IDGKR [TI]
16 位、双通道、超低毛刺脉冲、电压输出数模转换器 | DGK | 8 | -40 to 105;
| 型号： | DAC8552IDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 位、双通道、超低毛刺脉冲、电压输出数模转换器 | DGK | 8 | -40 to 105 脉冲 光电二极管 转换器 数模转换器 |
| 文件： | 总25页 (文件大小：608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC855
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
•
•
•
Relative Accuracy: 4LSB
The DAC8552 is a 16-bit, dual channel, voltage
output digital-to-analog converter (DAC) offering low
power operation and a flexible serial host interface.
Each on-chip precision output amplifier allows
rail-to-rail output swing to be achieved over the
supply range of 2.7V to 5.5V. The device supports a
standard 3-wire serial interface capable of operating
with input data clock frequencies up to 30MHz for
VDD = 5V.
Glitch Energy: 0.15nV-s
MicroPower Operation:
155µA per Channel at 2.7V
•
•
•
•
•
•
Power-On Reset to Zero-Scale
Power Supply: 2.7V to 5.5V
16-Bit Monotonic Over Temperature
Settling Time: 10µs to ±0.003% FSR
Ultra-Low AC Crosstalk: –100dB Typ
The DAC8552 requires an external reference voltage
to set the output range of each DAC channel. Also
incorporated into the device is a power-on reset
circuit which ensures that the DAC outputs power up
at zero-scale and remain there until a valid write
takes place. The DAC8552 provides a flexible
power-down feature, accessed over the serial
interface, that reduces the current consumption of
the device to 700nA at 5V.
Low-Power Serial Interface with
Schmitt-Triggered Inputs
•
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
•
•
Double-Buffered Input Architecture
Simultaneous or Sequential Output Update
and Power-down
The low-power consumption of this device in normal
operation makes it ideally suited for portable,
battery-operated equipment and other low-power
applications. The power consumption is 0.5mW per
channel at 2.7V, reducing to 1µW in power-down
mode.
•
Available in a Tiny MSOP-8 Package
APPLICATIONS
•
•
•
•
•
•
Portable Instrumentation
Closed-Loop Servo Control
Process Control
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
The DAC8552 is available in a MSOP-8 package
with a specified operating temperature range of
–40°C to +105°C.
VDD
VREF
Data
Buffer A
DAC
Register A
DAC A
DAC B
VOUT
A
Data
Buffer B
DAC
Register B
VOUTB
16
24-Bit,
SYNC
SCLK
DIN
Channel
Select
Load
Control
Power-Down
Control Logic
Serial-to-
Parallel
Shift
8
2
Control Logic
Resistor
Network
Register
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSP are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
DAC8552
www.ti.com
SLAS430A–JULY 2006–REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION(1)
MAXIMUM
RELATIVE
MAXIMUM
DIFFERENTIAL
SPECIFICATION
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
ACCURACY NONLINEARITY PACKAGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
(LSB)
(LSB)
LEAD
DAC8552IDGKT
Tape and Reel, 250
DAC8552
±12
±1
MSOP-8
DGK
–40°C to +105°C
D82
DAC8552IDGKR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted).(1)
UNIT
VDD to GND
–0.3V to 6V
–0.3V to VDD + 0.3V
–0.3V to VDD + 0.3V
–40°C to +105°C
–65°C to +150°C
+150°C
Digital input voltage to GND
VOUTA or VOUTB to GND
Operating temperature range
Storage temperature range
Junction temperature (TJ max)
Power dissipation
(TJ max – TA)/θJA
206°C/W
θJA
Thermal impedance
θJC
44°C/W
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
Relative accuracy
Measured by line passing through codes 513 and
64741
±4
±12
LSB
Differential nonlinearity
Zero code error
16-bit monotonic
±0.35
±2.5
±1
LSB
mV
Measured by line passing through codes 485 and
64741
±12
Zero code error drift
Full-scale error
±5
µV/°C
Measured by line passing through codes 485 and
64741
±0.1
±0.5
±0.2
% of FSR
Gain error
Measured by line passing through codes 485 and
64741
±0.08
% of FSR
Gain temperature coefficient
PSRR
±1
ppm of FSR/°C
Output unloaded
0.75
mV/V
(1) Linearity calculated using a reduced code range of 513 to 64741. Output unloaded.
2
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
OUTPUT CHARACTERISTICS(2)
Output voltage range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VREF
10
V
To ±0.003% FSR 0200h to FD00h, RL = 2kΩ;
0pF < CL < 200pF
8
Output voltage settling time
µs
RL = 2kΩ; CL = 500pF
12
1.8
Slew rate
V/µs
RL = ∞
470
Capacitive load stability
pF
RL = 2kΩ
1000
0.15
0.15
Code change glitch impulse
Digital feedthrough
1LSB change around major carry
50kΩ series resistance on digital lines
nV-s
nV-s
Full-scale swing on adjacent channel.
VDD = 5V, VREF = 4.096V
DC crosstalk
0.25
LSB
AC crosstalk
1kHz sine wave
–100
1
dB
DC output impedance
At mid-point input
Ω
VDD = 5V
50
20
2.5
5
Short circuit current
Power-up time
mA
VDD = 3V
Coming out of power-down mode, VDD = 5V
Coming out of power-down mode, VDD = 3V
µs
µs
AC PERFORMANCE
SNR
95
–85
87
THD
BW = 20kHz, VDD = 5V, fOUT = 1kHz,
1st 19 harmonics removed for SNR calculation
dB
SFDR
SINAD
84
REFERENCE INPUT
VREF = VDD = 5.5V
VREF = VDD = 3.6V
90
60
120
100
VDD
Reference current
µA
Reference input range
Reference input impedance
LOGIC INPUTS(2)
0
V
62
kΩ
Input current
±1
0.8
0.6
µA
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VINL, Input LOW voltage
VINH, Input HIGH voltage
V
2.4
2.1
V
Pin capacitance
POWER REQUIREMENTS
VDD
3
pF
2.7
5.5
V
Input code = 32768, no load, does not include
reference current
IDD (normal mode)
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
IDD (all power-down modes)
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
POWER EFFICIENCY
IOUT/IDD
340
310
500
480
VIH = VDD and VIL = GND
µA
µA
0.7
0.4
2
2
VIH = VDD and VIL = GND
ILOAD = 2mA, VDD = 5V
89
%
TEMPERATURE RANGE
Specified performance
–40
+105
°C
(2) Specified by design and characterization; not production tested.
3
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
PIN CONFIGURATION
DGK PACKAGE
MSOP-8
(Top View)
VDD
GND
DIN
1
2
3
4
8
7
6
5
VREF
DAC8552
VOUT
VOUT
B
A
SCLK
SYNC
PIN DESCRIPTIONS
PIN
1
NAME
VDD
FUNCTION
Power supply input, 2.7V to 5.5V
2
VREF
VOUT
VOUT
Reference voltage input
3
B
A
Analog output voltage from DAC B
Analog output voltage from DAC A
4
Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the
8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken
HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored
by the DAC8552). Schmitt-Trigger logic input.
5
SYNC
6
7
8
SCLK
DIN
Serial Clock Input. Data can be transferred at rates up to 30MHz at 5V. Schmitt-Trigger logic input.
Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input.
Schmitt-Trigger logic input.
GND
Ground reference point for all circuitry on the part.
4
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
SERIAL WRITE OPERATION
t9
t1
SCLK
1
24
t8
t2
t3
t7
t4
SYNC
t6
t5
DB23
DIN
DB0
DB23
TIMING CHARACTERISTICS(1)(2)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VDD = 2.7V to 3.6V
MIN
50
33
13
13
22.5
13
0
TYP
MAX
UNIT
(3)
t1
t2
t3
t4
t5
t6
t7
SCLK cycle time
SCLK HIGH time
SCLK LOW time
ns
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 5.5V
ns
ns
ns
ns
ns
ns
SYNC to SCLK rising edge setup time
Data setup time
0
5
5
4.5
4.5
0
Data hold time
24th SCLK falling edge to SYNC rising edge
0
50
33
100
t8
t9
Minimum SYNC HIGH time
ns
ns
24th SCLK falling edge to SYNC falling edge
(1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation Timing Diagram.
(3) Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
5
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
8
6
8
6
VDD = 5V, VREF = 4.9V, TA = +25°C
VDD = 5V, VREF = 4.9V, TA = +25°C
4
2
4
2
Channel A Output
Channel B Output
0
0
-2
-4
-6
-8
-2
-4
-6
-8
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 1.
Figure 2.
ZERO-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
7.5
5.0
5
0
VDD = 5V
VDD = 5V
VREF = 4.99V
VREF = 4.99V
CH B
CH A
2.5
CH B
CH A
0
-2.5
-5.0
-7.5
-5
-10
-40
0
40
80
120
-40
0
40
80
120
Temperature (°C)
Temperature (°C)
Figure 3.
Figure 4.
SOURCE CURRENT CAPABILITY
AT POSITIVE RAIL
SINK CURRENT CAPABILTY
AT NEGATIVE RAIL
6.0
5.6
5.2
4.8
4.4
4.0
0.150
0.125
0.100
0.075
0.050
0.025
0
VREF = VDD - 10mV
DAC Loaded with 0000h
VDD = 2.7V
VDD = 5.5V
VDD = 5.5V
VREF = VDD - 10mV
DAC Loaded with FFFFh
0
2
4
6
8
10
0
2
4
6
8
10
ISOURCE (mA)
ISINK (mA)
Figure 5.
Figure 6.
6
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
600
600
550
500
450
400
350
300
250
200
VREF = VDD, All DACs Powered
Reference Current Included, No Load
Reference Current Included
500
VDD = VREF = 5.5V
400
VDD = VREF = 3.6V
300
200
100
0
2.7
3.1
3.5
4.3
4.7
5.1
5.5
5.5
5
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
VDD (V)
Figure 7.
Figure 8.
SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
600
500
400
300
200
100
0
2400
2000
1600
1200
800
400
0
TA = 25°C, SYNC Input (all other inputs = GND)
CH A Powered Up; All Other Channels in Power-Down
Reference Current Included
VDD = VREF = 5.5V
VDD = VREF = 3.6V
VDD = VREF = 5.5V
0
1
2
3
4
5
-40
0
40
80
120
VLOGIC (V)
Temperature (°C)
Figure 9.
Figure 10.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
POWER SPECTRAL DENSITY
-40
-50
-60
-70
-80
-90
-100
VDD = 5V
VDD = 5V
-10
-30
VREF = 4.9V
VREF = 4.096V
fOUT = 1kHz
-1dB FSR Digital Input
fS = 1MSPS
f
= 1MSPS
CLK
Measurement Bandwidth = 20kHz
-50
-70
THD
-90
-110
-130
2nd Harmonic
1
3rd Harmonic
0
5
10
15
20
0
2
3
4
Frequency (kHz)
fOUT (kHz)
Figure 11.
Figure 12.
7
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
OUTPUT NOISE DENSITY
98
96
94
92
90
88
86
84
350
300
250
200
150
100
VREF = VDD = 5V
VDD = 5V
-1dB FSR Digital Input
fS = 1MSPS
VREF = 4.99V
Code = 7FFFh
No Load
Measurement Bandwidth = 20kHz
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.5
fOUT (kHz)
100
1k
10k
100k
Frequency (Hz)
Figure 13.
Figure 14.
FULL-SCALE SETTLING TIME: 5V RISING EDGE
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
VDD = 5V
VREF = 4.096V
From Code: D000
To Code: FFFF
Falling
Edge
1V/div
Rising Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 15.
Figure 16.
HALF-SCALE SETTLING TIME: 5V RISING EDGE
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
VDD = 5V
VREF = 4.096V
From Code: 4000
To Code: CFFF
Rising
Edge
1V/div
Falling
Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 17.
Figure 18.
8
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
VDD = 5V
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
VREF = 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Time (400ns/div)
Time (400ns/div)
Figure 19.
Figure 20.
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
VDD = 5V
VREF = 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 21.
Figure 22.
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
VDD = 5V
VREF = 4.096V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 23.
Figure 24.
9
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 2.7V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
8
6
8
6
VDD = 2.7V, VREF = 2.5V, TA = +25°C
VDD = 2.7V, VREF = 2.5V, TA = +25°C
4
2
4
2
Channel B Output
Channel A Output
0
0
-2
-4
-6
-8
-2
-4
-6
-8
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 25.
Figure 26.
ZERO-SCALE ERROR vs TEMPERATURE
FULL-SCALE ERROR vs TEMPERATURE
7.5
5.0
5
0
VDD = 2.7V
VDD = 2.7V
VREF = 2.69V
VREF = 2.69V
CH B
CH A
2.5
CH B
CH A
0
-2.5
-5.0
-7.5
-5
-10
-40
0
40
80
120
-40
0
40
80
120
Temperature (°C)
Temperature (°C)
Figure 27.
Figure 28.
SOURCE CURRENT CAPABILITY AT POSITIVE RAIL
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
3.0
800
TA = 25°C, SYNC Input (all other inputs = GND)
700
600
500
400
300
200
100
0
CH A Powered Up; All Other Channels in Power-Down
2.7
2.4
2.1
1.8
1.5
VDD = VREF = 2.7V
VDD = 2.7 V
VREF = VDD − 10mV
DAC loaded with FFFFh
0
2
4
6
8
10
0
0.5
1.0
1.5
2.0
2.5 2.7
ISOURCE (mA)
VLOGIC (V)
Figure 29.
Figure 30.
10
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SLAS430A–JULY 2006–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
FULL-SCALE SETTLING TIME: 2.7V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: FFFF
To Code: 0000
Rising
Edge
0.5V/div
VDD = 2.7V
VREF = 2.5V
From Code: 0000
To Code: FFFF
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 31.
Figure 32.
HALF-SCALE SETTLING TIME: 2.7V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: CFFF
To Code: 4000
VDD = 2.7V
VREF = 2.5V
From Code: 4000
To Code: CFFF
Rising
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Edge
0.5V/div
Time (2ms/div)
Time (2ms/div)
Figure 33.
Figure 34.
GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
VDD = 2.7V
VREF = 2.5V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Time (400ns/div)
Time (400ns/div)
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 37.
Figure 38.
GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 39.
Figure 40.
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THEORY OF OPERATION
DAC SECTION
VREF
The architecture of each channel of the DAC8552
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 41 shows a simplified
block diagram of the DAC architecture.
RDIVIDER
VREF
2
VREF
50kW
50kW
R
R
62kW
VOUT
REF(+)
Resistor String
REF(-)
To Output Amplifier
(2x Gain)
DAC
Register
GND
Figure 41. DAC8552 Architecture
The input coding for each device is unipolar straight
binary, so the ideal output voltage is given by:
D
65536
VOUT A, B + VREF
R
R
(1)
Where:
D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0
to 65535.
VOUTA,B refers to channel A or B.
RESISTOR STRING
Figure 42. Resistor String
The resistor string section is shown in Figure 42. It is
simply a divide-by-2 resistor followed by a string of
resistors, each of value R. The code loaded into the
DAC register determines at which node on the string
the voltage is tapped off. This voltage is then applied
to the output amplifier by closing one of the switches
connecting the string to the amplifier.
The write sequence begins by bringing the SYNC
line LOW. Data from the DIN line are clocked into the
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 30MHz,
making the DAC8552 compatible with high speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and
the shift register is locked. Further clocking does not
change the shift register data. Once 24 bits are
locked into the shift register, the eight MSBs are
used as control bits and the 16 LSBs are used as
data. After receiving the 24th falling clock edge, the
DAC8552 decodes the eight control bits and 16 data
bits to perform the required function, without waiting
for a SYNC rising edge. A new SPI sequence starts
at the next falling edge of SYNC. A rising edge of
SYNC before the 24-bit sequence is complete resets
the SPI interface; no data transfer occurs.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating
rail-to-rail voltages on its output which approaches
an output range of 0V to VDD (gain and offset errors
must be taken into account). Each buffer is capable
of driving a load of 2kΩ in parallel with 1000pF to
GND. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics.
SERIAL INTERFACE
The DAC8552 uses a 3-wire serial interface (SYNC,
SCLK, and DIN) that is compatible with SPI™,
QSP™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation
Timing Diagram for an example of a typical write
sequence.
After the 24th falling edge of SCLK is received, the
SYNC line may be kept LOW or brought HIGH. In
either case, the minimum delay time from the 24th
falling SCLK edge to the next falling SYNC edge
must be met in order to properly begin the next
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cycle. To assure the lowest power consumption of
the device, care should be taken that the levels are
as close to each rail as possible. (See the Typical
Characteristics section for the Supply Current vs
Logic Input Voltage transfer characteristic curve).
the destination of the data (or power-down
command) between DAC A and DAC B. The final
two control bits, PD0 (DB16) and PD1 (DB17), select
the power-down mode of one or both of the DAC
channels. The four modes are normal mode or any
one of three power-down modes. A more complete
description of the operational modes of the DAC8552
can be found in the Power-Down Modes section. The
remaining 16 bits of the 24-bit input word make up
the data bits. These bits are transferred to the
specified Data Buffer or DAC Register, depending on
the command issued by the control byte, on the 24th
falling edge of SCLK. See Table 1 and Table 2 for
more information.
INPUT SHIFT REGISTER
The input shift register of the DAC8552 is 24 bits
wide (shown in Figure 43) and is made up of eight
control bits (DB16–DB23) and 16 data bits
(DB0–DB15). The first two control bits (DB22 and
DB23) are reserved and must be '0' for proper
operation. LDA (DB20) and LD B (DB21) control the
updating of each analog output with the specified
16-bit data value or power- down command. Bit
DB19 is a don't care bit that does not affect the
operation of the DAC8552, and can be '1' or '0'. The
following control bit, Buffer Select (DB18), controls
DB23
DB12
0
0
LDB
D9
LDA
D8
X
Buffer Select
D6
PD1
D5
PD0
D5
D15
D3
D14
D2
D13
D1
D12
DB0
DB11
D11
D10
D7
D0
Figure 43. DAC8552 Data Input Register Format
Table 1. Control Matrix
D23
D22
D21
D20
D19
D18
D17
PD1
D16
D15
D14
D13–D0
Don't
Care
Buffer
Select
MSB-2...
LSB
Reserved
Reserved
Load B
Load A
PD0 MSB MSB-1
0 = A,
1 = B
(Always Write 0)
DESCRIPTION
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
#
#
#
0
0
Data
WR Buffer # w/Data
See Table 2
X
WR Buffer # w/Power-down Command
WR Buffer # w/Data and Load DAC A
0
0
Data
WR Buffer A w/Power-Down Command and LOAD DAC A
(DAC A Powered Down)
0
0
0
1
X
0
See Table 2
See Table 2
X
0
0
0
0
0
0
0
1
1
1
0
0
X
X
X
1
#
0
X
Data
X
WR Buffer B w/Power-Down Command and LOAD DAC A
WR Buffer # w/Data and Load DAC B
0
0
See Table 2
See Table 2
WR Buffer A w/Power-Down Command and LOAD DAC B
WR Buffer B w/Power-Down Command and LOAD DAC B
(DAC B Powered Down)
0
0
0
0
0
0
1
1
1
0
1
1
X
X
X
1
#
0
X
Data
X
0
0
WR Buffer # w/Data and Load DACs A and B
WR Buffer A w/Power-Down Command and Load DACs A and
B (DAC A Powered Down)
See Table 2
See Table 2
WR Buffer B w/Power-Down Command and Load DACs A and
B (DAC B Powered Down)
0
0
1
1
X
1
X
Table 2. Power-Down Commands
D17
PD1
0
D16
PD0
1
OUTPUT IMPEDANCE POWER DOWN COMMANDS
1kΩ
1
0
100kΩ
1
1
High Impedance
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SYNC INTERRUPT
3V). Not only does the supply current fall, but the
output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This configuration has the advantage that the
output impedance of the device is known while it is in
power-down mode. There are three different options
for power-down: The output is connected internally to
GND through a 1kΩ resistor, a 100kΩ resistor, or it is
left open-circuited (High-Impedance). The output
stage is illustrated in Figure 44.
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
addressed DAC register is updated on the 24th
falling edge. However, if SYNC is brought HIGH
before the 24th falling edge, it acts as an interrupt to
the write sequence; the shift register is reset and the
write sequence is discarded. Neither an update of
the data buffer contents, DAC register contents nor a
change in the operating mode occurs, as shown in
Figure 45.
Table 3. Operating Modes
PD1 (DB17)
PD0 (DB16)
OPERATING MODE
Normal Operation
POWER-ON RESET
0
—
0
0
—
1
The DAC8552 contains a power-on reset circuit that
controls the output voltage during power-up. Upon
power-up, the DAC registers are filled with zeros and
the output voltages are set to zero-scale; they
remain that way until a valid write sequence and load
command are made to the respective DAC channel.
The power-on reset is useful in applications where it
is important to know the state of the output of each
DAC output while the device is in the process of
powering up.
Power-down modes
Output typically 1kΩ to GND
Output typically 100kΩ to GND
High impedance
1
0
1
1
Resistor
String
DAC
Amplifier
VOUTA,B
No device pin should be brought high before power
is applied to the device.
Power-Down
Circuitry
Resistor
Network
POWER-DOWN MODES
The DAC8552 usees four modes of operation. These
modes are accessed by setting two bits (PD1 and
PD0) in the control register to one or both DACs.
Table 3 shows how the state of the bits correspond
to the register and perform a mode of operation on
each channel of the device. (Each DAC channel can
be powered down simultaneously or independently of
each other. Power-down occurs after proper data is
written into PD0 and PD1 and a Load command
occurs.) See the Operation Examples section for
additional information.
Figure 44. Output Stage During Power-Down
(High Impedance)
All analog circuitry is shut down when the
power-down mode is activated. Each DAC will exit
power-down when PD0 and PD1 are set to '0', new
data is written to the Data Buffer, and the DAC
channel receives a Load command. The time to exit
power-down is typically 2.5µs for VDD = 5V and 5µs
for VDD = 3V (see the Typical Characteristics).
When both bits are set to '0', the device works
normally with a typical power consumption of 450µA
at 5V. For the three power-down modes, however,
the supply current falls to 700nA at 5V (400nA at
24th Falling Edge
24th Falling Edge
SCLK
SYNC
1
2
1
2
Invalid Write - Sync Interrupt:
SYNC HIGH Before 24th Falling Edge
Valid Write - Buffer/DAC Update:
SYNC HIGH After 24th Falling Edge
DIN
DB23 DB22
DB1 DB0
DB23 DB22
DB0
Figure 45. Interrupt and Valid SYNC Timing
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OPERATION EXAMPLES
Example 1: Write to Data Buffer A Through Buffer B; Load DAC A Through DAC B Simultaneously
•
1st — Write to Data Buffer A:
Reserved
0
Reserved
0
LDB
0
LDA
0
DC
X
Buffer Select
0
PD1
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
•
2nd — Write to Data Buffer B and Load DAC A and DAC B simultaneously:
Reserved
0
Reserved
0
LDB
1
LDA
1
DC
X
Buffer Select
1
PD1
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
The DAC A and DAC B analog outputs simultaneously settle to the specified values upon completion of the 2nd
write sequence. (The Load command moves the digital data from the data buffer to the DAC register at which
time the conversion takes place and the analog output is updated. Completion occurs on the 24th falling SCLK
edge after SYNC LOW.)
Example 2: Load New Data to DAC A and DAC B Sequentially
•
1st — Write to Data Buffer A and Load DAC A: DAC A output settles to specified value upon completion:
Reserved
0
Reserved
0
LDB
0
LDA
1
DC
X
Buffer Select
0
PD1
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
•
2nd — Write to Data Buffer B and Load DAC B: DAC B output settles to specified value upon completion:
Reserved
0
Reserved
0
LDB
1
LDA
0
DC
X
Buffer Select
1
PD1
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
After completion of the 1st write cycle, the DAC A analog output settles to the voltage specified; upon
completion of write cycle 2, the DAC B analog output settles.
Example 3: Power-Down DAC A to 1kΩ and Power-Down DAC B to 100kΩ Simultaneously
•
1st — Write power-down command to Data Buffer A:
Reserved
0
Reserved
0
LDB
0
LDA
0
DC
X
Buffer Select
0
PD1
0
PD0
1
DB15
—
DB1
DB0
DB0
Don't Care
•
2nd — Write power-down command to Data Buffer B and Load DAC A and DAC B simultaneously:
Reserved
0
Reserved
0
LDB
1
LDA
1
DC
X
Buffer Select
1
PD1
1
PD0
0
DB15
—
DB1
Don't Care
The DAC A and DAC B analog outputs simultaneously power-down to each respective specified mode upon
completion of the 2nd write sequence.
Example 4: Power-Down DAC A and DAC B to High-Impedance Sequentially:
•
1st — Write power-down command to Data Buffer A and Load DAC A: DAC A output = Hi-Z:
Reserved
0
Reserved
0
LDB
0
LDA
1
DC
X
Buffer Select
0
PD1
1
PD0
1
DB15
—
DB1
DB0
DB0
Don't Care
•
2nd — Write power-down command to Data Buffer B and Load DAC B: DAC B output = Hi-Z:
Reserved
0
Reserved
0
LDB
1
LDA
0
DC
X
Buffer Select
1
PD1
1
PD0
1
DB15
—
DB1
Don't Care
The DAC A and DAC B analog outputs sequentially power-down to high-impedance upon completion of the 1st
and 2nd write sequences, respectively.
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MICROPROCESSOR INTERFACING
DAC8552 to 8051 INTERFACE
DAC8552 to 68HC11 INTERFACE
Figure 46 shows a serial interface between the
DAC8552 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8552, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8552,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second and third write cycle are initiated to
transmit the remaining data. P3.3 is taken HIGH
following the completion of the third write cycle. The
8051 outputs the serial data in a format that presents
the LSB first, while the DAC8552 requires its data
with the MSB as the first bit received. The 8051
transmit routine must therefore take this into account,
and mirror the data as needed
Figure 48 shows a serial interface between the
DAC8552 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8552, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
PC7
DAC8552(1)
SYNC
SCK
SCLK
DIN
MOSI
NOTE: (1) Additional pins omitted for clarity.
Figure 48. DAC8552 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8552, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
80C51/80L51(1)
P3.3
DAC8552(1)
SYNC
TXD
RXD
SCLK
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 46. DAC8552 to 80C51/80L51 Interface
DAC8552 to Microwire INTERFACE
DAC8552 to TMS320 DSP INTERFACE
Figure 49 shows the connections between the
DAC8552 and a TMS320 digital signal processor. By
decoding the FSX signal, multiple DAC8552s can be
connected to a single serial port of the DSP.
Figure 47 shows an interface between the DAC8552
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
clocked into the DAC8552 on the rising edge of the
SK signal.
Positive Supply
DAC8552
VDD
MicrowireTM
CS
DAC8552(1)
SYNC
0.1mF
10mF
TMS320 DSP
SCLK
DIN
SK
SO
FSX
DX
SYNC
DIN
Output A
Output B
VOUT
A
VOUT
B
NOTE: (1) Additional pins omitted for clarity.
SCLK
CLKX
Reference
Input
VREF
GND
0.1mF
1mF to 10mF
Figure 47. DAC8552 to Microwire Interface
Figure 49. DAC8552 to TMS320 DSP
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APPLICATION INFORMATION
In addition, the DAC8552 can achieve typical ac
performance of 96dB signal-to-noise ratio (SNR) and
–85dB total harmonic distortion (THD), making the
DAC8552 a solid choice for applications requiring
high SNR at output frequencies at or below 10kHz.
CURRENT CONSUMPTION
The DAC8552 typically consumes 170µA at VDD
=
5 V and 155µA at VDD = 2.7V for each active
channel, excluding reference current consumption.
Additional current consumption can occur at the
digital inputs if VIH << VDD. For most efficient power
operation, CMOS logic levels are recommended at
the digital input to the DAC.
OUTPUT VOLTAGE STABILITY
The DAC8552 exhibits excellent temperature stability
of 5ppm/°C typical output voltage drift over the
specified temperature range of the device. This
stability enables the output voltage of each channel
to stay within a ±25µV window for a ±1°C ambient
temperature change.
In power-down mode, typical current consumption is
700nA. A delay time of 10ms to 20ms after a
power-down command is issued to the DAC is
typically sufficient for the power-down current to drop
below 10µA.
Good
power-supply
rejection
ratio
(PSRR)
performance reduces supply noise present on VDD
from appearing at the outputs. Combined with good
dc noise performance and true 16-bit differential
linearity, the DAC8552 becomes an ideal choice for
closed-loop control applications.
DRIVING RESISTIVE AND CAPACITIVE
LOADS
The DAC8552 output stage is capable of driving
loads of up to 1000pF while remaining stable. Within
the offset and gain error margins, the DAC8552 can
operate rail-to-rail when driving a capacitive load.
Resistive loads of 2kΩ can be driven by the
DAC8552 while achieving good load regulation.
When the outputs of the DAC are driven to the
positive rail under resistive loading, the PMOS
transistor of each Class-AB output stage can enter
into the linear region. When this scenario occurs, the
added IR voltage drop deteriorates the linearity
performance of the DAC. This deterioration only
occurs within approximately the top 100mV of the
DACs output voltage characteristic. Under resistive
loading conditions, good linearity is preserved as
long as the output voltage is at least 100mV below
the VDD voltage.
SETTLING TIME AND OUTPUT GLITCH
PERFORMANCE
The DAC8552 settles to ±0.003% of its full-scale
range within 10µs, driving a 200pF, 2kΩ load. For
good settling performance, the outputs should not
approach the top and bottom rails. Small signal
settling time is under 1µs, enabling data update rates
exceeding 1MSPS for small code changes.
Many applications are sensitive to undesired
transient signals such as glitch. The DAC8552 has a
proprietary, ultra-low glitch architecture addressing
such applications. Code-to-code glitches rarely
exceed 1mV and they last under 0.3µs. Typical glitch
energy is an outstanding 0.15nV-s. Theoretical
worst-case glitch should occur during a 256LSB step,
but it is so low, it cannot be detected.
CROSSTALK AND AC PERFORMANCE
The DAC8552 architecture uses separate resistor
strings for each DAC channel in order to achieve
ultra-low crosstalk performance. dc crosstalk seen at
one channel during a full-scale change on the
neighboring channel is typically less than 0.5 LSBs.
The ac crosstalk measured (for a full-scale, 1kHz
sine wave output generated at one channel, and
measured at the remaining output channel) is
typically under –100dB.
DIFFERENTIAL AND INTEGRAL
NONLINEARITY
The DAC8552 uses precision, thin-film resistors to
achieve monotonicity and good linearity. Typical
linearity error is ±4LSBs, with a ±0.3mV error for a
5V range. Differential linearity is typically ±0.35LSBs,
with a ±27µV error for a consecutive code change.
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USING REF02 AS A POWER SUPPLY FOR
DAC8552
the DAC8552 is 340µA typical and 500µA max for
VDD = 5V. When a DAC output is loaded, the REF02
also needs to supply the current to the load. The
typical current required (with a 5kΩ load on a given
DAC output) is:
Due to the extremely low supply current required by
the DAC8552, a possible configuration is to use a
REF02 +5V precision voltage reference to supply the
required voltage to the DAC8552 supply input as well
as the reference input, as shown in Figure 50.
340µA + (5V/5kΩ) = 1.34mA
BIPOLAR OPERATION USING THE DAC8552
+15V
The DAC8552 has been designed for single-supply
operation but a bipolar output range is also possible
using the circuit in Figure 51. The circuit shown here
gives an output voltage range of ±VREF. Rail-to-rail
operation at the amplifier output is achievable using
an amplifier such as the OPA703, as shown in
Figure 51.
+5V
REF02
1.34mA
The output voltage for any input code can be
calculated as follows:
VDD, VREF
SYNC
Three-Wire
Serial
Interface
VOUT = 0V to 5V
SCLK
DIN
DAC8552
ǒR1 ) R2Ǔ
ǒR2Ǔ
ƫ
D
ǒ Ǔ
VOUT A, B +
ƪ
VREF
* VREF
65536
R1
R1
(2)
where D represents the input code in decimal
(0–65535).
Figure 50. REF02 as a Power Supply to the
DAC8552
With VREF = 5V, R1– R2 = 10kΩ.
10 D
ǒ Ǔ* 5V
VOUT A, B +
65536
This configuration is especially useful if the power
supply is quite noisy or if the system supply voltages
are at some value other than 5V. The REF02 will
output a steady supply voltage for the DAC8552. If
the REF02 is used, the current it needs to supply to
(3)
Using this example, an output voltage range of ±5V
with 0000h corresponding to a –5V output and
FFFFh corresponding to
a 5V output can be
achieved. Similarly, using VREF = 2.5V, a ±2.5V
output voltage range can be achieved.
+5V
R2
10kW
+6V
R1
10kW
±5V
OPA703
VDD, VREF
VOUTA,B
10mF
0.1mF
DAC8552
–6V
NOTE: Additional pins omitted for clarity.
Three-Wire
Serial Interface
Figure 51. Bipolar Operation with the DAC8552
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LAYOUT
The power applied to VDD should be well-regulated
and low-noise. Switching power supplies and dc/dc
converters will often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency
spikes. This noise can easily couple into the DAC
output voltage through various paths between the
power connections and analog output.
A
precision analog component requires careful
layout, adequate bypassing, and clean,
well-regulated power supplies.
The DAC8552 offers single-supply operation, and it
will often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
As with the GND connection, VDD should be
connected to a positive power-supply plane or trace
that is separate from the connection for digital logic
until they are connected at the power entry point. In
addition, a 1µF to 10µF capacitor in parallel with a
0.1µF bypass capacitor is strongly recommended. In
some situations, additional bypassing may be
required, such as a 100µF electrolytic capacitor or
Due to the single ground pin of the DAC8552, all
return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they are connected at the power
entry point of the system.
even
a Pi filter made up of inductors and
capacitors—all designed to essentially low-pass filter
the supply, removing the high-frequency noise.
20
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC8552IDGKR
DAC8552IDGKT
DAC8552IDGKTG4
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
2500 RoHS & Green Call TI | NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
-40 to 105
D82
D82
D82
250
250
RoHS & Green Call TI | NIPDAUAG
RoHS & Green Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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