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DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

DAC874xH HART^®和 FOUNDATION Fieldbus™ 以及 PROFIBUS PA 调

制解调器

1 特性

2 应用

1

•

兼容 HART 的物理层调制解调器

•

工业过程控制和自动化

PLC 或 DCS I/O 模块

–

1200Hz、2200Hz HART FSK 正弦波

现场和传感器变送器

TX 信号振幅的寄存器编程控制（仅适用于

DAC8741H）

3 说明

–

集成式 RX 解调器和带通滤波器，具有极少的外

部组件

DAC8740H 和 DAC8741H (DAC874xH) 是与 HART

^®、 FOUNDATION 现场总线™和 PROFIBUS PA 兼

容的低功耗调制解调器，设计用于工业过程控制和工业

自动化应用。

兼容 FOUNDATION 现场总线的 H1 控制器和介质

连接单元 (MAU)

–

基于曼彻斯特编码总线供电 (MBP) 的

31.25kbit/s 通信

在 HART 模式下，DAC874xH 集成所有必需电路，以

作为一个半双工 HART 物理层调制解调器，在从配置

或主配置中使用最少的外部过滤组件运行。在

FOUNDATION 现场总线模式下，DAC874xH 集成所

有必需电路，以作为兼容半双工 FOUNDATION 现场

总线的 H1 控制器和 MAU 运行。

–

集成曼彻斯特编码器和解码器

与 PROFIBUS PA 兼容

低静态电流：在典型工业工作温度范围（-40°C 至

+85°C）下最大值为 180µA

•

集成 1.5V 电压基准

灵活的时钟选项

–

内部振荡器

在 HART、FOUNDATION 现场总线或 PROFIBUS PA

模式下，可通过 UART 接口或 SPI 接口接入的集成式

FIFO 传输来自微控制器的数据流。SPI 接口包括一个

支持菊链的 SDO 引脚、各种中断以及其他扩展特

性。

外部晶体振荡器

外部 CMOS 时钟

•

数字接口

–

DAC8740H：UART

DAC8741H：SPI

器件信息⁽¹⁾

可靠性：CRC 位错校验、看门狗计时器（仅适用于

DAC8741H）

器件型号

DAC8740H

DAC8741H

封装

封装尺寸（标称值）

超薄四方扁平无引线

(VQFN) (24)

4mm x 4mm

•

宽工作温度范围：–55°C 至 +125°C

4mm × 4mm QFN 封装

超薄四方扁平无引线

(VQFN) (24)

4mm x 4mm

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。

简化原理图

IOVDD

CLK_CFG0 CLK_CFG1 CLKO

XEN X1 X2

REF_EN

REF

REG_CAP AVDD

Clock

Generator

Precision

Oscillator

Voltage

Reference

DAC

RST

CD / IRQ

Transmit

Modulator

HART

Buffer

MOD_OUT

MOD_INF

MOD_IN

UART_IN / CS

DUPLEX / SDI

UART_OUT / SDO

UART_RTS / SCLK

IF_SEL

MUX

Receive

Demodulator

Carrier

Detect

Bandpass

Filter

PA/FF

DGND

BPFEN

AGND

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS856

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

8.4 Device Functional Modes........................................ 19

8.5 Register Maps......................................................... 23

Application and Implementation ........................ 31

9.1 Application Information............................................ 31

9.2 Typical Application ................................................. 33

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 Timing Requirements.............................................. 11

7.7 Typical Characteristics............................................ 12

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 16

9

10 Power Supply Recommendations ..................... 37

11 Layout................................................................... 37

11.1 Layout Guidelines ................................................. 37

11.2 Layout Example .................................................... 37

12 器件和文档支持 ..................................................... 39

12.1 文档支持 ............................................................... 39

12.2 相关链接................................................................ 39

12.3 接收文档更新通知 ................................................. 39

12.4 社区资源................................................................ 39

12.5 商标....................................................................... 39

12.6 静电放电警告......................................................... 39

12.7 Glossary................................................................ 39

13 机械、封装和可订购信息....................................... 39

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (December 2018) to Revision D

Page

•

Added recommended operating temperature range, T_A, to the Recommended Operating Conditions table ........................ 7

Changed maximum temperature test conditions for all specifications in the Electrical Characteristics table from

+125℃ to +105℃ ................................................................................................................................................................... 8

Changes from Revision B (June 2018) to Revision C

Page

•

已删除从数据表中删除了 DAC8742H.................................................................................................................................... 1

Changes from Revision A (December 2017) to Revision B

Page

•

DAC8741H 和 DAC8742H 已发布至生产............................................................................................................................... 1

Changes from Original (June 2017) to Revision A

Page

•

首次公开发布的完整数据表..................................................................................................................................................... 1

DAC8740H 已发布至生产....................................................................................................................................................... 1

2

DAC8740H, DAC8741H

www.ti.com.cn

ZHCSH77D –JUNE 2017–REVISED MAY 2019

5 Device Comparison Table

PART NUMBER

DAC8740H

DIGITAL INTERFACE

UART

SPI

DAC8741H

6 Pin Configuration and Functions

RGE Package: DAC8740H

24-Pin VQFN

Top View

XEN

CLKO

1

2

3

4

5

6

18

17

16

15

14

13

AVDD

MOD_INF

MOD_IN

REF

CLK_CFG0

CLK_CFG1

RST

Thermal pad

MOD_OUT

REG_CAP

CD

Not to scale

Pin Functions: DAC8740H

TYPE

DESCRIPTION

NO.

NAME

Crystal oscillator enable. Logic low on this pin enables the crystal oscillator circuit; in

this mode, an external crystal is required. Logic high on this pin disables the internal

crystal oscillator circuit; in this mode an external CMOS clock or the internal oscillator

are required. No digital input pin should be left floating.

1

XEN

Digital input

Clock output. If using the internal oscillator or an external crystal, this pin can be

configured as a clock output.

2

3

4

CLKO

Digital output

Digital input

Clock configuration. This pin is used to configure the input/output clocking scheme.

No digital input pin should be left floating.

CLK_CFG0

CLK_CFG1

Clock configuration. This pin is used to configure the input/output clocking scheme.

No digital input pin should be left floating.

Reset. Logic low on this pin places the DAC874xH into power-down mode and resets

the device. Logic high returns the device to normal operation. No digital input pin

should be left floating.

5

RST

Digital input

HART mode.

Carrier detect. A logic high on this pin indicates a valid carrier is present.

FF or PA mode.

6

CD

Digital output

While not transmitting, a logic high on this pin indicates a valid carrier is present.

While transmitting, a logic high on this pin indicates that the jabber inhibitor has

triggered.

3

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

Pin Functions: DAC8740H (continued)

TYPE

DESCRIPTION

NO.

NAME

7

UART_IN

Digital input

UART data input. No digital input pin should be left floating.

HART mode.

Request to send. A logic high on this pin enables the demodulator and disables the

modulator. A logic low on this pin enables the modulator and disables the

demodulator. No digital input pin should be left floating.

Digital input,

Digital output

8

UART_RTS

FF or PA mode.

This pin reports transmit FIFO threshold information as programmed by the packet

initiation code.

Digital input. Logic high enables full-duplex, or internal loop-back, test mode. No

digital input pin should be left floating.

9

DUPLEX

UART_OUT

IOVDD

Digital input

Digital output

Supply

10

11

UART data output

Interface supply. Supply voltage for digital input and output circuitry. This voltage sets

the logical thresholds for the digital interface.

12

13

GND

Supply

Digital ground. Ground reference voltage for all digital circuitry of the device.

Capacitor for internal regulator.

REG_CAP

Analog output

Modem output. FSK output sinusoid in HART mode or Manchester coded data stream

in FOUNDATION Fieldbus and PROFIBUS PA modes. for stability, this pin requires

parallel capacitance of 5 nF to 22 nF in HART mode, or 0 pF to 100 pF in

FOUNDATION Fieldbus and PROFIBUS PA mode.

14

MOD_OUT

Analog output

Analog input or

output

When the internal reference is enabled, this pin outputs the internal reference voltage.

When the internal reference is disabled, this pin is the external 2.5-V reference input.

15

16

REF

HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded

data stream input. If an external filter is used, do not connect this pin.

MOD_IN

Analog input

If using the internal band-pass filter, connect 680 pF to this pin in HART mode, or 120

pF in FOUNDATION Fieldbus and PROFIBUS PA modes. If using an external filter,

connect the output of that filter to this pin.

17

MOD_INF

Analog input

18

19

20

21

22

AVDD

GND

X2

Supply

Power supply

Analog ground. Ground reference voltage for power supply input.

Crystal stimulus

Analog input

Supply

X1

Crystal ro clock input

GND

Digital ground. Ground reference voltage for all digital circuitry of the device.

Reference enable. Logic high enables the internal 1.5-V reference. No digital input pin

should be left floating.

23

24

REF_EN

BPF_EN

Digital input

Supply

Filter enable. A logic high enables the internal band-pass filter. No digital input pin

should be left floating.

Thermal

pad

Thermal pad

Thermal pad. Connected to GND if connected to an electrical potential.

4

DAC8740H, DAC8741H

www.ti.com.cn

ZHCSH77D –JUNE 2017–REVISED MAY 2019

RGE Package: DAC8741H

24-Pin VQFN

Top View

XEN

CLKO

1

2

3

4

5

6

18

17

16

15

14

13

AVDD

MOD_INF

MOD_IN

REF

CLK_CFG0

CLK_CFG1

RST

Thermal pad

MOD_OUT

REG_CAP

IRQ

Not to scale

Pin Functions: DAC8741H

TYPE

DESCRIPTION

NO.

NAME

Crystal oscillator enable. Logic low on this pin enables the crystal oscillator circuit; in

this mode, an external crystal is required. Logic high on this pin disables the internal

crystal oscillator circuit; in this mode, an external CMOS clock or the internal oscillator

are required. No digital input pin should be left floating.

1

XEN

Digital input

Clock output. If using the internal oscillator or an external crystal, this pin can be

configured as a clock output.

2

3

4

CLKO

Digital output

Digital input

Clock configuration. This pin is used to configure the input/output clocking scheme.

No digital input pin should be left floating.

CLK_CFG0

CLK_CFG1

Clock Configuration. This pin is used to configure the input/output clocking scheme.

No digital input pin should be left floating.

Reset. Logic low on this pin places the DAC874xH into power-down mode and resets

the device. Logic high returns the device to normal operation. No digital input pin

should be left floating.

5

6

RST

IRQ

Digital input

Digital Interrupt. The interrupt can be configured as edge sensitive or level sensitive

with positive or negative polarity, as set by the CONTROL register. Events that trigger

an interrupt are controlled by the Modem IRQ Mask register.

Digital output

SPI chip-select. Data bits are clocked into the serial shift register when CS is low.

When CS is high, SDO is in a high-impedance state and data on SDI are ignored. No

digital input pin should be left floating.

7

8

9

CS

SCLK

SDI

Digital input

SPI clock. Data can be transferred at rates up to 12.5 MHz. Schmitt-Trigger logic

input. No digital input pin should be left floating.

SPI data input. Data are clocked into the 24-bit input shift register on the falling edge

of the serial clock input. Schmitt-Trigger logic input. No digital input pin should be left

floating.

10

11

SDO

Digital output

Supply

SPI data output. Data are valid on the falling edge of SCLK.

Interface supply. Supply voltage for digital input and output circuitry. This voltage sets

the logical thresholds for the digital interface.

IOVDD

12

13

GND

Supply

Digital ground. Ground reference voltage for all digital circuitry of the device.

Capacitor for internal regulator

REG_CAP

Analog output

5

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

Pin Functions: DAC8741H (continued)

TYPE

DESCRIPTION

NO.

NAME

Modem output. FSK output sinusoid in HART mode or Manchester coded data stream

in FOUNDATION Fieldbus and PROFIBUS PA modes. For stability, this pin requires

parallel capacitance of 5 nF to 22 nF in HART mode, or 0 pF to 100 pF in

FOUNDATION Fieldbus and PROFIBUS PA mode.

14

MOD_OUT

Analog output

Analog Input or

output

When the internal reference is enabled, this pin outputs the internal reference voltage.

When the internal reference is disabled, this pin is the external 2.5-V reference input.

15

16

REF

HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded

data stream input. If an external filter is used, do not connect this pin.

MOD_IN

Analog input

If using the internal band-pass filter, connect 680 pF to this pin, or 120 pF in

FOUNDATION Fieldbus and PROFIBUS PA modes. If using an external filter,

connect the output of that filter to this pin.

17

MOD_INF

Analog input

18

19

20

21

22

AVDD

GND

X2

Supply

Power supply

Analog ground. Ground reference voltage for power supply input.

Crystal stimulus

Analog input

Supply

X1

Crystal or clock input

GND

Digital ground. Ground reference voltage for all digital circuitry of the device.

Reference enable. Logic high enables the internal 1.5-V reference. No digital input pin

should be left floating.

23

24

REF_EN

BPF_EN

Digital input

Supply

Filter enable. A logic high enables the internal band-pass filter. No digital input pin

should be left floating.

Thermal

pad

Thermal pad

Thermal pad. Connected to GND if connected to an electrical potential.

6

DAC8740H, DAC8741H

www.ti.com.cn

ZHCSH77D –JUNE 2017–REVISED MAY 2019

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

−0.3

−10

MAX

UNIT

AVDD to GND

6

IOVDD to GND

Input voltage

V

Analog output voltage to GND

AVDD + 0.3

IOVDD + 0.3

AVDD + 0.3

IOVDD + 0.3

10

Digital output voltage to GND

Analog output pin to GND

Output voltage

V

Digital output pin to GND

Input current

Input current to any pin except supply pins

mA

℃

Operating junction temperature, T_J

Storage temperature, T_stg

−55

125

−60

150

℃

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±8000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

AVDD

2.7

5.5

V

IOVDD

1.71

ANALOG INPUTS

External reference input voltage

DIGITAL INPUTS

2.375

2.5

2.625

V

3.6864-MHz clock

1.2288-MHz clock

3.6469

1.2165

3.6864

1.2288

3.7232

1.2411

External clock source frequency

(HART mode)

MHz

External clock source frequency

(FF or PA modes)

3.96

4

4.04

TEMPERATURE

Recommended operating temperature, T_A

−40

105

℃

7

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

7.4 Thermal Information

DAC8740H, DAC8741H

THERMAL METRIC⁽¹⁾

RGE

24 PINS

32.1

31.8

9.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

Ψ_JB

9.6

R_θJC(bot)

1.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

all specifications over –40°C to +105°C ambient operating temperature, 2.7 V ≤ AVDD ≤ 5.5 V, 1.71 V ≤ IOVDD ≤ 5.5 V,

internal reference, internal filter (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER REQUIREMENTS

AVDD and IOVDD Supply Current (HART Mode)

External clock, –40°C to +85°C

110

100

150

220

µA

External clock, –55°C to +105℃

External clock, –40°C to +85°C, external

reference

Demodulator active

140

210

µA

External clock, –55°C to +105℃, external

reference

External clock, –40°C to +85°C

160

150

180

250

µA

External clock, –55°C to +105℃

External clock, –40°C to +85°C, external

reference

Modulator active

Crystal oscillator

170

240

µA

External clock, –55°C to +105℃, external

reference

External crystal, 16 pF at XTAL1 and XTAL2

External crystal, 36 pF at XTAL1 and XTAL2

External reference

40

65

µA

Internal oscillator

SPI interface

105

180

Additional quiescent current required when

interfacing via SPI (DAC8741H only)

5

160

175

µA

AVDD and IOVDD Supply Current (FF/PA Mode)

External clock, –40°C to +85°C

220

330

µA

External clock, –55°C to +105℃

External clock, –40°C to +85°C, external

reference

Decoder active

Encoder active

200

320

µA

External clock, –55°C to +105℃, external

reference

External clock, –40°C to +85°C

175

165

250

360

µA

External clock, –55°C to +105℃

External clock, –40°C to +85°C, external

reference

235

350

µA

External clock, –55°C to +105℃, external

reference

External crystal, 16 pF at XTAL1 and XTAL2

External crystal, 36 pF at XTAL1 and XTAL2

40

65

µA

Crystal oscillator

SPI interface

Additional quiescent current required when

interfacing via SPI (DAC8741H)

5

µA

8

DAC8740H, DAC8741H

www.ti.com.cn

ZHCSH77D –JUNE 2017–REVISED MAY 2019

Electrical Characteristics (continued)

all specifications over –40°C to +105°C ambient operating temperature, 2.7 V ≤ AVDD ≤ 5.5 V, 1.71 V ≤ IOVDD ≤ 5.5 V,

internal reference, internal filter (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AVDD and IOVDD Supply Current (All Modes)

Internal reference disabled, –40°C to +85°C,

no active clock input

30

60

µA

Power-down mode

Internal reference disabled, –55°C to +105℃,

no active clock input

182

CLOCK REQUIREMENTS

EXTERNAL CLOCK (HART MODE)

3.6864-MHz clock

1.2288-MHz clock

3.6469

1.2165

3.6864

1.2288

3.7232

1.2411

MHz

External clock source frequency

EXTERNAL CLOCK (FF/PA MODE)

External clock source frequency

INTERNAL OSCILLATOR

Frequency

4-MHz clock

3.96

4

4.04

MHz

–40°C to +105℃

1.2165

1.2288

1.2411

VOLTAGE REFERENCE

INTERNAL REFERENCE VOLTAGE

Internal reference voltage

Load regulation

1.47

1.5

1.3

1

1.53

V

V/mA

µF

Capacitive load

Specified by design

OPTIONAL EXTERNAL REFERENCE VOLTAGE

External reference input voltage

2.375

2.5

4.5

2.625

V

Demodulator

µA

Modulator

External reference input current

Internal oscillator

Power-down

HART MODEM

MOD_IN INPUT (HART MODE)

External reference source, specified by

design. Signal applied at the input to the dc

blocking capacitor.

0

1.5

V_PP

Input voltage range

Receiver sensitivity

Internal reference source, specified by

design. Signal applied at the input to the dc

blocking capacitor.

V_PP

Threshold for successful carrier detection and

demodulation, assuming ideal sinusoidal

input FSK signals with valid preamble using

internal filter.

80

100

460

120

480

mV_PP

MOD_OUT OUTPUT (HART MODE)

AC-coupled (2.2 µF), measured at

MOD_OUT pin with 160-Ω load

Output voltage

450

Mark frequency

Internal oscillator

1200

2200

Hz

Space frequency

Frequency error

Phase continuity error

Internal oscillator

Internal oscillator, –40°C to +105℃

Specified by design

-1

1

0

%

Degrees

160-Ω, ac coupled with 2.2 µF, specified by

design

Minimum resistive load

160

Ω

RTS low, measured at the MOD_OUT pin, 1-

mA measurement current

13

Transmit impedance

RTS high, measured at the MOD_OUT pin,

±200-nA measurement current

250

kΩ

9

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

Electrical Characteristics (continued)

all specifications over –40°C to +105°C ambient operating temperature, 2.7 V ≤ AVDD ≤ 5.5 V, 1.71 V ≤ IOVDD ≤ 5.5 V,

internal reference, internal filter (unless otherwise noted)

PARAMETER

FF / PA MODEM

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MOD_IN INPUT (FF/PA MODE)

External reference source, specified by

design. Signal applied at the input to the DC

blocking capacitor.

0

1

Vp-p

Input voltage range

Internal reference enabled, specified by

design. Signal applied at the input to the DC

blocking capacitor.

0

1

Vp-p

µs

Edge-to-edge measurement of Manchester

encoded waveforms

Receiver jitter tolerance

Receiver sensitivity

-3.2

3.2

Threshold for successful carrier detection and

decoding, assuming ideal Manchester

encoded input trapezoidal signals with 6µs

rise time, valid preamble byte(s) and start

delimiter byte, using internal filter.

75

mVp-p

MOD_OUT OUTPUT (FF/PA MODE)

Output voltage

800

mVp-p

mV

Maximum difference in positive and negative

amplitude signals

Maximum amplitude difference

Transmit bit rate

-50

31.1875

-0.8

50

31.3125

0.8

31.25

kbit/s

µs

Measured with respect to ideal crossing of

high time and low time

Transmit jitter

Measured peak to trough distortion for

positive and negative amplitude voltage

outputs

Output signal distortion

-10

10

%

Rise and fall time

Slew rate

10% to 90% of peak to peak signal

8

µs

0.2

V/µs

DIGITAL REQUIREMENTS

DIGITAL INPUTS

0.7 x

IOVDD

VIH, input high voltage

V

0.3 x

IOVDD

VIL, input low voltage

0.8 x

IOVDD

CLK_CFG0, input high voltage

CLK_CFG0, input mid-scale voltage

CLK_CFG0, input low voltage

Specified by design

0.4 x

IOVDD

0.55 x

IOVDD

0.15 x

IOVDD

Input current

-1

1

µA

pF

Input capcitance

DIGITAL OUTPUTS

5

IOVDD -

0.5

VOH, output high voltage

VOL, output low voltage

200-µA source or sink

V

0.4

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7.6 Timing Requirements

all timing conditions specified by design (unless otherwise noted)

MIN

NOM

MAX

UNIT

SPI TIMING

SPI TIMING SPI TIMING SPI TIMING

SPI TIMING

t_c

SCLK cycle time

80

32

ns

us

ns

t_w1

SCLK high time

t_w2

SCLK low time

32

t_su

CS to SCLK falling edge setup time

Data setup time

32

t_su1

5

t_h1

Data hold time

5

t_d1

SCLK falling edge to CS rising edge

32

(1)

t_w3

Minimum CS high time

3.06

32

t_v

SCLK rising edge to SDO valid

Reset low time

t_rst

100

HART MODE TIMING

Carrier start time. Time from RTS falling edge to

transmit carrier reaching its first peak.

t_cstart

5

3

Bit-Times

Carrier stop time. Time from RTS rising edge to

transmit carrier amplitude falling below the receive

amplitude.

t_cstop

Carrier decay time. Time from RTS riding edge to

carrier amplitude dropping to zero.

t_cdecay

t_cdeton

t_cdetoff1

6

3

Bit-Times

ms

Carrier detect on. Time from valid carrier on receive

path to CD rising edge.

Carrier detect off. Time from valid carrier removed on

receive path to CD falling edge.

Carrier detect on when transitioning from transmit

mode to receive mode in the presence of a constant

valid receive carrier.

t_cdetoff2

2.1

25

ms

Crystal oscillator power-up time from enabling the

oscillator via clock configuration pins with 16-pF load

capacitors.

t_cos1

Crystal oscillator power-up time from enabling the

oscillator via clock configuration pins with 36-pF load

capacitors.

t_cos2

25

10

30

ms

µs

Reference power-up time from enabling via hardware

pin.

t_ref

Transition time from power-down mode to normal

operating mode with external clock and external

reference.

t_pow

(1) Time between two consecutive CS rising edges must be ≥3.06 µs.

t_c

1

2

24

t_w1

t_w2

t_d1

t_su

t_h1

t_w3

t_su1

MSB

LSB

t_w

t_rst

图 1. SPI Timing Diagram

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7.7 Typical Characteristics

0

-5

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

-10

-15

-20

-25

-30

-35

-40

-45

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

Frequency (Hz)

D002

D003

图 2. HART Mode External Band-Pass Filter Response

图 3. HART Mode Internal Band-Pass Filter Response

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-5

-10

-15

-20

-25

-30

-35

-40

-45

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

Frequency (Hz)

D004

D005

图 4. FF / PA Mode External Band-Pass Filter Response

图 5. FF / PA Mode Internal Band-Pass Filter Response

1.505

1.53

1.52

1.51

1.50

1.49

1.48

1.47

1.504

1.503

1.502

1.501

1.500

2.7

3.1

3.5

3.9

AVDD (V)

4.3

4.7

5.1

5.5

-55

-35

-15

5

25

45

65

85

105 125

Temperature (^oC)

D006

D007

图 6. Internal Reference Voltage vs AVDD

图 7. Internal Reference Voltage vs Temperature

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Typical Characteristics (接下页)

nRTS (2V/div)

MOD OUT (0.2V/div)

UART IN (2V/div)

MOD OUT (0.2V/div)

UART IN (2V/div)

0.1 ms/ div

D008

D009

图 8. HART TX Carrier Start Time

图 9. HART TX Carrier Stop / Decay Time

MOD IN (0.1V/div)

CD (2V/ div)

MOD IN (0.1V/div)

CD (2V/ div)

UART OUT (2V/div)

0.5 ms/ div

1 ms/ div

D010

D011

图 10. HART RX Carrier Detect Off Timing

图 11. HART RX Carrier Detect On Timing

10

9

8

7

6

5

4

3

2

1

0

130

120

110

100

90

Modulator Active

Demodulator Active

Modulator Active

Demodulator Active

80

70

60

50

1.5

2

2.5

3

3.5

IOVDD (V)

4

4.5

5

5.5

2.7

3

3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7

AVDD (V)

D012

D013

图 12. HART Mode IOVDD Supply Current vs Voltage With

图 13. HART Mode AVDD Supply Current vs Voltage With

External Reference

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Typical Characteristics (接下页)

10

165

150

135

120

105

90

Modulator Active

Demodulator Active

Modulator Active

9

Demodulator Active

8

7

6

5

4

3

2

1

0

75

60

45

1.5

2

2.5

3

3.5

IOVDD (V)

4

4.5

5

5.5

2.7

3

3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7

AVDD (V)

D016

BDP0F17_

图 14. HART Mode IOVDD Supply Current vs Voltage With

图 15. HART Mode AVDD Supply Current vs Voltage With

Internal Reference

32

28

152

Transmitting data

Receiving data

148

144

140

136

132

128

124

120

Transmitting data

24

Receiving data

20

16

12

8

4

0

1.5

2

2.5

3

3.5

IOVDD (V)

4

4.5

5

5.5

2.7

3

3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7

AVDD (V)

D014

BDP0F15_

图 16. FF / PA Mode IOVDD Supply Current vs Voltage With

图 17. FF / PA Mode AVDD Supply Current vs Voltage With

External Reference

32

28

164

Transmitting data

Receiving data

160

156

152

148

144

140

136

132

Transmitting data

24

Receiving data

20

16

12

8

4

0

1.5

2

2.5

3

3.5

IOVDD (V)

4

4.5

5

5.5

2.7

3

3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7

AVDD (V)

D018

BDP0F19_

图 18. FF / PA Mode IOVDD Supply Current vs Voltage With

图 19. FF / PA Mode AVDD Supply Current vs Voltage With

Internal Reference

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Typical Characteristics (接下页)

Time (0.5 ms/div)

D020

D021

图 20. Typical Manchester Encoded Trapezoid, No Filter

图 21. Typical Manchester Encoded Trapezoid, With

Suggested Filter Response

490

1.2kHz Signal

2.2kHz Signal

485

480

475

470

465

460

455

100 200 300 400 500 600 700 800 900 1000

R_LOAD(W)

D025

图 22. MOD_OUT Voltage vs R_LOAD

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8 Detailed Description

8.1 Overview

The DAC8740H and DAC8741H (DAC874xH) are HART© compliant and FOUNDATION Fieldbus or PROFIBUS

PA compatible low power modems designed for industrial process control and industrial automation applications.

In HART mode, the DAC874xH integrates all of the required circuitry to operate as half-duplex HART physical

layer modems, in either slave or master configurations with minimal external components for filtering. In

FOUNDATION Fieldbus mode, the DAC874xH integrate all of the required circuitry to operate as half-duplex

FOUNDATION Fieldbus compliant H1 Controllers and MAUs.

The HART, FOUNDATION Fieldbus, or PROFIBUS PA, data stream can be transferred from the microcontroller

through either a UART interface or an integrated FIFO accessed by a SPI interface. The SPI interface includes

an SDO pin for daisy-chain support, various interrupts, and other extended features.

8.2 Functional Block Diagram

IOVDD

CLK_CFG0 CLK_CFG1 CLKO

XEN X1 X2

REF_EN

REF

REG_CAP AVDD

Clock

Generator

Precision

Oscillator

Voltage

Reference

DAC

RST

CD / IRQ

Transmit

Modulator

HART

Buffer

MOD_OUT

MOD_INF

MOD_IN

UART_IN / CS

DUPLEX / SDI

UART_OUT / SDO

UART_RTS / SCLK

IF_SEL

MUX

Receive

Demodulator

Carrier

Detect

Bandpass

Filter

PA/FF

DGND

BPFEN

AGND

8.3 Feature Description

8.3.1 HART Modulator

In SPI mode, HART data is loaded into a transmit FIFO via the SPI serial interface. In UART mode, the UART

baud rate matches the HART baud rate, and therefore the FIFO is bypassed. In both cases, the input data are

translated into the mark and space frequency shift keyed (FSK) analog signals (1200 Hz and 2200 Hz,

respectively) used in HART communication using an internal HART modulator.

The HART modulator implements a look-up table containing 32 6-bit signed values that represent a single phase

continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a digital-to-

analog converter (DAC), at a clock frequency determined by the binary value of the input data, in order to create

the mark and space analog output signals used to represent HART data.

The modem operates in half-duplex mode, unless placed in full-duplex mode, where the modulator and

demodulator are not active simultaneously. The modem arbitrates over which component is active. To request

that the modulator is activated UART devices toggle the RTS pin low, SPI devices toggle the RTS bit in the

MODEM CONTROL register. These mechanics are explained in more detail in the respective sections of Device

Functional Modes.

In HART mode the MOD_OUT pin requires parallel capacitance of 5 nF to 22 nF, or 0 pF to 100 pF in

FOUNDATION Fieldbus and PROFIBUS PA mode for stability.

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Feature Description (接下页)

8.3.2 HART Demodulator

The HART demodulator converts the HART FSK input signals applied at the MOD_IN or MOD_INF pins,

depending on whether an external filter is implemented, to binary data that is loaded into a receive FIFO in SPI

mode. Data in the receive FIFO can then be read by the host controller via SPI serial interface. In UART mode

received data is directly fed through to the UART interface.

When a valid carrier is detected on devices using the UART interfaces, the CD pin will toggle high. For devices

using the SPI interface, the IRQ pin toggles, indicating an alarm condition. The MODEM STATUS register can

then be read to determine the source of the interrupt, which includes a bit for carrier detection in DB1. Hysteresis

is implemented with the carrier detect feature in order to prevent erroneous carrier detection signals. More details

are explained in the respective Device Functional Modes sections.

8.3.3 FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder

FOUNDATION Fieldbus or PROFIBUS PA data is loaded into a transmit FIFO via UART or SPI interfaces which

is translated into the Manchester encoded binary analog signals used in both FOUNDATION Fieldbus and

PROFIBUS PA bus protocols through an internal Manchester encoder.

The Manchester encoder interacts with the DAC to transmit positive and negative amplitude signals, with respect

to a positive common mode voltage, to create the Manchester encoded analog outputs at 31.25 kHz baud. A

binary 0 is represented by a low-to-high transition and a binary 1 is represented by a high-to-low transition.

In both UART and SPI interfaced device, the encoder is activated any time there is data available in the transmit

FIFO and the decoder is not receiving data. In order to prevent FIFO buffer overflow, for UART mode the CD pin

acts as an interrupt to indicate when the FIFO level has exceed a programmed threshold in the packet initiation

code. In SPI mode the transmit FIFO threshold programmed in the FIFO LEVEL SET register can trigger an

interrupt on the IRQ pin. Once the IRQ interrupts is triggered, the MODEM STATUS register can then be read to

determine the source of the interrupt, which includes a bit for the FIFO level in DB4. More details are explained

in the respective Device Functional Modes sections.

8.3.4 FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder

The FOUNDATION Fieldbus and PROFIBUS PA decoder converts the Manchester encoded data applied at the

MOD_IN or MOD_INF pins, depending on whether an external filter is implemented, to binary data that is loaded

into a receive FIFO. Data in the receive FIFO can then be read by the host controller via UART or SPI serial

interfaces.

When valid data is provided to the decoder, binary data is read out serially on the UART interface. For SPI

devices, the receive FIFO is loaded until the threshold programmed in FIFO LEVEL SET is met which will trigger

an interrupt on the IRQ pin. The MODEM STATUS register can then be read to determine the source of the

interrupt, which includes a bit for the FIFO level in DB7, indicating that data is ready to be read on the SPI bus.

More details are explained in the respective Device Functional Modes sections.

8.3.5 Internal Reference

An internal reference is included in the DAC874xH. The REF_EN pin is used to enable or disable the internal

reference, when the internal reference is disabled an external reference must be provided at the REF pin. In SPI

mode, the PDVREF bit in the CONTROL register can be used to enable or disable the internal reference via

software. If the REF_EN pin is set high, the register contents of the PDVREF bit is ignored. 表 1 summarizes

how to configure the reference in either UART or SPI modes.

表 1. Reference Configuration

INTERFACE

UART

SPI

PDVREF

1 (default)

0

REF_EN

REFERENCE MODE

External reference

Internal reference

External reference

0

1

0

SPI

1 (default)

0

SPI

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8.3.6 Clock Configuration

All of the devices in the DAC874xH family support a variety of clocking options in order to provide system

flexibility and reduce overall current consumption in HART applications. The clocking options include: an internal

oscillator (HART mode only), an external crystal oscillator, or an external CMOS clock. The selection of the

clocking scheme is controlled by the XEN, CLK_CFG1, and CLK_CFG0 pins as described in 表 2.

The internal oscillator takes approximately 50 ms to start oscillating from when it is enabled. During this time

period the device is unable to perform modulation or demodulation activities.

表 2. Clock Configuration Table

XEN

1

CLK_CFG1

CLK_CFG0

CLKO

No output

DESCRIPTION

MODE

0

1

0

1

0

1

0

1

0

1

3.6864-MHz CMOS clock connected at XTAL1

1.2288-MHz CMOS clock connected at XTAL1

Internal oscillator enabled

1

No output

1

0

No output

1

1.2288-MHz output

No output

Internal oscillator enabled, CLKO enabled

Crystal oscillator enabled

HART

0

1

3.6864-MHz output

1.8432-MHz output

1.2288-MHz output

No output

3.6864-MHz crystal oscillator, CLKO enabled

4-MHz CMOS clock connected at XTAL1

2-MHz CMOS clock connected at XTAL1

4-MHz crystal oscillator

0

1

0.5

FOUNDATION

Fieldbus and

PROFIBUS PA

1

No output

0

No output

0

4-MHz output

4-MHz crystal oscillator, CLKO enabled

8.3.7 Reset and Power-Down

The RST pin functions as both a hardware reset and a power-down. When the pin is brought low a reset is

issued, restoring all device components to their default state. While the pin is kept low, the device is in a power-

down state where the internal reference is disabled, the modulator and demodulator or encoder and decoder are

disabled, serial data output lines are high-impedance, MOD_OUT impedance is set to 70 kΩ, and the clock

output is disabled. If an external crystal oscillator is used, the crystal oscillator circuit remains active to reduce

start-up time when exiting the power-down state. Clock configuration pins remain active in power-down allowing

the crystal oscillator to be disabled if desired.

8.3.8 Full-Duplex Mode

In full-duplex mode the modulator and demodulator (HART mode) or encoder and decoder (FOUNDATION

Fieldbus or PROFIBUS PA mode) are simultaneously enabled. This allows a self-test feature to verify

functionality of the transmit and receive signal chains to improve system diagnostics.

8.3.9 I/O Selection

The DAC8740H implements a UART interface and the DAC8741H implements an SPI interface. The interface

mode is selected by the IF_SEL pin: a logic high on this pin sets the device to SPI mode and a logic low sets the

device to UART mode. An internal pull-down resistor is included to make sure the device powers up in a known

state, by default the pull-down sets the interface to UART mode. If changing I/O modes after power-up, a reset

command should be issued on RST.

8.3.10 Jabber Inhibitor

The DAC874xH implements a Jabber Inhibitor feature in FOUNDATION Fieldbus or PROFIBUS PA modes that

prevents the encoder from continuously transmitting data on the bus for longer than a programmed threshold

controlled by the UART or SPI interface. In SPI mode, this threshold is programmed by the PAFF_JABBER

register. In UART mode, this threshold is programmed by the four-byte initialization sequence before each

transmission. This information is described in further detail in the Device Functional Modes and Register Maps

sections.

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8.4 Device Functional Modes

8.4.1 UART Interfaced HART

When interfacing the HART modem via the UART interface, the device can be thought of as a simple UART-to-

HART or HART-to-UART direct feedthrough converter. The UART data is transmitted and received at 1200 baud,

which is matched to the HART FSK input and output signals.

The HART communication protocol is a half-duplex protocol which means that either the modulator or

demodulator is active, and never simultaneously enabled. The device arbitrates over which component of the

modem is active at all times based on activity on the HART bus. Bus activity is interfaced to the host controller

through the CD and RTS pins.

By default when RTS is high the demodulator is active and the modulator is inactive. When a valid carrier is

detected and data is being received by the modem, the CD pin is toggled high and binary UART data is provided

at the output. If a request to send is issued by toggling the RTS pin low while CD is high, the demodulator

remains at priority and any data provided at the UART input is ignored. When CD is low no valid carrier is

present and when RTS is brought low the modulator is activated and UART input data is latched into the

modulator and placed onto the HART bus.

8.4.2 UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA

FOUNDATION Fieldbus and PROFIBUS PA are half-duplex communication protocols where only the encoder or

decoder are active at any time and the DAC874xH arbitrates over which path is active. When interfacing the

FOUNDATION Fieldbus or PROFIBUS PA modem via the UART interface, data placed in the transmit FIFO is

automatically placed on the FF/PA bus until the FIFO is empty any time the device is not receiving data,

assuming correct data format.

When receiving data the decoder will expect a preamble byte(s) and a start delimiter byte. These bytes, as well

as the stop byte, will be stripped from the UART communication and only the first data byte will be transmitted to

start the data packet. The host controller must use a timer to detect the end of the packet. Each byte transmitted

on the UART will be at 57.6 kHz baud and byte spacing of 256 µs. If a new byte has not been started within 512

µs it can be assumed that the incoming packet has ended.

The device expects to see a four byte sequence to initiate transmission: 0xEA followed by 0x80-0x9F, where bits

4:3 of the second byte configure an interrupt threshold for the transmit FIFO level and bits 2:0 set the number of

preamble bytes to be transmitted. The third byte contains the information to configure the Jabber Inhibitor

followed by the final byte of 0xAE. To send inverted Manchester encoded data the first byte, 0xEA, is inverted to

0x15 and the first three bits of the second byte are inverted such that the range of values for the second byte are

from 0x60-0x7F. The functionality of bits 4:3 and 2:0 and the Jabber Inhibitor byte remain the same and the final

byte is inverted to 0x51. The details concerning this four byte sequence are explained in 表 3 to 表 5.

表 3. B3 and B2 UART Initialization Byte Sequence

B3

B2

D3

Mode

Noninverted

Inverted

D7:D0

D7

1

D6

0

D5

0

D4

D2

D1

D0

1

0

1

0

1

0

1

0

1

0

1

D2M_LEVEL

PRE_BYTES

0

1

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表 4. B1 and B0 UART Initialization Byte Sequence

B1

B0

Mode

Noninverted

Inverted

D7:D0

D7

1

D6

0

D5

1

D4

0

D3

1

D2

1

D1

1

D0

0

JABBER_TIMEOUT

0

1

0

1

0

1

表 5. B2 Bit-Field Definitions

CONTROL BITS

D2M_LEVEL

DESCRIPTION

0

1

0

1

0

1

Alarm on UART_RTS when transmit FIFO has less than 2 bytes loaded

Alarm on UART_RTS when transmit FIFO has less than 4 bytes loaded

Alarm on UART_RTS when transmit FIFO has less than 6 bytes loaded

Alarm on UART_RTS when transmit FIFO has less than 8 bytes loaded

PRE_BYTES

Number of preamble bytes is equivalent to the straight binary decimal value in this register plus one

The JABBER_TIMEOUT bits control the timeout period for the Jabber Inhibitor. If a value of 0x0 is programmed

the Jabber Inhibitor is disabled. Otherwise, the timer will be programmed in 2.048 ms increments such that the

timeout can be calculated as shown below. If the Jabber Inhibitor triggers the CD pin will be taken high. The CD

pin will be returned to logic low when the silence period of 3 seconds has ended.

TimeOut = JABBER_TIMEOUT × 2.048 ms

(1)

The encoder begins transmitting data after the following conditions are met: a valid four-byte transmission

initiation sequence has been sent to the device, the FIFO is not empty, and the device is not receiving data.

Transmission begins by sending the preamble byte or bytes, followed by a start delimiter. Then, the encoder

begins to remove data from the FIFO, and creates at least a five-byte lag of the encoder with respect to the

UART.

During transmission of a packet, the UART must take care to make sure that the FIFO does not become empty

before the packet is complete. The encoder transmits at a baud rate of 31.25 kHz or 256 µs per byte in the FIFO,

so the UART must keep up with this rate. The four-byte sequence that initiates a transmission includes setting a

transmit FIFO threshold in bits 4:3. When the FIFO level is less than or equal to this threshold, the UART_RTS

pin is taken high; this can be leveraged to make sure the FIFO is not prematurely empty. After the FIFO is

empty, a stop delimiter is placed on the bus, and a new packet can be initiated with a new four-byte transmission

initiation sequence.

The device expects a UART baud rate of 57.6 kHz. This baud rate is faster than the 31.25-kHz baud rate

specified by FOUNDATION Fieldbus and PROFIBUS PA; therefore, FIFO overflow is possible. To prevent FIFO

overflow, the UART_RTS pin FIFO threshold alarm can be leveraged by never adding more data to the FIFO

than the FIFO can contain, based on the programmed alarm threshold.

8.4.3 SPI Interfaced HART

When interfacing the HART modem via the SPI interface, the device uses transmit and receive FIFOs that are 9-

bits wide and 16 locations deep to buffer all HART data.

The HART communication protocol is half-duplex protocol which means that either the modulator or demodulator

is active, and never simultaneously enabled. The device arbitrates over which component of the modem is active

at all times based on activity on the HART bus. Bus activity is interfaced to the host controller through the IRQ

pin and MODEM STATUS register.

By default the demodulator is active and the modulator is inactive. When a valid carrier is detected and data is

being received by the modem, the CD bit (bit 1) in the MODEM STATUS register is set high. If the CD bit (bit 1)

in the MODEM IRQ MASK register is set to 0, this will also cause the IRQ pin to toggle as programmed in the

status CONTROL register. The IRQ pin may be programmed to be edge sensitive or level sensitive, the polarity

of the signal is also programmable. When the IRQ pin toggles, the MODEM STATUS register should be read to

determine the source of the interrupt. Receive data can be read from the RECEIVE FIFO by issuing an SPI read

command.

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Alternatively, the CD pin can be ignored by setting the CD bit (bit 1) in the MODEM IRQ MASK register to a 1. In

this mode the IRQ pin will not toggle when the CD bit in the MODEM STATUS register is a 1. Instead, a

RECEIVE FIFO read event can be triggered by the RECEIVE FIFO level threshold. This is achieved by

programming the FIFO LEVEL SET register (bits 7:4) to the desired threshold value from 1-15, if a full FIFO

(level 16 threshold) is desired the M2D FIFO FULL alarm can be used instead. If the M2D FIFO LEVEL bit (bit 7)

in the MODEM IRQ MASK register is set to 0, the IRQ pin will toggle and the MODEM STATUS register should

be read to determine the source of the interrupt. Receive data can then be read from the RECEIVE FIFO by

issuing an SPI read command.

If data is placed in the transmit FIFO while the demodulator is active and the CD bit is high, the data remains in

the FIFO until the modulator is activated. To request that the modulator is activated and the demodulator is

deactivated the RTS bit (bit 0) in the MODEM CONTROL register should be set high. When the modulator is

activated and the demodulator is deactivated the clear to send, or CTS, bit (bit 0) in the MODEM STATUS

register is set high. If the CTS bit (bit 0) in the MODEM IRQ MASK register is set to a 0 this will cause the IRQ

pin to toggle, indicating that transmit FIFO data will begin to be placed on the bus.

The level of the transmit FIFO may be monitored in order to avoid buffer overflow. This can be done either by

watching for a buffer full or buffer threshold event. To monitor by a FIFO level threshold the FIFO LEVEL SET

register (bits 3:0) can be programmed to the desired threshold value from 1-15. If the D2M FIFO LEVEL bit (bit

4) in the MODEM IRQ MASK register is set to a 0, this will cause the IRQ pin to toggle. Similarly an alarm can be

triggered based on the D2M FIFO FULL bit in the MODEM STATUS register.

8.4.4 SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA

FOUNDATION Fieldbus and PROFIBUS PA are half-duplex communication protocols, where only the encoder or

decoder are active at any time and the DAC874xH arbitrates over which path is active. When interfacing the

FOUNDATION Fieldbus or PROFIBUS PA encoder via SPI interface, data are placed in transmit and receive

FIFOs that are each 16-bytes deep to buffer all data.

When receiving data, the decoder expects a preamble byte(s) and a start delimiter byte, followed by the data

bytes for the packet, and concluded with a stop delimiter byte. All of these bytes are placed into the RECEIVE

FIFO where bits 7:0 represent the data, and bit 8 is used as a special bit to indicate the start of a packet, with

data 0x014D, the end of a packet, with data 0x0126, or a half-bit slip, with data 0x0100. If a half-bit slip occurs,

discard the packet. A timer is not necessary to detect the end of receiving a packet in SPI mode because the

stop delimiter is included in the RECEIVE FIFO data.

In order to prevent RECEIVE FIFO overflow, alarms are available to watch a threshold of the FIFO or when the

FIFO is full. If the FIFO is full it is possible for data to be lost. This is achieved by programming the FIFO LEVEL

SET register (bits 7:4) to the desired threshold value from 1-15, if a full FIFO (level 16 threshold) is desired the

M2D FIFO FULL alarm can be used instead. If the M2D FIFO LEVEL bit (bit 7) in the MODEM IRQ MASK

register is set to 0, the IRQ pin will toggle and the MODEM STATUS register should be read to determine the

source of the interrupt. Receive data can then be read from the RECEIVE FIFO by issuing an SPI read

command.

The encoder begins to send data by sending the preamble byte(s) followed by a start delimiter when the

TRANSMIT FIFO is not empty and the device is not receiving data. The number of preamble bytes used in the

packet is controlled by the PAFF PREAMBLE bits (bits14:12) in the MODEM CONTROL REGISTER. The

polarity of the Manchester encoded data can also be programmed by the PAFF POLARITY bit (bit 15) in the

MODEM CONTROL REGISTER. After transmitting the preamble byte(s) and start delimiter, the encoder begins

taking data from the TRANSMIT FIFO.

During transmission, the SPI controller must take care to make sure that the TRANSMIT FIFO does not become

empty before the packet is complete. When the TRANSMIT FIFO is empty a stop delimiter is placed on the bus.

The level of the transmit FIFO may be monitored in order to avoid buffer overflow. This monitoring can be done

either by watching for a buffer full or buffer threshold event. To monitor by a FIFO level threshold, program the

FIFO LEVEL SET register (bits 3:0) to the desired threshold value from 1-15. If the D2M FIFO LEVEL bit (bit 4)

in the MODEM IRQ MASK register is set to a 0, the IRQ pin toggles. Similarly, an alarm can be triggered based

on the D2M FIFO FULL bit in the MODEM STATUS register.

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The Jabber Inhibitor threshold is programmed by the PAFF_JABBER register (address 0x27). The 8-bit value

programmed in this register is used to calculate the threshold using 公式 2. When the timeout triggers, the

JAB_ON bit in the STATUS register is taken high, and transmission is blocked for the 3-second timeout period.

The JAB_OFF bit goes high when the timeout period has expired. Both JAB_ON and JAB_OFF bits trigger and

IRQ event, meaning the IRQ pin is triggered for both events.

TimeOut = JABBER_TIMEOUT × 2.048 ms

(2)

8.4.5 Digital Interface

8.4.5.1 UART

The behavior of the UART interface changes based on whether the device is operating in HART mode or in

FOUNDATION Fieldbus and PROFIBUS PA mode.

In HART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit or an 8O1 UART

character format. The transmit path of the device acts as a direct feedthrough of the UART input to the HART

FSK output, therefore the UART baud rate from the host controller must be 1200 Hz ±1% as required by the

HART standard. The receive path of the device will also operate at 1200 Hz ±1%.

In FOUNDATION Fieldbus and PROFIBUS PA mode the UART interface expects 1 start bit, 8 data bits, no parity

bit, and 1 stop bit or an 8N1 UART character format. In this mode the UART interfaces transmit and receive

FIFOs so the baud rate is not required to match the 31.25 kHz baud used by FOUNDATION Fieldbus and

PROFIBUS PA. In this mode the expected transmit and receive UART baud is 57.6 Hz ±2.5%.

8.4.5.1.1 UART Carrier Detect

The behavior of the carrier detect or CD pin changes depending on whether the device is in HART mode or

FOUNDATION Fieldbus and PROFIBUS PA mode.

In HART mode the pin operates as a carrier detect pin. When a valid carrier is detected and the modem is

receiving data the CD pin is taken high. When the CD pin is high, UART data sent to the device and the request

to send, or RTS, pin will be ignored until the carrier is no longer present.

In FOUNDATION Fieldbus and PROFIBUS PA the CD pin operates as a carrier detect pin when not in transmit

mode. When the CD pin is high, UART data sent to the device are ignored until the carrier is no longer present.

When in transmit mode the CD pin functions as an alarm indicator that the jabber inhibitor has triggered and

further UART transmission data are ignored. In general, if the CD pin is high, the host controller should not be

sending transmit data to the device.

8.4.5.2 SPI

The SPI interface can operate on SCLK speeds up to 12.5 MHz, but the frame-rate must be greater than 2442

ns in HART mode and 3000 ns in FOUNDATION Fieldbus and PROFIBUS PA mode. Frames must contain at

least 24-bits without CRC enabled and 32-bits with CRC enabled. The data within the frame are right justified,

meaning that upon the rising edge of CS the right-most, or last, 24-bits or 32-bits are evaluated as the input data

word. Two modes of SPI are supported by the interface: clock polarity 0 and clock phase 1, or clock polarity 1

and clock phase 0.

The SDO pin will output data on the rising edge of SCLK or the falling edge of CS. SDO will always provide

information from the previous frame, if the previous frame was a read then the output data will be the requested

data. If the previous write was a command or register write, that data will be repeated. This allows a method for

the user to verify what was written to the device. If CRC is enabled and write data is being repeated on SDO, the

CRC provided during the previous frame will be output – not a newly calculated CRC.

The SPI frame structure is shown in 表 6. The frame includes a read/write bit, followed by a 7-bit address, then

16-bit write data for a write frame or don’t care bits for a read frame. If CRC is enabled, an additional 8-bits are

placed at the end of the frame containing the CRC word.

表 6. SPI Frame Structure

R/W FRAME

Write Frame

Read Frame

D23

0

D22:16

D15:0

Write Data

X

7-Bit Address

1

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8.4.5.2.1 SPI Cyclic Redundancy Check

The SPI interface includes an optional CRC mode to enhance the reliability of the interface by blocking

erroneous commands sent to the device due to noise or other errors sources. When writing to or reading from

the device the last 8-bits in the frame contain the CRC word which is calculated based on the polynomial x⁸+ x²

+ x + 1. If a bad CRC word is included in a write-frame to the device, the frame will be ignored. When reading

from the device, the host controller should check the CRC word to validate the frame.

Read commands with a bad CRC value will output 0x80000000 and, in the case of a receive FIFO read, prevent

data from leaving the FIFO and subsequently being lost.

8.4.5.2.2 SPI Interrupt Request

SPI interfaced devices include an interrupt request, or IRQ, pin to communicate the occurrence of a variety of

events to the host controller. The behavior of the IRQ pin is controlled by the CONTROL register and MODEM

IRQ MASK register.

The CONTROL register allows the host controller to configure the IRQ pin as level sensitive or edge sensitive via

the IRQ LEVEL bit (bit 2). For both level sensitive and edge sensitive modes, the polarity of the IRQ pin can be

set via the IRQ POLARITY bit (bit 3) in the CONTROL register.

The MODEM IRQ MASK register allows the controller to decide which events are able to trigger the IRQ pin to

toggle. If a logic 0 is written to the respective bit, that event is allowed to toggle the IRQ pin. If a logic 1 is written

to the respective bit, the event is masked from the IRQ pin.

When an event occurs the IRQ pin signal, in the case of level-sensitive configurations, is latched and the IRQ pin

voltage stays at logic high until the status has been reset, or cleared, by reading the contents of the

MODEM_STATUS register. In the case of edge-sensitive configurations a pulse is generated any time a new

event is detected.

8.5 Register Maps

Table 7 lists the memory-mapped registers for the DAC8741H. All register offset addresses not listed in Table 7

should be considered as reserved locations and the register contents should not be modified.

Table 7. DAC8741H Registers

Offset

2h

Acronym

Register Name

Section

Go

CONTROL

CONTROL register

7h

RESET

RESET register

Go

20h

21h

22h

23h

24h

25h

27h

MODEM_STATUS

MODEM_IRQ_MASK

MODEM_CONTROL

FIFO_D2M

MODEM STATUS register

MODEM IRQ MASK register

MODEM CONTROL register

FIFO D2M register

Go

FIFO_M2D

FIFO M2D register

Go

FIFO_LEVEL_SET

PAFF_JABBER

FIFO LEVEL SET register

PAFF JABBER register

Go

Complex bit access types are encoded to fit into small table cells. Table 8 shows the codes that are used for

access types in this section.

Table 8. DAC8741H Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

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8.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]

This register controls the SPI watchdog timer, internal reference, CRC mode, IRQ pin behavior, and SDO pin

behavior.

CONTROL is shown in Figure 23 and described in Table 9.

Return to Summary Table.

Figure 23. CONTROL Register

15

14

13

12

11

10

9

8

WDTO

R/W

WDT

R/W

RESERVED

R

7

RESERVED

R

6

5

RESERVED

R

4

3

2

1

0

PDVREF

R/W

CRC_EN

R/W

IRQ_POL

R/W

IRQ_LEVEL

R/W

SDO_Z

R/W

SDO_B

R/W

Table 9. CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

SPI Watchdog Timer (based on 3.6864-MHz clock)

15-13

WDTO

R/W

100

D15

0

D14

0

D13

0

Timeout Period

50 ms

100 ms

0

1

0

1

0

500 ms

0

1

1 second

1

0

2 seconds (default)

3 seconds

4 seconds

5 seconds

1

0

1

0

1

12

WDT

R/W

0

0 = SPI Watchdog Timer Disabled (default)

1 = SPI Watchdog Timer Enabled

11-7

6

RESERVED

PDVREF

R

00000

1

Reserved

R/W

This bit is only functional if the hardware reference enabled is

enabled.

0 = Internal reference is powered down

1 = Internal reference is powered up (default)

5

4

RESERVED

CRC_EN

R

0

Reserved

R/W

0 = No CRC (default)

1 = CRC is enabled

3

2

1

0

IRQ_POL

IRQ_LEVEL

SDO_Z

R/W

0

1

0

0 = IRQ is active low (default)

1 = IRQ is active high

0 = IRQ creates a pulse for edge sensitivity (default)

1 = IRQ asserts to a level until MODEM STATUS is read

0 = SDO will be driven during writes and read requests

1 = SDO will be HiZ during writes requests (default)

SDO_B

0 = SDO will remain filled from last frame (default)

1 = SDO will clear with the beginning of each frame

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8.5.2 RESET Register (Offset = 7h) [reset = 0x0000]

Writing 0x0001 to this register will reset all registers to their default values and the FIFOs will be emptied.

RESET is shown in Figure 24 and described in Table 10.

Return to Summary Table.

Figure 24. RESET Register

15

7

14

6

13

5

12

11

3

10

2

9

1

8

RESERVED

R

4

RESERVED

R

0

RST

R/W

Table 10. RESET Register Field Descriptions

Bit

Field

Type

Reset

Description

15-1

RESERVED

R/W

000000000 Reserved

000000

0

RST

W

0

Writing a 1 to this bit triggers a software reset.

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8.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]

The modem status register is a read/write register. When an event occurs, the corresponding bit to indicate that

event is set to a logic 1 in this register. The status bits are sticky, meaning they are not cleared unless a 1 is

written to the corresponding bit position, except for carrier detect, or CD, which responds based on the

presences of a carrier, the FIFO level registers, which respond based on the conditions of the FIFOs, and

JAB_OFF and JAB_ON which represent the current status of the jabber inibhior. CTS will assert after RTS is set

and no carrier is present if not operating in full-duplex mode.

MODEM_STATUS is shown in Figure 25 and described in Table 11.

Return to Summary Table.

Figure 25. MODEM_STATUS Register

15

14

13

12

11

10

9

8

RST

R/W

JAB_OFF

R/W

JAB_ON

R/W

GAP

R/W

FRAME

R/W

PARITY

R/W

WDT

R/W

CRC

R/W

7

6

5

FIFO_M2D EMPTY

R/W

4

3

2

FIFO_D2M EMPTY

R/W

1

CD

R

0

CTS

R

FIFO_M2D LEVEL

R/W

FIFO_M2D FULL

R/W

FIFO_D2M LEVEL

R/W

FIFO_D2M FULL

R/W

Table 11. MODEM_STATUS Register Field Descriptions

Bit

15

14

Field

RST

Type

R/W

Reset

Description

0

A reset has occurred

JAB_OFF

This bit goes high when the jabber inhibitor timeout period has

expired

13

12

11

10

9

JAB_ON

R/W

R

0

This bit goes high when the jabber inhibitor has been triggered

A gap error in HART mode

GAP

FRAME

A frame error in HART mode or a 1/2-bit slip in FF/PA mode

A Parity error in HART mode

PARITY

WDT

The watchdog timer has expired

8

CRC

An incorrect CRC word was provided in a read or write command

The receive FIFO is at the programmed level

The receive FIFO is full

7

FIFO_M2D_LEVEL

FIFO_M2D_FULL

FIFO_M2D_EMPTY

FIFO_D2M_LEVEL

FIFO_D2M_FULL

FIFO_D2M_EMPTY

CD

6

5

The receive FIFO is empty

4

The transmit FIFO is at the programmed level

The transmit FIFO is full

3

2

The transmit FIFO is empty

1

In HART mode, a valid carrier has been detected

0

CTS

R

In HART mode, the modem is cleared to send data and the

modulator is active

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8.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]

This register controls which MODEM STATUS events are allowed to trigger an interrupt on the IRQ pin. A 0 in

the respective bit position allows the interrupt event to toggle the IRQ pin. A 1 in the respective bit position blocks

the interrupt event from toggling the IRQ pin, but the event can still be detected by reading the MODEM STATUS

register.

MODEM_IRQ_MASK is shown in Figure 26 and described in Table 12.

Return to Summary Table.

Figure 26. MODEM_IRQ_MASK Register

15

RESERVED

R

14

13

12

11

10

9

8

JAB_OFF

R/W

JAB_ON

R/W

GAP

R/W

FRAME

R/W

PARITY

R/W

WDT

R/W

CRC

R/W

7

6

5

FIFO_M2D EMPTY

R/W

4

3

2

FIFO_D2M EMPTY

R/W

1

0

FIFO_M2D LEVEL

R/W

FIFO_M2D FULL

R/W

FIFO_D2M LEVEL

R/W

FIFO_D2M FULL

R/W

CD

R/W

CTS

R/W

Table 12. MODEM_IRQ_MASK Register Field Descriptions

Bit

15

14

Field

Type

R/W

Reset

Description

RESERVED

JAB_OFF

0

Reserved

Writing a 1 to this bit blocks the JAB_OFF event from triggering the

IRQ pin

13

12

11

10

9

JAB_ON

R/W

0

1

0

1

Writing a 1 to this bit blocks the JAB_ON event from triggering the

IRQ pin

GAP

Writing a 1 to this bit blocks the GAP event from triggering the IRQ

FRAME

Writing a 1 to this bit blocks the FRAME event from triggering the

IRQ pin

PARITY

Writing a 1 to this bit blocks the PARITY event from triggering the

IRQ pin

WDT

Writing a 1 to this bit blocks the WDT event from triggering the IRQ

8

CRC

Writing a 1 to this bit blocks the CRC event from triggering the IRQ

7

FIFO_M2D_LEVEL

FIFO_M2D_FULL

FIFO_M2D_EMPTY

FIFO_D2M_LEVEL

FIFO_D2M_FULL

FIFO_D2M_EMPTY

Writing a 1 to this bit blocks the FIFO_M2D_LEVEL event from

triggering the IRQ pin

6

Writing a 1 to this bit blocks the FIFO_M2D_FULL event from

triggering the IRQ pin

5

Writing a 1 to this bit blocks the FIFO_M2D_EMPTY event from

triggering the IRQ pin

4

Writing a 1 to this bit blocks the FIFO_D2M_LEVEL event from

triggering the IRQ pin

3

Writing a 1 to this bit blocks the FIFO_D2M_FULL event from

triggering the IRQ pin

2

Writing a 1 to this bit blocks the FIFO_D2M_EMPTY event from

triggering the IRQ pin

1

0

CD

R/W

0

Writing a 1 to this bit blocks the CD event from triggering the IRQ pin

CTS

Writing a 1 to this bit blocks the CTS event from triggering the IRQ

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8.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]

This register controls various modem features including: FF/PA Manchester data polarity, number of FF/PA

preamble bits, analog output amplitude, modem enable, duplex mode, and request to send.

MODEM_CONTROL is shown in Figure 27 and described in Table 13.

Return to Summary Table.

Figure 27. MODEM_CONTROL Register

15

FFPA_POL

R/W

14

6

13

FFPA_PREAMBLE

R/W

12

11

10

RESERVED

R

9

8

TX_AMP

R/W

7

5

4

3

2

1

RESERVED

R

0

TX_AMP

R/W

MOD_EN

R/W

DUP_EN

R/W

RTS

R/W

Table 13. MODEM_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

15

FFPA_POL

R/W

0

Sets the transmitted polarity of the Manchester encoded data

0 = Logical 1 is transmitted as a transition from high-to-low (default)

1 = Logical 1 is transmitted as a transition from low-to-high

14-12

FFPA_PREAMBLE

R/W

0

Number of preamble bytes sent is the value programmed in this

register plus 1

11-9

8-4

RESERVED

TX_AMP

R

0

Reserved

R/W

00100

Unsigned binary value that controls the amplitude (HART mode only)

of the transmitted waveform in 25-mV_PPsteps. Default value 00100

for 500-mV_PPoutput amplitude. Amplitude may vary from 400 mV_PP

to 800 mV_PP

.

3

2

MOD_EN

DUP_EN

R/W

1

0

0 = Disables TX/RX of the modem

1 = Enables TX/RX of the modem (default)

0 – TX FIFO is not connected to RX FIFO (default)

1 = Connects TX FIFO to RX FIFO

1

0

RESERVED

RTS

R

0

Reserved

R/W

0 = No active request to send in HART mode (default)

1 = Active request to send in HART mode

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8.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]

This register interfaces the FIFO that transmits data from the digital interface to the modem.

FIFO_D2M is shown in Figure 28 and described in Table 14.

Return to Summary Table.

Figure 28. FIFO_D2M Register

15

7

14

6

13

5

12

11

LEVEL_FLAG

R

10

FULL_FLAG

R

9

8

PARITY_BIT

W

FIFO_LEVEL

R

EMPTY_FLAG

R

4

3

2

1

0

DATA

W

Table 14. FIFO_D2M Register Field Descriptions

Bit

Field

Type

R

Reset

Description

Reads back the current level of the FIFO, read only

15-12

11

10

9

FIFO_LEVEL

LEVEL_FLAG

FULL_FLAG

EMPTY_FLAG

PARITY_BIT

DATA

0

1

0

R

Indicates the programmed level has been reached, read only

Indicates the FIFO is full, read only

R

Indicates the FIFO is empty, read only

8

W

Odd parity for 8-bit data read on bus, write only

Data transmitted from the digital interface to the modem, write only

7-0

8.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]

This register interfaces the FIFO that receives data from the modem to the digital interface. This register is read

only

FIFO_M2D is shown in Figure 29 and described in Table 15.

Return to Summary Table.

Figure 29. FIFO_M2D Register

15

7

14

6

13

5

12

11

LEVEL_FLAG

R

10

FULL_FLAG

R

9

8

PARITY_BIT

R

FIFO_LEVEL

R

EMPTY_FLAG

R

4

3

2

1

0

DATA

R

Table 15. FIFO_M2D Register Field Descriptions

Bit

Field

Type

R

Reset

Description

Reads back the current level of the FIFO, read only

15-12

11

10

9

FIFO_LEVEL

LEVEL_FLAG

FULL_FLAG

EMPTY_FLAG

PARITY_BIT

DATA

0

1

0

R

Indicates the programmed level has been reached, read only

Indicates the FIFO is full, read only

R

Indicates the FIFO is empty, read only

8

R

Odd parity for 8-bit data read on bus, read only

Data transmitted from the modem to the digital interface, read only

7-0

R

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8.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]

This register programs the alarm threshold for both transmit and receive FIFOs. Each bit field allows for the FIFO

alarm threshold to be programmed to integer values from 1-15.

FIFO_LEVEL_SET is shown in Figure 30 and described in Table 16.

Return to Summary Table.

Figure 30. FIFO_LEVEL_SET Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R

4

3

M2D_LEVEL

R/W

D2M_LEVEL

R/W

Table 16. FIFO_LEVEL_SET Register Field Descriptions

Bit

Field

Type

R

Reset

Description

15-8

7-4

RESERVED

M2D_LEVEL

00000000

0000

Reserved

R/W

The binary value in this register sets the modulator FIFO alarm

threshold

3-0

D2M_LEVEL

R/W

0000

The binary value in this register sets the demodulator FIFO alarm

threshold

8.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]

This register controls the jabber inhibitor time-out behavior. The time-out can be calculated using the equation in

Table 17, with PAFF_JABBER in decimal format.

PAFF_JABBER is shown in Figure 31 and described in Table 17.

Return to Summary Table.

Figure 31. PAFF_JABBER Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R

4

3

PAFF_JABBER

R/W

Table 17. PAFF_JABBER Register Field Descriptions

Bit

Field

Type

R

Reset

Description

15-8

7-0

RESERVED

00000000

Reserved

PAFF_JABBER

R/W

TimeOut = JABBER_TIMEOUT * 2.048 ms

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DAC874xH family of devices integrates modem functionality for several largely used Industrial protocols:

Highway Addressable Remote Transducer (HART), FOUNDATION Fieldbus (FF), and PROFIBUS (PA). The

different modes are set via the CLK_CFGx pins of the device that allow the device to either enter HART or PAFF

mode. In HART mode, a 1200-Hz/2200-Hz HART FSK Signal is modulated and demodulated, while the PAFF

mode communicates thorugh a 31.25 Kbit/s Manchester coded/encoded signal. The small package sizes, wide

temperature range and low quiescent current make this device an excellent choice for applications in industrial

process control and automation.

9.1.1 Design Recommendations

Local power supply decoupling is recommended by placing 10-µF capacitors on the IOVDD and AVDD supply

lines, and 0.1-µF capacitors close to the DAC874XH supply pins. Ceramic capacitor types such as C0G or X7R

are recommended for its optimal performance across temperature, and very low dissipation factor. DC bias

characteristics of the capacitors should also be considered when selecting passive components, such as the

voltage rating and equivalent series resistance (ESR).

9.1.2 Selecting the Crystal or Resonator

Both communication modes, HART and PAFF, require different clocking frequencies for correct operation:

HART – 1.2288 MHz or 3.686 MHz, PAFF – 4 MHz. In addition to selecting the communication mode, the

CLK_CFGx and XEN pins also select whether an internal oscillator or external clock source is configured for

device operation. The configuration table is explained in 表 2. Accuracy over the applications temperature range

should be considered when selecting the external crystal or resonator. Furthermore, crystals with a low drift

specification over the desired application temperature range should also be selected when using the DAC874xH

devices in HART, FOUNDATION Fieldbus, and PROFIBUS PA applications as communication timing is critical.

In order to reduce quiescent current consumption, the XTAL nets should be optimized during layout to reduce

any length that may increase net capacitance. This increase in capacitance is directly proportion to current

consumption.

9.1.3 Included Functions and Filter Selection

As a highly integrated device, the DAC874xH not only includes the modulation and demodulation capabilities for

the previously described industrial protocols, but also includes an internal reference, and integrated receive

bandpass filter, with other aforementioned functions. In HART mode, an internal amplifier provides high output

drive capability, and can drive a wide range of purely capacitive loads, ranging from 5 nF to 22 nF. Load

conditions within this range maintain output stability. Two different filter configurations, external and internal, are

achievable through the BPF_EN digital input -- logic high on this pin enables the internal bandpass filter. The

external filter configuration is shown in 图 32. The example provided displays the DAC874XH device configured

with an external reference and external bandpass filter.

31

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

Application Information (接下页)

HART_OUT

4700pF

0.022µF

DAC8740H

14

AGND

MOD_OUT

EXT REF

16

MOD_IN

17

MOD_INF

1

XEN

X1

IOVDD

1.00M

1.50M

21

20

13

HART_IN

150k

300pF

X2

150pF

AGND

REG_CAP

19

12

22

AGND

DGND

1µF

25

AGND

PAD

AGND

图 32. HART Mode: DAC874XH Passive Selection For External Bandpass Filter and External Reference

The second configuration, which can reduce costs associated with PCB development and BOM component

counts, additionally aids in the optimization of board space. This optimization gives the user flexibility into

achieving industrial applications with smaller form factor sizes. The internal filter configuration, with correct

MOD_IN, MOD_INF, and MOD_OUT connections, is shown in 图 33.

HART_OUT

4700pF

0.022µF

DAC8740H

14

AGND

MOD_OUT

16

HART_IN

MOD_IN

MOD_INF

17

2200pF

680pF

1

XEN

X1

IOVDD

21

20

13

X2

AGND

REF

REG_CAP

19

12

22

AGND

DGND

1µF

25

AGND

PAD

AGND

图 33. HART Mode: DAC874xH Passive Selection For Internal Filter

32

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

9.2.1 Design Requirements

The application presented in 图 34 represents a loop-powered, 2-wire, smart 4-mA to 20-mA transmitter that

commonly resides in factory control and industrial automation sectors. In this application, the DAC8740H enables

a smart interface by providing HART communication, which is responsible for modulating two-way digital

information that encapsulate a wide variety of data, including device/sensor information, calibration data, and

system diagnostic information. This circuit has been successfully HART certification and registered with the

FieldComm Group.

9.2.2 Detailed Design Procedure

9.2.2.1 DAC8740H HART Modem

In this design, the DAC8740H internal reference and band-pass filter was chosen to optimize board area,

consequently reducing form factor and cost. X7R, 10% accurate, bypass capacitances of 1-µF and 0.1-µF values

were chosen for the reference and supplies, respectively.

The DAC8740H device interfaces with the MSP430FR5969, or other similar host controller, through a standard

UART interface. The DAC8740H digital pins connected through this interface include UART_RTS, UART_OUT

(TX), UART_IN (RX), and CD.

The remaining portion of the schematic includes other TI devices that aid in the realization of a highly accurate 4-

mA to 20-mA, 2-wire transmitter. This combination of circuitry is an excellent choice for remote signal

conditioning of a wide variety of sensors and transducers, including thermocouples, RTDs, thermistors, and strain

gauge bridges.

The two-wire transmitter is powered from an external DC power supply that is connected via the two BUS supply

lines. The transmitter communicates by sourcing a 4-mA to 20-mA current through the connected bus, and back

to the central host, which is typically a PLC analog input module. This expressed range of 4 mA to 20 mA is

typically employed to adhere to industry standard, and makes sure that the transmitter receives a minimum of 4

mA for correct powered operation.

Vref

R2

100k

V_REF/(R₂+R₃)

V_HART/(R₄)

R3

2.4k

R4

49.9k

V+

V_DAC/(R₅+R₆)

R5

R6

14.3k

R7

11.3k

DAC8830

10.0

A1

A2

C13

0.012

µ F

R8

60.4

I_LOOP

R9

1.80k

I_q

R10

10.0

1000pF

I₁

I₂

C20

R11

180

R12

10.0

V-

图 35. Simplified Schematic of the 2-Wire Current Loop

34

DAC8740H, DAC8741H

www.ti.com.cn

ZHCSH77D –JUNE 2017–REVISED MAY 2019

9.2.2.2 2-Wire Current Loop

The A2 op amp employs negative feedback to drive the potential at both input nodes, V+ and V–, to the same

voltage. This establishes the set of KCL equations (1) – assuming no HART communication, V_HART= 0 V.

I1 = V_DAC/ (25.6 kΩ) + V_REF/ (102.4 kΩ)

(3)

A2 also drives the base of the NPN BJT, Q1, which enables current to flow from its collector through emitter pins

and through the R8 resistor, while maintaining an equivalent potential drop from its input nodes to the net

represented by TP4. This configuration drives the combined voltage drop across R9 and R11 to the same

voltage drop across R10 and R12.

Using this relationship, along with current 公式 3 and 公式 4, I_OUTis calculated as follows:

I2 = I1 * (1.80 kΩ + 180) / (10 + 10) = I1 * (1.980 kΩ / 20) = I1 * 99

(4)

(5)

I_OUT= I1 + I2 = [V_DAC/ (25.6 kΩ) + V_REF/ (102.4 kΩ)] + I1 * 99 = [V_DAC/ (25.6 kΩ) + V_REF/ (102.4 kΩ)] * (100)

For a VREF value of 4.096 V, the zero-scale portion of the transfer function, [V_REF/ (102.4 kΩ)] * (100),

translates to 4 mA, while the span, [V_DAC/ (25.6 kΩ)] * 100, encompasses 16 mA. This final product is a system

capable of sourcing 4 mA to 20 mA, which is dependent on DAC output voltage. The value of R4 is responsible

for converting the 500-mV_PPHART signal into a 1-mA

of the 4-mA to 20-mA analog current signal.

frequency shift keyed (FSK) signal that resides on top

PP

9.2.2.3 Regulator

The primary supply for the transmitter is the TPS7A4101 device, which is a 50-V input, 50-mA Single output low-

dropout linear regulator with very low quiescent current, 25 µA. The device supplies a well-regulated voltage rail

(1% accuracy), operating within an extended temperature range of –40°C to +125°C, and also withstands and

maintains regulation during very high and fast voltage transients. In this design the LDO converts the external

supply to a 5-V rail that is used by the DAC8830, LM4132 and OPA333/OPA335. The 200-Ω resistor that

separates the loop supply from the LDO acts as a current limiting resistor at startup and additionally improves the

overall receiver impedance of the design.

Generally, series references are preferred over shunt references because of their lower power consumption; in

this case the LM4132 exhibits a maximum of 60-µA quiescent current. Moreover, the device has an initial

accuracy of 0.05% with a specified temperature coefficient of 10 ppm/°C or less, and is capable of operating with

these metrics at an extended temperature range of –40°C to +125°C.

In order to generate a 3.3-V supply for the DAC8740H, the TPS7B6933-Q1, a low-dropout linear regulator with

low quiescent current, is incorporated into the design. This LDO is capable of operating over a wide temperature

range of –40°C to 125°C, while exhibiting a maximum quiescent value of 25 µA over this temperature range.

9.2.2.4 DAC

After sufficient bypass, this precision reference voltage is applied to the VREF pin of the DAC8830 device. An

accurate reference along with an accurate DAC are largely responsible for the overall accuracy of the current

loop, as any accuracy errors associated with the DAC will propagate through the rest of the signal chain and

decrease the accuracy of the solution. In this case, the DAC8830, a 16-bit voltage-output DAC with excellent

linearity (1 LSB INL), low glitch, low noise, and fast settling was chosen to set the base line performance of the

design.

9.2.2.5 Amplifiers

Next, the voltage output is buffered with the OPA333 CMOS operation amplifier, which features near-zero drift

over time and temperature, low quiescent current (17 µA), and single supply operation with rail-to-rail output that

swings within 50 mV of the supply rail.

As with the OPA333, the OPA335 was chosen due to its excellent DC accuracy specifications. These parameters

include low input bias current, low offset voltage, and high CMRR/PSRR. In addition to these DC specifications,

the OPA335 features an operating bandwidth of up to 2 MHz, which provides ample margin for HART

communication.

35

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

9.2.2.6 Diodes

For transient voltage protection, a 40-V bidirectional transient voltage suppressor (TVS) diode is placed across

the BUS lines of the design. Certain criteria should be considered when making this diode selection, such as the

diode’s working voltage, breakdown voltage, leakage current and power rating. In addition to these parameters,

leakage current should also be factored into the design as it will impact the accuracy of the analog current loop.

2-wire polarity protection is also employed by using the DSRHD10 as a diode bridge rectifier. The placement of

this component makes sure that the current loop will always correctly operate regardless of the arrangement of

input connections. As with other elements, consider the leakage and biasing voltages because these voltages

affect system accuracy and compliance voltage.

9.2.2.7 Passives

Among the passives included in the design, the gain setting resistors should be chosen to exhibit tight tolerances

in order to achieve high accuracy. These resistors -- R4, R5, R6, R9, R11, R10, and R12 -- are primarily

responsible for setting the gain of the current loop, along with primary path of the output current flow. Since the

biased transistor, Q1, is responsible for sourcing most of the output current, components in the path of this

current flow should be chosen with appropriate power ratings. In this case R8 is a 0.25-W resistor.

9.2.3 Application Curves

Five hundred data points were taken on five different boards, producing the 4-mA to 20-mA transfer function

below in 图 36. The total unadjusted error (TUE) of the transmitters is displayed in 图 37.

图 36. 4-mA to 20-mA Transfer Function

图 37. Total Unadjusted Error Graph of Application Circuit

36

DAC8740H, DAC8741H

www.ti.com.cn

ZHCSH77D –JUNE 2017–REVISED MAY 2019

10 Power Supply Recommendations

The DAC874xH can operate with analog supplies from 2.7 V to 5.5 V and digital supplies from 1.71 V to 5.5 V,

enabling interfacing host controller platforms with low voltage digital logic. For applications that are particularly

focused on reducing power dissipation in the modem, use the lowest supply voltage available for both analog

and digital supplies.

11 Layout

11.1 Layout Guidelines

Precision designs require careful layout, the list below provides some insight into good layout practices.

•

Bypass all power-supply pins to ground with a low ESR ceramic bypass capacitor. The typical recommended

bypass capacitance is 0.1 to 1 µF ceramic with a X7R or NP0 dielectric.

Place power supply and reference bypass capacitors close to the terminals to minimize inductance and

optimize performance.

A high-quality ceramic type NP0 or X7R is recommended for its optimal performance across temperature, and

very low dissipation factor.

The digital and analog sections should have proper placement with respect to the digital and analog

components. The separation of analog and digital circuitry allows for better design and practice as it allows

less coupling into neighboring blocks, and minimizes the interaction between analog and digital return

currents.

11.2 Layout Example

Bypass

Capacitor

12

6

1

18

24

Bypass

Capacitor

图 38. DAC8740H Basic Layout Example

37

DAC8740H, DAC8741H

ZHCSH77D –JUNE 2017–REVISED MAY 2019

www.ti.com.cn

Layout Example (接下页)

图 39. 2-Wire Transmitter With DAC8740H HART Modem Layout - Top Layer

图 40. 2-Wire Transmitter With DAC8740H HART Modem Layout - Bottom Layer

38

DAC8740H, DAC8741H

www.ti.com.cn

ZHCSH77D –JUNE 2017–REVISED MAY 2019

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

德州仪器 (TI)，《DAC8742H 评估模块用户指南》（适用于 DAC8740H 和 DAC8741H）

12.2 相关链接

表 18 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品的快速

链接。

表 18. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

DAC8740H

DAC8741H

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 商标

E2E is a trademark of Texas Instruments.

FOUNDATION 现场总线 is a trademark of FieldComm Group.

HART is a registered trademark of FieldComm Group.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

39

GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

RGE0024F

VQFN - 1 mm max height

S

C

A

L

E

3

.

3

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

0.5

0.3

4.1

3.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

1 MAX

SEATING PLANE

0.08

0.05

0.00

2.8 0.1

2X 2.5

(0.2) TYP

12

7

EXPOSED

THERMAL PAD

20X 0.5

6

13

2X

25

2.5

1

SEE TERMINAL

DETAIL

18

0.30

24X

0.18

0.1

24

19

PIN 1 ID

(OPTIONAL)

C A

B

0.05

0.5

0.3

24X

4222437/A 12/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

4. Reference JEDEC registration MO-220.

www.ti.com

EXAMPLE BOARD LAYOUT

RGE0024F

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.8)

SYMM

24

19

24X (0.6)

1

18

24X (0.24)

(1.15)

TYP

25

SYMM

(3.8)

20X (0.5)

6

13

(

0.2) TYP

VIA

7

12

(R0.05)

ALL PAD CORNERS

(3.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222437/A 12/2015

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

6. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations

are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

RGE0024F

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.23)

(0.715) TYP

19

(R0.05) TYP

24

24X (0.6)

25

1

18

24X (0.24)

(0.715) TYP

SYMM

20X (0.5)

(3.8)

13

6

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

77% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4222437/A 12/2015

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC8741HRGET
厂家：	TEXAS INSTRUMENTS
描述：	符合 HART®、FOUNDATION Fieldbus™ 和 PROFIBUS PA 标准且具有 SPI 接口的调制解调器 \| RGE \| 24 \| -55 to 125 调制解调器
文件：	总48页 (文件大小：2812K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC8741HRGET [TI]

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