DAC8830IBD [TI]
16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters; 16位，超低功耗，电压输出数字 - 模拟转换器
| 型号： | DAC8830IBD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters |
| 文件： | 总34页 (文件大小：1284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC8831
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®
SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
16-Bit, Ultra-Low Power, Voltage-Output
Digital-to-Analog Converters
1
FEATURES
DESCRIPTION
234
•
16-Bit Resolution
The DAC8830 and DAC8831 are single, 16-bit,
serial-input, voltage-output digital-to-analog
•
•
•
•
•
•
•
•
2.7 V to 5.5 V Single-Supply Operation
Very Low Power: 15 μW for 3 V Power
High Accuracy, INL: 1 LSB
Low Noise: 10 nV/√Hz
converters (DACs) operating from a single 3 V to 5 V
power supply. These converters provide excellent
linearity (1 LSB INL), low glitch, low noise, and fast
settling (1.0 μS to 1/2 LSB of full-scale output) over
the specified temperature range of –40°C to +85°C.
The output is unbuffered, which reduces the power
consumption and the error introduced by the buffer.
Fast Settling: 1.0 μS
Fast SPI™ Interface, up to 50 MHz
Reset to Zero-Code
These parts feature a standard high-speed (clock up
to 50 MHz), 3 V or 5 V SPI serial interface to
communicate with a DSP or microprocessor.
Schmitt-Trigger Inputs for Direct Optocoupler
Interface
•
Industry-Standard Pin Configuration
The DAC8830 output is 0 V to VREF. However, the
DAC8831 provides bipolar output (±VREF
working with an external buffer. The DAC8830 and
DAC8831 are both reset to zero code after power up.
) when
APPLICATIONS
•
•
•
•
•
Portable Equipment
For optimum performance,
a
set of Kelvin
Automatic Test Equipment
Industrial Process Control
Data Acquisition Systems
Optical Networking
connections to external reference and analog ground
input are provided on the DAC8831.
The DAC8830 is available in an SO-8 package, and
the DAC8831 in an SO-14 package. Both have
industry standard pinouts (see Table 3, the
cross-reference table in the Application Information
section for details). The DAC8831 is also available in
a QFN-14 package.
DAC8830
DAC8831
Functional Block Diagram
Functional Block Diagram
VDD
VDD
−
VREF
−
F
S
VREF
RINV RFB
RFB
INV
VOUT
DAC
VREF
CS
+V
LDAC
VO
−
+
VOUT
DAC
AGND
CS
SCLK
SDI
−
V
OPA277
OPA704
OPA727
SCLK
SDI
Input
Register
AGNDF
AGNDS
DAC Latch
Input
Register
DAC Latch
DAC8830
DAC8831
DGND
DGND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
DAC8830
DAC8831
www.ti.com
SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
MINIMUM
RELATIVE
ACCURACY
(LSB)
POWER-
ON
RESET
VALUE
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
PACKAGE PACKAGE-
PACKAGE
DESIGNATOR
ORDERING
NUMBER
PRODUCT
MARKING
LEAD
DAC8830ID
DAC8830IDR
Tubes, 75
DAC8830ID
±4
±2
±1
±4
±2
±1
±4
±2
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8830I
SO-8
D
D
Tape and Reel, 2500
Tubes, 75
DAC8830IBD
DAC8830IBD
DAC8830ICD
DAC8831ID
8830I
8830I
8831I
8831I
8831I
8831I
8831I
8831I
SO-8
SO-8
DAC8830IBDR
DAC8830ICD
Tape and Reel, 2500
Tubes, 75
D
DAC8830ICDR
DAC8831ID
Tape and Reel, 2500
Tube, 50
SO-14
SO-14
SO-14
QFN-14
QFN-14
QFN-14
D
DAC8831IDR
Tape and Reel, 2500
Tube, 50
DAC8831IBD
DAC8831IBD
DAC8831ICD
DAC8831IRGY
DAC8831IBRGY
DAC8831ICRGY
D
DAC8831IBDR
DAC8831ICD
Tape and Reel, 2500
Tube, 50
D
DAC8831ICDR
DAC8831IRGYT
DAC8831IRGYR
DAC8831IBRGYT
DAC8831IBRGYR
DAC8831ICRGYT
DAC8831ICRGYR
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 1000
Tape and Reel, 250
Tape and Reel, 1000
Tape and Reel, 250
Tape and Reel, 1000
RGY
RGY
RGY
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)(1)
DAC8830, DAC8831
–0.3 to +7
UNIT
V
VDD to AGND
Digital input voltage to DGND
VOUT to AGND
–0.3 to +VDD + 0.3
–0.3 to +VDD + 0.3
–0.3 to +0.3
–40 to +85
–65 to +150
+150
V
V
AGND, AGNDF, AGNDS to DGND
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
Power dissipation
V
°C
°C
°C
(TJ max - TA) / θJA
54.9
W
QFN-14
SO-8
°C/W
°C/W
°C/W
Thermal impedance, θJA
136.9
SO-14
66.6
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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DAC8831
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SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VDD = +3 V or VDD = +5 V, VREF = +2.5 V unless otherwise noted.
DAC8830, DAC8831
TYP
PARAMETER
STATIC PERFORMANCE
CONDITIONS
MIN
MAX
UNIT
Resolution
16
bits
DAC8830ICD,
DAC8831ICD,
DAC8831ICRGY
±0.5
±0.5
±0.5
±1
±2
±4
DAC8830IBD,
DAC8831IBD,
DAC8831IBRGY
Linearity error
LSB
DAC8830ID,
DAC8831ID,
DAC8831IRGY
Differential linearity error
All grades
±0.5
±1
±1
±5
±7
LSB
LSB
TA = +25°C
Gain error
TA = –40°C to +85°C
Gain drift
±0.1
ppm/°C
LSB
TA = +25°C
±0.25
±1
±2
Zero code error
TA = –40°C to +85°C
Zero code drift
±0.05
ppm/°C
OUTPUT CHARACTERISTICS
All devices
Unipolar operation
Bipolar operation
0
+VREF
+VREF
V
V
Voltage output(1)
DAC8831 only
–VREF
Output impedance
Settling time
Slew rate(2)
6.25
1
kΩ
To 1/2 LSB of FS, CL = 10 pF
CL = 10 pF
μs
25
35
0.2
10
18
V/μs
nV-s
nV-s
Digital-to-analog glitch
Digital feedthrough(3)
1 LSB change around major carry
DAC8830
DAC8831
Output noise
TA = +25°C
nV/√Hz
Power-supply rejection
VDD varies ±10%
RFB / RINV
±1
LSB
Ω/Ω
%
1
±0.0015
±0.25
Bipolar resistor
matching
DAC8831 only
Ratio error
±0.0076
±5
TA = +25°C
Bipolar zero error
Bipolar zero drift
DAC8831 only
DAC8831 only
LSB
TA = –40°C to +85°C
±7
±0.2
ppm/°C
(1) The DAC8830 output is unipolar (0 V to +VREF). The DAC8831 output is bipolar (±VREF) when it connects to an external buffer (see the
Bipolar Output Operation section for details).
(2) Slew rate is measured from 10% to 90% of transition when the output changes from 0 to full-scale.
(3) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change; CS is held high, while SCLK and DIN signals are toggled.
Copyright © 2005–2007, Texas Instruments Incorporated
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SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, VDD = +3 V or VDD = +5 V, VREF = +2.5 V unless otherwise noted.
DAC8830, DAC8831
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNIT
REFERENCE INPUT
Reference input voltage range
Reference input impedance(4)
1.25
9
VDD
V
Unipolar mode
kΩ
Bipolar mode, DAC8831
Code = FFFFh
7.5
Reference –3dB bandwidth, BW
Reference feedthrough
1.3
1
MHz
mV
dB
Code = 0000h, VREF = 1 VPP at 100 kHz
Signal-to-noise ratio, SNR
92
Code = 0000h
Code = FFFFh
75
Reference input capacitance
pF
120
DIGITAL INPUTS
VDD = 2.7 V
VDD = 5 V
VDD = 2.7 V
VDD = 5 V
0.6
0.8
VIL
VIH
Input low voltage
Input high voltage
V
V
2.1
2.4
Input current
±1
10
μA
pF
V
Input capacitance
Hysteresis voltage
0.4
POWER SUPPLY
VDD Power-supply voltage
2.7
5.5
20
V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
5
5
IDD
Power-supply current
Power
μA
20
15
25
60
μW
°C
100
TEMPERATURE RANGE
Specified performance
–40
+85
(4) Reference input resistance is code-dependent, minimum at 8555h.
4
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DAC8830
DAC8831
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SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
PIN CONFIGURATIONS (NOT TO SCALE)
D PACKAGE
SO-8
D PACKAGE
SO-14
RGY PACKAGE
QFN-14
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
VOUT
AGND
VREF
VDD
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
RFB
VOUT
INV
DGND
SDI
13 12 11 10
9
DGND
LDAC
SDI
AGNDF
AGNDS
VREF−S
VREF−F
CS
CS
SCLK
VDD 14
8
7
SCLK
CS
NC
DAC8831
Thermal Pad(1)
8
SCLK
RFB
1
2
3
4
5
6
NOTE: (1) Exposed thermal pad in the QFN package
must be connected to analog ground.
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NO.
NAME
DAC8830
1
VOUT
Analog output of DAC
Analog ground
2
AGND
VREF
CS
3
Voltage reference input
4
Chip select input (active low). Data are not clocked into SDI unless CS is low
Serial clock input
5
SCLK
SDI
6
Serial data input. Data are latched into input register on the rising edge of SCLK.
Digital ground
7
DGND
VDD
8
Analog power supply, +3 V to +5 V
DAC8831
1
2
RFB
Feedback resistor. Connect to the output of external operational amplifier in bipolar mode.
Analog output of DAC
VOUT
3
AGNDF Analog ground (Force)
AGNDS Analog ground (Sense)
4
5
VREF–
VREF–
CS
S
Voltage reference input (Sense). Connect to external voltage reference
Voltage reference input (Force). Connect to external voltage reference
Chip select input (active low). Data are not clocked into SDI unless CS is low.
Serial clock input.
6
F
7
8
SCLK
NC
9
No internal connection
10
SDI
Serial data input. Data are latched into input register on the rising edge of SCLK.
Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the content
of the input register.
11
LDAC
12
13
14
DGND
INV
Digital ground
Junction point of internal scaling resistors. Connect to external operational amplifier inverting input in bipolar mode.
Analog power supply, +3 V to +5 V.
VDD
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SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
t
td
CS
DAC
Updated
t
Delay
t
sck
t
Lead
t
t
DSCLK
t
t
wsck
Lag
wsck
SCLK
t
t
su
ho
BIT15 (MSB)
--- Don't Care
BIT14
BIT0
SDI
BIT13, . . . ,1
Figure 1. DAC8830 Timing Diagram
Case1: LDAC tied to LOW
CS
t
td
DAC
Updated
t
Delay
t
sck
t
Lead
t
t
DSCLK
t
t
wsck
Lag
wsck
SCLK
t
t
su
ho
SDI
BIT 15 (MSB)
BIT 14
BIT 13, . . . ,1
BIT 0
LDAC
LOW
−−−Don’t Care
Case2: LDAC Active
CS
t
td
t
Delay
t
sck
t
Lead
t
t
DSCLK
t
t
wsck
Lag
wsck
SCLK
SDI
t
t
su
ho
BIT 15 (MSB)
BIT 14
BIT 13, . . . ,1
BIT 0
t
t
WLDAC
DLADC
DAC
HIGH
LDAC
Updated
−−−Don’t Care
Figure 2. DAC8831 Timing Diagram
6
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SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
TIMING CHARACTERISTICS: VDD = +5 V(1)(2)
At –40°C to +85°C, unless otherwise noted.
PARAMETER
MIN
20
10
10
10
10
10
30
10
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
tsck
SCLK period
twsck
tDelay
tLead
tLag
SCLK high or low time
Delay from SCLK high to CS low
CS enable lead time
CS enable lag time
tDSCLK
ttd
Delay from CS high to SCLK high
CS high between active period
Data setup time (input)
Data hold time (input)
tsu
tho
tWLDAC
tDLDAC
LDAC width
30
30
10
Delay from CS high to LDAC low
VDD high to CS low (power-up delay)
(1) Assured by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
TIMING CHARACTERISTICS: VDD = +3 V(1)(2)
At –40°C to +85°C, unless otherwise noted.
PARAMETER
MIN
20
10
10
10
10
10
30
10
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
tsck
SCLK period
twsck
tDelay
tLead
tLag
SCLK high or low time
Delay from SCLK high to CS low
CS enable lead time
CS enable lag time
tDSCLK
ttd
Delay from CS high to SCLK high
CS high between active period
Data setup time (input)
tsu
tho
Data hold time (input)
tWLDAC
tDLDAC
LDAC width
30
30
10
Delay from CS high to LDAC low
VDD high to CS low (power-up delay)
(1) Assured by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
Copyright © 2005–2007, Texas Instruments Incorporated
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SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C and VREF = +2.5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
−
−
−
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
0.50
0.75
1.00
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
−
−
−
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
0.50
0.75
1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 5.
Figure 6.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
−
−
−
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
0.50
0.75
1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 7.
Figure 8.
8
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SLAS449D–FEBRUARY 2005–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C and VREF = +2.5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
0.75
0.50
0.25
0
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
−
−
−
0.50
0.75
1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9.
Figure 10.
LINEARITY ERROR
vs REFERENCE VOLTAGE
LINEARITY ERROR
vs SUPPLY VOLTAGE
0.75
0.50
0.25
0
0.75
0.50
0.25
0
VREF = 2.5 V
DNL
DNL
INL
INL
−
−
−
0.25
0.50
0.25
0.50
−
0
1
2
3
4
5
6
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Reference Voltage (V)
Supply Voltage (V)
Figure 11.
Figure 12.
GAIN ERROR
vs TEMPERATURE
ZERO-CODE ERROR
vs TEMPERATURE
1.25
1.00
0.75
0.50
0.25
0
0.50
0.25
0
Bipolar Mode
VREF = 2.5 V
Bipolar Mode
Unipolar Mode
−
−
−
−
0.25
0.50
0.75
0.25
0.50
Unipolar Mode
VREF = 2.5 V
−
−
−
−
−
−
−
60
40 20
0
20
40
60
80 100 120 140
60
40 20
0
20
40
60
80 100 120 140
_
_
Temperature ( C)
Temperature ( C)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C and VREF = +2.5 V, unless otherwise noted.
REFERENCE CURRENT
vs CODE (UNIPOLAR MODE)
REFERENCE CURRENT
vs CODE (BIPOLAR MODE)
300
300
250
200
150
100
50
250
200
150
100
50
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
60
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 15.
Figure 16.
SUPPLY CURRENT
vs DIGITAL INPUT VOLTAGE
SUPPLY CURRENT
vs TEMPERATURE
800
5
4
3
2
1
0
VREF = 2.5 V
700
600
500
400
300
200
100
0
VDD = 5 V
VDD = 5 V
VLOGIC = 5 V
VDD = 3 V
VLOGIC = 3 V
VDD = 3 V
0
1
2
3
4
5
−
−
−
20
40
0
20 40
60
80 100 120 140
Digital Input Voltage (V)
_
Temperature ( C)
Figure 17.
Figure 18.
SUPPLY CURRENT
vs SUPPLY VOLTAGE
SUPPLY CURRENT
vs REFERENCE VOLTAGE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VREF = 2.5 V
VDD = 5 V
VDD = 3 V
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
Supply Voltage (V)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Reference Voltage (V)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C and VREF = +2.5 V, unless otherwise noted.
MAJOR-CARRY GLITCH
(FALLING)
MAJOR-CARRY GLITCH
(RISING)
VREF = 2.5V
VREF = 2.5V
5V/div
5V/div
LDAC
LDAC
VOUT
VOUT
0.1V/div
0.1V/div
Time (0.5ms/div)
Time (0.5ms/div)
Figure 21.
Figure 22.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
VREF = 2.5V
VREF = 2.5V
5V/div
5V/div
LDAC
LDAC
1V/div
VOUT
VOUT
1V/div
Time (0.2ms/div)
Time (0.2ms/div)
Figure 23.
Figure 24.
DIGITAL
FEEDTHROUGH
VREF = 2.5 V
SDI
5V/div
VOUT
20mV/div
Time (50ns/div)
Figure 25.
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TYPICAL CHARACTERISTICS: VDD = +3 V
At TA = +25°C and VREF = +2.5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
−
−
−
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
0.50
0.75
1.00
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 26.
Figure 27.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
−
−
−
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
0.50
0.75
1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 28.
Figure 29.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
−
−
−
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
0.50
0.75
1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS: VDD = +3 V (continued)
At TA = +25°C and VREF = +2.5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
−
−
−
−
−
−
−
−
0.25
0.50
0.75
1.00
0.25
0.50
0.75
1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 32.
Figure 33.
LINEARITY ERROR
vs REFERENCE VOLTAGE
GAIN ERROR
vs TEMPERATURE
1.00
0.75
0.50
0.25
0
0.75
0.50
0.25
0
Bipolar Mode
DNL
Unipolar Mode
−
0.25
0.50
0.75
1.00
−
−
−
0.25
0.50
VDD = 3 V
VREF = 2.5 V
−
−
INL
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−
−
−
60
40 20
0
20
40
60
80 100 120 140
_
Temperature ( C)
Reference Voltage (V)
Figure 34.
Figure 35.
ZERO-CODE ERROR
vs TEMPERATURE
REFERENCE CURRENT
vs CODE (UNIPOLAR MODE)
0.50
0.25
0
300
250
200
150
100
50
VDD = 3 V
VREF = 2.5 V
Unipolar Mode
−
0.25
0.50
0.75
Bipolar Mode
−
−
0
−
−
−
60
40 20
0
20
40
60
80 100 120 140
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
_
Temperature ( C)
Figure 36.
Figure 37.
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TYPICAL CHARACTERISTICS: VDD = +3 V (continued)
At TA = +25°C and VREF = +2.5 V, unless otherwise noted.
REFERENCE CURRENT
vs CODE (BIPOLAR MODE)
DIGITAL
FEEDTHROUGH
300
VREF = 2.5 V
250
200
150
100
50
SDI
5V/div
VOUT
20mV/div
0
Time (50ns/div)
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 38.
Figure 39.
MAJOR-CARRY GLITCH
(FALLING)
MAJOR-CARRY GLITCH
(RISING)
VREF = 2.5V
VREF = 2.5V
5V/div
5V/div
LDAC
LDAC
VOUT
VOUT
0.1V/div
0.1V/div
Time (0.5ms/div)
Time (0.5ms/div)
Figure 40.
Figure 41.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
VREF = 2.5V
VREF = 2.5V
5V/div
5V/div
LDAC
LDAC
1V/div
VOUT
VOUT
1V/div
Time (0.2ms/div)
Time (0.2ms/div)
Figure 42.
Figure 43.
THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC8830 and DAC8831 are single, 16-bit, serial-input, voltage-output DACs. They operate from a single
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supply ranging from 2.7 V to 5 V, and typically consume 5 μA. Data are written to these devices in a 16-bit word
format, via an SPI serial interface. To ensure a known power-up state, these parts are designed with a power-on
reset function. The DAC8830 and DAC8831 are reset to zero code. In unipolar mode, the DAC8830 and
DAC8831 are reset to 0 V, and in bipolar mode, the DAC8831 is reset to –VREF. Kelvin sense connections for the
reference and analog ground are included on the DAC8831.
DIGITAL-TO-ANALOG SECTIONS
The DAC architecture for both devices consists of two matched DAC sections and is segmented. A simplified
circuit diagram is shown in Figure 44. The four MSBs of the 16-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining
12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R
R
VOUT
2R
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
VREF
12−Bit R−2R Ladder
Four MSBs Decoded into
15 Equal Segments
Figure 44. DAC Architecture
OUTPUT RANGE
The output of the DAC is
VOUT = (VREF × Code)/65536.
Where Code is the decimal data word loaded to the DAC latch.
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POWER-ON RESET
Both devices have a power-on reset function to ensure the output is at a known state upon power-up. In the
DAC8830 and DAC8831, at power-up, the DAC latch and Input Registers contain all 0s until new data are loaded
from the input serial shift register. Therefore, after power-up, the output from pin VOUT of the DAC8830 is 0 V.
The output from pin VOUT of the DAC8831 is 0 V in unipolar mode and –VREF in bipolar mode.
However, the serial register of the DAC8830 and DAC8831 is not cleared on power-up, so its contents are
undefined. When loading data initially to the device, 16 bits or more should be loaded to prevent erroneous data
appearing on the output. If more than 16 bits are loaded, the last 16 are kept; if less than 16 are loaded, bits will
remain from the previous word. If the device must be interfaced with data shorter than 16 bits, the data should be
padded with 0s at the LSBs.
Serial Interface
The digital interface is a standard 3-wire connection compatible with SPI, QSPI™, Microwire™, and TI DSP
interfaces, which can operate at speeds up to 50 M-bits/sec. The data transfer is framed by CS, the chip select
signal. The DAC works as a bus slave. The bus master generates the synchronize clock, SCLK, and initiates the
transmission. When CS is high, the DAC is not accessed, and the clock SCLK and serial input data SDI are
ignored. The bus master accesses the DAC by driving pin CS low. Immediately following the high-to-low
transition of CS, the serial input data on pin SDI is shifted out from the bus master synchronously on the falling
edge of SCLK, and latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high
transition of CS transfers the contents of the input shift register to the input register. All data registers are 16-bit.
It takes 16 clocks of SCLK to transfer one data word to the parts. To complete a whole data word, CS must go
high immediately after 16 SCLKs are clocked in. If more than 16 SCLKs are applied during the low state of CS,
the last 16 bits are transferred to the input register on the rising edge of CS. However, if CS is not kept low
during the entire 16 SCLK cycles, data is corrupted. In this case, reload the DAC with a new 16-bit word.
In the DAC8830, the contents of the input register are transferred into the DAC latch immediately when the input
register is loaded, and the DAC output is updated at the same time.
The DAC8831 has an LDAC pin allowing the DAC latch to be updated asynchronously by bringing LDAC low
after CS goes high. In this case, LDAC must be maintained high while CS is low. If LDAC is tied permanently
low, the DAC latch is updated immediately after the input register is loaded (caused by the low-to-high transition
of CS).
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APPLICATION INFORMATION
Unipolar Output Operation
These DACs are capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low supply current
(typically 5 μA) and a low offset error. The DAC8830 provides a unipolar output swing ranging from 0 V to VREF
.
The DAC8831 can be configured to output both unipolar and bipolar voltages. Figure 45 and Figure 46 show a
typical unipolar output voltage circuit for each device, respectively. The code table for this mode of operation is
shown in Table 1.
Table 1. Unipolar Code
DAC LATCH CONTENTS
MSB
LSB
ANALOG OUTPUT
VREF × (65,535/65,536)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
VREF × (32,768/65,536) = 1/2 VREF
VREF × (1/65,536)
0 V
+5 V
+2.5 V
+
µ
10
F
µ
0.1
F
µ
0.1
F
OPA277
OPA704
OPA727
VDD
VREF
VO = 0 to +VREF
VOUT
DAC
AGND
CS
SCLK
SDI
Input
Register
DAC Latch
DAC8830
DGND
Figure 45. Unipolar Output Mode of DAC8830
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+5 V
+2.5 V
+
µ
µ
F
0.1
F
10
µ
0.1
F
OPA277
OPA704
OPA727
−
VREF
−
F
VDD
S
VREF
RINV
RFB
+V
RFB
LDAC
INV
VO = 0 to +VREF
VOUT
DAC
CS
SCLK
SDI
−
V
AGNDF
AGNDS
Input
Register
DAC Latch
DAC8831
DGND
Figure 46. Unipolar Output Mode of DAC8831
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation:
Unipolar Mode Worst-Case Output
D
2
ǒV
GEǓ ) V
ZSE
V
+
) V
) INL
OUT_UNI
REF
16
Where:
VOUT_UNI = Unipolar mode worst-case output
D = Code loaded to DAC
VREF = Reference voltage applied to part
VGE = Gain error in volts
VZSE = Zero-scale error in volts
INL = Integral nonlinearity in volts
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Bipolar Output Operation
With the aid of an external operational amplifier, the DAC8831 may be configured to provide a bipolar voltage
output. A typical circuit of such an operation is shown in Figure 47. The matched bipolar offset resistors RFB and
RINV are connected to an external operational amplifier to achieve this bipolar output swing; typically, RFB = RINV
= 28 kΩ.
+5 V
+2.5 V
+
µ
µ
F
0.1
F
10
µ
0.1
F
−
VREF
−
F
VDD
S
VREF
RINV
RFB
RFB
INV
+V
LDAC
−
= VREF to +VREF
VO
VOUT
DAC
OPA277
OPA704
OPA727
CS
SCLK
SDI
−
V
AGNDF
AGNDS
Input
Register
DAC Latch
DAC8831
DGND
Figure 47. Bipolar Output Mode of DAC8831
Table 2 shows the transfer function for this output operating mode. The DAC8831 also provides a set of Kelvin
connections to the analog ground and external reference inputs.
Table 2. Bipolar Code
DAC LATCH CONTENTS
MSB
LSB
ANALOG OUTPUT
+VREF × (32,767/32,768)
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+VREF × (1/32,768)
0 V
–VREF × (1/32,768)
–VREF × (32,768/32,768) = –VREF
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation:
Bipolar Mode Worst-Case Output
ǒ
ƪ V
Ǔ (
)ƫ
)
(
OUT_UNI ) VOS 2 ) RD * VREF 1 ) RD
VOUT_BIP
+
2)RD
1 ) ǒ
Ǔ
A
Where:
VOS = External operational amplifier input offset voltage
RD = RFB and RIN resistor matching error
A = Operational amplifier open-loop gain
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Output Amplifier Selection
For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This provides the
±VREF output.
In a single-supply application, selection of a suitable operational amplifier may be more difficult because the
output swing of the amplifier does not usually include the negative rail; in this case, AGND. This output swing can
result in some degradation of the specified performance unless the application does not use codes near 0.
The selected operational amplifier needs to have low-offset voltage (the DAC LSB is 38 μV with a 2.5 V
reference), eliminating the need for output offset trims. Input bias current should also be low because the bias
current multiplied by the DAC output impedance (approximately 6.25 kΩ) adds to the zero-code error.
Rail-to-rail input and output performance are required. For fast settling, the slew rate of the operational amplifier
should not impede the settling time of the DAC. Output impedance of the DAC is constant and
code-independent, but in order to minimize gain errors the input impedance of the output amplifier should be as
high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds
another time constant to the system, thus increasing the settling time of the output. A higher 3 dB amplifier
bandwidth results in a shorter effective settling time of the combined DAC and amplifier.
Reference and Ground
Since the input impedance is code-dependent, the reference pin should be driven from a low impedance source.
The DAC8830 and DAC8831 operate with a voltage reference ranging from 1.25 V to VDD. References below
1.25 V result in reduced accuracy.
The DAC full-scale output voltage is determined by the reference. Table 1 and Table 2 outline the analog output
voltage for particular digital codes.
For optimum performance, Kelvin sense connections are provided on the DAC8831. If the application does not
require separate force and sense lines, they should be tied together close to the package to minimize voltage
drops between the package leads and the internal die.
Power Supply and Reference Bypassing
For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed
with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
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CROSS-REFERENCE
The DAC8830 and DAC8831 have an industry-standard pinout configuration (see Table 3).
Table 3. Cross-Reference
INL
(LSB)
DNL
(LSB)
POWER-ON
RESET TO
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSS
REFERENCE
MODEL
AD5541CR,
MAX541AESA
DAC8830ICD
DAC8830IBD
DAC8830ID
±1
±2
±4
±1
±1
±1
Zero Code
Zero Code
Zero Code
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Small Outline IC
8-Lead Small Outline IC
8-Lead Small Outline IC
SO-8
SO-8
SO-8
AD5541BR,
MAX541BESA
AD5541AR,
MAX541CESA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
±1
±2
±4
±1
±2
±1
±2
±4
±1
±1
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8-Lead Plastic DIP
8-Lead Plastic DIP
8-Lead Plastic DIP
8-Lead Small Outline IC
8-Lead Small Outline IC
8-Lead Plastic DIP
8-Lead Plastic DIP
8-Lead Plastic DIP
PDIP-8
PDIP-8
PDIP-8
SO-8
MAX541AEPA
MAX541BEPA
MAX541CEPA
AD5541LR
±1
±1
±1.5
±1
SO-8
AD5541JR
PDIP-8
PDIP-8
PDIP-8
MAX541AEPA
MAX541BEPA
MAX541CEPA
±1
±1
AD5542CR,
MAX542AESD
DAC8831ICD
DAC8831IBD
DAC8831ID
±1
±2
±4
±1
±1
±1
Zero Code
Zero Code
Zero Code
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
14-Lead Small Outline IC
14-Lead Small Outline IC
14-Lead Small Outline IC
SO-14
SO-14
SO-14
AD5542BR,
MAX542BESD
AD5542AR,
MAX542CESD
DAC8831ICRGY
±1
±2
±4
±1
±2
±4
±1
±2
±1
±2
±4
±1
±1
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
Zero Code
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
14-Lead QFN
14-Lead QFN
QFN-14
QFN-14
QFN-14
PDIP-14
PDIP-14
PDIP-14
SO-14
N/A
DAC8831IBRGY
N/A
DAC8831IRGY
±1
14-Lead QFN
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
±1
14-Lead Plastic DIP
14-Lead Plastic DIP
14-Lead Plastic DIP
14-Lead Small Outline IC
14-Lead Small Outline IC
14-Lead Small Outline IC
14-Lead Small Outline IC
14-Lead Small Outline IC
MAX542ACPD
MAX542BCPD
MAX542CCPD
AD5542LR
AD5542JR
MAX542AEPD
MAX542BEPD
MAX542CEPD
±1
±1
±1
±1.5
±1
0°C to +70°C
SO-14
0°C to +70°C
SO-14
±1
0°C to +70°C
SO-14
±1
0°C to +70°C
SO-14
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PACKAGING INFORMATION
Orderable Device
DAC8830IBD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
VQFN
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DAC
8830I
DAC8830IBDG4
DAC8830IBDR
DAC8830IBDRG4
DAC8830ICD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
2500
2500
75
Green (RoHS
& no Sb/Br)
DAC
8830I
8
Green (RoHS
& no Sb/Br)
DAC
8830I
D
8
Green (RoHS
& no Sb/Br)
DAC
8830I
D
8
Green (RoHS
& no Sb/Br)
DAC
8830I
DAC8830ICDG4
DAC8830ICDR
DAC8830ICDRG4
DAC8830ID
D
8
75
Green (RoHS
& no Sb/Br)
DAC
8830I
D
8
2500
2500
75
Green (RoHS
& no Sb/Br)
DAC
8830I
D
8
Green (RoHS
& no Sb/Br)
DAC
8830I
D
8
Green (RoHS
& no Sb/Br)
DAC
8830I
DAC8830IDG4
DAC8830IDR
D
8
75
Green (RoHS
& no Sb/Br)
DAC
8830I
D
8
2500
2500
50
Green (RoHS
& no Sb/Br)
DAC
8830I
DAC8830IDRG4
DAC8831IBD
D
8
Green (RoHS
& no Sb/Br)
DAC
8830I
D
14
14
14
14
14
Green (RoHS
& no Sb/Br)
DAC8831I
DAC8831I
DAC8831I
DAC8831I
BKE
DAC8831IBDG4
DAC8831IBDR
DAC8831IBDRG4
DAC8831IBRGYT
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
250
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
RGY
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
DAC8831IBRGYTG4
DAC8831ICD
ACTIVE
VQFN
SOIC
SOIC
SOIC
SOIC
VQFN
VQFN
SOIC
SOIC
SOIC
SOIC
VQFN
VQFN
RGY
14
14
14
14
14
14
14
14
14
14
14
14
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
BKE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
50
50
Green (RoHS
& no Sb/Br)
DAC8831I
DAC8831I
DAC8831I
DAC8831I
BKE
DAC8831ICDG4
DAC8831ICDR
DAC8831ICDRG4
DAC8831ICRGYT
DAC8831ICRGYTG4
DAC8831ID
Green (RoHS
& no Sb/Br)
D
2500
2500
250
250
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
RGY
RGY
D
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
BKE
Green (RoHS
& no Sb/Br)
DAC8831I
DAC8831I
DAC8831I
DAC8831I
BKE
DAC8831IDG4
D
50
Green (RoHS
& no Sb/Br)
DAC8831IDR
D
2500
2500
250
250
Green (RoHS
& no Sb/Br)
DAC8831IDRG4
DAC8831IRGYT
DAC8831IRGYTG4
D
Green (RoHS
& no Sb/Br)
RGY
RGY
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
BKE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC8830, DAC8831 :
Enhanced Product: DAC8830-EP, DAC8831-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC8830IBDR
DAC8830ICDR
DAC8830IDR
SOIC
SOIC
SOIC
SOIC
VQFN
SOIC
VQFN
SOIC
VQFN
D
D
8
2500
2500
2500
2500
250
330.0
330.0
330.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8
D
8
6.4
5.2
2.1
DAC8831IBDR
DAC8831IBRGYT
DAC8831ICDR
DAC8831ICRGYT
DAC8831IDR
D
14
14
14
14
14
14
6.5
9.0
2.1
RGY
D
3.85
6.5
3.85
9.0
1.35
2.1
2500
250
RGY
D
3.85
6.5
3.85
9.0
1.35
2.1
2500
250
DAC8831IRGYT
RGY
3.85
3.85
1.35
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC8830IBDR
DAC8830ICDR
DAC8830IDR
SOIC
SOIC
SOIC
SOIC
VQFN
SOIC
VQFN
SOIC
VQFN
D
D
8
2500
2500
2500
2500
250
367.0
367.0
367.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
367.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
8
D
8
DAC8831IBDR
DAC8831IBRGYT
DAC8831ICDR
DAC8831ICRGYT
DAC8831IDR
D
14
14
14
14
14
14
RGY
D
2500
250
RGY
D
2500
250
DAC8831IRGYT
RGY
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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