DAC904U [TI]
14-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER; 14位， 165MSPS数位类比转换器
| 型号： | DAC904U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总23页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC904
DAC904
SBAS095C – MAY 2002
14-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● COMMUNICATION TRANSMIT CHANNELS
WLL, Cellular Base Station
Digital Microwave Links
● SINGLE +5V OR +3V OPERATION
●
HIGH SFDR: 20MHz Output at 100MSPS: 64dBc
● LOW GLITCH: 3pV-s
Cable Modems
● LOW POWER: 170mW at +5V
● WAVEFORM GENERATION
● INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
● MEDICAL/ULTRASOUND
● HIGH-SPEED INSTRUMENTATION AND
CONTROL
● VIDEO, DIGITAL TV
battery-operated systems. Further optimization can be realized
by lowering the output current with the adjustable full-scale
option.
DESCRIPTION
The DAC904 is a high-speed, Digital-to-Analog Converter (DAC)
offering a 14-bit resolution option within the family of high-
performance converters. Featuring pin compatibility among fam-
ily members, the DAC908, DAC900, and DAC902 provide a
component selection option to an 8-, 10-, and 12-bit resolution,
respectively. All models within this family of DACs support
update rates in excess of 165MSPS with excellent dynamic
performance, and are especially suited to fulfill the demands of
a variety of applications.
For noncontinuous operation of the DAC904, a power-down
mode results in only 45mW of standby power.
The DAC904 comes with an integrated 1.24V bandgap refer-
ence and edge-triggered input latches, offering a complete
converter solution. Both +3V and +5V CMOS logic families can
be interfaced to the DAC904.
The reference structure of the DAC904 allows for additional
flexibility by utilizing the on-chip reference, or applying an
external reference. The full-scale output current can be adjusted
over a span of 2-20mA, with one external resistor, while main-
taining the specified dynamic performance.
The advanced segmentation architecture of the DAC904 is
optimized to provide a high Spurious-Free Dynamic Range
(SFDR) for single-tone, as well as for multi-tone signals—
essential when used for the transmit signal path of communica-
tion systems.
The DAC904 is available in SO-28 and TSSOP-28 packages.
The DAC904 has a high impedance (200kΩ) current output with
a nominal range of 20mA and an output compliance of up to
1.25V. The differential outputs allow for both a differential or
single-ended analog signal interface. The close matching of the
current outputs ensures superior dynamic performance in the
differential configuration, which can be implemented with a
transformer.
+VA
BW
+VD
DAC904
IOUT
IOUT
BYP
LSB
Switches
FSA
Current
Sources
REFIN
Segmented
Switches
INT/EXT
Utilizing a small geometry CMOS process, the monolithic DAC904
can be operated on a wide, single-supply range of +2.7V to
+5.5V. Its low power consumption allows for use in portable and
Latches
PD
+1.24V Ref.
14-Bit Data Input
D13...D0
AGND
CLK
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
+VA to AGND......................................................................... –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD ............................................................................... –6V to +6V
CLK, PD to DGND ....................................................... –0.3V to VD + 0.3V
D0-D13 to DGND ......................................................... –0.3V to VD + 0.3V
IOUT, IOUT to AGND .......................................................... –1V to VA + 0.3V
BW, BYP to AGND....................................................... –0.3V to VA + 0.3V
ESD damage can range from subtle performance degradation
tocompletedevicefailure. Precisionintegratedcircuitsmaybe
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
REFIN, FSA to AGND ................................................... –0.3V to VA + 0.3V
INT/EXT to AGND ........................................................ –0.3V to VA + 0.3V
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
Storage Temperature ..................................................................... +125°C
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
DAC904U
SO-28
DW
"
PW
"
–40°C to +85°C
DAC904U
DAC904U
DAC904U/1K
DAC904E
Rails, 28
Tape and Reel, 1000
Rails, 52
"
DAC904E
"
"
"
"
TSSOP-28
–40°C to +85°C
DAC904E
"
"
"
DAC904E/2K5
Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
DEMO BOARD ORDERING INFORMATION
DEMO BOARD
PRODUCT
ORDERING NUMBER
COMMENT
DAC904U
DAC904E
DEM-DAC90xU
DEM-DAC904E
Populated evaluation board without DAC. Order sample of desired DAC90x model separately.
Populated evaluation board including the DAC904E.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U, E
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
14
Bits
OUTPUT UPDATE RATE
Output Update Rate (fCLOCK
Full Specified Temperature Range, Operating
2.7V to 3.3V
4.5V to 5.5V
Ambient, TA
125
165
–40
165
200
MSPS
MSPS
°C
)
+85
STATIC ACCURACY(1)
TA = +25°C
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
fCLOCK = 25MSPS, fOUT = 1.0MHz
±2.5
±3.0
LSB
LSB
DYNAMIC PERFORMANCE
TA = +25°C
Spurious-Free Dynamic Range (SFDR)
fOUT = 1.0MHz, fCLOCK = 25MSPS
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
fOUT = 20.2MHz, fCLOCK = 100MSPS
fOUT = 25.3MHz, fCLOCK = 125MSPS
fOUT = 41.5MHz, fCLOCK = 125MSPS
fOUT = 27.4MHz, fCLOCK = 165MSPS
fOUT = 54.8MHz, fCLOCK = 165MSPS
Spurious-Free Dynamic Range within a Window
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
Total Harmonic Distortion (THD)
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 2.1MHz, fCLOCK = 125MSPS
Two Tone
To Nyquist
72
79
76
68
68
64
60
55
60
55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
2MHz Span
4MHz Span
82
82
dBc
dBc
–75
–74
dBc
dBc
fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS
63
dBc
DAC904
2
SBAS095C
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U, E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (Cont.)
Output Settling Time(2)
Output Rise Time(2)
to 0.1%
10% to 90%
10% to 90%
30
2
2
ns
ns
ns
Output Fall Time(2)
Glitch Impulse
3
pV-s
DC-ACCURACY
Full-Scale Output Range(3)(FSR)
Output Compliance Range
Gain Error
Gain Error
Gain Drift
All Bits HIGH, IOUT
2.0
–1.0
–10
–10
20.0
+1.25
+10
mA
V
With Internal Reference
With External Reference
With Internal Reference
With Internal Reference
With Internal Reference
±1
±2
±120
%FSR
%FSR
ppmFSR/°C
%FSR
ppmFSR/°C
%FSR/V
%FSR/V
pA/√Hz
kΩ
+10
Offset Error
Offset Drift
–0.025
+0.025
±0.1
Power-Supply Rejection, +VA
Power-Supply Rejection, +VD
Output Noise
Output Resistance
Output Capacitance
–0.2
–0.025
+0.2
+0.025
I
OUT = 20mA, RLOAD = 50Ω
50
200
12
I
OUT, IOUT to Ground
pF
REFERENCE
Reference Voltage
Reference Tolerance
+1.24
±10
±50
10
V
%
Reference Voltage Drift
Reference Output Current
Reference Input Resistance
Reference Input Compliance Range
Reference Small-Signal Bandwidth(4)
ppmFSR/°C
µA
MΩ
V
1
0.1
1.25
1.3
MHz
DIGITAL INPUTS
Logic Coding
Straight Binary
Latch Command
Rising Edge of Clock
Logic HIGH Voltage, VIH
Logic LOW Voltage, VIL
Logic HIGH Voltage, VIH
Logic LOW Voltage, VIL
+VD = +5V
+VD = +5V
+VD = +3V
+VD = +3V
+VD = +5V
+VD = +5V
3.5
2
5
0
3
V
V
V
1.2
0.8
0
V
(5)
Logic HIGH Current, IIH
±20
±20
5
µA
µA
pF
Logic LOW Current, IIL
Input Capacitance
POWER SUPPLY
Supply Voltages
+VA
+VD
+2.7
+2.7
+5
+5
+5.5
+5.5
V
V
Supply Current(6)
IVA
24
1.1
8
170
50
45
30
2
15
230
mA
mA
mA
mW
mW
mW
IVA, Power-Down Mode
IVD
Power Dissipation
+5V, IOUT = 20mA
+3V, IOUT = 2mA
Power Dissipation, Power-Down Mode
Thermal Resistance, θJA
SO-28
75
50
°C/W
°C/W
TSSOP-28
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32x IREF; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an
internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.
DAC904
SBAS095C
3
www.ti.com
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
DESIGNATOR
DESCRIPTION
Top View
SO, TSSOP
1
2
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
PD
Data Bit 1 (D13), MSB
Data Bit 2 (D12)
Data Bit 3 (D11)
Data Bit 4 (D10)
Data Bit 5 (D9)
Data Bit 6 (D8)
Data Bit 7 (D7)
Data Bit 8 (D6)
Data Bit 9 (D5)
Data Bit 10 (D4)
Data Bit 11 (D3)
Data Bit 12 (D2)
3
4
5
6
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
1
2
3
4
5
6
7
8
9
28 CLK
27 +VD
26 DGND
25 NC
7
8
9
10
11
12
13
14
15
24 +VA
Data Bit 13 (D1)
Data Bit 14 (D0), LSB
23 BYP
22 IOUT
21 IOUT
20 AGND
19 BW
Power Down, Control Input; Active
HIGH. Contains internal pull-down circuit;
may be left unconnected if not used.
DAC904
16
17
INT/EXT
REFIN
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation
Reference Input/Ouput. See Applications
section for further details.
Bit 10 10
Bit 11 11
Bit 12 12
Bit 13 13
Bit 14 14
18
19
FSA
BW
Full-Scale Output Adjust
18 FSA
17 REFIN
16 INT/EXT
15 PD
Bandwidth/Noise Reduction Pin:
Bypass with 0.1µF to +VA for Optimum
Performance. (Optional)
20
21
22
23
24
25
26
27
28
AGND
IOUT
Analog Ground
Complementary DAC Current Output
IOUT
DAC Current Output
BYP
+VA
Bypass Node: Use 0.1µF to AGND
Analog Supply Voltage, 2.7V to 5.5V
No Internal Connection
Digital Ground
NC
DGND
+VD
Digital Supply Voltage, 2.7V to 5.5V
Clock Input
CLK
TYPICAL CONNECTION CIRCUIT
+5V
+5V
0.1µF(1)
+VA
+VD
BW
DAC904
IOUT
1:1
VOUT
IOUT
LSB
FSA
Switches
BYP
Current
Sources
REFIN
Segmented
MSB
50Ω
0.1µF
20pF(1)
50Ω
20pF(1)
RSET
Switches
0.1µF
INT/EXT
PD
Latches
+1.24V Ref.
14-Bit Data Input
D13.......D0
AGND
CLK
DGND
NOTE: (1) Optional components.
DAC904
4
SBAS095C
www.ti.com
TIMING DIAGRAM
t2
t1
CLOCK
D13 D0
t
t
H
S
Data Changes
Data Changes
Stable Valid Data
t
t
SET
PD
Iout or
Iout
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
t2
tS
tH
tPD
tSET
Clock Pulse HIGH Time
Clock Pulse LOW Time
Data Setup Time
Data Hold Time
Propagation Delay Time
3
3
1.0
1.5
1
ns
ns
ns
ns
ns
ns
Output Settling Time to 0.1%
30
DAC904
SBAS095C
5
www.ti.com
TYPICAL CHARACTERISTICS: VD = VA = +5V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
TYPICAL INL
TYPICAL DNL
10
8
10
8
6
6
4
4
2
2
0
0
–2
–4
–6
–8
–10
–2
–4
–6
–8
–10
DAC Code
DAC Code
SFDR vs fOUT AT 25MSPS
SFDR vs fOUT AT 50MSPS
90
85
80
75
70
65
60
85
80
75
70
65
60
55
–6dBFS
–6dBFS
0dBFS
0dBFS
0
2.0
4.0
6.0
8.0
10.0
12.0
0
5.0
10.0
15.0
20.0
25.0
Frequency (MHz)
Frequency (MHz)
SFDR vs fOUT AT 100MSPS
SFDR vs fOUT AT 125MSPS
85
80
75
70
65
60
55
50
45
85
80
75
70
65
60
55
50
45
–6dBFS
–6dBFS
0dBFS
0dBFS
0
10.0
20.0
30.0
40.0
50.0
0
10.0
20.0
30.0
40.0
50.0
60.0
Frequency (MHz)
Frequency (MHz)
DAC904
6
SBAS095C
www.ti.com
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 165MSPS
SFDR vs fOUT AT 200MSPS
80
75
70
65
60
55
50
45
40
80
75
70
65
60
55
50
45
40
–6dBFS
–6dBFS
0dBFS
0dBFS
0
10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0
Frequency (MHz)
0
10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0
Frequency (MHz)
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS
SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS
85
80
75
70
65
60
55
50
45
80
75
70
65
60
55
50
45
40
2.1MHz
X
Diff (–6dBFS)
*
X
5.04MHz
*
*
*
10.1MHz
X
20.2MHz
IOUT (–6dBFS)
X
X
X
40.4MHz
Diff (0dBFS)
X
X
X
X
X
IOUT (0dBFS)
0
10.0
20.0
30.0
40.0
50.0
2
5
10
20
Frequency (MHz)
IOUTFS (mA)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
2.1MHz
THD vs fCLOCK AT fOUT = 2.1MHz
85
80
75
70
65
60
55
50
45
–70
–75
–80
–85
–90
–95
–100
2HD
4HD
10.1MHz
40.4MHz
X
X
X
X
3HD
X
X
X
X
X
X
X
–40
–20
0
25
50
70
85
0
25
50
100
125
150
Temperature (°C)
f
CLOCK (MSPS)
DAC904
SBAS095C
7
www.ti.com
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DUAL-TONE OUTPUT SPECTRUM
FOUR-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15 20
25
30
35
40
45 50
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
TYPICAL CHARACTERISTICS: VD = VA = +3V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 25MSPS
SFDR vs fOUT AT 50MSPS
85
80
75
70
65
60
55
85
80
75
70
65
60
55
–6dBFS
–6dBFS
0dBFS
0dBFS
0
2.0
4.0
6.0
8.0
10.0
12.0
0
5.0
10.0
15.0
20.0
25.0
Frequency (MHz)
Frequency (MHz)
SFDR vs fOUT AT 100MSPS
SFDR vs fOUT AT 125MSPS
85
80
75
70
65
60
55
50
45
85
80
75
70
65
60
55
50
45
–6dBFS
–6dBFS
0dBFS
0dBFS
0
10.0
20.0
30.0
40.0
50.0
0
10.0
20.0
30.0
40.0
50.0
60.0
Frequency (MHz)
Frequency (MHz)
DAC904
8
SBAS095C
www.ti.com
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS
SFDR vs fOUT AT 165MSPS
80
75
70
65
60
55
50
45
40
85
80
75
70
65
60
55
50
45
Diff (–6dBFS)
–6dBFS
IOUT (–6dBFS)
0dBFS
Diff (0dBFS)
IOUT (0dBFS)
20.0
0
10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0
Frequency (MHz)
0
10.0
30.0
40.0
50.0
Frequency (MHz)
SFDR vs IOUTFS and fOUT AT 100MSPS
2.1MHz
THD vs fCLOCK AT fOUT = 2.1MHz
80
75
70
65
60
55
50
45
40
–70
–75
–80
–85
–90
–95
–100
2HD
5.04MHz
X
X
X
X
10.1MHz
4HD
3HD
20.2MHz
*
40.4MHz
*
*
*
2
5
10
20
0
25
50
100
125
150
IOUTFS (mA)
f
CLOCK (MSPS)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
2.1MHz
DUAL-TONE OUTPUT SPECTRUM
80
75
70
65
60
55
50
45
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10.1MHz
40.4MHz
X
X
X
X
X
X
X
–40
–20
0
25
50
70
85
0
5
10
15 20
25
30
35
40
45 50
Temperature (°C)
Frequency (MHz)
DAC904
SBAS095C
9
www.ti.com
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
FOUR-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
Frequency (MHz)
The segmented architecture results in a significant reduction
of the glitch energy, and improves the dynamic performance
(SFDR) and DNL. The current outputs maintain a very high
output impedance of greater than 200kΩ.
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC904 uses the current steering
technique to enable fast switching and a high update rate. The
core element within the monolithic DAC is an array of seg-
mented current sources that are designed to deliver a full-scale
output current of up to 20mA, as shown in Figure 1. An internal
decoder addresses the differential current switches each time
the DAC is updated and a corresponding output current is
formed by steering all currents to either output summing node,
IOUT or IOUT. The complementary outputs deliver a differential
output signal that improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by a
factor of two, compared to single-ended operation.
The full-scale output current is determined by the ratio of the
internal reference voltage (1.24V) and an external resistor,
R
SET. The resulting IREF is internally multiplied by a factor of
32 to produce an effective DAC output current that can range
from 2mA to 20mA, depending on the value of RSET
.
The DAC904 is split into a digital and an analog portion, each
of which is powered through its own supply pin. The digital
section includes edge-triggered input latches and the de-
coder logic, while the analog section comprises the current
source array with its associated switches and the reference
circuitry.
+3V to +5V
Digital
+3V to +5V
Analog
0.1µF(1)
Bandwidth
Control
BW
+VA
+VD
DAC904
Full-Scale
Adjust
Resistor
IOUT
IOUT
1:1
VOUT
LSB
Switches
FSA
PMOS
Current
Source
Array
Ref
Control
Amp
Ref
Input REFIN
Segmented
MSB
Switches
50Ω
400pF
RSET
2kΩ
20pF(1)
50Ω
20pF(1)
0.1µF
0.1µF
BYP
INT/EXT
Ref
Buffer
Latches and Switch
Decoder Logic
PD
Power Down
+1.24V Ref
(internal pull-down)
14-Bit Data Input
D13...D0
AGND
Analog
CLK
DGND
Clock
Input
Digital
Ground
Ground
NOTE: Supply bypassing not shown.
NOTE: (1) Optional.
FIGURE 1. Functional Block Diagram of the DAC904.
10
DAC904
SBAS095C
www.ti.com
DAC TRANSFER FUNCTION
The total output current, IOUTFS, of the DAC904 is the sum-
mation of the two complementary output currents:
+VA
DAC904
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/16384)
(2)
(3)
IOUT
RL
IOUT
RL
IOUT = IOUTFS • (16383 – Code/16384)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the reference
current IREF, which is determined by the reference voltage
FIGURE 2. Equivalent Analog Output.
and the external setting resistor, RSET
.
+VD = 5V. Note that the compliance range decreases to
about 1V for a selected output current of IOUTFS = 2mA.
Care should be taken that the configuration of the DAC904
does not exceed the compliance range to avoid degradation
of the distortion performance and integral linearity.
IOUTFS = 32 • IREF = 32 • VREF/RSET
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5V. This is the case for a 50Ω doubly-terminated load and
a 20mA full-scale output current. A variety of loads can be
adapted to the output of the DAC904 by selecting a suitable
transformer while maintaining optimum voltage levels at
IOUT and IOUT. Furthermore, using the differential output
configuration in combination with a transformer will be instru-
mental for achieving excellent distortion performance. Com-
mon-mode errors, such as even-order harmonics or noise,
can be substantially reduced. This is particularly the case
with high output frequencies and/or output amplitudes below
full-scale.
VOUT = IOUT • RLOAD
(5)
(6)
VOUT = IOUT • RLOAD
The value of the load resistance is limited by the output
compliance specification of the DAC904. To maintain speci-
fied linearity performance, the voltage for IOUT and IOUT
should not exceed the maximum allowable compliance range.
The two single-ended output voltages can be combined to
find the total differential output swing:
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a reduced performance level.
(7)
(2 • Code – 16383)
VOUTDIFF = VOUT – VOUT
=
• IOUTFS • RLOAD
16384
ANALOG OUTPUTS
The DAC904 provides two complementary current outputs,
IOUT and IOUT. The simplified circuit of the analog output
stage representing the differential topology is shown in
Figure 2. The output impedance of 200kΩ 12pF for IOUT
and IOUT results from the parallel combination of the differen-
tial switches, along with the current sources and associated
parasitic capacitances.
INPUT CODE (D13 - D0)
IOUT
IOUT
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0000
20mA
10mA
0mA
0mA
10mA
20mA
TABLE I. Input Coding versus Analog Output Current.
OUTPUT CONFIGURATIONS
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the break-
down voltage of the CMOS process, and exceeding it will
compromise the reliability of the DAC904, or even cause
permanent damage. With the full-scale output set to 20mA,
the positive compliance equals 1.25V, operating with
The current output of the DAC904 allows for a variety of
configurations, some of which are illustrated below. As men-
tioned previously, utilizing the converter’s differential outputs
will yield the best dynamic performance. Such a differential
output circuit may consist of an RF transformer (see Figure 3)
or a differential amplifier configuration (see Figure 4). The
DAC904
SBAS095C
11
www.ti.com
DIFFERENTIAL CONFIGURATION USING AN OP AMP
transformer configuration is ideal for most applications with ac
coupling, while op amps will be suitable for a DC-coupled
configuration.
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feed-
back op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC904 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor values
shown were selected to result in a symmetric 25Ω loading for
each of the current outputs since the input impedance of the
difference amplifier is in parallel to resistors RL, and should
be considered.
The single-ended configuration (see Figure 6) may be consid-
ered for applications requiring a unipolar output voltage. Con-
necting a resistor from either one of the outputs to ground will
convert the output current into a ground-referenced voltage
signal. To improve on the DC linearity, an I-to-V converter can
be used instead. This will result in a negative signal excursion
and, therefore, requires a dual supply amplifier.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance, as
shown in Figure 3. The appropriate transformer should be
carefully selected based on the output frequency spectrum
and impedance requirements. The differential transformer
configuration has the benefit of significantly reducing com-
mon-mode signals, thus improving the dynamic performance
over a wide range of frequencies. Furthermore, by selecting
a suitable impedance ratio (winding ratio), the transformer
can be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
The model shown in Figure 3 has a 1:1 ratio and may be
used to interface the DAC904 to a 50Ω load. This results in
a 25Ω load for each of the outputs, IOUT and IOUT. The output
signals are ac coupled and inherently isolated because of the
transformer's magnetic coupling.
R2
402Ω
R1
200Ω
IOUT
VOUT
DAC904
IOUT
OPA680
R3
200Ω
CDIFF
–5V +5V
RL
28.7Ω
R4
402Ω
RL
26.1Ω
FIGURE 4. Difference Amplifier Provides Differential to Single-
Ended Conversion and AC-Coupling.
As shown in Figure 3, the transformer’s center tap is con-
nected to ground. This forces the voltage swing on IOUT and
The OPA680 is configured for a gain of 2. Therefore, oper-
ating the DAC904 with a 20mA full-scale output will produce
a voltage output of ±1V. This requires the amplifier to operate
off of a dual power supply (±5V). The tolerance of the
resistors typically sets the limit for the achievable common-
mode rejection. An improvement can be obtained by fine
tuning resistor R4.
I
OUT to be centered at 0V. In this case the two resistors, RS,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be ob-
served. Alternatively, if the center tap is not connected, the
signal swing will be centered at RS • IOUTFS/2. However, in
this case, the two resistors (RS) must be used to enable the
necessary DC-current flow for both outputs.
This configuration typically delivers a lower level of ac perfor-
mance than the previously discussed transformer solution
because the amplifier introduces another source of distor-
tion. Suitable amplifiers should be selected based on their
slew-rate, harmonic distortion, and output swing capabilities.
High-speed amplifiers like the OPA680 or OPA687 may be
considered. The ac performance of this circuit may be
improved by adding a small capacitor, CDIFF, between the
ADT1-1WT
(Mini-Circuits)
1:1
IOUT
outputs IOUT and IOUT, as shown in Figure 4. This will introduce
RS
50Ω
a real pole to create a low-pass filter in order to slew-limit the
DAC’s fast output signal steps that otherwise could drive the
amplifier into slew-limitations or into an overload condition;
both would cause excessive distortion. The difference ampli-
fier can easily be modified to add a level shift for applications
requiring the single-ended output voltage to be unipolar, i.e.,
swing between 0V and +2V.
Optional
RDIFF
DAC904
RL
IOUT
RS
50Ω
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
DAC904
12
SBAS095C
www.ti.com
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The full-scale output voltage is defined by the product of
IOUTFS • RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
The circuit example of Figure 5 shows the signal output
currents connected into the summing junction of the OPA2680,
which is set up as a transimpedance stage, or I-to-V con-
verter. With this circuit, the DAC’s output will be kept at a
virtual ground, minimizing the effects of output impedance
variations, and resulting in the best DC linearity (INL). How-
ever, as mentioned previously, the amplifier may be driven
into slew-rate limitations, and produce unwanted distortion.
This may occur especially at high DAC update rates.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25Ω load.
+5V
50Ω
1/2
OPA2680
–VOUT = IOUT • RF
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor may be mutually
adjusted to provide the desired output signal swing and
performance.
RF1
DAC904
CF1
IOUT
CD1
RF2
CF2
IOUTFS = 20mA
VOUT = 0V to +0.5V
CD2
IOUT
IOUT
DAC904
1/2
OPA2680
IOUT
50Ω
50Ω
–VOUT = IOUT • RF
25Ω
50Ω
–5V
FIGURE 6. Driving a Doubly-Terminated 50Ω Cable Directly.
FIGURE5.Dual,Voltage-FeedbackAmplifierOPA2680Forms
Differential Transimpedance Amplifier.
INTERNAL REFERENCE OPERATION
The DAC904 has an on-chip reference circuit that comprises
a 1.24V bandgap reference and a control amplifier. Ground-
ing pin 16, INT/EXT, enables the internal reference opera-
tion. The full-scale output current, IOUTFS, of the DAC904 is
determined by the reference voltage, VREF, and the value of
resistor RSET. IOUTFS can be calculated by:
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2
)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise-gain
peaking. To achieve a flat transimpedance frequency re-
sponse, the pole in each feedback network should be set to:
IOUTFS = 32 • IREF = 32 • VREF / RSET
(10)
The external resistor RSET connects to the FSA pin (Full-
Scale Adjust), see Figure 7. The reference control amplifier
operates as a V-to-I converter producing a reference current,
1
GBP
=
(8)
2πRFCF 4πRFCD
with GBP = Gain Bandwidth Product of OPA,
I
REF, which is determined by the ratio of VREF and RSET, as
shown in Equation 10. The full-scale output current, IOUTFS
,
which will give a corner frequency f-3dB of approximately:
results from multiplying IREF by a fixed factor of 32.
GBP
f−3dB
=
(9)
2πRFCD
DAC904
SBAS095C
13
www.ti.com
Optional
Bandlimiting
Capacitor
+5V
CCOMPEXT
0.1µF
+5V
CCOMPEXT
0.1µF
BW
+VA
DAC904
BW
+VA
DAC904
VREF
RSET
VREF
RSET
IREF
=
IREF
=
FSA
FSA
Ref
Control
Amp
Current
Sources
Ref
Control
Amp
Current
Sources
REFIN
External
Reference
REFIN
CCOMP
400pF
RSET
CCOMP
400pF
2kΩ
INT/EXT
RSET
0.1µF
+5V
INT/EXT
+1.24V Ref.
+1.24V Ref.
FIGURE 8. External Reference Configuration.
FIGURE 7. Internal Reference Configuration.
Using the internal reference, a 2kΩ resistor value results in a
20mA full-scale output. Resistors with a tolerance of 1% or
better should be considered. Selecting higher values, the con-
verter output can be adjusted from 20mA down to 2mA.
Operating the DAC904 at lower than 20mA output currents may
be desirable for reasons of reducing the total power consump-
tion, improving the distortion performance, or observing the
output compliance voltage limitations for a given load condition.
DIGITAL INPUTS
The digital inputs, D0 (LSB) through D13 (MSB) of the
DAC904 accepts standard-positive binary coding. The digital
input word is latched into a master-slave latch with the rising
edge of the clock. The DAC output becomes updated with
the following falling clock edge (refer to the electrical charac-
teristic table and timing diagram for details). The best perfor-
mance will be achieved with a 50% clock duty cycle, how-
ever, the duty cycle may vary as long as the timing specifi-
cations are met. Additionally, the setup and hold times may
be chosen within their specified limits.
It is recommended to bypass the REFIN pin with a ceramic chip
capacitor of 0.1µF or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
1.3MHz. For optional ac performance, an additional capacitor
(CCOMPEXT) should be applied between the BW pin and the
analog supply, +VA, as shown in Figure 7. Using a 0.1µF
capacitor, the small-signal bandwidth and output impedance of
the control amplifier is further diminished, reducing the noise
that is fed into the current source array. This also helps shunting
feedthrough signals more effectively, and improving the noise
performance of the DAC904.
All digital inputs are CMOS compatible. The logic thresholds
depend on the applied digital supply voltage such that they
are set to approximately half the supply voltage;
Vth = +VD/2 (±20% tolerance). The DAC904 is designed to
operate over a supply range of 2.7V to 5.5V.
POWER-DOWN MODE
The DAC904 features a power-down function that can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic HIGH
to the PD pin will initiate the power-down mode, while a logic
LOW enables normal operation. When left unconnected, an
internal active pull-down circuit will enable the normal opera-
tion of the converter.
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by applying a logic
HIGH (+VA) to pin INT/EXT. An external reference voltage
can then be driven into the REFIN pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
GROUNDING, DECOUPLING, AND
LAYOUT INFORMATION
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external refer-
ence should stay within the compliance range of the refer-
ence input (0.1V to 1.25V).
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
DAC904
14
SBAS095C
www.ti.com
The DAC904 uses separate pins for its analog and digital
supply and ground connections. The placement of the decou-
pling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most cases
0.1µF ceramic chip capacitors at each supply pin are ad-
equate to provide a low impedance decoupling path. Keep in
mind that their effectiveness largely depends on the proximity
to the individual supply and ground pins. Therefore, they
should be located as close as physically possible to those
device leads. Whenever possible, the capacitors should be
located immediately under each pair of supply/ground pins
on the reverse side of the pc-board. This layout approach will
minimize the parasitic inductance of component leads and
pcb runs.
different supply currents and signal traces. Generally, analog
supply and ground planes should only extend into analog
signal areas, such as the DAC output signal and the refer-
ence signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can be
realized with a short track of approximately 1/8 inch (3mm).
The power to the DAC904 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decou-
pling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc-board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage that can then be
connected to the +VA supply pin of the DAC904.
Further supply decoupling with surface mount tantalum ca-
pacitors (1µF to 4.7µF) may be added as needed in proximity
of the converter.
Low noise is required for all supply and ground connections
to the DAC904. It is recommended to use a multilayer pc-
board utilizing separate power and ground planes. Mixed
signal designs require particular attention to the routing of the
While designing the layout, it is important to keep the analog
signal traces separate from any digital line, in order to
prevent noise coupling onto the analog signal path.
DAC904
SBAS095C
15
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DAC904E
DAC904E/2K5
DAC904E/2K5G4
DAC904EG4
DAC904U
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
DW
DW
DW
DW
28
28
28
28
28
28
28
28
50
2500
2500
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
20
Green (RoHS
& no Sb/Br)
DAC904U/1K
DAC904U/1KG4
DAC904UG4
SOIC
1000
1000
20
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC904E/2K5
DAC904U/1K
TSSOP
SOIC
PW
DW
28
28
2500
1000
330.0
330.0
16.4
32.4
6.9
10.2
1.8
3.1
12.0
16.0
16.0
32.0
Q1
Q1
11.35 18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC904E/2K5
DAC904U/1K
TSSOP
SOIC
PW
DW
28
28
2500
1000
367.0
367.0
367.0
367.0
38.0
55.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明