DAC91001 [TI]
具有超低噪声、低干扰和出色 THD 的 18 位单调 DAC;
| 型号： | DAC91001 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有超低噪声、低干扰和出色 THD 的 18 位单调 DAC |
| 文件： | 总52页 (文件大小：3244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
DACx1001 20 位、18 位和 16 位的低噪声、超低谐波失真、快速趋稳、高
电压输出数模转换器 (DAC)
1 特性
3 说明
1
•
•
•
•
20 位单调性：1-LSB DNL（最大值）
20 位 DAC11001A、18 位 DAC91001 和 16 位
DAC81001 (DACx1001) 是高精度、低噪声、电压输
出、单通道数模转换器 (DAC)。DACx1001 根据设计
具有单调性，可以在所有范围内提供低于 4LSB（最大
值）的出色线性度。
积分线性：4-LSB INL（最大值）
低噪声：7nV/√Hz
独立于代码的低干扰：
1nV-s
•
•
•
•
•
出色的 THD：1kHz fOUT 时为 -105 dB
快速趋稳：1µs
非缓冲电压输出可提供低噪声性能 (7nV/√Hz) 和快速
稳定时间 (1µs)，因此这款器件非常适合低噪声、快速
控制环路和波形生成 应用中的数字输入 D 类音频放大
器。DACx1001 兼具增强型抗尖峰脉冲电路以及独立
于代码的超低干扰 (1nV-s)，可实现干净的波形斜升和
超低总谐波失真 (THD)。
灵活的输出范围：VREFPF 至 VREFNF
集成式精密反馈电阻器
50MHz、4 线 SPI 兼容接口
–
–
读回
菊花链
DACx1001 器件包含上电复位电路，因此 DAC 能够使
用寄存器中的已知值供电。使用外部基准，可以实现
•
•
温度范围：-40°C 至 +125°C
封装：48 引脚 TQFP
VREFPF 到 VREFNF 的 DAC 输出，包括非对称输出范
2 应用
围。
•
•
•
•
•
•
•
•
•
实验室和现场仪表
DACx1001 使用一个在高达 50MHz 的时钟频率下运行
的通用 4 线串行接口。DACx1001 的额定工业工作温
度范围为 -40°C 至 +125°C。
光谱仪
模拟输出模块
电池测试
器件信息(1)
半导体测试
器件型号
DAC11001
封装
封装尺寸（标称值）
任意波形发生器 (AWG)
MRI
DAC91001（预发布） TQFP (48)
DAC81001（预发布）
7.00mm × 7.00mm
X 射线系统
专业音频放大器（机架式）
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
功能方框图
高精度控制环路电路
Gain/
Attenuation
IOVDD DVDD VCC
AVDD
REFPS
REFPF
THS4011
C1
Sensor
Output
+
VREFP
ROFS
RCM
REFPS
REFPF
REFNS
REFNF
SCLK
SDIN
œ
œ
Linear
Actuator
Power
Amplifier
+
DACx1001
THS4011
Power On Reset
C2
THS4011
œ
SYNC
SDO
RFB
OUT
+
VREFN
Buffer
Registers
DAC
Register
DAC
LDAC
CLR
Power
Down Logic
ALARM
REFNF
REFNS
DGND
VSS AGND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEL0
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 25
8.5 Programming........................................................... 26
8.6 Register Map........................................................... 28
Application and Implementation ........................ 33
9.1 Application Information............................................ 33
9.2 Typical Application ................................................. 33
9.3 System Examples .................................................. 38
9.4 What to Do and What Not to Do ............................ 41
9.5 Initialization Set Up ................................................ 41
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information Package................................... 6
7.5 Electrical Characteristics........................................... 7
9
10 Power Supply Recommendations ..................... 42
10.1 Power-Supply Sequencing.................................... 44
11 Layout................................................................... 45
11.1 Layout Guidelines ................................................. 45
11.2 Layout Example .................................................... 45
12 器件和文档支持 ..................................................... 46
12.1 器件支持................................................................ 46
12.2 文档支持................................................................ 46
12.3 相关链接................................................................ 46
12.4 接收文档更新通知 ................................................. 46
12.5 支持资源................................................................ 46
12.6 商标....................................................................... 46
12.7 静电放电警告......................................................... 46
12.8 Glossary................................................................ 46
13 机械、封装和可订购信息....................................... 46
7.6 Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5
V............................................................................... 10
7.7 Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5
V............................................................................... 11
7.8 Timing Requirements: Read and Daisy-Chain
Write, 4.5 V ≤ DVDD ≤ 5.5 V..................................... 12
7.9 Timing Requirements: Read and Daisy-Chain Write,
2.7 V ≤ DVDD < 4.5 V............................................... 13
7.10 Typical Characteristics.......................................... 15
Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 22
8
4 修订历史记录
Changes from Original (October 2019) to Revision A
Page
•
已更改 将 DAC11001A 器件从“预告信息（预发布）”更改为“生产数据（正在供货）” ........................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
5 Device Comparison Table
DEVICE
RESOLUTION
20-bit
DAC11001A
DAC91001 (preview)
DAC81001 (preview)
18-bit
16-bit
6 Pin Configuration and Functions
PFB Package
48-Pin TQFP
Top View
NC
AGND
REFPF
REFPS
REFNF
REFNS
OUT
1
36
35
34
33
32
31
30
29
28
27
26
25
NC
2
AGND
SDO
SYNC
SDIN
SCLK
CLR
3
4
5
6
7
AGND-OUT
RFB
8
NC
9
IOVDD
DVDD
DGND
NC
ROFS
10
11
12
RCM
NC
Not to scale
Copyright © 2019, Texas Instruments Incorporated
3
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
2, 35, 38,
40, 42, 43,
46, 47
Analog
ground
AGND
Connect to 0 V.
Analog
ground
AGND-OUT
AGND-TnH
8
Connect to 0 V. Measure DAC output voltage with respect to this node.
Connect to 0 V. Integrated deglitcher clock ground..
Analog
ground
14
ALARM
AVDD
CLR
19
39, 41
30
Output
Power
Input
Alarm output
Positive low voltage analog power supply
DAC registers clear pin, active low
16, 17, 20,
21, 22, 23,
26
Digital
ground
DGND
Connect to 0 V.
DVDD
RFB
27
9
Power
Input
Digital power supply pin
Integrated precision resistor feedback node
Interface power supply pin
IOVDD
LDAC
28
18
Power
Input
Load DAC pin, active low
1, 12, 13,
15, 24, 25,
29, 36, 37,
48
NC
—
No connection, leave floating
OUT
7
11
5
Output
Input
Input
Input
Input
Input
Input
Unbuffered voltage output
RCM
Integrated precision resistor common-mode node
External negative reference input. Connect to 0 V for unipolar DAC output.
External negative reference sense node
External positive reference input
REFNF
REFNS
REFPF
REFPS
ROFS
6
3
4
External positive reference sense node
Integrated precision resistor offset node
10
Serial clock input of serial peripheral interface (SPI). Schmitt-trigger logic input.
Data are transferred at rates of up to 50 MHz.
SCLK
31
Input
Serial data input. Schmitt-trigger logic input.
Data are clocked into the input shift register on the falling edge of the serial clock input.
SDIN
SDO
32
34
33
Input
Output
Input
Serial data output. Data are valid on the falling edge of SCLK.
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless
SYNC is low. When SYNC is high, the SDO pin is in high-impedance status.
SYNC
VCC
VSS
45
44
Power
Power
Analog positive power supply
Analog negative power supply
4
Copyright © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
AVDD to AGND
7
Positive supply voltage
Negative supply voltage
Positive reference voltage
VCC to VSS
–0.3
40
V
V
V
VCC to AGND
–0.3
40
VSS to AGND
–19
0.3
VREFPF to VREFNF
VREFPF to VCC
VREFPF to AGND
VREFNF to AGND
VREFNF to VSS
–0.3
40
–0.3
VCC + 0.3
–0.3
40
–19
0.3
Negative reference voltage
V
VSS – 0.3
–0.3
0.3
7
Digital and IO power supply
Digital input(s) to DGND
DVDD, IOVDD to DGND
V
V
DGND – 0.3
VSS
IOVDD + 0.3
VCC
to AGND (VSS = AGND)
to VSS
VOUT, VRFB, VRCM, VROFS
V
0
VCC
Alarm pin voltage, ALARM to DGND
Digital output, SDO to DGND
Current into any pin
–0.3
DVDD + 0.3
DVDD + 0.3
10
V
V
–0.3
–10
mA
°C
°C
TJ
Junction temperature
150
Tstg
Storage temperature
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±1000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2019, Texas Instruments Incorporated
5
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
5.5
–3
UNIT
V
AVDD to AGND
4.5
VSS to AGND
–18
V
VCC to AGND
8
33
V
VCC to VSS
11
2.7
36
V
DVDD to DGND
5.5
5.5
0.3
V
IOVDD to DGND
AGND to DGND
VIH digital input high voltage
VIL digital input low voltage
VREFPF to AGND
VREFNF to AGND
VREFPF to VREFNF
1.7
V
–0.3
V
0.7 × IOVDD
V
0.3 × IOVDD
V
3
–15
3
15
0
V
V
30
V
TA
Operating temperature
–40
125
°C
7.4 Thermal Information Package
DAC11001A, DAC91001,
DAC81001
THERMAL METRIC(1)
UNIT
PFB (TQFP)
48 PINS
51.0
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
10.3
16.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJB
16.0
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
7.5 Electrical Characteristics
at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and
VREFNF, 20-bit orderable used, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical
specifications at TA = 25°C, (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX UNIT
DAC11001A
20
18
Resolution
DAC91001
DAC81001
Bits
16
Relative accuracy(2)
–4
4
INL
Relative accuracy(2)(3)(4)
Relative accuracy(2)(4)
Relative accuracy drift over time(2)
Differential nonlinearity(2)(3)
–2.6
–2
2.6
2
LSB
DACx1001A TA = 25°C
TA = 25°C, 1000 hrs
0.1
LSB
LSB
DNL
–1
–4
1
4
TA = 0°C to 70°C, code 0d into DAC,
unipolar ranges only
Zero code error(4)
TA = –40°C to +125°C, code 0d into
DAC, unipolar ranges only
LSB
–4
4
TA = 25°C, unipolar ranges only
±2
TA = 0°C to 70°C, code 0d into DAC,
unipolar ranges only
±0.04
ppm
FSR/°C
Zero code error temperature coefficient
TA = –40°C to +125°C, code 0d into
DAC, unipolar ranges only
±0.04
TA = 0°C to 70°C
–8
–8
8
8
TA = 0°C to 70°C, VREFPF = 3 V,
VREFNF = –10 V
ppm of
FSR
Gain error(2)(4)
TA = –40°C to +125°C
TA = 25°C
–10
10
±2
TA = 0°C to 70°C
±0.04
TA = 0°C to 70°C, VREFPF = 3 V,
VREFNF = –10 V
ppm
FSR/°C
Gain error temperature coefficient
±0.04
±0.04
TA = –40°C to +125°C
TA = 0°C to 70°C, code 1048575d into
DAC
–8
–6
8
6
TA = 0°C to 70°C, code 1048575d into
DAC, VREFPF = 3 V, VREFNF = –10 V
Positive full-scale error(4)
LSB
TA = –40°C to +125°C, code 1048575d
into DAC
–10
10
TA = 25°C
±2
TA = 0°C to 70°C
±0.04
TA = 0°C to 70°C, VREFPF = 3 V,
VREFNF = –10 V
ppm
FSR/°C
Full-scale error temperature coefficient
±0.04
±0.04
TA = –40°C to +125°C
OUTPUT CHARACTERISTICS
Headroom
From VREFPF to VCC
From VREFNF to VSS
From ROFS to RCM
From RCM to RFB
3
3
V
V
Footroom
5
5
DC impedance
kΩ
kΩ
ZO
DC output impedance
2.5
(1) Specified for the following pairs: VREFPF = 5 V and VREFNF = 0 V; VREFPF = 10 V and VREFNF = 0 V; VREFPF = +5 V and VREFNF = –5 V;
VREFPF = +10 V and VREFNF = –10 V.
(2) Calculated between code 0d to 1048575d.
(3) With device temperature calibration mode enabled and used.
(4) Specified by design, not production tested.
Copyright © 2019, Texas Instruments Incorporated
7
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and
VREFNF, 20-bit orderable used, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical
specifications at TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C, VCC = 15 V ± 20%,
VSS = –15 V
1.5
Power supply rejection ratio (dc)
µV/V
TA = 25°C, VCC = 15 V,
VSS = –15 V ± 20%
1
VOLTAGE REFERENCE INPUT
DAC at midscale, VREFPF = 10 V,
VREFNF = 0 V
Reference input impedance (REFPF)
Reference input impedance (REFNF)
5.5
7
kΩ
DAC at midscale, VREFPF = 10 V,
VREFNF = 0 V
DYNAMIC PERFORMANCE
VREFPF = 10 V, VREFNF = 0 V,
full-scale settling to 0.1%FSR
1
2.5
2.5
50
VREFPF = 10 V, VREFNF = 0 V,
full-scale settling to ±1 LSB
ts
Output voltage settling time(5)
µs
VREFPF = 10 V, VREFNF = 0 V,
1-mV step settling to ±1 LSB
VREFPF = 10 V, VREFNF = 0 V, full-scale
step, measured at OUT pin
SR
Slew rate
V/µs
V
Measured at unbuffered DAC voltage
output, VREFPF = 10 V, VREFNF = 0 V
Power-on glitch magnitude
–0.2
0.4
3
0.1-Hz to 10-Hz, DAC at midscale,
VREFPF = 10 V, VREFNF = 0 V
µVpp
µVrms
Vn
Output noise
100-kHz bandwidth, DAC at midscale,
VREFPF = 10 V, VREFNF = 0 V
Measured at 1 kHz, 10 kHz, 100 kHz,
DAC at mid scale, VREFPF = 10 V,
VREFNF = 0 V
Output noise density
Spurious free dynamic range
7
nV/√Hz
DAC update rate = 400 kHz, fOUT = 1
kHz, VOUTPP = 0 V to 10 V
–105
–105
–105
–105
95
dB
dB
dB
dB
dB
dB
SFDR
THD
DAC update rate = 400 kHz, fOUT = 1
kHz, VOUTPP = 3 V to –10 V
DAC update rate = 400 kHz, fOUT = 1
kHz, VOUTPP = 0 V to 10 V
Total harmonic distortion
DAC update rate = 400 kHz, fOUT = 1
kHz, VOUTPP = 3 V to –10 V
200-mV 50-Hz or 60-Hz sine wave
superimposed on VSS, VCC = 15 V
Power supply rejection ratio (ac)
200-mV 50 Hz or 60 Hz sine wave
superimposed on VCC, VSS = –15 V
95
±1 LSB change around mid code
(including feedthrough), VREFPF = 10 V,
VREFNF = 0 V, measured at output of
buffer op amp
Code change glitch impulse
1
5
nV-s
mV
±1 LSB change around mid code
(including feedthrough), VREFPF = 10 V,
VREFNF = 0 V, measured at output of
buffer op amp
Code change glitch impulse magnitude
VREFPF = 10 V ± 10%, VREFNF = 0 V,
frequency = 100 Hz, DAC at zero scale
Reference feedthrough
Reference feedthrough
–90
–90
dB
dB
VREFNF = –10 V ± 10%, VREFPF = 10 V,
frequency = 100 Hz, DAC at full scale
(5) Adaptive TnH mode. TnH action is disabled for large code steps. For small steps, TnH action happens with a hold time of 1.2µs.
8
Copyright © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and
VREFNF, 20-bit orderable used, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical
specifications at TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
At SCLK = 1 MHz, DAC output static at
midscale, 10-V range
Digital feedthrough
1
nV-s
DIGITAL INPUTS
Hysteresis voltage
Input current
0.4
±5
10
V
µA
pF
Pin capacitance
Per pin
DIGITAL OUTPUTS
VOL
Output low voltage
sinking 200 µA
0.4
V
V
IOVDD
–
VOH
Output high voltage
sourcing 200 µA
0.5
High impedance leakage
±5
10
µA
pF
High impedance output capacitance
POWER
VREFPF = 10 V, VREFNF = 0 V, midscale
code
IAVDD
Current flowing into AVDD
Current flowing into VCC
Current flowing into VSS
Current flowing into DVDD
Current flowing into IOVDD
1.5
7
mA
mA
mA
mA
mA
mA
mA
VREFPF = 10 V, VREFNF = 0 V, midscale
code
IVCC
VREFPF = 10 V, VREFNF = 0 V, midscale
code
IVSS
7
VREFPF = 10 V, VREFNF = 0 V, midscale
code
IDVDD
IIOVDD
IREFPF
IREFNF
0.5
0.1
VREFPF = 10 V, VREFNF = 0 V, midscale
code, all digital input pins static at IOVDD
VREFPF = 10 V, VREFNF = 0 V, midscale
code
Reference input current (VREFPF
)
5
5
VREFPF = 10 V, VREFNF = 0 V, midscale
code
Reference input current (VREFNF
)
Copyright © 2019, Texas Instruments Incorporated
9
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
7.6 Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2,
SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
33
UNIT
SCLK frequency, 1.7 V ≤ IOVDD < 2.7 V
fSCLK
MHz
SCLK frequency, 2.7 V ≤ IOVDD ≤ 5.5 V
50
SCLK high time, 1.7 V ≤ IOVDD < 2.7 V
15
10
15
10
13
8
tSCLKHIGH
tSCLKLOW
tSDIS
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK low time, 1.7 V ≤ IOVDD < 2.7 V
SCLK low time, 2.7 V ≤ IOVDD ≤ 5.5 V
SDI setup, 1.7 V ≤ IOVDD < 2.7 V
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V
SDI hold, 1.7 V ≤ IOVDD < 2.7 V
13
8
tSDIH
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V
SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SYNC high time, 1.7 V ≤ IOVDD < 2.7 V
23
18
15
10
55
50
10
5
tCSS
tCSH
tCSHIGH
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V
tCSIGNORE
Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤
IOVDD < 2.7 V
50
50
tLDACSL
ns
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤
IOVDD ≤ 5.5 V
LDAC low time, 1.7 V ≤ IOVDD < 2.7 V
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V
CLR low time, 1.7 V ≤ IOVDD < 2.7 V
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V
20
20
20
20
tLDACW
ns
ns
tCLRW
10
Copyright © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
7.7 Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2,
SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
20
UNIT
SCLK frequency, 1.7 V ≤ IOVDD < 2.7 V
fSCLK
MHz
SCLK frequency, 2.7 V ≤ IOVDD ≤ 5.5 V
25
SCLK high time, 1.7 V ≤ IOVDD < 2.7 V
25
20
25
20
21
16
21
16
41
36
25
20
100
100
10
5
tSCLKHIGH
tSCLKLOW
tSDIS
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK low time, 1.7 V ≤ IOVDD < 2.7 V
SCLK low time, 2.7 V ≤ IOVDD ≤ 5.5 V
SDI setup, 1.7 V ≤ IOVDD < 2.7 V
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V
SDI hold, 1.7 V ≤ IOVDD < 2.7 V
tSDIH
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V
SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SYNC high time, 1.7 V ≤ IOVDD < 2.7 V
tCSS
tCSH
tCSHIGH
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V
tCSIGNORE
Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤
IOVDD < 2.7 V
100
100
tLDACSL
ns
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤
IOVDD ≤ 5.5 V
LDAC low time, 1.7 V ≤ IOVDD < 2.7 V
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V
CLR low time, 1.7 V ≤ IOVDD < 2.7 V
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V
40
40
40
40
tLDACW
ns
ns
tCLRW
Copyright © 2019, Texas Instruments Incorporated
11
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
7.8 Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2,
SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX UNIT
1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
10
20
fSCLK
SCLK frequency
SCLK high time
SCLK low time
MHz
15
30
50
25
33
16
50
25
33
16
13
8
tSCLKHIGH
ns
tSCLKLOW
ns
SDI setup, 1.7 V ≤ IOVDD < 2.7 V
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V
SDI hold, 1.7 V ≤ IOVDD < 2.7 V
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V
tSDIS
ns
ns
ns
ns
ns
ns
13
8
tSDIH
SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SYNC high time, 1.7 V ≤ IOVDD < 2.7 V
30
20
15
10
55
50
10
5
tCSS
tCSH
tCSHIGH
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V
tCSIGNORE
Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD
2.7 V
<
50
50
tLDACSL
ns
ns
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD
5.5 V
≤
LDAC low time, 1.7 V ≤ IOVDD < 2.7 V
20
20
20
20
0
tLDACW
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V
CLR low time, 1.7 V ≤ IOVDD < 2.7 V
tCLRW
ns
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
SCLK falling edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
SCLK falling edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V
SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V
35
0
25
ns
35
tSDODLY
0
0
25
0
20
ns
20
tSDOZ
0
12
Copyright © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
7.9 Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2,
SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX UNIT
1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
8
16
fSCLK
SCLK frequency
SCLK high time
SCLK low time
MHz
10
20
62
31
50
25
62
31
50
25
21
16
21
16
41
36
25
20
100
100
10
5
tSCLKHIGH
ns
tSCLKLOW
ns
SDI setup, 1.7 V ≤ IOVDD < 2.7 V
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V
SDI hold, 1.7 V ≤ IOVDD < 2.7 V
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V
tSDIS
ns
ns
ns
ns
ns
ns
tSDIH
SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V
SYNC high time, 1.7 V ≤ IOVDD < 2.7 V
tCSS
tCSH
tCSHIGH
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V
tCSIGNORE
Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD
2.7 V
<
100
100
tLDACSL
ns
ns
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD
5.5 V
≤
LDAC low time, 1.7 V ≤ IOVDD < 2.7 V
40
40
40
40
0
tLDACW
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V
CLR low time, 1.7 V ≤ IOVDD < 2.7 V
tCLRW
ns
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V
SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0
SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0
SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1
SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1
SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V
SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V
40
0
30
ns
40
tSDODLY
0
0
30
0
20
ns
20
tSDOZ
0
版权 © 2019, Texas Instruments Incorporated
13
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
tCSS
tCSH
tCSHIGH
SYNC
SCLK
tCSIGNORE
tSCLKLOW
tSCLKHIGH
tSDIH
Bit 31
tSDIS
SDIN
Bit 1
Bit 0
LDAC1
tCLRW
tLDACSL tLDACW
CLR
图 1. Serial Interface Write Timing: Standalone Mode
tCSHIGH
tCSS
tCSH
SYNC
SCLK
tCSIGNOR
E
tSCLKLOW
tSCLKHIGH
FIRST READ COMMAND
Bit 22
ANY COMMAND
Bit 22
SDIN
Bit 31
Bit 0
Bit 31
Bit 0
tSDIH
tSDIS
DATA FROM FIRST
READ COMMAND
SDO
Bit 31
Bit 22
Bit 0
tSDODZ
tSDODLY
LDAC1
tCLRW
tLDACSL tLDACW
CLR
图 2. Serial Interface Read and Write Timing: Daisy-Chain Mode
14
版权 © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
7.10 Typical Characteristics
at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as
output and reference amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)
4
3
1
0.8
0.6
0.4
0.2
0
2
1
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
UP, 5 V
UP, 10 V
BP, 10 V
UP, 10 V (gain = 2x)
UP, 5 V
UP, 10 V
BP, 10 V
UP, 10 V, [gain = 2x]
0
262144
524288
Code
786432
1048575
0
262144
524288
Code
786432
1048575
图 3. . Integral Linearity Error vs Digital Input Code
图 4. Differential Linearity Error vs Digital Input Code
4
1
0.8
3
2
1
0
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
INL max, UP, 5 V
INL max, UP, 10 V
INL max, BP, 10 V
INL min, UP, 5 V
INL min, UP, 10 V
INL min, BP, 10 V
INL max, UP, 10 V, [gain 2x]
INL min, UP, 10 V, [gain 2x]
DNL max, UP, 5 V
DNL max, UP, 10 V
DNL max, BP, 10 V
DNL min, UP, 5 V
DNL min, UP, 10 V
DNL min, BP, 10 V
DNL max, UP, 10 V [gain 2x]
DNL min, UP, 10 V [gain 2x]
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature calibration enabled
图 5. Integral Linearity Error vs Temperature
图 6. Differential Linearity Error vs Temperature
4
3
10
8
6
2
4
1
2
0
0
-2
-4
-6
-8
-10
-1
-2
-3
-4
UP, 5 V
BP, 5 V
UP, 10 V
BP, 10 V
UP, 5 V
BP, 5 V
UP, 10 V
BP, 10 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature calibration enabled
Temperature calibration enabled
图 7. Zero Code Error vs Temperature
图 8. Positive Full-Scale Error vs Temperature
版权 © 2019, Texas Instruments Incorporated
15
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as
output and reference amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)
15
12
9
4
3
2
6
1
3
0
0
-3
-6
-9
-12
-15
-1
-2
-3
-4
UP, 5 V
BP, 5 V
UP, 10 V
BP, 10 V
INL min, UP, 5 V
INL max, UP, 5 V
INL min, BP, ê5 V
INL max, BP, ê5 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
11
11.5
12
12.5
13
13.5
14
14.5
15
Supply Voltage, VCC (V) = -VSS (V)
Temperature calibration enabled
图 9. Gain Error vs Temperature
图 10. Integral Linearity Error vs Supply Voltage
1
0.8
0.6
0.4
0.2
0
10
8
6
4
2
0
-0.2
-0.4
-0.6
-0.8
-1
-2
-4
-6
-8
-10
DNL min, UP, 5 V
DNL max, UP, 5 V
DNL min, BP, ê5 V
DNL max, BP, ê5 V
BP, ê5 V
UP, 5 V
11
11.5
12
12.5
13
13.5
14
14.5
15
11
11.5
12
12.5
13
13.5
14
14.5
15
Supply Voltage, VCC (V) = -VSS (V)
Supply Voltage, VCC (V) = -VSS (V)
图 11. Differential Linearity Error vs Supply Voltage
图 12. Zero Code Error vs Supply Voltage
4
4
3.2
2.4
1.6
0.8
0
BP, 5 V
UP, 5 V
BP, 5 V
UP, 5 V
3.2
2.4
1.6
0.8
0
-0.8
-1.6
-2.4
-3.2
-4
-0.8
-1.6
-2.4
-3.2
-4
11
11.5
12
12.5
13
13.5
14
14.5
15
11
11.5
12
12.5
13
13.5
14
14.5
15
Supply Voltage, VCC (V) = -VSS (V)
Supply Voltage, VCC (V) = -VSS (V)
图 13. Positive Full-Scale Error vs Supply Voltage
图 14. Gain Error vs Supply Voltage
16
版权 © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as
output and reference amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)
4
1
0.8
0.6
0.4
0.2
0
3
2
1
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
INL min
INL max
DNL min
DNL max
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10
Reference Voltage, VREFPF (V) = -VREFNF (V)
Reference Voltage, VREFPF (V) = -VREFNF (V)
图 15. Integral Linearity Error vs Reference Voltage
图 16. Differential Linearity Error vs Reference Voltage
4
0
3.2
2.4
1.6
0.8
0
-0.2
-0.4
-0.6
-0.8
-1
-0.8
-1.6
-2.4
-3.2
-4
-1.2
-1.4
-1.6
-1.8
-2
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10
Reference Voltage, VREFPF (V) = -VREFNF (V)
Reference Voltage, VREFPF (V) = -VREFNF (V)
图 17. Zero Code Error vs Reference Voltage
图 18. Gain Error vs Reference Voltage
1.5
1.2
0.9
0.6
0.3
0
20
IDVDD
IIOVDD
16
12
8
-0.3
-0.6
-0.9
-1.2
-1.5
4
0
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10
0
262144
524288
Code
786432
1048576
Reference Voltage, VREFPF (V) = -VREFNF (V)
VREFPF = 10 V, VREFNF = 0 V
图 20. Supply Current (DVDD and IOVDD
)
图 19. Positive Full-Scale Error vs Reference Voltage
vs Digital Input Code
版权 © 2019, Texas Instruments Incorporated
17
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as
output and reference amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)
7
5
IREFPF
IIREFNF
5
3
3
1
1
IVCC
IIVSS
-1
-3
-5
-7
-1
-3
-5
0
262144
524288
Code
786432
1048576
0
262144
524288
Code
786432
1048576
VREFPF = 10 V, VREFNF = 0 V
VREFPF = 10 V, VREFNF = 0 V
图 21. Supply Current (VCC and VSS
)
图 22. Reference Current (VREFPF and VREFNF
)
vs Digital Input Code
vs Digital Input Code
2
1.6
1.2
0.8
0.4
0
50
40
30
20
10
0
IAVDD
IDVDD)
0
262144
524288
Code
786432
1048576
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VREFPF = 10 V, VREFNF = 0 V
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
图 23. Supply Current (AVDD) vs Digital Input Code
图 24. Supply Current (DVDD) vs Temperature
12
8
8
6
IVCC
IVSS
IREFPF
IREFNF
4
4
2
0
0
-2
-4
-6
-8
-4
-8
-12
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
图 25. Supply Current (VCC and VSS
)
图 26. Reference Current (VREFPF and VREFNF
)
vs Temperature
vs Temperature
18
版权 © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as
output and reference amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)
12
2
1.8
1.6
1.4
1.2
1
IAVDD
8
4
0
0.8
0.6
0.4
0.2
0
-4
-8
-12
IVCC
14
IVSS
14.5 15
11
11.5
12
12.5
13
13.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Supply Voltage, VCC (V) = -VSS (V)
VREFPF = 5 V, VREFNF = 0 V, DAC at midcode
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
图 28. Supply Current (VCC and VSS) vs Supply Voltage
图 27. Supply Current (AVDD) vs Temperature
1000
800
600
400
200
0
50
IOVDD = 5 V
IOVDD = 3 V
IOVDD = 1.8 V
40
30
20
10
0
0
0.5
1
1.5
2
Logic Voltage, VLOGIC (V)
2.5
3
3.5
4
4.5
5
0
0.2
0.4
0.6
Logic Voltage, VLOGIC (V)
0.8
1
1.2
1.4
1.6
1.8
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
图 29. Supply Current (IOVDD
)
图 30. Supply Current (IOVDD = 1.8 V)
vs Input Pin Logic Level
vs Input Pin Logic Level
0.005
0.004
0.003
0.002
0.001
0
15
10
5
0.005
0.004
0.003
0.002
0.001
0
15
VOUT
LDAC
VOUT
LDAC
10
5
0
0
-5
-5
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
-35
-0.001
-0.002
-0.003
-0.004
-0.001
-0.002
-0.003
-0.004
-0.005
DACV glitch (0.4 nV-s)
DAC Glitch (0.75 nV-s)
3E-6 4E-6
-0.005
0
1E-6
2E-6
Time (s)
5E-6
0
1E-6
2E-6
3E-6
Time (s)
4E-6
5E-6
VREFPF = 10 V, VREFNF = –10 V, DAC transition midcode – 1 to
midcode
VREFPF = 10 V, VREFNF = –10 V, DAC transition midcode to
midcode – 1
图 31. Glitch Impulse, Rising Edge, 1-LSB Step
版权 © 2019, Texas Instruments Incorporated
图 32. Glitch Impulse, Falling Edge, 1-LSB Step
19
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Typical Characteristics (接下页)
at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as
output and reference amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)
1.6
1.4
1.2
1
1.6
1.4
1.2
1
VOUT glitch, rise
VOUT glitch, fall
VOUT glitch, rise
VOUT glitch, fall
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
Code
Code
VREFPF = 10 V, VREFNF = –10 V
VREFPF = 10 V, VREFNF = 0 V
图 33. Segment Glitch Impulse, 1-LSB Step
图 34. Segment Glitch Impulse, 1-LSB Step
1.6
1.4
1.2
1
10.033
10.028
10.023
10.018
10.013
10.008
10.003
9.998
40
30
20
10
0
VOUT (zoomed)
Settling band (+0.1%)
Settling band (-0.1%)
VOUT
LDAC
VOUT glitch, rise
VOUT glitch, fall
0.8
0.6
0.4
0.2
0
-10
-20
-30
-40
-50
9.993
9.988
0
1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5
Time(s)
VREFPF = 10 V, VREFNF = 0 V
Code
VREFPF = 5 V, VREFNF = 0 V
图 35. Segment Glitch Impulse, 1-LSB Step
图 36. Full-Scale Settling Time, Rising Edge
0.012
0.01
45
42
39
36
33
30
27
24
21
18
15
12
9
0.0025
0.00245
0.0024
20
VOUT (zoomed)
Settling band (+0.1%)
Settling band (-0.1%)
VOUT
LDAC
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.01
-0.012
-0.014
-0.016
-0.018
-0.02
10
0
0.00235
0.0023
-10
-20
-30
-40
-50
-60
0.00225
0.0022
VOUT (zoomed)
Settling band (+1 LSB)
Settling band (-1 LSB)
LDAC
6
3
0
-3
0.00215
0.0021
0
1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5
Time(s)
0
1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5
Time(s)
VREFPF = 10 V, VREFNF = 0 V
VREFPF = 10 V, VREFNF = 0 V, DAC transitions 100 codes around
midscale
图 38. 100 Codes Settling Time, Rising Edge
图 37. Full-Scale Settling Time, Falling Edge
20
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DAC11001A, DAC91001, DAC81001
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ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as
output and reference amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)
40
0.0013
0.00125
0.0012
0.00115
0.0011
0.00105
0.001
16
8
0
0
-40
-8
-80
-16
-24
-32
-120
-160
-200
VOUT (zoomed)
Settling band (+1 LSB)
Settling band (-1 LSB)
LDAC
0
1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5
Time(s)
100
4100
8100
12100
Frequency (Hz)
16100
20100
24000
VREFPF = 10 V, VREFNF = 0 V, DAC transitions 100 codes around
midscale
VREFPF = 10 V, VREFNF = 0 V, DAC output frequency = 1 kHz,
DAC update rate = 400 kHz
图 39. 100 Codes Settling Time, Falling Edge
图 40. Total Harmonic Distortion (THD + N)
vs Frequency
10
VOUT (0.1 mV/Div)
Zero code
Mid code
Full code
9.25
8.5
7.75
7
6.25
5.5
4.75
4
Time (1 s/Div)
500
1000 2000
5000 10000 20000
Frequency (Hz)
50000 100000
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode, measured at DAC
output pin
VREFPF = 10 V, VREFNF = 0 V, measured at DAC output
图 42. DAC Output Noise: 0.1 Hz to 10 Hz
图 41. DAC Output Noise Spectral Density
0.001
10
0.00075
0.0005
0.00025
0
5
0
-5
-10
-15
-20
-0.00025
-0.0005
-0.00075
-0.001
-25
-30
VOUT
SCLK
0
5E-7
1E-6
Time (s)
1.5E-6
2E-6
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode, measured at DAC output pin
图 43. Clock Feedthrough
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8 Detailed Description
8.1 Overview
The 20-bit DAC11001A, 18-bit DAC91001, and 16-bit DAC81001 (DACx1001) are single-channel DACs. The
unbuffered DAC output architecture is based on an R2R ladder that is designed to provide monotonicity over
wide reference and temperature ranges (1-LSB DNL). This architecture provides a very low-noise (7 nV/√Hz) and
fast-settling (1 µs) output. The DACx1001 also implement a deglitch circuit that enables low, code-independent
glitch at the DAC output. This is extremely useful for creating ultra low harmonic distortion waveform generation.
The DACx1001 requires external reference voltages on REFPF and REFNF pins. The output of the DAC ranges
from VREFNF to VREFPF. See the Recommended Operating Conditions for VREFPF and VREFNF voltage ranges.
The DACx1001 also includes precision matched gain setting pins (ROFS, RCM, and RFB), Using these pins and
an external op amp, the DAC output can be scaled. The DACx1001 incorporate a power-on-reset circuit that
makes sure that the DAC output powers up at zero scale, and remains at zero scale until a valid DAC command
is issued. The DACx1001 use a 4-wire serial interface that operates at clock rates of up to 50 MHz.
8.2 Functional Block Diagram
IOVDD DVDD VCC
AVDD
REFPS
REFPF
ROFS
RCM
SCLK
SDIN
Power On Reset
SYNC
SDO
RFB
OUT
Buffer
Registers
DAC
Register
DAC
LDAC
CLR
Power
Down Logic
ALARM
REFNF
REFNS
DGND
VSS AGND
8.3 Feature Description
8.3.1 Digital-to-Analog Converter Architecture
The DACx1001 provide 20-bit monotonic outputs using an R2R ladder architecture. The DAC output ranges
between VREFNF and VREFPF based on the 20-bit DAC data, as described in 公式 1:
CODE
VOUT = (VREFPF - VREFNF )ì
+ VREFNF
2N
where
•
•
•
CODE is the decimal equivalent of the DAC-DATA loaded to the DAC.
N is the bits of resolution; 20 for DAC1101A, 18 for DAC91001, 16 for DAC81001.
VREFPF, VREFNF is the reference voltage (positive and negative).
(1)
22
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DAC11001A, DAC91001, DAC81001
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ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Feature Description (接下页)
8.3.2 External Reference
The DACx1001 require external references (REFPF and REFNF) to operate. See the Recommended Operating
Conditions for VREFPF and VREFNF voltage ranges.
The DACx1001 also contain dedicated sense pins, REFPS for REFPF and REFNS for REFNF. The reference
pins are unbuffered; therefore, use a reference driver circuit for these pins. Set the VREFVAL bits (address 02h)
as per a reference span equal to (VREFPF – VREFNF). For example, the VREFVAL bits must be set to 0100 for
VREFPF = 5 V and VREFNF = –5 V.
图 44 shows an example reference drive circuit for DACx1001. 表 1 shows the op-amp options for the reference
driver circuit.
VREFP
+
Voltage
Reference
REFPF
œ
C1
REFPS
ROFS
RCM
DACx1001
RFB
C2
REFNS
REFNF
œ
œ
œ
VOUT
DAC-OUT
+
+
+
VREFN
图 44. Reference Drive Circuit
表 1. Reference Op Amp Options
SELECTION PARAMETERS
Low voltage and current noise
Low offset and drift
OP AMPS
OPA211, OPA827, OPA828
OPA189
8.3.3 Output Buffers
The DACx1001 outputs are unbuffered. Use an external op amp to buffer the DAC output. The DAC output
voltage ranges from VREFPF to VREFNF. Two gain-setting resistors are integrated in the DACx1001. These
resistors are used to scale the DAC output, minimize the bias current mismatch of the external op amp, and
generate a negative reference for the REFNF pin. See the Embedded Resistor Configurations section for more
information. 表 2 shows the op amp options for the output drive circuit.
表 2. Output Op Amp Options
SELECTION PARAMETERS
Low bias current
OP AMPS
OPA827, OPA828
OPA211, OPA828
OPA189
Low noise
Low offset and drift
OPA827, OPA828, OPA1612,
THS4011
Fast settling and low THD
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DAC11001A, DAC91001, DAC81001
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8.3.4 Internal Power-On Reset (POR)
The DACx1001 incorporate two internal POR circuits for the DVDD, AVDD, IOVDD, VCC, and VSS supplies. The
POR signals are ANDed together, so that all supplies must be at the minimal specified values for the device to
not be in a reset condition. These POR circuits initialize internal registers, as well as set the analog outputs to a
known state while the device supplies are ramping. All registers are reset to default values. The DACx1001
power on with the DAC registers set to zero scale. The DAC can be powered down by writing 1 to PDN (bit 4,
address 02h). Typically, the POR function can be ignored as long as the device supplies power up and maintain
the specified minimum voltage levels. However, in the case of supply drop or brownout, the DACx1001 can have
an internal POR reset event. 图 45 represents the internal POR threshold levels for the DVDD, AVDD, IOVDD, VCC
,
and VSS supplies.
Supply (V)
Supply Max
Specified supply
voltage range
No power-on reset
Supply Min
Operation Threshold
Undefined
POR Threshold
Power-on reset
0.00
图 45. Relevant Voltage Levels for the POR Circuit
For the DVDD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply minimum) to 5.5 V
(supply maximum). For a DVDD supply region between 2.5 V (undefined operation threshold) and 1.6 V (POR
threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a DVDD
supply less than 1.6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 1.6 V
for approximately 1 ms.
For the AVDD supply, no internal POR occurs for nominal supply operation from 4.5 V (supply minimum) to 5.5 V
(supply maximum). For an AVDD supply region between 4.1 V (undefined operation threshold) and 3.3 V (POR
threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an AVDD
supply less than 3.3 V (POR threshold), the internal POR resets as long as the supply voltage is less than 3.3 V
for approximately 1 ms.
For the VCC supply, no internal POR occurs for nominal supply operation from 8 V (supply minimum) to 36 V
(supply maximum). For VCC supply voltages between 7.5 V (undefined operation threshold) to 6 V (POR
threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a VCC
supply less than 6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 6 V for
approximately 1 ms.
For the VSS supply, no internal POR occurs for nominal supply operation from –3 V (supply minimum) to –18 V
(supply maximum). For VSS supply voltages between –2.7 V (undefined operation threshold) to –1.8 V (POR
threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a VSS
supply greater than –1.8 V (POR threshold), the internal POR resets as long as the supply voltage is higher than
–1.8 V for approximately 1 ms.
24
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DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
For the IOVDD supply, no internal POR occurs for nominal supply operation from 1.8 V (supply minimum) to 5.5 V
(supply maximum). For IOVDD supply voltages between 1.5 V (undefined operation threshold) and 0.8 V (POR
threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an IOVDD
supply less than 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is less than 0.8 V
for approximately 1 ms.
In case the DVDD, AVDD, IOVDD, VCC, or VSS supply drops to a level where the internal POR signal is
indeterminate, power cycle the device followed using a software reset.
8.3.5 Temperature Drift and Calibration
The DACx1001 includes a calibration circuit that significantly reduces the temperature drift on integrated and
differential nonlinearities. By default, this feature is disabled. Enable the temperature calibration feature by writing
1 to the EN_TMP_CAL bit (address 02h, B23). After the EN_TMP_CAL bit is set, issue a calibration cycle by
writing 1 to RCLTMP (address 04h, B8). At this point, the device enters a calibration cycle. Do not issue any
DAC update command during this period. The device has the capability to indicate the end of calibration using
two methods:
1. Read the status bit ALM (address 05h, B12) using SPI.
2. Issue an alarm on the ALARM pin by setting logic 0. To enable this feature, write 1 to ENALMP bit (address
02h, B12).
After the calibration cycle completes, update the DAC code to observe the impact at the DAC output. If the
environmental temperature changes after calibration, then recalibrate the device.
8.3.6 DAC Output Deglitch Circuit
The DACx1001 include a deglitch (track-and-hold) circuit at the output. This circuit is enabled by default. The
deglitch circuit minimizes the code-to-code glitch at the DAC output at the expense of the DAC update rate. This
circuit is disabled by writing 1 to DIS_TNH (bit 7, address 06h). Disable this circuit to enable faster update of the
DAC output, but with higher code-to-code glitches.
8.4 Device Functional Modes
8.4.1 Fast-Settling Mode and THD
The DACx1001 R2R ladder and deglitch circuit reduce the harmonic distortion for waveform generation
applications. The fast settling bit (FSET, bit 10, address 02h) is set to 1 by default, so that the DAC is configured
for enhanced THD performance. The FSET bit can be reset to 0 using an SPI write to enable fast-settling mode.
In this mode, the DAC deglitcher circuit can be configured using TNH_MASK (bits 19:18, address 02h). These
bits disable the deglitch circuit for code changes specified in 表 7. These bits are only writable when FSET = 0
(fast settling enabled) and DIS_TNH = 0 (deglitch circuit enabled).
8.4.2 DAC Update Rate Mode
The DACx1001 maximum update rate can be configured up to 1 MHz by using UP_RATE (bits 6:4, address
06h). These bits change the hold timing of the deglitch circuit. The bits are set to a 0.5-MHz DAC update rate by
default for enhanced THD performance. Changing the maximum update rate of the DAC impacts THD
performance.
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DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
8.5 Programming
The DACx1001 family of devices is controlled through a flexible four-wire serial interface that is compatible with
serial interfaces used on many microcontrollers and DSP controllers. The interface provides read and write
access to all registers of the DACx1001 devices. Additionally, the interface can be configured to daisy-chain
multiple devices for write operations.
Each serial interface access cycle is exactly 32 bits long, as shown in 图 46. A frame is initiated by asserting
SYNC pin low. The frame ends when the SYNC pin is deasserted high. The first bit is read/write bit B31. A write
is performed when this bit is set to 0, and a read is performed when this bit is set to 1. The next 7 bits are
address bits B30 to B24. The next 20 bits are data. For all writes, data are clocked on the falling edge of SCLK.
As 图 47 shows, for read access and daisy-chain operation, the data are clocked out on the SDO terminal on the
rising edge of SCLK.
SYNC
1
2
3
4
5
6
7
8
9
31 32
SCLK
SDIN
Write Command
D31 D30 D29 D28 D27 D26 D25 D24 D23
‡‡‡
D1 D0
图 46. Serial Interface Write Bus Cycle: Standalone Mode
SYNC
SCLK
1
2
3
4
5
6
7
8
9
31 32
1
2
3
4
5
6
7
8
9
10
31 32
Read Command
D31 D30 D29 D28 D27 D26 D25 D24 D23
Any Command
SDIN
SDO
‡‡‡
‡‡‡
‡‡‡
D1 D0
D31 D30 D29 D28 D27 D26 D25 D24 D23
Read Data
D1 D0
D1 D0
Z-state
D22
D31 D30 D29 D28 D27 D26 D25 D24 D23
图 47. Serial Interface Read Bus Cycle
8.5.1 Daisy-Chain Operation
For systems that contain several DACx1001 devices, the SDO pin is used to daisy-chain the devices together.
The daisy-chain feature is useful in reducing the number of serial interface lines. The first falling edge on the
SYNC pin starts the operation cycle, as shown in 图 48. SCLK is continuously applied to the input shift register
while the SYNC pin is kept low. The DAC is updated with the data on rising edge of SYNC pin.
SYNC
1
2
3
4
5
6
7
8
9
31 32 33
63 64 65
95 96 97
127 128
SCLK
SDIN
SDO
Device A Command
D31 D30 D29 D28 D27 D26 D25 D24
D23 œ D0
Device B Command
Device C Command Device D Command
Device A Command Device B Command Device C Command
图 48. Serial Interface Daisy-Chain Write Cycle
If more than 32 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line.
These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO
output of the first device to the SDI input of the next device in the chain, a multiple-device interface is
constructed. Each device in the system requires 32 clock pulses.
26
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DAC11001A, DAC91001, DAC81001
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ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Programming (接下页)
As a result, the total number of clock cycles must be equal to 32 × N, where N is the total number of devices in
the daisy-chain. When the serial transfer to all devices is complete the SYNC signal is taken high. This action
transfers the data from the SPI shift registers to the internal register of each device in the daisy-chain and
prevents any further data from being clocked into the input shift register. The DACx1001 implement a bit that
enables higher speeds for clocking out data from the SDO pin. Enable this feature by setting FSDO (bit 13,
address 02h) to 1. See Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V and for more
information.
8.5.2 CLR Pin Functionality and Software Clear
The CLR pin is an asynchronous input pin to the DAC. When activated, this level-sensitive pin clears the DAC
buffers and DAC latches to the DAC-CLEAR-DATA bits (address 03h). The device exits clear mode on the
SYNC rising edge of the next valid write to the device. If the CLR pin receives a logic 0 during a write sequence
during normal operation, the clear mode is activated and the buffer and DAC registers are immediately cleared.
The DAC registers can also be cleared using the SCLR bit (address 04h, B5); the contents are cleared at the
rising edge of SYNC.
8.5.3 Output Update (Synchronous and Asynchronous)
The DACx1004 devices offer both a software and hardware simultaneous update and control function. The DAC
double-buffered architecture has been designed so that new data can be entered for the DAC without disturbing
the analog output. Data updates can be performed either in synchronous or in asynchronous mode, depending
on the status of LDAC-MODE bit (address 02h, B14).
8.5.3.1 Synchronous Update
In synchronous mode (LDACMODE = 1), the LDAC pin is used as an active-low signal for simultaneous DAC
updates. Data buffers must be loaded with the desired data before an LDAC low pulse. After an LDAC low pulse,
the DAC is updated with the last contents of the corresponding data buffers. If the content of a data buffer is not
changed, the DAC output remains unchanged after the LDAC pin is pulsed low.
8.5.3.2 Asynchronous Update
In asynchronous mode (LDACMODE = 0), data are updated with the rising edge of the SYNC (when daisy-chain
mode is enabled, DSDO = 0), or at the 32nd falling edge of SCLK (When daisy-chain mode is disabled, DSDO =
1). For asynchronous updates, the LDAC pin is not required, and it must be connected to 0 V permanently.
8.5.4 Software Reset Mode
The DACx1001 implements a software reset feature. The software reset function uses the SRST bit (address
04h, B6). When this bit is set to 1, the device resets to the default state.
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DAC11001A, DAC91001, DAC81001
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www.ti.com.cn
8.6 Register Map
表 3. Register Map
BIT
REGISTER
NAME
31
W
30-24
00h
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3-0
0h
0h
NOP
NOP
DAC-DATA
R/W
01h
DAC-DATA (20 bits, 18 bits, or 16 bits, left-justified)
EN_
TMP_
CAL
LDAC
MODE
CONFIG1
R/W
R/W
02h
03h
0h
TNH_MASK
0h
FSDO
ENALMP
DSDO
FSET
VREFVAL
0
PDN
0h
0h
DAC-CLEAR-
DATA
DAC-CLEAR-DATA (8 bits left justified)
000h
000h
TRIGGER
STATUS
CONFIG2
R/W
R
04h
05h
06h
0000h
RCLTMP
0
SRST
SCLR
0
0h
0h
0h
ALM
00h
DIS_TNH
R/W
0000h
TNH_SETTING
28
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ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
表 4. Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.6.1 NOP Register (address = 00h) [reset = 0x000000h]
图 49. NOP Register Format
31
30
29
28
27
26
25
24
23
22
21
5
20
4
19
3
18
2
17
1
16
0
Read/
Write
Address
NOP
W
W
W
15
14
13
12
11
10
9
8
7
6
NOP
W
0h
W
表 5. NOP Register Field Descriptions
Bit
31
Field
Write
Type
W
Reset
N/A
Description
Write when set to 0
00h
30:24
23:4
3:0
Address
NOP
0h
W
N/A
W
00000h
N/A
No operation - Write 00000h
N/A
W
8.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h]
图 50. DAC-DATA Register Format
31
30
14
29
13
28
27
26
25
24
23
22
21
20
19
18
17
16
0
Read/
Write
Address
DAC-DATA (20-bit, 18-bit, or 16-bit, left justified)
R/W
15
W
R/W
12
11
10
9
8
7
6
5
4
3
2
1
DAC-DATA (20-bit, 18-bit, or 16-bit, left justified)
R/W
0h
W
表 6. DAC-DATA Register Field Descriptions
Bit
31
Field
Type
R/W
W
Reset
N/A
N/A
0h
Description
Read/Write
Address
Read when set to 1 or write when set to 0
01h
30:24
23:4
DAC-DATA[19:0]
R/W
Stores the 20-bit, 18-bit, or 16-bit data to be loaded to DAC in
MSB aligned straight binary format.
Data follows the format below:
DAC1101A: { DAC-DATA[19:0] }
DAC91001: { DAC-DATA[17:0], 0, 0 }
DAC81001: { DAC-DATA[15:0], 0, 0, 0, 0}
3:0
0h
W
N/A
N/A
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8.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
图 51. CONFIG1 Register Format
31
30
29
28
27
26
25
24
23
22
21
0h
20
19
18
17
1
16
0
Read/
Write
Address
EN_
TMP_
CAL
TNH_MASK
0h
W
R/W
W
R/W
7
W
R/W
15
0h
14
13
12
11
10
9
8
6
5
4
3
2
LDAC FSDO ENALMP DSDO FSET
MODE
VREFVAL
0h
PDN
0h
W
R/W
W
R/W
W
表 7. CONFIG1 Register Field Descriptions
Bit
31
Field
Type
R/W
W
Reset
N/A
N/A
0h
Description
Read/Write
Address
Read when set to 1 or write when set to 0
02h
30:24
23
EN_TMP_CAL
R/W
Enables and disables the temperature calibration feature
0 : Temperature calibration feature disabled (default)
1 : Temperature calibration feature enabled
22:20
19-18
0h
W
N/A
0h
N/A
TNH_MASK
R/W
Mask track and hold (TNH) circuit. This bit is writable only when FSET = 0
[fast-settling mode] and DIS_TNH = 0 [track-and-hold enabled]
00: TNH masked for code jump > 2^14 (default)
01: TNH masked for code jump > 2^15
10: TNH masked for code jump > 2^13
11: TNH masked for code jump > 2^12
17:15
14
0h
W
N/A
1
N/A
LDACMODE
R/W
Synchronous or asynchronous mode select bit
0 : DAC output updated on SYNC rising edge
1 : DAC updated on LDAC falling edge (default)
13
12
11
10
9:6
FSDO
R/W
R/W
R/W
R/W
R/W
0h
0h
1h
1h
2h
Enable Fast SDO
0 : Fast SDO disabled (Default)
1 : Fast SDO enabled
ENALMP
DSDO
Enable ALARM pin to be pulled low, end of temperature calibration cycle
0 : No alarm on the ALARM pin
1 : Indicates end of temperature calibration cycle. ALARM pin pulled low.
Enable SDO (for readback and daisy-chain)
1 : SDO enabled (default)
0 : SDO disabled
FSET
Fast-settling vs enhanced THD mode
0 : Fast settling
1 : Enhanced THD (default)
VREFVAL
Reference span value bits
0000: Invalid
0001: Invalid
0010: Reference span = 5 V ± 1.25 V (default)
0011: Reference span = 7.5 V ± 1.25 V
0100: Reference span = 10 V ± 1.25 V
0101: Reference span = 12.5 V ± 1.25 V
0110: Reference span = 15 V ± 1.25 V
0111: Reference span = 17.5 V ± 1.25 V
1000: Reference span = 20 V ± 1.25 V
1001: Reference span = 22.5 V ± 1.25 V
1010: Reference span = 25 V ± 1.25 V
1011: Reference span = 27.5 V± 1.25 V
1100: Reference span = 30 V ± 1.25 V
5
4
0
W
N/A
0h
N/A
PDN
R/W
Powers down and power up the DAC
0 : DAC power up (default)
1 : DAC power down
3:0
0000
R/W
N/A
N/A
30
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8.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
图 52. DAC-CLEAR-DATA Register Format
31
30
14
29
13
28
12
27
26
25
24
23
22
21
20
19
18
17
1
16
0
Read/
Write
Address
DAC-CLEAR-DATA (8 bits, left justified)
R/W
15
W
R/W
11
10
9
8
7
6
5
4
3
2
000h
W
0h
W
表 8. DAC-CLEAR-DATA Register Field Descriptions
Bit
31
Field
Type
R/W
W
Reset
N/A
Description
Read/Write
Address
Read when set to 1 or write when set to 0
03h
30:24
23:16
N/A
DAC-CLEAR-DATA
R/W
00h
Stores the 8-bit data to be loaded to DAC in left-justified,
straight-binary format. DAC data registers updated with this
value when CLR pin asserted low
15:0
000h
W
N/A
N/A
8.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
图 53. TRIGGER Register Format
31
30
14
29
13
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
Read/
Write
Address
00h
W
R/W
15
W
12
00h
W
11
10
9
8
7
6
5
4
RCLTMP
R/W
0h
W
SRST SCLR
R/W R/W
0h
W
0h
W
表 9. TRIGGER Register Field Descriptions
Bit
31
Field
Type
R/W
W
Reset
N/A
N/A
N/A
0h
Description
Read/Write
Address
0000h
Read when set to 1 or write when set to 0
30:24
23:9
8
04h
W
Unused
RCLTMP
R/W
Trigger temperature recalibration DAC Codes
0 : No temperature recalibration (default)
1 : DAC codes recalibrated, ALARM pin is pulled low (if
ENALMP = 1) and ALM bit (Address 05) is set 1 upon calibration
completion. Subsequent DAC codes will use latest calibrated
coefficients.
7
6
0h
W
N/A
0h
NA
SRST
R/W
Software reset
0 : No software reset (default)
1 : Software reset initiated, device in default state
5
SCLR
R/W
0h
Software clear
0 : No software clear (default)
1 : Software clear initiated, DAC registers in clear mode, DAC
code set by clear select register (address 03h). DAC output
clears on 32nd SCLK falling (DSDO = 1) or SYNC rising edge
(DSDO = 0)
4
0h
0h
W
W
N/A
N/A
N/A
N/A
3:0
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8.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
图 54. STATUS Register Format
31
30
29
13
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
Read/
Write
Address
00h
W
R
W
15
14
0h
W
12
ALM
R
11
10
9
8
7
6
5
00h
W
0h
W
表 10. STATUS Register Field Descriptions
Bit
31
Field
Type
R
Reset
N/A
N/A
N/A
0
Description
Read/Write
Address
000h
Read when set to 1 , read only
30:24
23:13
12
W
05h
N/A
W
ALM
R
Alarm indicator bit, This bit is not masked by ENALMP bit
0 :Temperature recalibration in progress
1 : DAC codes recalibrated, ALARM pin is pulled low (if
ENALMP = 1) Subsequent DAC codes will use latest calibrated
coefficients. Reading back this register resets ALARM pin to 1
status.
11:4
3:0
00h
0h
W
W
N/A
N/A
N/A
N/A
8.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
图 55. CONFIG2 Register Format
31
30
14
29
13
28
12
27
26
25
24
23
22
21
20
00h
19
3
18
2
17
1
16
0
Read/
Write
Address
R/W
15
W
W
11
10
9
8
7
6
5
4
00h
DIS_TNH
R/W
UP_RATE
R/W
0h
W
W
表 11. CONFIG2 Register Field Descriptions
Bit
31
Field
Type
R/W
W
Reset
N/A
N/A
N/A
0h
Description
Read/Write
Address
0000h
Read when set to 1 or write when set to 0
30:24
23:8
7
06h
N/A
W
DIS_TNH
R/W
Disable track and hold:
0 : Track and hold enabled (default)
1 : Track and hold disabled
6-4
UP_RATE
R/W
4h
DAC output max update rate:
000: 1 MHz with 38-MHz SCLK
001: 0.9 MHz with 34-MHz SCLK
010: 0.8 MHz with 31-MHz SCLK
011: 1.2 MHz with 45-MHz SCLK
100: 0.5 MHz with 21-MHz SCLK, (default)
101: 0.45 MHz with 18-MHz SCLK
110: 0.4 MHz with 16-MHz SCLK
111: 0.6 MHz with 24-MHz SCLK
3:0
0h
W
N/A
N/A
32
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ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DACx1001 family of DACs are targeted for high-precision applications where ultra-high dc accuracy, ultra-
low noise, fast settling, or high total harmonic distortion (THD) is required. The DACx1001 provides 20-bit
monotonic resolution. This device finds application in high-performance source measure unit (SMU), battery test
equipment (BTE), arbitrary waveform generation (AWG), and closed-loop control applications such as
microelectromechanical system (MEMS) actuators, linear actuators, precision motor control, lens autofocus
control in precision microscopy, lens control in mass spectrometer, beam control in electron beam lithography,
and so on.
9.2 Typical Application
9.2.1 Source Measure Unit (SMU)
A source measure unit (SMU) is a common building block in memory and semiconductor test equipment and
bench-top source measure units. A DAC is used in an SMU to force a desired voltage or a current to a device-
under-test (DUT). 图 56 provides a simplified circuit diagram of the force-DAC in an SMU.
RCABLE
1 Mꢀ
INA188
œ
1
R2
R1
SW
GV
DUT
+
2
OPA828
VREFP
+
INA188
RCABLE
GI
REFPS
REFPF
REFNS
REFNF
1 Mꢀ
œ
C1
œ
RSENSE
+
DACx1001
OPA828
C2
œ
+
VREFN
OPA828
图 56. Source Measure Unit
9.2.1.1 Design Requirements
•
•
Force voltage range: ±10 V
Force current range: ±20 mA
9.2.1.2 Detailed Design Procedure
The DAC11001A is an excellent choice for this application to meet the 20-bit resolution requirement. Switch SW
is used to toggle between force-voltage and force-current modes, as shown in 图 56. The OPA828 is a high-
precision amplifier that provides a good balance between dc and ac performance, and can supply ±30-mA output
current. The INA188 is a zero-drift instrumentation amplifier with gain selected with an external resistor. The
external resistor is not shown in the drawing for simplicity. The gain resistor is not required for a gain of 1. 公式 2
shows the calculation of the voltage gain when switch SW is in position 1.
≈
’
÷
R1
1
AV
=
x 1+
∆
GV
R2 ◊
«
(2)
33
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Typical Application (接下页)
Precision reference sources are available at 5 V or less. Use a ±5-V reference with a 2x gain configuration to get
an output of ±10 V. The DAC output amplifier sets the gain at 2, assuming GV = 1, as shown in 公式 3. R1 and R2
are 1-kΩ each. 公式 3 shows the calculation for the current gain when the switch is in the position 2.
≈
’
÷
R1
1
AV
=
x 1+
∆
RSENSExGI
R2 ◊
«
(3)
In order to get ±20-mA output current range with R1 = R2, RSENSEx GI must be 500. Choose GI as 50 so that
RSENSE can be 10-Ω. For a ±20mA output current, the voltage drop across RSENSE is ±200-mV. Choose a higher
value for GI and a smaller resistance value for RSENSE in case the design requires a lower voltage headroom.
There is no equation to select C1 and C2. The values of C1 and C2 depend on the stability criteria of the
reference buffers when driving the reference inputs of DACx1001. The values are obtained through simulation.
For the OPA828, use C1 = C2 = 100 pF. The 1-MΩ resistors in the circuit are used for making sure the amplifiers
are not left in open loop.
9.2.1.3 Application Curves
Measured on BP-DAC11001EVM, external 10-V reference
source
Measured on BP-DAC11001EVM, external 10-V reference
source
图 57. INL at ±10-V Output
图 58. DNL at ±10-V Output
34
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Typical Application (接下页)
9.2.2 Battery Test Equipment (BTE)
Battery test equipment is used for lithium-ion battery formation, end-of-line testing, and diagnostics. For battery
diagnostics, high-precision DACs, such as the DACx1001, are required to maintain a highly stable voltage over
temperature and time.
OPA189
+
VREFP
REFPS
REFPF
REFNS
REFNF
Battery
Charge/
Discharge
Circuit
œ
C1
œ
VSET/
ISET
RSENSE
+
DACx1001
OPA189
C2
œ
+
OPA189
图 59. Battery Test Equipment
9.2.2.1 Design Requirements
•
•
Output range: 0 V to 5 V
System level temperature drift: ±2 ppm/°C
9.2.2.2 Detailed Design Procedure
To get unipolar output from DACx1001, connect the negative reference input to ground as shown in 图 59. The
OPA189 is a zero-drift amplifier with ±0.02 ppm/°C. The DACx1001 has a temperature drift of offset error of
±0.04 ppm/°C. The temperature drifts of the DAC and amplifier might be neglected when compared to the
temperature drift of the reference source. The best reference sources offer temperature drifts of the order of
±2.5 ppm/°C to ±3 ppm/°C. A temperature calibration is needed for the voltage reference to achieve the goal of
±2 ppm/°C.
9.2.2.3 Application Curves
Measured on BP-DAC11001EVM, REF6250 onboard reference
source (5 V)
Measured on BP-DAC11001EVM, REF6250 onboard reference
source (5 V)
图 60. INL at 0-V to 5-V Output
图 61. DNL at 0-V to 5-V Output
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Typical Application (接下页)
9.2.3 High-Precision Control Loop
High-precision control loops are used in precision motion-control applications, such as linear actuator control,
servo motor control, galvanometer control, and more. The key requirements for such applications is resolution,
monotonicity, settling time, and code-to-code glitch. 图 62 provides a simplified circuit of a linear actuator control
circuit, wherein the DACx1001 commands the set point and an analog loop controls the actuator.
Gain/
Attenuation
THS4011
C1
Sensor
Output
+
VREFP
REFPS
REFPF
REFNS
REFNF
œ
œ
Linear
Actuator
Power
Amplifier
+
DACx1001
THS4011
C2
THS4011
œ
+
VREFN
图 62. High-Precision Control Loop
9.2.3.1 Design Requirements
•
•
•
DNL: ±1 LSB max at 20-bits
Settling time: < 2 µs
Code-to-code Glltch: < 2 nV-s
9.2.3.2 Detailed Design Procedure
The DACx1001 provides 20-bit monotonic resolution at < ±1 LSB DNL. The device provides < 2 µs setting time
and < 2 nV-s code-to-code glitch for major carry transition. The reference and output buffer used for this design
is the THS4011, a high-speed amplifier with a 90-ns settling time. For the best settling response, use C1 and C2
between 10 pF to 50 pF.
9.2.3.3 Application Curves
Measured on BP-DAC11001EVM, REF6250 onboard reference
source (5 V)
Measured on BP-DAC11001EVM, REF6250 onboard reference
source (5 V)
图 63. INL at ±5-V Output
图 64. DNL at ±5-V Output
36
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ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Typical Application (接下页)
9.2.4 Arbitrary Waveform Generation (AWG)
Arbitrary waveform generation circuits are common in memory and semiconductor test equipment. These circuits
are used to generate reference ac waveforms to test semiconductor devices. The key performance parameters
of such circuits are THD, SNR, and the update rate. 图 65 shows the basic building block example of an AWG
circuit using the DACx1001.
Optional Gain
OPA828
C1
R2
R1
+
VREFP
REFPS
REFPF
REFNS
REFNF
œ
œ
VOUT
+
DACx1001
OPA1611
C2
OPA828
œ
+
VREFN
图 65. Arbitrary Waveform Generation
9.2.4.1 Design Requirements
•
•
THD at 1 kHz: > –105 dB
Update rate: 100 kHz
9.2.4.2 Detailed Design Procedure
The DACx1001 provides a THD of –105 dB at 1 kHz. The device provides update rates of up to 1 MHz, with
marginal degradation in THD at higher frequencies. The OPA828 provides the best balance between the voltage
and current noise densities, and is therefore an excellent choice to use as reference buffers. The OPA1611 is a
low-distortion amplifier for high-THD applications.
9.2.4.3 Application Curves
The test conditions for the THD values in the graph of 图 66 are a ±3-V reference input on the BP-
DAC11001EVM, and an external 3x gain at the DAC output. The THD calculation considers 11 harmonics; the
even harmonics are omitted. When two DACs are used in a differential output mode, the even harmonics are
cancelled to a large extent. 图 66 shows an ideal scenario, when the even harmonics are completely cancelled
out.
图 66. THD vs Frequency
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9.3 System Examples
This section provides details on the digital interface and the embedded resistor configurations.
9.3.1 Interfacing to a Processor
The DACx1001 family of DACs works with a 4-wire SPI interface. The digital interface of the DACx1001 to a
processor is shown in 图 67. The DACx1001 has an LDAC input option for synchronous output update. In ac-
signal generation applications, the jitter in the LDAC signal contributes to signal-to-noise ratio (SNR). Therefore,
the LDAC signal must be generated from a low-jitter timer in the processor. The CLR and ALARM pins are static
signals, and therefore can be connected to general-purpose input-output (GPIO) pins on the processor. All
active-low signals (SYNC, LDAC, CLR, and ALARM) must be pulled up to IOVDD using 10-kΩ resistors. ALARM
is an output pin from the DAC, so the corresponding GPIO on the processor must be configured as an input.
Either poll the GPIO, or configured the GPIO as an interrupt to detect any failure alarm from the DAC. When
using a high SCLK frequency, use source termination resistors, as shown in Interfacing to a Processor. Typically,
33-Ω resistors work on printed circuit boards (PCBs) with a 50-Ω trace impedance.
IOVDD
IOVDD
RS
RS
SCLK
MOSI
MISO
CS
SCLK
SDIN
SDO
RS
RS
RS
Processor
SYNC
LDAC
CLR
DACx1001
TIMER
GPIO
GPIO
ALARM
DGND
DGND
RPULLUP
IOVDD
图 67. Interfacing to a Processor
9.3.2 Interfacing to a Low-Jitter LDAC Source
When the processor is not able to provide a low-jitter source for the LDAC signal, an external low-jitter LDAC
source can be used, as shown in 图 68. The processor can take the LDAC signal as an interrupt and trigger the
SPI frame synchronously.
IOVDD
IOVDD
RS
RS
SCLK
MOSI
MISO
CS
SCLK
SDIN
SDO
RS
RS
Processor
SYNC
LDAC
CLR
DACx1001
INT
GPIO
GPIO
ALARM
RPULLUP
IOVDD
DGND
DGND
RS
RS
Low-Jitter
LDAC Source
图 68. Interfacing to an External LDAC Source
38
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System Examples (接下页)
9.3.3 Embedded Resistor Configurations
The DACx1001 provides two embedded resistors with values is double the value of the output impedance of the
R2R ladder. These resistors can be used in various configurations, as shown in the following subsections.
9.3.3.1 Minimizing Bias Current Mismatch
The bias current mismatch in the output amplifier can lead to offset error at the output. To minimize mismatch,
the amplifier must have a matching resistor to that of the R2R output impedance on the feedback path. The
feedback resistors are used in parallel for this purpose, as shown in 图 69. Some amplifiers may become
unstable with a feedback resistor in the buffer configuration. Therefore, a compensation capacitor (CCOMP) might
be needed, as shown. The typical value of this capacitor is in the range of 22 pF to 100 pF, depending on the
amplifier.
ROFS
DACx1001
2xROUT
CCOMP
RCM
2xROUT
RFB
œ
ROUT
VOUT
DAC-OUT
+
图 69. Minimizing Bias Current Mismatch
9.3.3.2 2x Gain configuration
The circuit of 图 69 can be configured for 2x gain by connecting one of the resistor ends to ground, as shown in
图 70.
ROFS
DACx1001
2xROUT
CCOMP
RCM
2xROUT
RFB
œ
ROUT
VOUT
DAC-OUT
+
图 70. 2x Gain Configuration
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System Examples (接下页)
9.3.3.3 Generating Negative Reference
Generating a negative reference is a challenge because of the fact that the circuit needs an inverting amplifier
involving resistors. The resistor mismatch and temperature drift can lead to inaccuracy. The embedded, matched
resistors in DACx1001 can be used as shown in 图 71, the inverting amplifier configuration, to generate an
accurate negative reference voltage.
VREFP
+
Voltage
Reference
REFPF
œ
C1
REFPS
ROFS
RCM
DACx1001
RFB
C2
REFNS
REFNF
œ
œ
œ
VOUT
DAC-OUT
+
+
+
VREFN
图 71. Generating Negative Reference
40
版权 © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
9.4 What to Do and What Not to Do
9.4.1 What to Do
•
•
•
Follow recommended grounding, decoupling, and layout schemes for achieving best accuracy.
Use a low-jitter LDAC source for best ac performance.
Choose the appropriate amplifiers depending on the application requirements as explained in above sections.
9.4.2 What Not to Do
•
•
Do not apply the reference before the DAC power supplies are powered on.
Do not use the reference source directly with the DAC reference inputs without using buffers. or else the
accuracy drastically degrades.
9.5 Initialization Set Up
The following text shows the pseudocode to get started with the DACx1001:
//SPI Settings
//Mode: Mode-1 (CPOL: 0, CPHA: 1)
//CS Type: Active Low, Per Packet
//Frame length: 32
//SYNTAX: WRITE <REGISTER (HEX ADDRESS>, <HEX DATA>
//Select VREF, TnH mode (Good THD), LDAC mode and power-up the DAC
WRITE CONFIG (0x02), 0x004C80
//Write zero code to the DAC
WRITE DACDATA (0x01), 0x000000
//Write mid code to the DAC
WRITE DACDATA (0x01), 0x7FFFF0
//Write full code to the DAC
WRITE DACDATA (0x01), 0xFFFFF0
版权 © 2019, Texas Instruments Incorporated
41
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
10 Power Supply Recommendations
To get the best performance out of the DACx1001, the power supply, grounding, and decoupling are very
important. Use a PCB with a ground-plane reference, which helps in confining the digital return currents. A low
mutual inductance path is created just beneath the high-frequency digital traces causing the return currents to
follow the respective signal traces, thus minimizing crosstalk. On the other hand, dc signals spread over the
ground plane without being confined below the signal trace. Therefore, in precision dc applications, limiting the
common-impedance coupling is very difficult unless the ground planes are physically separated. 图 72 shows a
method to divide the grounds so that there is no common-mode current flow between the grounds, while
maintaining the same dc potential across all grounds. This circuit assumes that the REFGND and LOAD-GND
are provided from isolated power sources, therefore, there is no common-mode current flow through the
reference or the load.
Analog
Power
Inputs
+
+
IOVDD
DGND
Isolated Reference
Power
œ
œ
Isolated Load
Power
AGND
+
+
œ
Load
Circuit
+
VREFP
VOUT
œ
REFPS
REFPF
REFNS
REFNF
œ
REFGND
C1
C2
œ
Signal
Input
LOAD-GND
Reference
Generation
Circuit
+
DACx1001
œ
+
VREFN
LOAD-GND
DGND
AGND
AGND-OUT
REFGND
REFGND
Single-Point Short
图 72. Power and Signal Grounding
When the load circuit is powered from a source referenced to AGND, and the LOAD-GND is shorted to AGND at
the far end, the AGND-OUT must no longer be shorted to AGND locally near the DAC. The local shorting creates
a ground loop, otherwise. The resulting connection that avoids the ground loop is shown in 图 73.
Analog
Power
Inputs
+
+
IOVDD
DGND
Isolated Reference
Power
œ
œ
AGND Shared Between
DAC and Load
AGND
+
+
œ
Load
Circuit
+
VREFP
VOUT
œ
REFPS
REFPF
REFNS
REFNF
œ
REFGND
C1
C2
œ
Signal
Input
AGND
Reference
Generation
Circuit
+
DACx1001
œ
+
VREFN
AGND
DGND
AGND
AGND-OUT
REFGND
LOAD-GND
REFGND
Single-Point Short
Single-Point Short
图 73. Grounding Scheme When AGND is Load Ground
When the reference source is powered from a power source with AGND as the ground, there is a possibility of
common-impedance coupling causing a code-dependent shift in the reference voltage. To avoid undesired
coupling, drive REFGND using a buffer that maintains the reference ground potential equals to that of AGND-
OUT, as shown in 图 74.
42
版权 © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
Analog
Power
Inputs
+
+
IOVDD
DGND
AGND Shared Between
DAC and Reference
œ
œ
AGND Shared Between
DAC and Load
AGND
+
+
œ
Load
Circuit
+
VREFP
VOUT
œ
REFPS
REFPF
REFNS
REFNF
œ
AGND
C1
C2
œ
Signal
Input
AGND
Reference
Generation
Circuit
+
DACx1001
œ
+
VREFN
AGND
DGND
AGND
AGND-OUT
LOAD-GND
Kelvin Connection
Close to the Pin
œ
Single-Point Short
Single-Point Short
+
REFGND
图 74. Connecting the Reference Ground
Channel-to-channel dc crosstalk is a major concern in multichannel applications, such as battery test equipment.
While the DACx1001 is single-channel, the crosstalk problem can appear at a system level when using multiple
DACx1001 devices. The problem becomes severe when the grounds of the loads are shorted together creating a
possible ground loop. In such cases, avoid the local short between AGND and AGND-OUT. Use a single short
between AGND and DGND for all the DACs. If the PCB layout allows for the digital signal and analog power
supplies to be kept separate, DGND and AGND can be combined to a single ground plane. 图 75 shows an
example circuit for minimizing dc crosstalk across DAC channels in a system.
Analog
Power
Inputs
+
+
IOVDD
DGND
œ
œ
AGND
+
+
œ
Load
Circuit
+
VREFP1
VOUT1
œ
REFPS
REFPF
REFNS
REFNF
œ
AGND
C1
C2
œ
Signal
Input
AGND
Reference
Generation
Circuit
+
DACx1001
œ
ICROSSTALK = 0
+
VREFN1
AGND
DGND
AGND
AGND-OUT1
LOAD-GND1
Kelvin Connection
Close to the Pin
œ
Single-Point Short
+
REFGND1
Single-Point Short
Common to all DACs
AGND Shared
Across DACs,
Analog
Power
Inputs
+
+
References, And
Loads
IOVDD
DGND
AGND
œ
œ
DGND Shared
Across DACs
DGND
AGND
+
+
œ
Load
Circuit
+
VREFP2
VOUT2
œ
REFPS
REFPF
REFNS
REFNF
œ
AGND
C3
C4
œ
Signal
Input
AGND
Reference
Generation
Circuit
+
DACx1001
œ
ICROSSTALK = 0
+
VREFN2
AGND
DGND
AGND
AGND-OUT2
LOAD-GND2
Kelvin Connection
Close to the Pin
œ
Single-Point Short
+
REFGND2
图 75. Minimizing Multichannel DC Crosstalk
版权 © 2019, Texas Instruments Incorporated
43
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
Power-supply bypassing and decoupling is key to keep power supply noise, switching transients, and common-
mode currents away from the DAC output. There are three main objective of power-supply bypassing:
•
•
•
Filtering: Filter out noise and ripple from power supplies
Bypassing: Supply switching or load transient currents locally by avoiding trace inductances
Decoupling: Stop local transient currents from impacting other circuits
To achieve these objectives, use the following 3-element scheme. Place a decoupling capacitor close to every
power supply pin to provide the local current path for load and circuit switching transients. This capacitor must be
referenced to the respective load ground for best load transient suppression. Use a 0.1-µF to 1-µF, X7R,
multilayer ceramic capacitor (MLCC) for this purpose. For analog power supplies, a 10-Ω series resistor provides
the best decoupling. For filtering the power supply noise and ripple, 10-µF capacitors work best when placed at
the power entry point of the board. An example decoupling scheme is shown in 图 76.
10 ꢀ
10 …F
10 ꢀ
10 …F
VSS
VCC
œ
1 …F
1 …F
+
15V
+
15V
œ
AGND
AGND
AGND
AGND
Ferrite
bead
10 ꢀ
10 …F
AVDD
DVDD
0.1 …F
1 …F
+
5V
œ
AGND
AGND
DGND
Ferrite
bead
IOVDD
0.1 …F
10 …F
+
3.3V
œ
DGND
DGND
图 76. Power-Supply Decoupling
10.1 Power-Supply Sequencing
The DACx1001 do not require any power-supply sequence. However, the power supplies to the AVDD pin must
be capable of providing 30-mA of current if VSS ramps before AVDD. This current is derived from the AVDD pin,
and flows out of the VSS pin. This condition is transient, and the device stops consuming this current when the
power supplies are ramped up. To avoid this condition, make sure to ramp AVDD before VSS
.
44
版权 © 2019, Texas Instruments Incorporated
DAC11001A, DAC91001, DAC81001
www.ti.com.cn
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
11 Layout
11.1 Layout Guidelines
PCB layout plays a significant role for achieving desired ac and dc performance from the DACx1001. The
DACx1001 has a pinout that supports easy splitting of the noisy and quiet grounds. The digital signals are
available on two adjacent sides of the device; whereas, the power and analog signals are available separate
sides. 图 77 shows an example layout, where the different ground planes have been clearly demarcated. The
figure also shows the best positions for the single-point shorts between the ground planes. For best power-
supply bypassing, place the bypass capacitors close to the respective power pins as shown. Provide unbroken
ground reference planes for the digital signal traces, especially for the SPI and LDAC signals.
11.2 Layout Example
POWER INPUT
VCC
VSS
AVDD1
AVDD2
AGND
REFRENCE
INPUTS
PLANE
IOVDD
AGND and
DGND short
DIGITAL
SIGNALS
AGND-OUT and
AGND short
DAC_OUT
EMBEDDED
DAC11001
RESISTORS
IOVDD
DGND
PLANE
DVDD
AGND-OUT
PLANE
IOVDD
DIGITAL
SIGNALS
图 77. Layout Example
版权 © 2019, Texas Instruments Incorporated
45
DAC11001A, DAC91001, DAC81001
ZHCSKD4A –OCTOBER 2019–REVISED DECEMBER 2019
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
BP-DAC11001 评估模块
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
德州仪器 (TI)，《BP-DAC11001EVM 用户指南》
德州仪器 (TI)，《代码对代码干扰在精密 应用 中产生的影响》应用简介
12.3 相关链接
表 12 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具与软件，以及立即订购快速访问。
表 12. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
DAC11001A
DAC91001
12.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
46
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC11001APFBR
DAC11001APFBT
DAC81001PFBR
DAC81001PFBT
DAC91001PFBR
DAC91001PFBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
PFB
PFB
PFB
PFB
PFB
PFB
48
48
48
48
48
48
1000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
250 RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DAC11001A
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
DAC11001A
DAC81001
DAC81001
DAC91001
DAC91001
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC11001APFBR
DAC81001PFBR
DAC91001PFBR
TQFP
TQFP
TQFP
PFB
PFB
PFB
48
48
48
1000
1000
1000
330.0
330.0
330.0
16.4
16.4
16.4
9.6
9.6
9.6
9.6
9.6
9.6
1.5
1.5
1.5
12.0
12.0
12.0
16.0
16.0
16.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC11001APFBR
DAC81001PFBR
DAC91001PFBR
TQFP
TQFP
TQFP
PFB
PFB
PFB
48
48
48
1000
1000
1000
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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