DAC9881SRGETG4 [TI]
适用于高精度应用的 18 位、单通道、低噪声电压输出 DAC | RGE | 24 | -40 to 105;
| 型号： | DAC9881SRGETG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于高精度应用的 18 位、单通道、低噪声电压输出 DAC | RGE | 24 | -40 to 105 转换器 数模转换器 |
| 文件： | 总38页 (文件大小：1433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A–MAY 2008–REVISED AUGUST 2008
18-Bit, Single-Channel, Low-Noise, Voltage-Output
DIGITAL-TO-ANALOG CONVERTER
1
FEATURES
DESCRIPTION
234
•
18-Bit Monotonic Over Temperature Range
Relative Accuracy: ±2LSB Max
Low-Noise: 24nV/√Hz
The DAC9881 is an 18-bit, single-channel,
voltage-output digital-to-analog converter (DAC). It
features 18-bit monotonicity, excellent linearity, very
low-noise, and fast settling time. The on-chip
precision output amplifier allows rail-to-rail output
swing to be achieved over the full supply range of
2.7V to 5.5V.
•
•
•
•
Fast Settling: 5µs
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
•
•
•
Single Power Supply: +2.7V to +5.5V
DAC Loading Control
The device supports a standard SPI serial interface
capable of operating with input data clock frequencies
up to 50MHz. The DAC9881 requires an external
reference voltage to set the output range of the DAC
channel. A programmable power-on reset circuit is
also incorporated into the device to ensure that the
DAC output powers up at zero-scale or midscale, and
remains there until a valid write command.
Selectable Power-On Reset to Zero-Scale or
Midscale
•
•
Power-Down Mode
Unipolar Straight Binary or
Twos Complement Input Mode
Additionally, the DAC9881 has the capability to
function in either unipolar straight binary or twos
complement mode. The DAC9881 provides
low-power operation. To further save energy,
power-down mode can be achieved by accessing the
PDN pin, thereby reducing the current consumption to
25µA at 5V. Power consumption is 4mW at 5V,
reducing to 125µW in power-down mode.
•
•
Fast SPI™ Interface with Schmitt-Triggered
Inputs: up to 50MHz, 1.8V/3V/5V Logic
Small Package: QFN-24, 4mm × 4mm
APPLICATIONS
•
•
•
•
Automatic Test Equipment
Precision Instrumentation
Industrial Control
The DAC9881 is available in a 4mm × 4mm QFN-24
package with a specified temperature range of –40°C
to +105°C.
Data Acquisition Systems
DGND
IOVDD
AGND
AVDD
VREFH-S VREFH-F
DAC9881
RST
RSTSEL
USB/BTC
GAIN
Power-On
Reset
Control
Logic
Resistor
Network
SDI
CS
PDN
VOUT
RFB
SCLK
Input
Register
DAC
Latch
DAC
(1)
RFB
SDOSEL
Serial Out
Control
NOTE: (1) RFB = 5kW for gain = 1,
RFB = 10kW for gain = 2.
SDO
LDAC
VREFL-S
VREFL-F
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
SPI, QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
DAC9881
SBAS438A–MAY 2008–REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PRODUCT
DAC9881S
DAC9881SB
±3
±2
–1/+2
±1
QFN-24
QFN-24
RGE
RGE
–40°C to +105°C
–40°C to +105°C
DAC9881
DAC9881B
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
DAC9881
–0.3 to 6
UNIT
V
AVDD to AGND
IOVDD to DGND
–0.3 to 6
V
Digital input voltage to DGND
VOUT to AGND
–0.3 to IOVDD + 0.3
–0.3 to AVDD + 0.3
–40 to +105
–65 to +150
+150
V
V
Operating temperature range
Storage temperature range
°C
°C
°C
°C/W
V
Maximum junction temperature (TJ max)
Thermal impedance (θJA
)
46
Human body model (HBM)
3000
ESD ratings
Charged device model (CDM)
1000
V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A–MAY 2008–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications at TA = TMIN to TMAX, AVDD = +4.75V to +5.5V, IOVDD = +1.8V to +5.5V, VREFH = 5V, VREFL = 0V, and gain =
1X mode, unless otherwise noted.
DAC9881
PARAMETER
ACCURACY(1)
CONDITIONS
MIN
TYP
MAX
UNIT
Measured by line
passing through
codes 2048 and
260096
DAC9881S
DAC9881SB
DAC9881S
DAC9881SB
±2
±1
±3
±2
+2
±1
LSB
LSB
LSB
LSB
Integral linearity error
Measured by line
passing through
codes 2048 and
260096
–1
18
±0.75
±0.5
Differential linearity error
Monotonicity
Bits
LSB
LSB
TA = +25°C, code = 2048
TMIN to TMAX, code = 2048
Code = 2048
±16
±32
Zero-scale error
Zero-scale drift(2)
Gain error
±0.25
±16
±0.8 ppm/°C of FSR
TA = +25°C, measured by line passing through codes 2048
and 260096
±32
LSB
Gain temperature drift(2)
PSRR(2)
Measured by line passing through codes 2048 and 260096
VOUT = full-scale, AVDD = +5V ±10%
±0.25
±0.4
32
ppm/°C
LSB/V
ANALOG OUTPUT(2)
Voltage output(3)
0
AVDD
V
ppm of FSR
ppm of FSR
mA
Device operating for 500 hours at +25°C
Device operating for 1000 hours at +25°C
0.1
0.2
Output voltage drift vs time
Output current(4)
2.5
Maximum load capacitance
Short-circuit current
200
pF
+31/–50
mA
REFERENCE INPUT(2)
VREFH input voltage range
VREFH input capacitance
VREFH input impedance
VREFL input voltage range
VREFL input capacitance
VREFL input impedance
DYNAMIC PERFORMANCE(2)
AVDD = +5.5V
1.25
–0.2
5.0
5
AVDD
+0.2
V
pF
kΩ
V
4.5
0
4.5
5
pF
kΩ
To ±0.003% FS, RL = 10kΩ, CL = 50pF, code 04000h to
3C000h
Settling time
Slew rate
5
µs
From 10% to 90% of 0V to +5V
VREFH = 5V, gain = 1X mode
VREFH = 2.5V, gain = 1X mode
2.5
37
18
9
V/µs
nV-s
nV-s
Code = 1FFFFh to
Code change glitch
VREFH = 1.25V, gain = 1X mode
20000h to 1FFFFh
nV-s
VREFH = 2.5V, gain = 2X mode
21
10
1
nV-s
VREFH = 1.25V, gain = 2X mode
nV-s
Digital feedthrough
CS = high, fSCLK = 1kHz
nV-s
Gain = 1
24
40
2
30
48
nV/√Hz
nV/√Hz
µVPP
f = 1kHz to 100kHz,
full-scale output
Output noise voltage density
Output noise voltage
Gain = 2
f = 0.1Hz to 10Hz, full-scale output
(1) DAC output range is 0V to +5V. 1LSB = 19µV.
(2) Ensured by design. Not production tested.
(3) The output from the VOUT pin = [(VREFH – VREFL)/262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0V to AVDD
The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
(4) Refer to Figure 26, Figure 27, and Figure 28 for details.
.
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SBAS438A–MAY 2008–REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued)
All specifications at TA = TMIN to TMAX, AVDD = +4.75V to +5.5V, IOVDD = +1.8V to +5.5V, VREFH = 5V, VREFL = 0V, and gain =
1X mode, unless otherwise noted.
DAC9881
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS(5)
IOVDD = 4.5V to 5.5V
IOVDD = 2.7V to 3.3V
IOVDD = 1.7V to 2.0V
IOVDD = 4.5V to 5.5V
IOVDD = 2.7V to 3.3V
IOVDD = 1.7V to 2.0V
3.8
2.1
IOVDD + 0.3
IOVDD + 0.3
IOVDD + 0.3
0.8
V
V
High-level input voltage, VIH
Low-level input voltage, VIL
1.5
V
–0.3
–0.3
–0.3
V
0.6
V
0.3
V
Digital input current (IIN
)
±1
5
±10
µA
pF
Digital input capacitance
DIGITAL OUTPUT(5)
IOVDD = 2.7V to 5.5V, IOH = –1mA
IOVDD = 1.7V to 2.0V, IOH = –500µA
IOVDD = 2.7V to 5.5V, IOL = 1mA
IOVDD = 1.7 to 2.0V, IOL = 500µA
IOVDD – 0.2
IOVDD – 0.2
V
V
V
V
High-level output voltage, VOH
Low-level output voltage, VOL
0.2
0.2
POWER SUPPLY
AVDD
+4.75
+1.7
+5.0
+5.5
AVDD
1.5
V
V
IOVDD
AIDD
VIH = IOVDD, VIL = DGND
VIH = IOVDD, VIL = DGND
PDN pin = IOVDD
0.85
1
mA
µA
µA
mW
IOIDD
10
AIDD power-down
Power dissipation
TEMPERATURE RANGE
Specified performance
25
50
AVDD = 5.0V
4.3
7.5
–40
+105
°C
(5) Ensured by design. Not production tested.
4
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DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A–MAY 2008–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: AVDD = 2.7V
All specifications at TA = TMIN to TMAX, AVDD = +2.7V to +3.3V, IOVDD = +1.8V to AVDD, VREFH = 2.5V, VREFL = 0V and gain =
1X mode, unless otherwise noted.
DAC9881
PARAMETER
ACCURACY(1)
CONDITIONS
MIN
TYP
MAX
UNIT
Measured by line
passing through
codes 2048 and
262143
DAC9881S
DAC9881SB
DAC9881S
DAC9881SB
±2.5
±2
±3.5
±3
LSB
LSB
LSB
LSB
Integral linearity error
Measured by line
passing through
codes 2048 and
262143
±1
±2
Differential linearity error
Zero-scale error
±0.75
±1.5
TA = +25°C, code = 2048
TMIN to TMAX, code = 2048
Code = 2048
±32
±64
LSB
LSB
Zero-scale drift(2)
Gain error
±0.5
±32
±1.6 ppm/°C of FSR
TA = +25°C, measured by line passing through codes 2048
and 262143
±64
LSB
Gain temperature drift(2)
PSRR(2)
Measured by line passing through codes 2048 and 262143
VOUT = full-scale, AVDD = +3V ±10%
±0.5
±0.8
64
ppm/°C
LSB/V
ANALOG OUTPUT(2)
Voltage output(3)
0
AVDD
V
ppm of FSR
ppm of FSR
mA
Device operating for 500 hours at +25°C
Device operating for 1000 hours at +25°C
0.2
0.4
Output voltage drift vs time
Output current(4)
2.5
Maximum load capacitance
200
pF
Short-circuit current
+31/–50
mA
REFERENCE INPUT(2)
VREFH input voltage range
VREFH input capacitance
VREFH input impedance
VREFL input voltage range
VREFL input capacitance
VREFL input impedance
DYNAMIC PERFORMANCE(2)
AVDD = +3V
1.25
–0.2
2.5
5
AVDD
+0.2
V
pF
kΩ
V
4.5
0
4.5
5
pF
kΩ
To ±0.003% FS, RL = 10kΩ, CL = 50pF, code 04000h to
3C000h
Settling time
Slew rate
5
µs
From 10% to 90% of 0V to +2.5V
2.5
18
9
V/µs
nV-s
VREFH = 2.5V, gain = 1X mode
Code = 1FFFFh to
Code change glitch
VREFH = 1.25V, gain = 1X mode
20000h to 1FFFFh
nV-s
VREFH = 1.25V, gain = 2X mode
10
1
nV-s
Digital feedthrough
CS = high, fSCLK = 1kHz
nV-s
Gain = 1
24
40
2
30
48
nV/√Hz
nV/√Hz
µVPP
f = 1kHz to 100kHz,
full-scale output
Output noise voltage density
Output noise voltage
Gain = 2
f = 0.1Hz to 10Hz, full-scale output
(1) DAC output range is 0V to +2.5V. 1LSB = 9.5µV.
(2) Ensured by design. Not production tested.
(3) The output from the VOUT pin = [(VREFH – VREFL)/262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0V to AVDD
The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
(4) Refer to Figure 55, Figure 56, and Figure 57 for details.
.
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SBAS438A–MAY 2008–REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 2.7V (continued)
All specifications at TA = TMIN to TMAX, AVDD = +2.7V to +3.3V, IOVDD = +1.8V to AVDD, VREFH = 2.5V, VREFL = 0V and gain =
1X mode, unless otherwise noted.
DAC9881
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS(5)
IOVDD = 2.7V to 3.3V
IOVDD = 1.7V to 2.0V
IOVDD = 2.7V to 3.3V
IOVDD = 1.7V to 2.0V
2.1
1.5
IOVDD + 0.3
IOVDD + 0.3
0.6
V
V
High-level input voltage, VIH
Low-level input voltage, VIL
–0.3
–0.3
V
0.3
V
Digital input current (IIN
)
±1
5
±10
µA
pF
Digital input capacitance
DIGITAL OUTPUT(5)
IOVDD = 2.7V to 3.3V, IOH = –1mA
IOVDD = 1.7V to 2.0V, IOH = –500µA
IOVDD = 2.7V to 3.3V, IOL = 1mA
IOVDD = 1.7 to 2.0V, IOL = 500µA
IOVDD – 0.2
IOVDD – 0.2
V
V
V
V
High-level output voltage, VOH
Low-level output voltage, VOL
0.2
0.2
POWER SUPPLY
AVDD
+2.7
+1.7
+3.0
+3.3
AVDD
1.2
V
V
IOVDD
AIDD
VIH = IOVDD, VIL = DGND
VIH = IOVDD, VIL = DGND
PDN pin = IOVDD
0.75
1
mA
µA
µA
mW
IOIDD
10
AIDD power-down
Power dissipation
TEMPERATURE RANGE
Specified performance
25
50
AVDD = 3.0V
2.3
3.6
–40
+105
°C
(5) Ensured by design. Not production tested.
6
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DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A–MAY 2008–REVISED AUGUST 2008
PIN CONFIGURATION
RGE PACKAGE(1)
QFN-24
(TOP VIEW)
1
2
3
4
5
6
18 PDN
SCLK
SDI
17 RST
16 USB/BTC
15 GAIN
14 RSTSEL
13 NC
LDAC
AGND
AVDD
DAC9881
(Thermal Pad)(1)
VREFL-S
(1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left
floating. Keep the thermal pad separate from the digital ground, if possible.
TERMINAL FUNCTIONS
TERMINAL
NO.
1
NAME
SCLK
SDI
I/O
DESCRIPTION
I
I
SPI bus serial clock input
SPI bus serial data input
2
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input
register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the
DAC latch is updated. It is recommended to connect this pin to IOVDD through a pull-up resistor.
3
LDAC
I
4
5
AGND
AVDD
I
I
Analog ground
Analog power supply
6
VREFL-S
VREFH-S
VOUT
I
Reference low input sense
Reference high input sense
Output of output buffer
7
I
8
O
I
9
RFB
Feedback resistor connected to the inverting input of the output buffer.
Reference low input force
Reference high input force
Do not connect.
10
11
12
13
VREFL-F
VREFH-F
NC
I
I
—
—
NC
Do not connect.
Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data
= 20000h. If RSTSEL = DGND, then register data = 00000h.
14
15
16
17
18
RSTSEL
GAIN
I
I
I
I
I
Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD
.
Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in twos
complement format when the pin is connected to DGND.
USB/BTC
RST
Reset input (active low). Logic low on this pin causes the device to perform a reset.
Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT
pin connects to AGND through a 10kΩ resistor.
PDN
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is
high, SDO is in a high-impedance state. It is recommended to connect this pin to IOVDD through a pull-up resistor.
19
20
CS
I
I
SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out
from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register
are shifted out from the SDO pin; this is Daisy-Chain mode for daisy-chained communication.
SDOSEL
21
22
23
24
AVDD
DGND
SDO
I
I
Analog power supply. Must be connected to pin 5.
Digital ground
O
I
SPI bus serial data output. Refer to the Timing Diagrams for further detail.
Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic.
IOVDD
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TIMING DIAGRAMS
Case 1: Standalone operation without SDO, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t5
t6
t7
SCLK
t8
t9
Bit 23 (N)
Bit 22 (N)
Bit 1 (N)
Bit 0 (N)
SDI
Low
LDAC
Case 2: Standalone operation without SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t5
t6
t7
SCLK
t8
t9
Bit 23 (N)
Bit 22 (N)
Bit 1 (N)
Bit 0 (N)
SDI
t14
t15
High
LDAC
DAC Latch
Updated
Bit 23 = MSB
Bit 0 = LSB
= Don’t Care
Figure 1. Timing Diagram for Standalone Operation without SDO
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TIMING CHARACTERISTICS for Figure 1(1)(2)(3)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
MAX
40
UNIT
MHz
MHz
ns
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
fSCLK
Maximum clock frequency
50
50
30
10
8
t1
Minumum CS high time
ns
ns
Delay from CS falling edge to SCLK rising
edge
t2
ns
0
ns
Delay from SCLK falling edge to CS falling
edge
t3
0
ns
10
10
15
10
25
20
10
10
8
ns
t4
SCLK low time
SCLK high time
SCLK cycle time
ns
ns
t5
ns
ns
t6
ns
ns
Delay from SCLK rising edge to CS rising
edge
t7
ns
ns
t8
Input data setup time
Input data hold time
5
ns
5
ns
t9
5
ns
10
5
ns
Delay from CS rising edge to LDAC falling
edge
t14
ns
15
10
ns
t15
LDAC pulse width
ns
(1) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
(2) Ensured by design. Not production tested.
(3) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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Case 1: Standalone operation with output from SDO, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t5
t6
t7
SCLK
t8
t9
Bit 23 (N)
Bit 22 (N)
Bit 1 (N)
Bit 0 (N)
SDI
t11
t12
t13
Bit 23 (N - 1)
from Input Reg.
Bit 22 (N - 1)
from Input Reg.
Bit 1 (N - 1)
from Input Reg.
Bit 0 (N - 1)
from Input Reg.
High-Z
High-Z
SDO
t10
Low
LDAC
Case 2: Standalone operation with output from SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t5
t6
t7
SCLK
t8
t9
Bit 23 (N)
Bit 22 (N)
Bit 1 (N)
Bit 0 (N)
SDI
t11
t12
t13
Bit 23 (N - 1)
from Input Reg.
Bit 22 (N - 1)
from Input Reg.
Bit 1 (N - 1)
from Input Reg.
Bit 0 (N - 1)
from Input Reg.
High-Z
High-Z
SDO
t10
t14
t15
High
LDAC
DAC Latch
Updated
Bit 23 = MSB
Bit 0 = LSB
= Don’t Care
Figure 2. Timing Diagram for Standalone Operation with SDO
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Case 1: Daisy Chain, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t5
t6
t7
SCLK
t8
t9
Bit 23 (N)
Bit 22 (N)
Bit 0 (N)
Bit 23 (N + 1)
Bit 0 (N + 1)
SDI
t11
t12
Bit 23 (N)(1)
t13
Bit 0 (N)
High-Z
High-Z
SDO
t10
Low
LDAC
Case 2: Daisy Chain, LDAC active.
t1
t2
CS
Input Register
Updated
t3
t4
t5
t6
t7
SCLK
t8
t9
Bit 23 (N)
Bit 22 (N)
Bit 0 (N)
Bit 23 (N + 1)
Bit 0 (N + 1)
SDI
t11
t12
t13
Bit 23 (N)(1)
Bit 0 (N)
High-Z
High-Z
SDO
t10
t14
t15
High
LDAC
DAC Latch
Updated
Bit 23 = MSB
Bit 0 = LSB
= Don’t Care
NOTE: (1) SDO data delayed from SDI by 24 clock cycles.
Figure 3. Timing Diagram for Daisy Chain Mode, Two Cascaded Devices
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TIMING CHARACTERISTICS for Figure 2 and Figure 3(1)(2)(3)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
MAX
20
UNIT
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD
fSCLK
Maximum clock frequency
25
50
30
10
8
t1
Minumum CS high time
Delay from CS falling edge to SCLK rising
edge
t2
0
Delay from SCLK falling edge to CS falling
edge
t3
0
25
20
25
20
50
40
10
10
5
t4
SCLK low time
SCLK high time
SCLK cycle time
t5
t6
Delay from SCLK rising edge to CS rising
edge
t7
t8
Input data setup time
5
5
t9
Input data hold time
5
15
10
20
15
t10
t11
t12
t13
t14
t15
Delay from CS falling edge to SDO valid
Delay from SCLK falling edge to SDO valid
SDO data hold from SCLK rising edge
Delay from CS rising edge to SDO high-Z
t5
t5
8
5
10
5
Delay from CS rising edge to LDAC falling
edge
15
10
LDAC pulse width
(1) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
(2) Ensured by design. Not production tested.
(3) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
12
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TYPICAL CHARACTERISTICS: AVDD = +5V
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
2.0
1.5
2.0
1.5
TA = +25°C
TA = +25°C
1.0
1.0
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
0
0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
0
0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 4.
Figure 5.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
2.0
1.5
2.0
1.5
TA = -40°C
TA = -40°C
1.0
1.0
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 6.
Figure 7.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
2.0
1.5
2.0
1.5
TA = +105°C
TA = +105°C
1.0
1.0
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
2.0
1.5
2.0
1.5
INL Max
1.0
1.0
DNL Max
DNL Min
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
INL Min
-40
-20
0
20
40
60
80
100
120
120
6.0
-40
-20
0
20
40
60
80
100
120
120
6.0
Temperature (°C)
Temperature (°C)
Figure 10.
Figure 11.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (GAIN = 2X MODE)
vs TEMPERATURE (GAIN = 2X MODE)
2.0
1.5
2.0
1.5
INL Max
1.0
1.0
DNL Max
DNL Min
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
INL Min
VREFH = 2.5V
VREFL = 0V
VREFH = 2.5V
VREFL = 0V
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
Figure 12.
Figure 13.
LINEARITY ERROR
vs SUPPLY VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs SUPPLY VOLTAGE
2.0
1.5
2.0
1.5
INL Max
INL Min
1.0
1.0
DNL Max
DNL Min
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
VREFH = 2.5V
VREFL = 0V
VREFH = 2.5V
VREFL = 0V
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
Supply Voltage (V)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
2.0
1.5
2.0
1.5
INL Max
INL Min
1.0
1.0
DNL Max
DNL Min
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
0
1.0
2.0
3.0
4.0
5.0
6.0
0
1.0
2.0
3.0
4.0
5.0
6.0
Reference Voltage (V)
Reference Voltage (V)
Figure 16.
Figure 17.
FULL-SCALE AND ZERO-SCALE ERROR
vs TEMPERATURE
FULL-SCALE AND ZERO-SCALE ERROR
vs TEMPERATURE (GAIN = 2X MODE)
1.0
0.8
1.0
0.8
VREFH = 2.5V
VREFL = 0V
0.6
0.6
0.4
0.4
Full-Scale Error
Zero-Scale Error
Full-Scale Error
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
Zero-Scale Error
-55 -35 -15
5
25
45
65
85
105 125
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
Figure 18.
Figure 19.
AVDD SUPPLY CURRENT
vs DIGITAL INPUT CODE
AVDD SUPPLY CURRENT
vs DIGITAL INPUT CODE (GAIN = 2X MODE)
1100
1000
900
800
700
600
500
400
300
200
1000
900
800
700
600
500
400
300
200
100
0
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
AVDD = 5.0V
VREFH = 5.0V
VREFL = 0V
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
AVDD=2.7V
VREFH=1.25V
VREFL=0V
AVDD = 2.7V
VREFH = 2.7V
VREFL = 0V
AVDD = 2.7V
VREFH = 2.5V
VREFL = 0V
0
65536
131072
196608
262144
0
65536
131072
196608
262144
Digital Input Code
Digital Input Code
Figure 20.
Figure 21.
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TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
AVDD SUPPLY CURRENT
vs TEMPERATURE
AVDD POWER-DOWN CURRENT
vs TEMPERATURE
1200
1000
800
600
400
200
0
50
40
30
20
10
0
VREFH = 5.0V
VREFH = 2.5V
VREFL = 0V
AVDD = 5.0V
AVDD = 2.7V
VREFL = 0V
Gain = 1X Mode
Gain = 2X Mode
DAC Code Set to 3F000h
-55 -35 -15
5
25
45
65
85
105 125
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
Figure 22.
Figure 23.
REFERENCE CURRENT
vs DIGITAL INPUT CODE
REFERENCE CURRENT
vs DIGITAL INPUT CODE (GAIN = 2X MODE)
1.5
1.0
1.5
1.0
VREFH = 2.5V
VREFL = 0V
VREFH Current
VREFH Current
0.5
0.5
0
0
VREFL Current
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
VREFL Current
0
65536
131072
196608
262144
0
65536
131072
196608
262144
Digital Input Code
Digital Input Code
Figure 24.
Figure 25.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AVDD Rail)
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.00
DAC Loaded with 3FFFFh
DAC Loaded with 3FFFFh
4.95
4.90
4.85
4.80
4.75
DAC Loaded with 3F800h
DAC Loaded with 3F000h
DAC Loaded with 3E000h
DAC Loaded with 00000h
0
3
6
9
12
15
0
1
2
3
4
5
I(SOURCE/SINK) (mA)
ISOURCE (mA)
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AGND Rail)
IOVDD SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
200
180
160
140
120
100
80
0.25
0.20
0.15
0.10
0.05
0
IOVDD = 5V
DAC Loaded with 02000h
DAC Loaded with 01000h
DAC Loaded with 00800h
60
40
IOVDD = 2.7V
20
DAC Loaded with 00000h
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Logic Input Voltage (V)
0
1
2
3
4
5
ISINK (mA)
Figure 28.
Figure 29.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
Large-Signal Output
2V/div
Small-Signal Error
Large-
Signal
Output
Small-Signal Error
2V/div
5V/div
1mV/div
1mV/div
LDAC
Signal
LDAC
Signal
Code Change: 00000h to 3FFFFh
Output Loaded with 10kW and
50pF to AGND
Code Change: 3FFFFh to 00000h
Output Loaded with 10kW and
50pF to AGND
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 30.
Figure 31.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
Small-Signal Error
2V/div
5V/div
1mV/div
1mV/div
LDAC
Signal
LDAC
Signal
Code Change: 04000h to 3C000h
Output Loaded with 10kW and
50pF to AGND
Code Change: 3C000h to 04000h
Output Loaded with 10kW and
50pF to AGND
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 32.
Figure 33.
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TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
VREFH = 2.5V
VREFH = 2.5V
Large-Signal Output
2V/div
Small-Signal Error
Large-
Signal
Output
Small-Signal Error
2V/div
5V/div
1mV/div
1mV/div
LDAC
Signal
LDAC
Signal
Code Change: 00000h to 3FFFFh
Output Loaded with 10kW and
50pF to AGND
Code Change: 3FFFFh to 00000h
Output Loaded with 10kW and
50pF to AGND
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 34.
Figure 35.
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
VREFH = 2.5V
VREFH = 2.5V
Large-Signal Output
Small-Signal Error
2V/div
Large-Signal Output
Small-Signal Error
2V/div
5V/div
1mV/div
1mV/div
LDAC
Signal
LDAC
Signal
Code Change: 04000h to 3C000h
Output Loaded with 10kW and
50pF to AGND
Code Change: 3C000h to 04000h
Output Loaded with 10kW and
50pF to AGND
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 36.
Figure 37.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code Change: 1FFFFh to 20000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +5V
Gain = 1X Mode
VREFH = +5V
Integrated Glitch Energy (28nV-s)
VOUT Signal
VOUT Signal
100mV/div
100mV/div
Integrated Glitch Energy (38nV-s)
Code Change: 20000h to 1FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 38.
Figure 39.
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TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code Change: 1FFFFh to 20000h
Gain = 1X Mode
VREFH = +2.5V
Gain = 1X Mode
VREFH = +2.5V
Output Loaded with 10kW and
50pF to AGND
Integrated Glitch Energy (15nV-s)
VOUT Signal
VOUT Signal
100mV/div
100mV/div
Integrated Glitch Energy (17nV-s)
Code Change: 20000h to 1FFFFh
Output Loaded with 10kW and
5V/div
LDAC
Signal
5V/div
LDAC
Signal
50pF to AGND
Time (2ms/div)
Time (2ms/div)
Figure 40.
Figure 41.
OUTPUT NOISE DENSITY
vs FREQUENCY
LOW-FREQUENCY OUTPUT NOISE
(0.1Hz to 10Hz)
180
160
140
120
100
80
DAC Code Set to 20000h
Output Unloaded
60
Gain = 2X Mode
Gain = 1X Mode
40
20
0
1
Time (1s/div)
10
100
1k
10k
100k
Frequency (Hz)
Figure 42.
Figure 43.
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TYPICAL CHARACTERISTICS: AVDD = +2.7V
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
3.0
2.0
2.0
1.5
TA = +25°C
TA = +25°C
1.0
1.0
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-1.0
-2.0
-3.0
0
0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
0
0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 44.
Figure 45.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
3.0
2.0
2.0
1.5
TA = -40°C
TA = -40°C
1.0
1.0
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-1.0
-2.0
-3.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 46.
Figure 47.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
3.0
2.0
2.0
1.5
TA = +105°C
TA = +105°C
1.0
1.0
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-1.0
-2.0
-3.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 48.
Figure 49.
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TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued)
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
4.0
3.0
2.0
1.5
INL Max
INL Min
DNL Max
2.0
1.0
1.0
0.5
0
0
DNL Min
-1.0
-2.0
-3.0
-4.0
-0.5
-1.0
-1.5
-2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Reference Voltage (V)
Reference Voltage (V)
Figure 50.
Figure 51.
AVDD SUPPLY CURRENT
vs TEMPERATURE
REFERENCE CURRENT
vs DIGITAL INPUT CODE
1000
900
800
700
600
500
400
300
200
100
0
1.00
0.75
0.50
0.25
0
VREFH = 2.5V
VREFL = 0V
VREF = 2.5V, Gain = 1X Mode
VREF = 1.25V, Gain = 2X Mode
VREFH Current
VREFL Current
-0.25
-0.50
-0.75
-1.00
DAC Code Set to 3FFFFh
-55 -35 -15
5
25
45
65
85
105 125
0
65536
131072
196608
262144
Temperature (°C)
Digital Input Code
Figure 52.
Figure 53.
REFERENCE CURRENT
vs DIGITAL INPUT CODE (GAIN = 2X MODE)
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
1.00
0.75
0.50
0.25
0
3.0
2.5
2.0
1.5
1.0
0.5
0
DAC Loaded with 3FFFFh, VREFH = 2.7V
VREFH = 1.25V
VREFL = 0V
DAC Loaded with 3FFFFh, VREFH = 2.5V
VREFH Current
VREFL Current
-0.25
-0.50
-0.75
-1.00
DAC Loaded with 00000h
0
65536
131072
196608
262144
0
3
6
9
12
15
Digital Input Code
I(SOURCE/SINK) (mA)
Figure 54.
Figure 55.
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TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued)
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AVDD Rail)
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AGND Rail)
2.70
2.65
2.60
2.55
2.50
2.45
2.40
0.25
0.20
0.15
0.10
0.05
0
DAC Loaded with 3FFFFh
DAC Loaded
with 01000h
DAC Loaded
with 3F800h
DAC Loaded
DAC Loaded
with 3E000h
DAC Loaded
with 00800h
with 02000h
DAC Loaded
with 3F000h
DAC Loaded with 3FFFFh, VREFH = 2.5V
VREFH = 2.7V, unless otherwise noted.
DAC Loaded with 00000h
0
1
2
3
4
5
0
1
2
3
4
5
ISOURCE (mA)
ISINK (mA)
Figure 56.
Figure 57.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
Code Change: 3FFFFh to 00000h
Output Loaded with 10kW and
50pF to AGND
Large-Signal Output
1V/div
Large-Signal Output
Small-Signal Error
Small-Signal Error
1V/div
5V/div
1mV/div
1mV/div
Code Change: 00000h to 3FFFFh
Output Loaded with 10kW and
50pF to AGND
LDAC
Signal
LDAC
Signal
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 58.
Figure 59.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
Large-Signal Output
1V/div
Large-Signal Output
Small-Signal Error
1V/div
5V/div
1mV/div
1mV/div
Small-Signal Error
Code Change: 04000h to 3C000h
Output Loaded with 10kW and
50pF to AGND
Code Change: 3C000h to 04000h
Output Loaded with 10kW and
50pF to AGND
LDAC
Signal
LDAC
Signal
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 60.
Figure 61.
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TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued)
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code Change: 1FFFFh to 20000h
Gain = 1X Mode
VREFH = +2.5V
Gain = 1X Mode
VREFH = +2.5V
Output Loaded with 10kW and
50pF to AGND
Integrated Glitch Energy (17.5nV-s)
VOUT Signal
VOUT Signal
100mV/div
100mV/div
Integrated Glitch Energy (16.5nV-s)
Code Change: 20000h to 1FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 62.
Figure 63.
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THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC9881 is a single-channel, 18-bit, serial-input, voltage-output digital-to-analog converter (DAC). The
architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier
that serves as a buffer, as shown in Figure 64. The on-chip output buffer allows rail-to-rail output swings while
providing a low output impedance to drive loads. The DAC9881 operates from a single analog power supply that
ranges from 2.7V to 5.5V, and typically consumes 850µA when operating with a 5V supply. Data are written to
the device in a 24-bit word format, via an SPI serial interface. To enable compatibility with 1.8V, 3V, or 5V logic
families, an IOVDD supply pin is provided. This pin allows the DAC9881 input and output logic to be powered
from the same logic supply used to interface signals to and from the device. Internal voltage translators are
included in the DAC9881 to interface digital signals to the device core. See Figure 65 for the basic configuration
of the DAC9881.
To ensure a known power-up state, the DAC9881 is designed with a power-on reset function. Upon power-up,
the DAC9881 is reset to either zero-scale or midscale depending on the state of the RSTSEL pin. A harrdware
reset can be performed by using the RST and RSTSEL pins.
(1)
RFB
RFB
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
5kW
VREFH
5kW
NOTE: (1) RFB = 5kW for gain = 1
RFB = 10kW for gain = 2.
VREFH-F
VREFH-S
VREFL-F
VREFL-S
Figure 64. DAC9881 Architecture
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+5V
+
0.1mF
1mF
+
0.1mF
1mF
SCLK
PDN
1
2
3
4
5
6
18
17
16
15
14
13
Clock
SDI
LDAC
AGND
AVDD
RST
Reset DAC Registers
Serial Data In
USB/BTC
GAIN
Load DAC Registers
DAC9881
RSTSEL
NC
(Thermal Pad)
VREFL-S
0V to +5.0V
External Reference
+5.0000V
Figure 65. Basic Configuration
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ANALOG OUTPUT
The DAC9881 offers a force and sense output configuration for the high open-loop gain output amplifier. This
feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 66), thus
ensuring an accurate output voltage. The output buffer VOUT and RFB pins are provided so that the output op amp
buffer feedback can be connected at the load. Without a driven load, the DAC9881 output typically swings to
within 15mV of the AGND and AVDD supply rails. Because of the high accuracy of these DACs, system design
problems such as grounding and wiring resistance become very important. A 18-bit converter with a 5V full-scale
range has an LSB value of 19µV. The DAC9881 has a typical feedback resistor current of 0.5mA; thus, a series
wiring resistance of only 100mΩ (RW1) causes a voltage drop of 50µV. In terms of a system layout, the resistivity
of a typical 1-ounce copper-clad printed circuit board (PCB) is 0.5mΩ per square. For a 0.5mA current, a
0.25mm wide printed circuit conductor 25mm long results in a voltage drop of 25µV. Note that the wiring
resistance of RW2 is not critical as long as the feedback resistor (RFB) is connected at the driven load.
+5V
+
0.1mF
1mF
+
0.1mF
1mF
SCLK
PDN
1
2
3
4
5
6
18
17
16
15
14
13
Clock
SDI
LDAC
AGND
AVDD
RST
Reset DAC Registers
Serial Data In
USB/BTC
GAIN
Load DAC Registers
DAC9881
RSTSEL
NC
(Thermal Pad)
VREFL-S
VOUT
External Reference
+5.0000V
Figure 66. Analog Output Closed-Loop Configuration
(RW1 and RW2 represent wiring resistance)
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REFERENCE INPUTS
The reference high input, VREFH, can be set to any voltage in the range of 1.25V to AVDD. The reference low
input, VREFL, can be set to any voltage in the range of –0.2V to +0.2V (to provide a small offset to the output of
the DAC9881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from
approximately 0.5mA to 1mA in the gain = 1X mode of operation. The reference high and low inputs appear as
variable loads to the external reference circuit. If the external references can source or sink the required current,
and if low impedance connections are made to the VREFH and VREFL pins, external reference buffers are not
required. Figure 65 shows a simple configuration of the DAC9881 using external references without force and
sense reference buffers.
Kelvin sense connections for the reference high and low are included on the DAC9881. When properly used with
external reference buffer op amps, these reference Kelvin sense pins ensure that the driven reference high and
low voltages remain stable versus varying reference load currents. Figure 67 shows an example of a reference
force and sense configuration of the DAC9881 operating from a single analog reference voltage. Both the VREFL
and VREFH reference voltages are set to levels of 100mV from the DAC9881 supply rails, and are derived from a
+5V external reference. Figure 68 illustrates the effect of not using the reference force and sense buffers to drive
the DAC9881 VREFL and VREFH pins. Figure 69 shows the improvement when using the reference buffers. A slight
degradation in INL and DNL performance is seen without the use of the force and sense buffer configuration.
SCLK
1
SDI
2
LDAC
3
+5V
AGND
4
5
6
External Reference
+5.0000V
AVDD
DAC9881
OPA2350
VREFL-S
2200pF
2kW
50W
+4.900V
1000pF
96kW
+0.100V
50W
1000pF
2kW
2200pF
NOTE: VREFL can be connected to AGND if VREFL is not biased.
Figure 67. Buffered References (VREFH = +4.900V and VREFL = 100mV).
2.0
1.5
2.0
1.5
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
2.0
1.5
2.0
1.5
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 68. Linearity and Differential Linearity Error
for Figure 65 without Reference Buffers
Figure 69. Linearity and Differential Linearity Error
for Figure 67 with Reference Buffers
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OUTPUT RANGE
The maximum output range of the DAC9881 is VREFL to (VREFH – VREFL) × G, where G is the output buffer gain
set by the GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin
is connected to IOVDD, the output buffer gain = 2. The output range must not be greater than AVDD; otherwise,
output saturation occurs. The DAC9881 output transfer function is given in Equation 1:
VREFH - VREFL
VOUT
=
´ CODE ´ Buffer Gain + VREFL
262144
(1)
Where:
CODE = 0 to 262143. This is the digital code loaded to the DAC.
Buffer Gain = 1 or 2 (set by the GAIN pin).
VREFH = reference high voltage applied to the device.
VREFL = reference low voltage applied to the device.
INPUT DATA FORMAT
The USB/BTC pin defines the input data format. When this pin is connected to IOVDD, the input data format is
straight binary, as shown in Table 1. When this pin is connected to DGND, the input data format is twos
complement, as shown in Table 2.
Table 1. Output vs Straight Binary Code
USB CODE
3FFFFh
30000h
5V RANGE
+4.99998
+3.75000
+2.50000
+1.25000
0.00000
DESCRIPTION
+Full-Scale – 1LSB
3/4-Scale
20000h
Midscale
10000h
1/4-Scale
00000h
Zero-Scale
Table 2. Output vs Twos Complement Code
BTC CODE
1FFFFh
10000h
5V RANGE
+4.99998
+3.75000
+2.50000
+2.49998
+1.25000
0.00000
DESCRIPTION
+Full-Scale – 1LSB
3/4-Scale
00000h
Midscale
3FFFFh
30000h
Midscale – 1LSB
1/4-Scale
20000h
Zero-Scale
POWER DOWN
The DAC9881 has a hardware power-down function. When the PDN pin is high, the device is in power-down
mode. When the device is in power-down, the VOUT pin is connected to ground through an internal 10kΩ resistor,
but the contents of the input register and the DAC latch do not change and SPI communication remains active.
When the PDN pin returns low, the device returns to normal operation.
HARDWARE RESET
When the RST pin is low, the device is in hardware reset mode, and the input register and DAC latch are set to
the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode, and the
input register and DAC latch maintain the reset value until new data are written.
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POWER-ON RESET
The DAC9881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and
the output from the VOUT pin are set to the value defined by the RSTSEL pin.
PROGRAM RESET VALUE
After a power-on reset or a hardware reset, the output voltage from the VOUT pin and the values of the input
register and DAC latch are determined by the status of the RSTSEL pin and the input data format, as shown in
Table 3.
Table 3. Reset Value
RSTSEL PIN
DGND
USB/BTC PIN
IOVDD
INPUT FORMAT
Straight Binary
VOUT
0
VALUE OF INPUT REGISTER AND DAC LATCH
00000h
20000h
00000h
20000h
IOVDD
IOVDD
Straight Binary
Midscale
Midscale
0
DGND
DGND
Twos Complement
Twos Complement
IOVDD
DGND
SERIAL INTERFACE
The DAC9881 is controlled by a versatile three-wire serial interface that operates at clock rates of up to 50MHz
and is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards.
Input Shift Register
Data are loaded into the device as a 24-bit word under the control of the serial clock input, SCLK. The timing
diagrams for this operation are shown in the Timing Diagram section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be
transferred into the device only while CS is low. When CS is high, the SCLK and SDI signals are blocked out,
and SDO is in high-Z status. To start the serial data transfer, CS should be taken low, observing the minimum
delay from CS falling edge to SCLK rising edge, t2. After CS goes low, serial input data from SDI are clocked into
the device input shift register on the rising edges of SCLK for 24 or more clock pulses. If a frame contains less
than 24 bits of data, the frame is invalid. Invalid input data are not written into the input register and DAC,
although the input register and DAC will continue to hold data from the preceding valid data cycle. If more than
24 bits of data are transmitted in one frame, the last 24 bits are written into the shift register and DAC. CS may
be taken high after the rising edge of the 24th SCLK pulse, observing the minimum SCLK rising edge to CS
rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of
CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and
DAC output can be updated by taking the LDAC pin low. Table 4 shows the input shift register data word format.
D17 is the MSB of the 18-bit DAC data.
Table 4. Input Shift Register Data Word Format
B17
B0
BIT
B23 B22 B21 B20 B19 B18 (MSB) B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB)
DATA X(1)
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
(1) X = don't care.
Stand-Alone Mode
When the SDOSEL pin is tied to IOVDD, the interface is in Stand-Alone mode. This mode provides serial
readback for diagnostic purposes. The new input data (24 bits) are clocked into the device shift register and the
existing data in the input register (24 bits) are shifted out from the SDO pin. If more than 24 SCLKs are clocked
when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last
24 bits of input data remain in the shift register. If less than 24 SCLKs are clocked while CS is low, the data from
the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further details.
Daisy-Chain Mode
When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several
DACs, the SDO pin may be used to daisy-chain several devices together.
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In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 24
clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are
clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the SDI input
on the next DAC in the chain, a multi-DAC interface is constructed. 24 clock pulses are required for each DAC in
the chain. Therefore, the total number of clock cycles must be equal to (24 x N), where N is the total number of
devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action
prevents any further data from being clocked into the input shift register. The contents in the shift registers are
transferred into the relevant input registers on the rising edge of the CS signal.
A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high
some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC
registers, and all analog outputs update simultaneously.
DOUBLE-BUFFERED INTERFACE
The DAC9881 has a double-buffered interface consisting of two register banks: the input register and the DAC
latch. The input register is connected directly to the input shift register and the digital code is transferred to the
input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the
resistor R-2R ladder. The contents of the DAC latch defines the output from the DAC.
Access to the DAC latch is controlled by the LDAC pin. When LDAC is high, the DAC latch is latched and the
input register can change state without affecting the contents of the DAC latch. When LDAC is low, however, the
DAC latch becomes transparent and the contents of the input register is transferred to the DAC register.
Load DAC Pin (LDAC)
LDAC transfers data from the input register to the DAC latch (and, therefore, updates the DAC output). The
contents of the DAC latch (and the output from DAC) can be changed in two ways, depending on the status of
LDAC.
Synchronous Mode
When LDAC is tied low, the DAC latch updates as soon as new data are transferred into the input register after
the rising edge of CS.
Asynchronous Mode
When LDAC is high, the DAC latch is latched. The DAC latch (and DAC output) is not updated at the same time
that the input register is written to. When LDAC goes low, the DAC latch updates with the contents of the input
register.
1.8V TO 5V LOGIC INTERFACE
All digital input and output pins are compatible with any logic supply voltage between 1.8V and 5V. Connect the
interface logic supply voltage to the IOVDD pin. Although timing is specified down to 2.7V (see the Timing
Characteristics), IOVDD can operate as low as 1.8V, but with degraded timing and temperature performance. For
the lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels
should be as close as possible to GND.
POWER-SUPPLY SEQUENCE
For the device to work properly, IOVDD must not come up before AVDD, and the reference voltage must come up
after the AVDD supply. Additionally, because the DAC input shift register is not reset during a power-on reset or
hardware reset, the CS pin must not be unintentionally asserted during power-up of the device. To avoid
improper power-up, it is recommended that the CS and LDAC pins be connected to IOVDD through pull-up
resistors. To ensure that the electrostatic discharge (ESD) protection circuitry of this device is not activated, all
other digital pins must be held at ground potential until IOVDD is applied.
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DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A–MAY 2008–REVISED AUGUST 2008
APPLICATION INFORMATION
BIPOLAR OPERATION USING THE DAC9881
The DAC9881 is designed for single-supply operation; however, a bipolar output is also possible using the circuit
shown in Figure 70. This circuit gives a bipolar output voltage of VBIP. When GAIN = 1, VBIP can be calculated
using Equation 2:
R3 R3
+
R2 R1
CODE
R3
R1
VBIP(CODE) = 1 +
´
-
´ VREF
262144
(2)
Where:
VBIP(CODE) = bipolar output voltage versus CODE from the OPA211.
CODE = 0 to 262143. This is the digital code loaded to the DAC.
VREF = reference high voltage applied to the DAC9881.
By first choosing a value for resistor R3, R1 and R2 can be determined by Equation 3 and Equation 4,
respectively:
VREF
R1
=
´ R3
VBIP
REF ´ R3
BIP - VREF
(3)
(4)
V
R2
=
V
Where:
VBIP= peak desired output voltage for bipolar output.
VREF = reference high voltage applied to the DAC9881. NOTE: VBIP ≥ VREF
.
R3 = OPA211 feedback resistor chosen by user.
Note that R2 is not required in the circuit of Figure 70 for bipolar output voltage ranges equal to ±VREF
.
Using the previous equations, and with VREF = 5V and R3 set to 10kΩ, a ±8V output span can be achieved with
R1 calculated to be 6.25kΩ and R2 to be 16.67kΩ.
Similarly, a near ±15V rail-to-rail output can be achieved with R1 calculated to be 3.33kΩ and R2 calculated to be
5kΩ.
VREFL
+15V
VOUT
DAC9881
VBIP
R2
OPA211
VREFH
-15V
R3
R1
VREF
NOTE: Some pins omitted for clarity.
Figure 70. Bipolar Operation Using the DAC9881
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): DAC9881
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2008
PACKAGING INFORMATION
Orderable Device
DAC9881SBRGER
DAC9881SBRGET
DAC9881SRGER
DAC9881SRGET
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RGE
24
24
24
24
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
VQFN
VQFN
RGE
RGE
RGE
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
DAC9881SBRGER
DAC9881SBRGET
DAC9881SRGER
DAC9881SRGET
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
24
24
24
24
3000
250
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
1.5
1.5
1.5
1.5
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC9881SBRGER
DAC9881SBRGET
DAC9881SRGER
DAC9881SRGET
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
24
24
24
24
3000
250
340.5
340.5
340.5
340.5
333.0
333.0
333.0
333.0
20.6
20.6
20.6
20.6
3000
250
Pack Materials-Page 2
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