DCR010505U/1K

更新时间:2024-10-30 05:39:32
品牌:TI
描述:微型 1W 隔离稳压直流/直流转换器 | DVB | 12 | -40 to 85

DCR010505U/1K 概述

微型 1W 隔离稳压直流/直流转换器 | DVB | 12 | -40 to 85 DC/DC转换器 电源模块

DCR010505U/1K 规格参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:MODULE
包装说明:SOP, SOP28,.4针数:28
Reach Compliance Code:compliantECCN代码:EAR99
Factory Lead Time:12 weeks风险等级:0.68
模拟集成电路 - 其他类型:DC-DC REGULATED POWER SUPPLY MODULE控制模式:VOLTAGE
最大输入电压:5.5 V最小输入电压:4.5 V
标称输入电压:5 VJESD-30 代码:R-PDSO-G12
JESD-609代码:e4长度:17.9 mm
最大负载调整率:2.5%湿度敏感等级:3
功能数量:1输出次数:1
端子数量:12最高工作温度:85 °C
最低工作温度:-40 °C最大输出电流:0.2 A
最大输出电压:5.1 V最小输出电压:4.9 V
标称输出电压:5 V封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260保护:THERMAL
认证状态:Not Qualified纹波电压(主输出):0.003 Vrms
座面最大高度:2.3 mm子类别:Other Analog ICs
表面贴装:YES技术:HYBRID
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大总功率输出:1 W微调/可调输出:NO
宽度:7.5 mmBase Number Matches:1

DCR010505U/1K 数据手册

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DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403  
ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
DCR01 1W1000VRMS 隔离式稳压直流/直流转换器模块  
1 特性  
3 说明  
1kV 隔离运行):1 秒测试  
• 在隔离层中施加连续电压60VDC42.5VAC  
UL1950 认证组件  
10 PDIP 12 SOP 封装  
• 输入电压5V12V 24V  
• 输出电压3.3V 5V  
• 器件间同步  
400kHz 开关频率  
• 短路保护  
• 过热保护  
• 高效率  
DCR01 系列是高效的输入隔离式、输出稳压直流/直流  
转换器系列。除了电隔离式 1W 标称输出功率能力,  
这一系列的直流/直流转换器还提供超低的输出噪声、  
热保护和高精度等特性。  
DCR01 系列器件集此类特性和较小的尺寸于一体适  
用于各种应用并且对需要信号路径隔离的应用来说,  
它是一个易于使用的解决方案。  
CAUTION  
该产品具有运行隔离功能仅可用于信号  
隔离。不可用于需要增强型隔离的安全隔  
离电路。请参阅特性说明中的定义。  
55°C 125FIT  
2 应用  
器件信息  
使用点功率转换  
数字接口功率  
消除接地环路  
电源降噪  
封装(1)  
封装尺寸标称值)  
22.86mm × 6.61mm  
17.90mm × 7.50mm  
器件型号  
PDIP (10)  
SOP (12)  
DCR01  
(1) 如需了解所有可用封装请参阅数据表末尾的可订购产品附  
录。  
+VS  
VREC  
+VOUT  
SYNC  
Input  
Controller  
LDO  
ERROR  
Regulator  
ENABLE  
-VS  
-VOUT  
DCR01 方框图  
本文档旨在为方便起见提供有TI 产品中文版本的信息以确认产品的概要。有关适用的官方英文版本的最新信息请访问  
www.ti.com其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前请务必参考最新版本的英文版本。  
English Data Sheet: SBVS013  
 
 
 
 
 
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403  
ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
www.ti.com.cn  
Table of Contents  
8.4 Device Functional Modes..........................................15  
9 Application and Implementation..................................16  
9.1 Application Information............................................. 16  
9.2 Typical Application.................................................... 18  
10 Power Supply Recommendations..............................19  
11 Layout...........................................................................20  
11.1 Layout Guidelines................................................... 20  
11.2 Layout Examples.....................................................20  
12 Device and Documentation Support..........................22  
12.1 接收文档更新通知................................................... 22  
12.2 支持资源..................................................................22  
12.3 Trademarks.............................................................22  
12.4 Electrostatic Discharge Caution..............................22  
12.5 术语表..................................................................... 22  
13 Mechanical, Packaging, and Orderable  
1 特性................................................................................... 1  
2 应用................................................................................... 1  
3 说明................................................................................... 1  
4 Revision History.............................................................. 2  
5 Device Comparison Table...............................................3  
6 Pin Configuration and Functions...................................4  
7 Specifications.................................................................. 5  
7.1 Absolute Maximum Ratings........................................ 5  
7.2 ESD Ratings............................................................... 5  
7.3 Recommended Operating Conditions.........................5  
7.4 Thermal Information....................................................5  
7.5 Electrical Characteristics.............................................6  
7.6 Typical Characteristics................................................7  
8 Detailed Description......................................................12  
8.1 Overview...................................................................12  
8.2 Functional Block Diagram.........................................12  
8.3 Feature Description...................................................12  
Information.................................................................... 22  
4 Revision History  
Changes from Revision D (June 2016) to Revision E (July 2022)  
Page  
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1  
• 向2 添加了链接...............................................................................................................................................1  
Added Efficiency and Load Regulation plots for DCR011203P to 7.6 ...........................................................7  
Changes from Revision C (May 2003) to Revision D (January 2016)  
Page  
• 添加了器件信表、器件比表、ESD 表、热性能信表、特性说部分、器件功能模式应用和实  
部分、电源相关建部分、部分、器件和文档支部分、以及机械、封装和可订购信部分............ 1  
• 删除了封装/订购信请参阅数据表末尾POA......................................................................................... 1  
Added additional graphs to 7.6 ..................................................................................................................... 7  
Added Isolation section to the Feature Description section .............................................................................12  
Added a typical application design to the Application Information section ...................................................... 16  
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ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
5 Device Comparison Table  
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic  
(unless otherwise noted)  
Supply Current (mA)  
Input  
Voltage  
VS (V)  
Output  
Voltage  
VO (V)  
Output  
Current  
(mA)  
Ripple (1)  
(mVp-p)  
Noise (2)  
(mVp-p)  
IO = 100%  
LOAD  
Device Number (3)  
IO = 0 mA  
IO = 10 mA  
Typical  
Typical  
Maximum  
Typical  
Typical  
35  
Typical  
18  
Typical  
28  
Typical  
335  
339  
306  
306  
173  
136  
125  
123  
97  
DCR010503P  
DCR010503U  
DCR010505P  
DCR010505U  
DCR011203P  
DCR011203U  
DCR011205P  
DCR011205U  
DCR012403P  
DCR012403U  
DCR012405P  
DCR012405U  
5
8
3.3  
300  
23  
24  
33  
5
6
20  
25  
40  
5
3.3  
5
200  
9
20  
25  
40  
390  
300  
10  
8
54  
13  
17  
22  
13  
17  
12  
24  
6
45  
13  
18  
200  
6
21  
14  
19  
390  
300  
10  
8
22  
17  
18  
3.3  
5
22  
15  
17  
75  
10  
13  
22  
15  
18  
69  
200  
32  
15  
18  
67  
(1) 20-MHz bandwidth, 50% load  
(2) 100-MHz bandwidth, 50% load  
(3) The last character in the part number denotes the package type (P = PDIP, U = SOP).  
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DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403  
ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
www.ti.com.cn  
6 Pin Configuration and Functions  
1
2
18  
17  
1
2
3
28  
27  
26  
+VS  
NC  
SYNC  
-VS  
+VS  
+VS  
NC  
SYNC  
-VS  
-VS  
DCR01P  
DCR01U  
7
8
9
12  
11  
10  
12  
13  
14  
17  
16  
15  
VREC  
-VOUT  
+VOUT  
ERROR  
ENABLE  
DNC  
VREC  
-VOUT  
+VOUT  
ERROR  
ENABLE  
DNC  
6-1. 10-Pin PDIP NVE Package (Top View)  
6-2. 12-Pin SOP DVB Package (Top View)  
6-1. Pin Functions  
Pin  
PDIP  
I/O  
Description  
Name  
ENABLE  
ERROR  
DNC  
SOP  
16  
11  
12  
10  
2
I
Output voltage enable  
17  
O
Error flag active low  
Do not connect.  
No connection  
Synchronization input  
Output ground  
Voltage output  
Rectified output  
Input ground  
15  
I
NC  
3
SYNC  
VOUT  
+VOUT  
VREC  
18  
8
28  
13  
O
O
O
I
9
14  
7
12  
17  
1
26, 27  
1, 2  
VS  
+VS  
I
Voltage input  
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ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1) (2)  
MIN  
MAX  
7
UNIT  
5-V input devices  
Input voltage  
12-V input devices  
24-V input devices  
15  
V
29  
Surface temperature of device body or pins  
(maximum 10 s)  
Lead temperature  
PDIP package  
SOP package  
270  
°C  
Reflow solder temperature  
Storage temperature, Tstg  
Surface temperature of device body or pins  
260  
125  
°C  
°C  
60  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under  
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device  
reliability.  
(2) See the package option addendum at the end of the datasheet for additional package information.  
7.2 ESD Ratings  
VALUE  
±1000  
±250  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
4.5  
NOM  
5
MAX  
5.5  
UNIT  
V
5-V input devices  
12-V input devices  
24-V input devices  
Input voltage  
10.8  
21.6  
40  
12  
13.2  
26.4  
85  
24  
Operating temperature  
°C  
7.4 Thermal Information  
DCR01  
DVB (SOP)  
THERMAL METRIC(1)  
NVE (PDIP)  
UNIT  
10 PINS  
12 PINS  
RθJA  
RθJC(top)  
RθJB  
ψJT  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
60  
26  
24  
7
60  
26  
24  
7
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
24  
24  
ψJB  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
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DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403  
ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
www.ti.com.cn  
7.5 Electrical Characteristics  
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OUTPUT  
DCR01xx03  
DCR01xx05  
3.3  
5
Nominal output voltage (+VOUT  
)
V
Setpoint accuracy  
Output short-circuit protected  
Line regulation  
0.5%  
Infinite  
1
2%  
Duration  
mV/V  
Over line and load  
Temperature variation  
INPUT  
IO = 10 mA to full load, over +VS range  
1%  
2.5%  
1%  
40°C TA +85°C  
DCR0105xx  
DCR0112xx  
DCR0124xx  
5
12  
24  
Nominal input voltage (+VS)  
V
Voltage range  
10%  
10%  
Reflected ripple current  
ISOLATION  
20-MHz bandwidth, IO = 100% Load  
Voltage  
8
mAp-p  
1
kVrms  
V/s  
1-s flash test  
dV/dt  
500  
30  
Leakage current  
DC  
nA  
Isolation  
Continuous working  
voltage across isolation  
barrier  
60  
VDC  
AC  
42.5  
VAC  
pF  
Barrier capacitance  
25  
OUTPUT ENABLE CONTROL  
Logic high input voltage  
Logic high input current  
Logic low input voltage  
Logic low input current  
2
VREC  
0.5  
V
nA  
V
2 < VENABLE < VREC  
100  
0.2  
0 < VENABLE < 0.5  
All 3.3-V outputs  
All 5-V outputs  
100  
3.3  
5
nA  
Rectified output, VREC  
V
ERROR FLAG  
Logic high open-collector leakage  
Logic low output voltage  
THERMAL SHUTDOWN  
VERROR = 5 V  
Sinking 2 mA  
10  
µA  
V
0.4  
Temperature activated  
150  
130  
Junction temperature  
°C  
Temperature deactivated  
SYNCHRONIZATION PIN  
Max external capacitance on SYNC pin  
Internal oscillator frequency  
External synchronization frequency  
External synchronization signal high  
External synchronization signal low  
TEMPERATURE RANGE  
3
880  
880  
3
pF  
kHz  
kHz  
V
720  
720  
2.5  
0
800  
0.4  
V
Operating  
85  
°C  
40  
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ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
7.6 Typical Characteristics  
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2 µF, CFILTER = 1 µF, COUT = 0.1 µF (unless otherwise noted)  
70  
60  
50  
40  
30  
20  
10  
0
70  
60  
50  
40  
30  
20  
10  
0
Ambient Temp  
85°C  
25°C  
Ambient Temp  
85°C  
25°C  
-40°C  
-40°C  
0
0
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
0
0
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
D001  
D002  
DCR010503  
DCR010505  
7-1. Efficiency vs Load  
7-2. Efficiency vs Load  
70  
60  
50  
40  
30  
20  
10  
0
70  
60  
50  
40  
30  
20  
10  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
D003  
D004  
DCR011203P  
DCR011205P  
7-3. Efficiency vs Load  
7-4. Efficiency vs Load  
70  
60  
50  
40  
30  
20  
10  
0
70  
60  
50  
40  
30  
20  
10  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
D005  
D006  
DCR012403P  
DCR012405P  
7-5. Efficiency vs Load  
7-6. Efficiency vs Load  
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ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
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5.016  
5.013  
5.01  
5.06  
5.04  
5.02  
5
Device Number  
DCR012405  
DCR011205  
DCR010505  
Ambient Temp  
85°C  
25°C  
-40°C  
5.007  
5.004  
5.001  
4.998  
4.995  
4.992  
4.989  
4.986  
4.983  
4.98  
4.96  
4.94  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
D010  
D008  
All 5-V Output Devices  
DCR010505P  
7-7. 5-V Output Load Regulation  
7-8. Load Regulation  
3.305  
3.3025  
3.3  
3.32  
Device Number  
DCR010503  
DCR012403  
DCR011203  
Ambient Temp  
85°C  
25°C  
3.315  
3.31  
-40°C  
3.2975  
3.295  
3.2925  
3.29  
3.305  
3.3  
3.295  
3.29  
3.2875  
3.285  
3.2825  
3.28  
3.285  
3.28  
3.275  
3.27  
3.2775  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
D009  
D007  
All 3.3-V Output Devices  
DCR010503P  
7-9. 3.3-V Output Load Regulation  
7-10. Load Regulation  
18  
16  
14  
12  
10  
8
30.0  
25.0  
20.0  
15.0  
10.0  
5.0  
6
4
2
0
0
0
20  
40  
Load (%)  
60  
80  
100  
0
20  
40  
Load (%)  
60  
80  
100  
DCR011203P  
DCR012403P  
20-MHz Bandwidth  
All devices except for  
DCR011203P and  
DCR012403P  
20-MHz Bandwidth  
7-12. Output Voltage Ripple  
7-11. Output Voltage Ripple  
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ZHCSQT7E OCTOBER 2001 REVISED JULY 2022  
80  
70  
60  
50  
40  
30  
20  
10  
120.0  
100.0  
80.0  
60.0  
40.0  
20.0  
0
0
0
0
20  
40  
Load (%)  
60  
80  
100  
20  
40  
Load (%)  
60  
80  
100  
DCR011203P  
100-MHz Bandwidth  
All 5-V Input Devices  
100-MHz Bandwidth  
7-14. Output Voltage Noise  
7-13. Output Voltage Noise  
60.0  
50.0  
40.0  
30.0  
20.0  
10.0  
0
500ns/div  
0%  
20%  
40%  
60%  
80%  
100%  
20-MHz Bandwidth  
Load%  
DCR011205P  
100-MHz Bandwidth  
7-16. Input Current Reflected Ripple  
7-15. Output Voltage Noise  
500ns/div  
200ns/div  
100-MHz Bandwidth  
20-MHz Bandwidth  
7-17. Input Current Reflected Ripple  
7-18. DCR010505P Output Voltage Ripple at  
100% Load  
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200ns/div  
200ns/div  
100-MHz Bandwidth  
20-MHz Bandwidth  
7-19. DCR010505P Output Voltage Noise at  
7-20. DCR010503P Output Voltage Ripple at  
100% Load  
100% Load  
Load Current  
Output Voltage  
200ns/div  
10µs/div  
100-MHz Bandwidth  
7-22. DCR010503P Load Transient Response  
7-21. DCR010503P Output Voltage Noise at  
100% Load  
Load Current  
Load Current  
Output Voltage  
Output Voltage  
10µs/div  
10µs/div  
7-23. DCR010503P Load Transient Response  
7-24. DCR010505P Load Transient Response  
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Load Current  
Output Voltage  
10µs/div  
7-25. DCR010505P Load Transient Response  
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8 Detailed Description  
8.1 Overview  
The DCR01 series of power modules offer isolation from a regulated power supply operating from a choice of  
input voltages. The DCR01s provide a regulated 3.3-V or 5-V output voltage at a nominal output power of 1 W or  
above. The DCR01 devices include a low dropout linear regulator internal to the device to achieve a well-  
regulated output voltage. The DCR01 devices are specified for operational isolation only. The circuit design uses  
an advanced BiCMOS and DMOS process.  
8.2 Functional Block Diagram  
SYNC  
+VS  
VREC  
+VOUT  
Oscillator  
800 kHz  
Divide-by-2  
Reset  
LDO  
Regulator  
Power  
Stage  
ERROR  
ENABLE  
Watchdog  
Startup  
PSU Thermal  
Shutdown  
Input  
Controller  
-VS  
-VOUT  
8.3 Feature Description  
8.3.1 Isolation  
Underwriters Laboratories, ULdefines several classes of isolation that are used in modern power supplies.  
Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit, which is so  
designated and protected so that under normal and single fault conditions, the voltage between any two  
accessible parts or between an accessible part and the equipment earthing terminal for operational isolation  
does not exceed steady state 42.5-VRMS or 60-VDC peak for more than one second.  
8.3.1.1 Operation or Functional Isolation  
The type of isolation used in the DCR01 products is referred to as operational or functional isolation. Insulated  
wire used in the construction of the transformer acts as the primary isolation barrier. A high-potential (hipot), one-  
second duration test (dielectric voltage, withstand test) is a production test used to verify that the isolation barrier  
is functioning. Products with operational isolation must never be used as an element in a safety-isolation system.  
8.3.1.2 Basic or Enhanced Isolation  
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and  
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the  
insulated wire in the construction of the transformer. Input and output circuits must also be physically separated  
by specified distances.  
备注  
The DCR01 products do not provide basic or enhanced isolation.  
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8.3.1.3 Working Voltage  
For a device with operational isolation, the continuous working voltage that can be applied across the device in  
normal operation must be less than 42.5 VRMS or 60 VDC  
.
WARNING  
Do not use the device as an element of a safety isolation system that exceeds the SELV limit.  
If the device is expected to function correctly with more than 42.5 VRMS or 60 VDC applied continuously across  
the isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe  
voltage, and further isolation or insulation systems must form a barrier between these circuits and any user-  
accessible circuitry according to safety standard requirements.  
8.3.1.4 Isolation Voltage Rating  
The terms Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation  
test voltage are all terms that relate to the same thing; a test voltage applied for a specified time across a  
component designed to provide electrical isolation to verify the integrity of that isolation. TIs DCR01 series of  
DC/DC converters are all 100% production tested at 1.0 kVAC for one second.  
8.3.1.5 Repeated High-Voltage Isolation Testing  
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending  
on materials, construction, and environment. The DCR01 series of DC/DC converters have toroidal, enameled,  
wire isolation transformers with no additional insulation between the primary and secondary windings. While a  
device can be expected to withstand several times the stated test voltage, the isolation capability depends on  
the wire insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual  
chemical degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-  
voltage tests and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage  
by 20% from specified test voltage with a duration limit of one second per test.  
8.3.2 Power Stage  
The DCR01 series of devices use a push-pull, center-tapped topology. The DCR01 devices switch at 400 kHz  
(divide-by-2 from an 800-kHz oscillator).  
8.3.3 Rectification  
The output of the transformer is full wave rectified and filtered by the external 1-μF ceramic capacitor connected  
to VREC  
.
8.3.4 Regulator  
The internal low dropout linear regulator provides a well-regulated output voltage throughout the operating range  
of the device.  
8.3.5 Oscillator and Watchdog  
The onboard, 800-kHz oscillator generates the switching frequency through a divide-by-2 circuit. The oscillator  
can be synchronized to other DCR01 device circuits or an external source, and is used to minimize system  
noise.  
A watchdog circuit monitors the operation of the oscillator circuit. The oscillator can be disabled by pulling the  
SYNC pin low. When the SYNC pin goes low, the output pins transition into tri-state mode, which occurs within  
2 μs.  
8.3.6 ERROR Flag  
The DCR01 has an ERROR pin, which provides a power good flag, as long as the internal regulator is in  
regulation. If the ERROR output is required, place a 10-kΩ resistor between the ERROR pin and the output  
voltage.  
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8.3.7 Synchronization  
When more than one DC/DC converter is switching in an application, beat frequencies and other electrical  
interference can be generated. This interference occurs because of the small variations in switching frequencies  
between the DC/DC converters.  
The DCR01 series of devices overcome this interference by allowing devices to be synchronized to one another.  
Synchronize up to eight devices by connecting the SYNC pins of each device, taking care to minimize the  
capacitance of tracking. Stray capacitance (greater than 3 pF) reduces the switching frequency, or can  
sometimes stop the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3 V.  
For an application that uses more than eight synchronized devices, use an external device to drive the SYNC  
pins. The External Synchronization of the DCP01/02 Series of DC/DC Converters application report describes  
this configuration.  
备注  
During the start-up period, all synchronized devices draw maximum current from the input  
simultaneously. If the input voltage falls below approximately 4 V, the devices may not start up. A  
ceramic capacitor must be connected close to the input pin of each device. Use a 2.2-μF capacitor  
for 5-V input devices, and a 0.47-μF capacitor for the 12-V and 24-V devices.  
8.3.8 Construction  
The basic construction of the DCR01 series of devices is the same as standard integrated circuits. The molded  
package contains no substrate. The DCR01 series of devices are constructed using an IC, low dropout linear  
regulator, rectifier diodes, and a wound magnetic toroid on a leadframe. Because the package contains no  
solder, the devices do not require any special printed-circuit board (PCB) assembly processing. This architecture  
results in an isolated DC/DC converter with inherently high reliability.  
8.3.9 Thermal Considerations  
Due to the high power density of this device, it is advisable to provide ground planes on the input and output  
rails. The output regulator is mounted on a copper leadframe, and a ground plane serves as an efficient  
heatsink.  
8.3.10 Decoupling Ripple Reduction  
Due to the very low forward resistance of the DMOS switching transistors, high current demands are placed  
upon the input supply for a short time. By using a good-quality low Equivalent Series Resistance (ESR) capacitor  
of 2.2 μF (minimum) for the 5-V input devices and a 0.47-μF capacitor for the 12-V and 24-V devices, placed  
close to the IC supply input pins, the effects on the power supply can be minimized.  
The high switching frequency of 400 kHz allows relatively small values of capacitors to be used for filtering the  
rectified output voltage. A good-quality, low-ESR, 1-μF ceramic capacitor placed close to the VREC pin and  
output ground is required and reduces the ripple. The output at VREC is full wave rectified and produces a ripple  
of 800 kHz.  
TI recommends that a 0.1-μF, low-ESR, ceramic capacitor is connected close to the output pin and ground to  
reduce noise on the output. The capacitor values listed are minimum values. If lower ripple is required, the filter  
capacitor must be increased in value to 2.2 μF.  
As with all switching power supplies, the best performance is obtained with low-ESR, ceramic capacitors  
connected close to the device pins. If low-ESR, ceramic capacitors are not used, the ESR generates a voltage  
drop when the capacitor is supplying the load power. Often a larger capacitor is chosen for this purpose, when a  
low-ESR, smaller capacitor performs as well.  
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备注  
TI does not recommend that the DCR01 be fitted using an IC socket, as this degrades performance.  
8.4 Device Functional Modes  
8.4.1 Device Disable and Enable  
Each of the DCR01 series devices can be disabled or enabled by driving the SYNC pin using an open-drain  
CMOS gate. If the SYNC pin is pulled low, the DCR01 becomes disabled. The disable time depends upon the  
external loading. The internal disable function is implemented in 2 μs. Removal of the pulldown causes the  
DCR01 to be enabled.  
Capacitive loading on the SYNC pin must be minimized (3 pF) to prevent a reduction in the oscillator  
frequency. The External Synchronization of the DCP01/02 Series of DC/DC Converters application report  
describes disable and enable control circuitry. This document contains information on how to null the effects of  
additional capacitance on the SYNC pin. The frequency of the oscillator can be measured at VREC, since this is  
the fundamental frequency of the ripple component.  
8.4.2 Regulated Output Disable and Enable  
The regulated output of the DCR01 can be disabled by pulling the ENABLE pin LOW. Disabling the output  
voltage this way still produces a voltage on the VREC pin. When using the ENABLE control, TI recommends  
placing a 10-kΩ resistor between the VREC and ENABLE pins. The ENABLE pin only controls the internal linear  
regulator.  
If disabling the regulated output is not required, pull the ENABLE pin HIGH by shorting it directly to the VREC pin,  
which enables the regulated output voltage, thus allowing the output to be controlled from the isolated side.  
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9 Application and Implementation  
备注  
以下应用部分中的信息不属TI 器件规格的范围TI 不担保其准确性和完整性。TI 的客 户应负责确定  
器件是否适用于其应用。客户应验证并测试其设计以确保系统功能。  
9.1 Application Information  
9.1.1 DCR01 Single Voltage Output  
The DCR01 can be used to provide a single voltage output by connecting it as shown in 9-1. The ERROR  
output signal is pulled up to the value of VOUT. The value of RERR depends on the loading on the ERROR line,  
however, the total load on the ERROR line must not exceed the value given in the Electrical Charcteristics.  
The output can be permanently enabled by connecting the ENABLE pin to the VREC pin. The DCR01 can be  
enabled remotely by connecting the ENABLE pin to VREC through a pullup resistor (REN); the value of this  
resistor is not critical for the DCR01 as only a small current flows. The switch SW1 can be used to pull the  
ENABLE pin LOW, thus disabling the output. The switching devices can be a bipolar transistor, FET, or a  
mechanical device; the main load that it sees is REN  
.
SYNC  
+VOUT  
+VOUT  
RERR  
10 k  
VIN  
+VS  
ERROR  
VREC  
ERROR  
COUT  
0.1 µF  
(1)  
CIN  
REN  
10kꢀ  
SW1  
DCR01  
ENABLE  
CFILTER  
1 µF  
œVS  
œVOUT  
œVOUT  
A. CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low-ESR, ceramic capacitors are required.  
9-1. DCR01 Single Output Voltage  
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9.1.2 Generating Two Positive Output Voltages  
Two DCR01s can be used to create output voltages of +3.3 V and +5 V, as shown in 9-2. The two DCR01s  
are connected in self-synchronization, thus locking the oscillators of both devices to a single frequency. The  
ERROR and ENABLE facilities can be used in a similar configuration for a single DCR01. The filter capacitors  
connected to the VREC pins (CFILTER) must be kept separate from each other and connected in close proximity to  
their respective DCR01.  
+VOUT  
VIN  
+VS  
+VOUT1  
RERR  
10 k  
ERROR  
VREC  
ERROR1  
(1)  
CIN  
COUT  
0.1 µF  
DCR01  
ENABLE  
CFILTER  
1 µF  
œVS  
SYNC  
œVOUT  
-VOUT  
+VOUT  
SYNC  
+VS  
+VOUT2  
RERR  
10 kꢀ  
VIN  
ERROR  
VREC  
ERROR2  
COUT  
0.1 µF  
(1)  
DCR01  
CIN  
ENABLE  
CFILTER  
1 µF  
œVS  
œVOUT  
A. CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low-ESR, ceramic capacitors are required.  
9-2. Two Positive Voltages from Self-Synchronized DCR01s  
9.1.3 Generation of Dual Polarity Voltages from Two Self-Synchronized DCR01s  
Two DCR01s can be configured to produce a dual polarity supply (that is, ±5 V); the circuit must be connected  
as shown in 9-3.  
Observe that both devices are producing a positive regulated output; therefore the ERROR, ENABLE, and  
VREC are all relative to the VOUT pin of that particular device and must not be directly connected together, or  
in the case of the negative output device, connected to the common 0-V output.  
+VOUT  
VIN  
+VS  
VPOS O/P  
ERROR  
VREC  
(1)  
CIN  
COUT  
0.1 µF  
DCR01  
ENABLE  
CFILTER  
1 µF  
œVS  
SYNC  
œVOUT  
0V  
+VOUT  
SYNC  
+VS  
VIN  
ERROR  
VREC  
COUT  
0.1 µF  
(1)  
DCR01  
CIN  
ENABLE  
CFILTER  
1 µF  
VNEG O/P  
œVS  
œVOUT  
A. CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low-ESR, ceramic capacitors are required.  
9-3. Dual Polarity Voltage Generation  
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9.2 Typical Application  
+VOUT = 5V  
DCR010505  
SYNC  
+VS  
+VOUT  
RERR  
10 k  
VIN = 5V  
ERROR  
COUT  
0.1 µF  
CIN  
2.2 µF  
VREC  
ENABLE  
CFILTER  
1.0 µF  
œVS  
œVOUT  
œVOUT  
Copyright © 2016, Texas Instruments Incorporated  
9-4. DCR01 Typical Schematic  
9.2.1 Design Requirements  
For this design example, use the parameters listed in 9-1 and follow the design procedure.  
9-1. Design Example Parameters  
Design Parameter  
Input voltage, VIN  
Output voltage, VOUT  
Output current rating  
Isolation  
Value  
5 V typical  
5 V regulated  
200 mA  
1000-V operational  
9.2.2 Detailed Design Procedure  
9.2.2.1 Input Capacitor  
For this design, a 2.2-μF ceramic capacitor is required for the input decoupling capacitor.  
9.2.2.2 Output Capacitor  
For this design, a 0.1-μF ceramic capacitor is required for between +VOUT and VOUT  
.
9.2.2.3 Filter Capacitor  
A high-quality, low-ESR, 1-μF ceramic capacitor placed close to the VREC pin and output ground is required to  
reduce output voltage ripple.  
9.2.2.4 ERROR Flag  
Place a 10-kΩresistor between the ERROR pin and the output voltage to provide a power good signal when the  
internal regulator is in regulation.  
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9.2.3 Application Curves  
70  
60  
50  
40  
30  
20  
10  
0
5.06  
Ambient Temp  
85°C  
25°C  
5.04  
-40°C  
5.02  
5
4.98  
Ambient Temp  
4.96  
4.94  
85°C  
25°C  
-40°C  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
0
10  
20  
30  
40  
50  
Load (%)  
60  
70  
80  
90 100  
D008  
D002  
9-6. DCR010505 Load Regulation  
9-5. DCR010505 Efficiency  
10 Power Supply Recommendations  
The DCR01 is a switching power supply, and as such, can place high peak current demands on the input supply.  
To avoid the supply falling momentarily during the fast switching pulses, ground and power planes must be used  
to connect the power to the input of DCR01. If this connection is not possible, then the supplies must be  
connected in a star formation with the traces made as wide as possible.  
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11 Layout  
11.1 Layout Guidelines  
Carefully consider the layout of the PCB for the best results to be obtained.  
Input and output power and ground planes provide a low-impedance path for the input and output power. For the  
output, the positive and negative voltage outputs conduct through wide traces to minimize losses.  
A good-quality, low-ESR, ceramic capacitor placed as close as practical across the input reduces reflected ripple  
and ensure a smooth start-up.  
A good-quality, low-ESR, ceramic capacitor placed as close as practical across the rectifier output terminal and  
output ground to provide the best ripple and noise performance.  
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the  
effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the  
input decoupling capacitor, because this capacitor supplies the transient current associated with the fast  
switching waveforms of the power drive circuits.  
If the SYNC pin is being used, the tracking between device SYNC pins must be short to avoid stray capacitance.  
Never connect a capacitor to the SYNC pin. If the SYNC pin is not being used it is advisable to place a guard  
ring (connected to input ground) around this pin to avoid any noise pick-up. Ensure that no other trace is in close  
proximity to this trace SYNC trace to decrease the stray capacitance on this pin. The stray capacitance affects  
the performance of the oscillator.  
11-1 shows a schematic for a single DCR01, SOP package device. 11-2 and 11-3 show a typical layout  
for the SOP package DCR01 device. The layout shows proper placement of capacitors and power planes.  
11.2 Layout Examples  
DCR01U  
U1  
1
2
+VS  
+VS  
-VS  
+VS  
C1  
SYNC 28  
26  
27  
œVS  
œVS  
ERROR 17  
ENABLE 16  
VREC  
-VOUT  
+VOUT  
12  
13  
14  
VREC  
C2  
œVOUT  
C3  
+VOUT  
11-1. DCR01 PCB Schematic, U Package  
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U1  
SYNC  
SYNC  
+VS  
-VS  
+VS  
-VS  
C1  
C2  
VREC  
VREC  
ERROR  
ERROR  
ENABLE  
ENABLE  
-VOUT  
-VOUT  
+VOUT  
+VOUT  
C3  
11-2. PCB Layout Example, Component-Side  
11-3. PCB Layout Example, Non-Component-  
View  
Side View  
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12 Device and Documentation Support  
12.1 接收文档更新通知  
要接收文档更新通知请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册即可每周接收产品信息更  
改摘要。有关更改的详细信息请查看任何已修订文档中包含的修订历史记录。  
12.2 支持资源  
TI E2E支持论坛是工程师的重要参考资料可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范并且不一定反映 TI 的观点请参阅  
TI 《使用条款》。  
12.3 Trademarks  
Underwriters Laboratories, ULis a trademark of UL LLC.  
TI E2Eis a trademark of Texas Instruments.  
所有商标均为其各自所有者的财产。  
12.4 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
12.5 术语表  
TI 术语表  
本术语表列出并解释了术语、首字母缩略词和定义。  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
Copyright © 2022 Texas Instruments Incorporated  
22  
Submit Document Feedback  
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403  
 
 
 
 
 
 
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
19-Jul-2022  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
NVE  
DVB  
DVB  
DVB  
NVE  
DVB  
DVB  
DVB  
DVB  
NVE  
DVB  
DVB  
DVB  
NVE  
DVB  
DVB  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
DCR010503P  
DCR010503U  
ACTIVE  
PDIP  
SOP  
SOP  
SOP  
PDIP  
SOP  
SOP  
SOP  
SOP  
PDIP  
SOP  
SOP  
SOP  
PDIP  
SOP  
SOP  
10  
12  
12  
12  
10  
12  
12  
12  
12  
10  
12  
12  
12  
10  
12  
12  
20  
RoHS &  
Non-Green  
NIPDAU  
N / A for Pkg Type  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
N / A for Pkg Type  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
DCR010503P  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
28  
RoHS &  
Non-Green  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
DCR010503U  
DCR010503U  
DCR010503U  
DCR010505P  
DCR010505U  
DCR010505U  
DCR010505U  
DCR010505U  
DCR011203P  
DCR011203U  
DCR011203U  
DCR011203U  
DCR011205P  
DCR011205U  
DCR011205U  
DCR010503U/1K  
DCR010503UE4  
DCR010505P  
1000  
28  
RoHS &  
Non-Green  
RoHS &  
Non-Green  
20  
RoHS &  
Non-Green  
DCR010505U  
28  
RoHS &  
Non-Green  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
N / A for Pkg Type  
DCR010505U/1K  
DCR010505U/1KE4  
DCR010505UE4  
DCR011203P  
1000  
1000  
28  
RoHS &  
Non-Green  
RoHS &  
Non-Green  
RoHS &  
Non-Green  
20  
RoHS &  
Non-Green  
DCR011203U  
28  
RoHS &  
Non-Green  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
N / A for Pkg Type  
DCR011203U/1K  
DCR011203UE4  
DCR011205P  
1000  
28  
RoHS &  
Non-Green  
RoHS &  
Non-Green  
20  
RoHS &  
Non-Green  
DCR011205U  
28  
RoHS &  
Non-Green  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
DCR011205U/1K  
1000  
RoHS &  
Non-Green  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
19-Jul-2022  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
DCR011205UE4  
DCR012403P  
ACTIVE  
SOP  
PDIP  
SOP  
PDIP  
SOP  
SOP  
SOP  
DVB  
12  
10  
12  
10  
12  
12  
12  
28  
RoHS &  
Non-Green  
NIPDAU  
Level-3-260C-168 HR  
N / A for Pkg Type  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
DCR011205U  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
NVE  
20  
RoHS &  
Non-Green  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
DCR012403P  
DCR012403U  
DCR012405P  
DCR012405U  
DCR012405U  
DCR012405U  
DCR012403U  
DCR012405P  
DVB  
28  
RoHS &  
Non-Green  
Level-3-260C-168 HR  
N / A for Pkg Type  
NVE  
20  
RoHS &  
Non-Green  
DCR012405U  
DCR012405U/1K  
DCR012405UE4  
DVB  
28  
RoHS &  
Non-Green  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
DVB  
1000  
28  
RoHS &  
Non-Green  
DVB  
RoHS &  
Non-Green  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
19-Jul-2022  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TUBE  
T - Tube  
height  
L - Tube length  
W - Tube  
width  
B - Alignment groove width  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
DCR010503P  
DCR010503U  
DCR010503UE4  
DCR010505P  
DCR010505U  
DCR010505UE4  
DCR011203P  
DCR011203U  
DCR011203UE4  
DCR011205P  
DCR011205U  
DCR011205UE4  
DCR012403P  
DCR012403U  
DCR012405P  
DCR012405U  
DCR012405UE4  
NVE  
DVB  
DVB  
NVE  
DVB  
DVB  
NVE  
DVB  
DVB  
NVE  
DVB  
DVB  
NVE  
DVB  
NVE  
DVB  
DVB  
PDIP  
SOP  
SOP  
PDIP  
SOP  
SOP  
PDIP  
SOP  
SOP  
PDIP  
SOP  
SOP  
PDIP  
SOP  
PDIP  
SOP  
SOP  
10  
12  
12  
10  
12  
12  
10  
12  
12  
10  
12  
12  
10  
12  
10  
12  
12  
20  
28  
28  
20  
28  
28  
20  
28  
28  
20  
28  
28  
20  
28  
20  
28  
28  
533.4  
532.13  
532.13  
533.4  
14.33  
14.73  
14.73  
14.33  
14.73  
14.73  
14.33  
14.73  
14.73  
14.33  
14.73  
14.73  
14.33  
14.73  
14.33  
14.73  
14.73  
13.03  
5.13  
8.07  
6.6  
5.13  
6.6  
13.03  
5.13  
8.07  
6.6  
532.13  
532.13  
533.4  
5.13  
6.6  
13.03  
5.13  
8.07  
6.6  
532.13  
532.13  
533.4  
5.13  
6.6  
13.03  
5.13  
8.07  
6.6  
532.13  
532.13  
533.4  
5.13  
6.6  
13.03  
5.13  
8.07  
6.6  
532.13  
533.4  
13.03  
5.13  
8.07  
6.6  
532.13  
532.13  
5.13  
6.6  
Pack Materials-Page 1  
MECHANICAL DATA  
MPDI055 – APRIL 2001  
NVE (R-PDIP-T10/18)  
PLASTIC DUAL-IN-LINE  
D
0.920 (23,37)  
0.880 (22,35)  
18  
10  
0.280 (7,11)  
0.240 (6,10)  
D
1
Index  
9
Area  
E
0.070 (1,78)  
0.195 (4,95)  
0.115 (2,92)  
0.325 (8,26)  
0.300 (7,62)  
0.045 (1,14)  
Base  
Plane  
0.210 (5,33)  
MAX  
–C–  
Seating  
Plane  
E
0.150 (3,81)  
0.115 (2,92)  
0.300 (7,63)  
0.014 (0,36)  
0.008 (0,20)  
0.005 (0,13)  
MIN 4 PL  
0.100 (2,54)  
D
0.015 (0,38)  
MIN  
Full Lead  
0.022 (0,56)  
0.014 (0,36)  
0.060 (1,52)  
0.000 (0,00)  
0.010 (0,25) M  
C
0.430 (10,92)  
F
MAX  
F
4202497/A 03/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001-AC with the exception  
of lead count.  
D. Dimensions do not include mold flash or protrusions.  
Mold flash or protrusions shall not exceed 0.010 (0,25).  
E. Dimensions measured with the leads constrained to be  
perpendicular to Datum C.  
F. Dimensions are measured at the lead tips with the  
leads unconstrained.  
G. A visual index feature must be located within the  
cross-hatched area.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OUTLINE  
DVB0012A  
SOP - 2.65 mm max height  
S
C
A
L
E
0
.
9
0
0
PLASTIC SMALL OUTLINE  
C
10.65  
10.01  
SEATING PLANE  
PIN 1 ID  
AREA  
A
0.1 C  
8X 1.27  
28  
1
18.1  
17.7  
NOTE 3  
2X 16.51  
14  
15  
0.51  
0.33  
12X  
7.6  
7.4  
B
0.25  
C A  
B
0.32  
0.23  
TYP  
2.65 MAX  
SEE DETAIL A  
0.3  
8
0
1.27  
0.1  
0.40  
DETAIL A  
TYPICAL  
4222497/A 10/2015  
NOTES:  
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. Reference JEDEC registration MS-013.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DVB0012A  
SOP - 2.65 mm max height  
PLASTIC SMALL OUTLINE  
12X (2)  
SYMM  
1
28  
12X (0.6)  
(R0.05)  
TYP  
SYMM  
(16.51)  
8X (1.27)  
14  
15  
(9.3)  
LAND PATTERN EXAMPLE  
SCALE:6X  
METAL UNDER  
METAL  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
SOLDER MASK  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4222497/A 10/2015  
NOTES: (continued)  
5. Publication IPC-7351 may have alternate designs.  
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DVB0012A  
SOP - 2.65 mm max height  
PLASTIC SMALL OUTLINE  
12X (2)  
SYMM  
1
28  
12X (0.6)  
(R0.05)  
SYMM  
(16.51)  
8X (1.27)  
14  
15  
(9.3)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:6X  
4222497/A 10/2015  
NOTES: (continued)  
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
8. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
重要声明和免责声明  
TI“按原样提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,  
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验  
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成  
本、损失和债务,TI 对此概不负责。  
TI 提供的产品受 TI 的销售条款ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改  
TI 针对 TI 产品发布的适用的担保或担保免责声明。  
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE  
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2022,德州仪器 (TI) 公司  

DCR010505U/1K CAD模型

  • 引脚图

  • 封装焊盘图

  • DCR010505U/1K 替代型号

    型号 制造商 描述 替代类型 文档
    DCR010505U/1KE4 TI 微型 1W 隔离稳压直流/直流转换器 | DVB | 12 | -40 to 85 类似代替
    DCR010505U TI 微型 1W 隔离稳压直流/直流转换器 | DVB | 12 | -40 to 85 类似代替

    DCR010505U/1K 相关器件

    型号 制造商 描述 价格 文档
    DCR010505U/1KE4 TI 微型 1W 隔离稳压直流/直流转换器 | DVB | 12 | -40 to 85 获取价格
    DCR010505U1K BB Miniature, 1W Isolated REGULATED DC/DC CONVERTERS 获取价格
    DCR010505UE4 TI 微型 1W 隔离稳压直流/直流转换器 | DVB | 12 | -40 to 85 获取价格
    DCR0112 BB Miniature, 1W Isolated REGULATED DC/DC CONVERTERS 获取价格
    DCR011203 BB Miniature, 1W Isolated REGULATED DC/DC CONVERTERS 获取价格
    DCR011203 TI 微型 1W 隔离稳压直流/直流转换器 获取价格
    DCR011203P BB Miniature, 1W Isolated REGULATED DC/DC CONVERTERS 获取价格
    DCR011203P TI 微型 1W 隔离稳压直流/直流转换器 | NVE | 10 | -40 to 85 获取价格
    DCR011203U BB Miniature, 1W Isolated REGULATED DC/DC CONVERTERS 获取价格
    DCR011203U TI 微型 1W 隔离稳压直流/直流转换器 | DVB | 12 | -40 to 85 获取价格

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