DDC112_14 [TI]
Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER;
| 型号： | DDC112_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总34页 (文件大小：1146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
D
D
C1
DDC112
12
D
®
D
C
11
2
SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004
Dual Current Input 20-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
ꢀ MONOLITHIC CHARGE MEASUREMENT A/D
The DDC112 is a dual input, wide dynamic range, charge-
digitizing analog-to-digital (A/D) converter with 20-bit resolu-
tion. Low-level current output devices, such as photosensors,
can be directly connected to its inputs. Charge integration is
continuous as each input uses two integrators; while one is
being digitized, the other is integrating.
CONVERTER
ꢀ DIGITAL FILTER NOISE REDUCTION:
3.2ppm, rms
ꢀ INTEGRAL LINEARITY:
±0.005% Reading ±0.5ppm FSR
For each of its two inputs, the DDC112 combines current-to-
voltage conversion, continuous integration, programmable
full-scale range, A/D conversion, and digital filtering to achieve
a precision, wide dynamic range digital result. In addition to
the internal programmable full-scale ranges, external integrat-
ing capacitors allow an additional user-settable full-scale
range of up to 1000pC.
ꢀ HIGH PRECISION, TRUE INTEGRATING FUNC-
TION
ꢀ PROGRAMMABLE FULL-SCALE
ꢀ SINGLE SUPPLY
ꢀ CASCADABLE OUTPUT
To provide single-supply operation, the internal A/D converter
APPLICATIONS
ꢀ DIRECT PHOTOSENSOR DIGITIZATION
utilizes a differential input, with the positive input tied to VREF
.
When the integration capacitor is reset at the beginning of
each integration cycle, the capacitor charges to VREF. This
charge is removed in proportion to the input current. At the
end of the integration cycle, the remaining voltage is com-
ꢀ CT SCANNER DAS
ꢀ INFRARED PYROMETER
ꢀ PRECISION PROCESS CONTROL
ꢀ LIQUID/GAS CHROMATOGRAPHY
ꢀ BLOOD ANALYSIS
pared to VREF.
The high-speed serial shift register which holds the result of
the last conversion can be configured to allow multiple DDC112
units to be cascaded, minimizing interconnections. The
DDC112 is available in an SO-28 or TQFP-32 package and is
offered in two performance grades.
Protected by US Patent #5841310
AVDD
AGND
VREF
DVDD DGND
CAP1A
CAP1A
CHANNEL 1
DCLK
IN1
Dual
Switched
Integrator
DVALID
CAP1B
CAP1B
∆Σ
Modulator
DXMIT
DOUT
DIN
Digital
Filter
Digital
Input/Output
CAP2A
CAP2A
CHANNEL 2
RANGE2
RANGE1
RANGE0
IN2
Control
Dual
Switched
Integrator
CAP2B
CAP2B
TEST
CLK
CONV
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000-2004, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
AVDD to DVDD ....................................................................... –0.3V to +6V
AVDD to AGND ..................................................................... –0.3V to +6V
DVDD to DGND ..................................................................... –0.3V to +6V
AGND to DGND ............................................................................... ±0.3V
VREF Voltage to AGND ........................................... –0.3V to AVDD + 0.3V
Digital Input Voltage to DGND .............................. –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND ........................... –0.3V to DVDD + 0.3V
Package Power Dissipation............................................. (TJMAX – TA)/θJA
Maximum Junction Temperature (TJMAX) ...................................... +150°C
Thermal Resistance, SO, θJA .................................................... +150°C/W
Thermal Resistance, TQFP, θJA ................................................ +100°C/W
Lead Temperature (soldering, 10s) ............................................... +300°C
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommendsthat allintegratedcircuitsbehandledwith
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
tocompletedevicefailure. Precisionintegratedcircuitsmaybe
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY ERROR
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
PRODUCT
PACKAGE-LEAD
DDC112U
±0.025% Reading ±1.0ppm FSR
–40°C to +85°C
SO-28
DW
"
DDC112U
DDC112U/1K
DDC112UK
Rails
"
"
"
"
Tape and Reel
Rails
DDC112UK
±0.025% Reading ±1.0ppm FSR
0°C to +70°C
SO-28
DW
"
"
"
"
"
PJT
"
DDC112UK/1K
DDC112Y/250
DDC112Y/2K
DDC112YK/250
DDC112YK/2K
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
DDC112Y
±0.025% Reading ±1.0ppm FSR
–40°C to +85°C
TQFP-32
"
"
"
"
DDC112YK
±0.025% Reading ±1.0ppm FSR
0°C to +70°C
TQFP-32
PJT
"
"
"
"
"
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. (2) Models with a slash
(/) are available only in Tape and Reel in the quantities indicated (/1K indicates 1000 devices per reel). Ordering 1000 pieces of DDC112U/1K will get a single 1000-
piece Tape and Reel.
DDC112
2
SBAS085B
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = +5V, DDC112U, Y: TINT = 500µs, CLK = 10MHz, DDC112UK, YK: TINT = 333.3µs, CLK = 15MHz, VREF = +4.096V, continuous mode
operation, and internal integration capacitors, unless otherwise noted.
DDC112U, Y
TYP
DDC112UK, YK
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
ANALOG INPUTS
External, Positive Full-Scale
Range 0
CEXT = 250pF
1000
ꢀ
pC
Internal, Positive Full-Scale
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Negative Full-Scale Input
47.5
95
142.5
190
237.5
285
332.5
50
52.5
105
157.5
210
262.5
315
367.5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
pC
pC
pC
pC
pC
pC
pC
pC
100
150
200
250
300
350
–0.4% of Positive FS
DYNAMIC CHARACTERISTICS
Conversion Rate
Integration Time, TINT
Integration Time, TINT
System Clock Input (CLK)
Data Clock (DCLK)
2
3
ꢀ
kHz
µs
µs
MHz
MHz
Continuous Mode
Non-Continuous Mode
500
50
1
1,000,000
333.3
ꢀ
ꢀ
10
12
12
ꢀ
15
15
ACCURACY
Noise, Low-Level Current Input(1) CSENSOR = 0pF, Range 5 (250pC)
CSENSOR = 25pF, Range 5 (250pC)
3.2
3.8
4.2
ꢀ
ꢀ
ꢀ
ppm of FSR(3), rms
ppm of FSR, rms
ppm of FSR, rms
(2)
CSENSOR = 50pF, Range 5 (250pC)
6.0
7
Differential Linearity Error
±0.005% Reading ±0.5ppm
FSR (max)
±0.005% Reading ±0.5ppm
FSR (typ)
ꢀ
Integral Linearity Error(4)
ꢀ
±0.025% Reading ±1.0ppm
FSR (max)
ꢀ
No Missing Codes
Input Bias Current
Range Error
Range Error Match(5)
Range Sensitivity to VREF
Offset Error
Offset Error Match(5)
DC Bias Voltage(6) (Input VOS
Power-Supply Rejection Ratio
Internal Test Signal
20
0.1
ꢀ
ꢀ
Bits
pA
% of FSR
% of FSR
TA = +25°C
Range 5 (250pC)
All Ranges
VREF = 4.096 ±0.1V
Range 5, (250pC)
10
5
0.5
ꢀ
ꢀ
ꢀ
0.1
1:1
±200
±100
±0.05
±25
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
±600
ppm of FSR
ppm of FSR
)
±2
±200
ꢀ
ꢀ
mV
ppm of FSR/V
13
±10
pC
%
Internal Test Accuracy
PERFORMANCE OVER TEMPERATURE
Offset Drift
Offset Drift Stability
±0.5
±0.2
3
0.01
2
±3(10)
ppm of FSR/°C
ꢀ
±1
ꢀ
ꢀ
25
ꢀ
±0.7(10) ppm of FSR/minute
µV/°C
DC Bias Voltage Drift
Input Bias Current Drift
Input Bias Current
Range Drift(7)
Applied to Sensor Input
+25°C to +45°C
TA = +75°C
1(10)
50(10)
ꢀ
ꢀ
50(10)
pA/°C
pA
ppm/°C
ppm/°C
Range 5 (250pC)
Range 5 (250pC)
25
±0.05
0
Range Drift Match(5)
REFERENCE
Voltage
Input Current(8)
4.000
4.096
150
4.200
ꢀ
ꢀ
225
ꢀ
275
V
µA
TINT = 500µs
DIGITAL INPUT/OUTPUT
Logic Levels
VIH
VIL
VOH
VOL
4.0
–0.3
4.5
DVDD + 0.3
+0.8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
V
µA
IOH = –500µA
IOL = 500µA
0.4
+10
ꢀ
ꢀ
Input Current, IIN
Data Format(9)
–10
ꢀ
Straight Binary
ꢀ
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Supply Current
Analog Current
Digital Current
AVDD and DVDD
4.75
5.25
100
ꢀ
ꢀ
V
AVDD = +5V
DVDD = +5V
14.8
1.2
80
15.2
1.8
85
mA
mA
mW
Total Power Dissipation
130
TEMPERATURE RANGE
Specified Performance
Storage
–40
–60
+85
+100
0
ꢀ
+70
ꢀ
°C
°C
ꢀ Specifications same as DDC112U, Y.
NOTES: (1) Input is less than 1% of full scale. (2) CSENSOR is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range.
(4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which
is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing TINT (see the Voltage Reference
section). (9) Data format is Straight Binary with a small offset (see the Data Retrieval section). (10) Ensured by design but not production tested.
DDC112
SBAS085B
3
www.ti.com
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
LABEL DESCRIPTION
Top View
SO
1
IN1
Input 1: analog input for Integrators 1A and 1B. The
integrator that is active is set by the CONV input.
2
3
4
5
6
7
8
AGND
CAP1B
CAP1B
CAP1A
CAP1A
AVDD
Analog Ground
External Capacitor for Integrator 1B
External Capacitor for Integrator 1B
External Capacitor for Integrator 1A
External Capacitor for Integrator 1A
Analog Supply, +5V Nominal
TEST
Test Control Input. When HIGH, a test charge is applied
to the A or B integrators on the next CONV transition.
IN1
AGND
CAP1B
CAP1B
CAP1A
CAP1A
AVDD
1
2
3
4
5
6
7
8
9
28 IN2
27 AGND
9
CONV
Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH → side A is
integrating, CONV LOW → side B is integrating. CONV
must be synchronized with CLK (see Figure 2).
26 CAP2B
25 CAP2B
24 CAP2A
23 CAP2A
22 VREF
10
11
CLK
System Clock Input, 10MHz Nominal
DCLK
Serial Data Clock Input. This input operates the serial I/
O shift register.
12
DXMIT
Serial Data Transmit Enable Input. When LOW, this
input enables the internal serial shift register.
DDC112U
TEST
21 AGND
13
14
15
16
17
DIN
Serial Digital Input. Used to cascade multiple DDC112s.
Digital Supply, +5V Nominal
DVDD
DGND
DOUT
CONV
20 RANGE2 (MSB)
19 RANGE1
18 RANGE0 (LSB)
17 DVALID
16 DOUT
Digital Ground
CLK 10
DCLK 11
DXMIT 12
DIN 13
Serial Data Output, Hi-Z when DXMIT is HIGH
DVALID Data Valid Output. A LOW value indicates valid data is
available in the serial I/O register.
18
19
20
21
22
23
24
25
26
27
28
RANGE0 Range Control Input 0 (least significant bit)
RANGE1 Range Control Input 1
RANGE2 Range Control Input 2 (most significant bit)
DVDD 14
15 DGND
AGND
VREF
Analog Ground
External Reference Input, +4.096V Nominal
External Capacitor for Integrator 2A
External Capacitor for Integrator 2A
External Capacitor for Integrator 2B
External Capacitor for Integrator 2B
Analog Ground
CAP2A
CAP2A
CAP2B
CAP2B
AGND
IN2
Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.
DDC112
4
SBAS085B
www.ti.com
PIN CONFIGURATION
Top View
TQFP
CAP1A
CAP1A
AVDD
NC
1
2
3
4
5
6
7
8
24 CAP2A
23 CAP2A
22 VREF
21 AGND
20 NC
DDC112Y
NC
TEST
CONV
CLK
19 NC
18 RANGE2 (MSB)
17 RANGE1
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
PIN
LABEL
DESCRIPTION
1
2
3
4
5
6
CAP1A
CAP1A
AVDD
NC
External Capacitor for Integrator 1A
External Capacitor for Integrator 1A
Analog Supply, +5V Nominal
No Connection
15
DVALID Data Valid Output. A LOW value indicates valid data is
available in the serial I/O register.
16
17
18
19
20
21
22
23
24
25
26
27
28
RANGE0 Range Control Input 0 (least significant bit)
RANGE1 Range Control Input 1
RANGE2 Range Control Input 2. (most significant bit)
NC
No Connection
NC
No Connection
TEST
Test Control Input. When HIGH, a test charge is
applied to the A or B integrators on the next CONV
transition.
NC
No Connection
AGND
VREF
Analog Ground
7
CONV
Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH side A is
integrating, CONV LOW side B is integrating CONV
must be synchronized with CLK (see text).
External Reference Input, +4.096V Nominal
External Capacitor for Integrator 2A
External Capacitor for Integrator 2A
External Capacitor for Integrator 2B
External Capacitor for Integrator 2B
Analog Ground
CAP2A
CAP2A
CAP2B
CAP2B
AGND
IN2
8
9
CLK
System Clock Input, 10MHz Nominal
DCLK
Serial Data Clock Input. This input operates the
serial I/O shift register.
10
11
DXMIT
DIN
Serial Data Transmit Enable Input. When LOW, this
input enables the internal serial shift register.
Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.
Serial Digital Input. Used to cascade multiple
DDC112s.
29
IN1
Input 1: analog input for Integrators 1A and 1B. The
integrator that is active is set by the CONV input.
12
13
14
DVDD
DGND
DOUT
Digital Supply, +5V Nominal
Digital Ground
30
31
32
AGND
CAP1B
CAP1B
Analog Ground
External Capacitor for Integrator 1B
External Capacitor for Integrator 1B
Serial Data Output, Hi-Z when DXMIT is HIGH
DDC112
SBAS085B
5
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted.
NOISE vs TINT
NOISE vs CSENSOR
6
5
4
3
2
1
0
70
60
50
40
30
20
10
0
Range 1
CSENSOR = 50pF
CSENSOR = 0pF
Range 2
Range 0
(CEXT = 250pF)
Range 7
Range 5
0.1
1
10
INT (ms)
100
1000
0
200
400
600
800
1000
T
CSENSOR (pF)
NOISE vs TEMPERATURE
NOISE vs INPUT LEVEL
5
4.5
4
9
8
7
6
5
4
3
2
1
0
Range 1
CSENSOR = 50pF
3.5
3
Range 2
Range 3
CSENSOR = 0pF
2.5
2
1.5
1
Range 7
CSENSOR = 0pF
Range 5
0.5
0
10
20
30
40
50
60
70
80
90
10 100
–40
–15
10
35
60
85
Input Level (% of Full-Scale)
Temperature (°C)
RANGE DRIFT vs TEMPERATURE
IB vs TEMPERATURE
2000
1500
1000
500
10
1
Ranges 1 - 7
(Internal Integration Capacitor)
All Ranges
0
0.1
0.01
–500
–1000
–1500
–40
–15
10
35
60
85
25
35
45
55
65
75
85
Temperature (°C)
Temperature (°C)
DDC112
6
SBAS085B
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted.
OFFSET DRIFT vs TEMPERATURE
INPUT VOS vs RANGE
36
35
34
33
32
31
30
100
50
All Ranges
0
–50
–100
25
35
45
55
65
75
85
1
2
3
4
5
6
7
Range
Temperature (°C)
ANALOG SUPPLY CURRENT vs TEMPERATURE
DIGITAL SUPPLY CURRENT vs TEMPERATURE
18
16
14
12
10
8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6
4
2
0
–40
–15
10
35
60
85
–40
–15
10
35
60
85
Temperature (°C)
Temperature (°C)
CROSSTALK vs FREQUENCY
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
600
500
400
300
200
100
0
0
–20
Separation Measured
Between Inputs 1 and 2
–40
–60
–80
–100
–120
–140
0
25
50
75
100
0
100
200
300
400
500
Frequency (KHz)
Frequency (Hz)
DDC112
SBAS085B
7
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The DVALID output goes LOW when the shift register
contains valid data.
THEORY OF OPERATION
The basic operation of the DDC112 is illustrated in Figure 1.
The device contains two identical input channels where each
performs the function of current-to-voltage integration fol-
lowed by a multiplexed analog-to-digital (A/D) conversion.
Each input has two integrators so that the current-to-voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma (∆Σ) converter
via a four input multiplexer. With the DDC112 in the continu-
ous integration mode, the output of the integrators from one
side of both of the inputs will be digitized while the other two
integrators are in the integration mode as illustrated in the
timing diagram in Figure 2. This integration and A/D conver-
sion process is controlled by the system clock, CLK. With a
10MHz system clock, the integrator combined with the delta-
sigma converter accomplishes a single 20-bit conversion in
approximately 220µs. The results from side A and side B of
each signal input are stored in a serial output shift register.
The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (DXMIT), a valid data pin
(DVALID), a serial data output pin (DOUT), and a serial data
input pin (DIN). The DDC112 contains only one A/D con-
verter, so the conversion process is interleaved between the
two inputs, as shown in Figure 2. The integration and
conversion process is fundamentally independent of the data
retrieval process. Consequently, the CLK frequency and
DCLK frequencies need not be the same. DIN is only used
when multiple converters are cascaded and should be tied to
DGND otherwise. Depending on TINT, CLK, and DCLK, it is
possible to daisy-chain over 100 converters. This greatly
simplifies the interconnection and routing of the digital out-
puts in cases where a large number of converters are
needed.
AVDD
AGND
VREF
DVDD
DGND
CAP1A
CAP1A
Input 1
DCLK
IN1
Dual
Switched
Integrator
DVALID
DXMIT
DOUT
DIN
CAP1B
CAP1B
∆Σ
Modulator
Digital
Filter
Digital
Input/Output
CAP2A
CAP2A
Input 2
RANGE2
RANGE1
RANGE0
IN2
Control
Dual
Switched
Integrator
CAP2B
CAP2B
TEST
CLK
CONV
FIGURE 1. Block Diagram.
IN1, Integrator A
Integrate
Integrate
IN1, Integrator B
IN2, Integrator A
Integrate
Integrate
Integrate
Integrate
Integrate
Integrate
IN1A
IN2A
IN2, Integrator B
Conversion in Progress
IN1B
IN2B
IN1A
IN2A
IN1B
IN2B
DVALID
FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).
DDC112
8
SBAS085B
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DEVICE OPERATION
CF
INPUT RANGE
(pC, typ)
RANGE2
RANGE1
RANGE0 (pF, typ)
Basic Integration Cycle
0
0
0
External
Up to 1000
The fundamental topology of the front end of the DDC112 is
a classical analog integrator, as shown in Figure 3. In this
diagram, only Input 1 is shown. This representation of the
input stage consists of an operational amplifier, a selectable
feedback capacitor network (CF), and several switches that
implement the integration cycle. The timing relationships of
all of the switches shown in Figure 3 are illustrated in
Figure 4. Figure 4 is used to conceptualize the operation of
the integrator input stage of the DDC112 and should not be
used as an exact timing tool for design. Block diagrams of
the reset, integrate, converter, and wait states of the inte-
grator section of the DDC112 are shown in Figure 5. This
internal switching network is controlled externally with the
convert command (CONV), range selection pins (RANGE0-
RANGE2), and the system clock (CLK). For the best noise
performance, CONV must be synchronized with the rising
edge of CLK. It is recommended CONV toggle within ±10ns
of the rising edge of CLK.
12.5 to 250
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
12.5
25
–0.2 to 50
–0.4 to 100
–0.6 to 150
–0.8 to 200
–0.1 to 250
–1.2 to 300
–1.4 to 350
37.5
50
62.5
75
87.5
TABLE I. Range Selection of the DDC112.
SRESET (see Figures 4 and 5a). This is done during the reset
time. In this manner, the selected capacitor is charged to the
reference voltage, VREF. Once the integration capacitor is
charged, SREF1, and SRESET are switched so that VREF is no
longer connected to the amplifier circuit while it waits to begin
integrating (see Figure 5b). With the rising edge on CONV,
INTA closes which begins the integration of Channel A. This
puts the integrator stage into its integrate mode (see
Figure 5c).
S
The noninverting inputs of the integrators are internally
referenced to ground. Consequently, the DDC112 analog
ground should be as clean as possible. The range switches,
along with the internal and external capacitors (CF) are
shown in parallel between the inverting input and output of
the operational amplifier. Table I shows the value of the
integration capacitor (CF) for each range. At the beginning of
Charge from the input signal is collected on the integration
capacitor causing the voltage output of the amplifier to
decrease. A falling edge CONV stops the integration by
switching the input signal from side A to side B (SINTA and
S
INTB). Prior to the falling edge of CONV, the signal on side
B was converted by the A/D converter and reset during the
time that side A was integrating. With the falling edge of
CONV, side B starts integrating the input signal. Now the
output voltage of side A’s operational amplifier is presented
to the input of the ∆Σ A/D converter (see Figure 5d).
a conversion, the switches SA/D, SINTA, SINTB, SREF1, SREF2
,
and SRESET are set (see Figure 4).
At the completion of an A/D conversion, the charge on the
integration capacitor (CF) is reset with SREF1 and
CAP1A
CAP1A
SREF1
VREF
50pF
RANGE2
RANGE1
RANGE0
25pF
12.5pF
SREF2
SINTA
SA/D1A
Input
Current
IN1
SRESET
To Converter
Integrator A
ESD
Protection
Diode
SINTB
Photodiode
Integrator B (same as A)
FIGURE 3. Basic Integrator Configuration for Input 1 Shown with a 250pC (CF = 62.5pF) Input Range.
DDC112
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CONV
CLK
SINTA
SINTB
SREF1
SREF2
SRESET
SA/D1A
Configuration of
Integrator A
Convert
Wait
Integrate
Convert
Wait
VREF
Integrator A
Voltage Output
FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3.
SREF1
CF
VREF
SINT
SREF2
SREF1
CF
IN
VREF
To Converter
SRESET
SA/D
SINT
SREF2
IN
To Converter
SRESET
SA/D
a) Reset Configuration
SREF1
CF
b) Wait Configuration
VREF
SINT
SREF2
SREF1
CF
IN
VREF
To Converter
SRESET
SA/D
SINT
SREF2
IN
To Converter
SRESET
SA/D
c) Integrate Configuration
d) Convert Configuration
FIGURE 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC112.
DDC112
10
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Determining the Integration Capacitor (CF) Value
EXTERNAL CAPACITOR PINS
INTEGRATOR
DDC112U, UK
DDC112Y, YK
Channel
Side
The value of the integrator’s feedback capacitor, the integra-
tion period, and the reference voltage determine the positive
full-scale (+FS) value of the DDC112. The approximate
positive full-scale value of the DDC112 is given by the
following equations:
5 and 6
3 and 4
23 and 24
25 and 26
1 and 2
1
1
2
2
A
B
A
B
31 and 32
23 and 24
25 and 26
TABLE II. External Capacitor Connections with Range Con-
figuration of RANGE2-RANGE0 = 000.
QIN = IIN × T
INT
Since the range accuracy depends on the characteristics of
the integration capacitor, they must be carefully selected. An
external integration capacitor should have low-voltage coef-
ficient, temperature coefficient, memory, and leakage cur-
rent. The optimum selection depends on the requirements of
the specific application. Suitable types include chip-on-glass
(COG) ceramic, polycarbonate, polystyrene, and silver mica.
QFS = 0.96 VREF × CF
(
)
0.96 VREF × CF
(
)
IFS
=
T
INT
or
I
FS × T
INT
CF
=
(0.96) VREF
Voltage Reference
The 0.96 factor allows the front end integrators to reach full-
scale without having to completely swing to ground. The
negative full-scale (–FS) range is approximately 0.4% of the
positive full-scale range. For example, Range 5 has a nomi-
nal +FS range of 250pC. The –FS range is then approxi-
mately –1pC. This relationship holds for external capacitors
as well and is independent of VREF (for VREF within the
allowable range, see the Electrical Characteristics table).
The external voltage reference is used to reset the integra-
tion capacitors before an integration cycle begins. It is also
used by the ∆Σ converter while the converter is measuring
the voltage stored on the integrators after an integration
cycle ends. During this sampling, the external reference must
supply charge needed by the ∆Σ converter. For an integration
time of 500µs, this charge translates to an average VREF
current of approximately 150µA. The amount of charge
needed by the ∆Σ converter is independent of the integration
time; therefore, increasing the integration time lowers the
average current. For example, an integration time of 1000µs
lowers to average VREF current to 75µA.
Integration Capacitors
There are seven different capacitors available on-chip for
each side of each channel in the DDC112. These internal
capacitors are trimmed in production to achieve the specified
performance for range error of the DDC112. The range
control pins (RANGE0-RANGE2) change the capacitor value
for all four integrators. Consequently, both inputs and both
sides of each input will always have the same full-scale
range unless external capacitors are used.
It is critical that VREF be stable during the different modes of
operation in Figure 5. The ∆Σ converter measures the volt-
age on the integrator with respect to VREF. Since the
integrator’s capacitors are initially reset to VREF, any droop in
VREF from the time the capacitors are reset to the time when
the converter measures the integrator’s output will introduce
an offset. It is also important that VREF be stable over longer
periods of time as changes in VREF correspond directly to
changes in the full-scale range. Finally, VREF should intro-
duce as little additional noise as possible.
External integration capacitors may be used instead of the
internal capacitors values by setting [RANGE2-RANGE0 =
000]. The external capacitor pin connections are summa-
rized in Table II. Usually, all four external capacitors are
equal in value; however, it is possible to have differing pairs
of external capacitors between Input 1 and Input 2 of the
DDC112. Regardless of the selected value of the capacitor,
it is strongly recommended that the capacitors for sides A
and B be the same.
For reasons mentioned above, it is strongly recommended
that the external reference source be buffered with an
operational amplifier, as shown in Figure 6. In this circuit,
the voltage reference is generated by a 4.096V reference.
+5V
0.10µF
+5V
7
0.47µF
2
3
1
To VREF
Pin 22 of
the DDC112
6
OPA350
10kΩ
2
REF3040
+
10µF
0.1µF
+
10µF
0.10µF
4
3
FIGURE 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC112.
DDC112
SBAS085B
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A low-pass filter to reduce noise connects it to an opera-
tional amplifier configured as a buffer. This amplifier should
have a unity-gain bandwidth greater than 4MHz, low noise,
0
–10
–20
–30
–40
–50
and input/output common-mode ranges that support VREF
.
Following the buffer are capacitors placed close to the
DDC112 VREF pin. Even though the circuit in Figure 6 might
appear to be unstable due to the large output capacitors, it
works well for most operational amplifiers. It is NOT recom-
mended that series resistance be placed in the output lead
to improve stability since this can cause droop in VREF which
produces large offsets.
1
TINT
0.1
TINT
10
TINT
100
TINT
DDC112 Frequency Response
The frequency response of the DDC112 is set by the front end
integrators and is that of a traditional continuous time integra-
tor, as shown in Figure 7. By adjusting TINT, the user can
change the 3dB bandwidth and the location of the notches in
the response. The frequency response of the ∆Σ converter that
follows the front end integrator is of no consequence because
the converter samples a held signal from the integrators. That
is, the input to the ∆Σ converter is always a DC signal. Since
the output of the front end integrators are sampled, aliasing can
occur. Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will fold back down to
lower frequencies.
Frequency
FIGURE 7. Frequency Response of the DDC112.
integration capacitors of both Input 1 and Input 2. This fixed
charge can be transferred to the integration capacitors either
once during an integration cycle or multiple times. In the case
where multiple packets are transferred during one integration
period, the 13pC charge is additive. This mode can be used
in both the continuous and noncontinuous mode timing. The
timing diagrams for test mode are shown in Figure 8. The top
three lines in Figure 8 define the timing when one packet of
13pC is sent to the integration capacitors. The bottom three
lines define the timing when multiple packets are sent to the
integration capacitors.
Test Mode
When TEST is used, pins IN1 and IN2 are grounded and
packets of approximately 13pC charge are transferred to the
Test Mode Disabled
Action
Test Mode Enabled
13pC into A 13pC into B
Test Mode Disabled
Integrate B
Integrate A
13pC into B
13pC into A
Integrate B
Integrate A
CONV
TEST
t1
t2
Test Mode Disabled
Test Mode Enabled
26pC into A 39pC into B
Test Mode Disabled
Action
Integrate B Integrate A
13pC into B
52pC into A
Integrate B
Integrate A
CONV
TEST
t4
t5
t2
t4
t1
t3
FIGURE 8. Timing Diagram of the Test Mode of the DDC112.
CLK = 10MHz
TYP
CLK = 15MHz
TYP
SYMBOL
DESCRIPTION
MIN
MAX
MIN
MAX
UNITS
t1
t2
t3
t4
Setup Time for Test Mode Enable
Setup Time for Test Mode Disable
Hold Time for Test Mode Enable
100
100
100
5.4
100
100
100
3.6
ns
ns
ns
µs
From Rising Edge of TEST to the Edge of CONV
while Test Mode Enabled
t5
Rising Edge to Rising Edge of TEST
5.4
3.6
µs
TABLE III. Timing for the DDC112 in the Test Mode.
12
DDC112
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TEST and CONV work together to implement this feature.
The test mode is entered when TEST is HIGH prior to a
CONV edge. At that point, a CONV edge triggers the ground-
ing of the analog inputs and the switching of 13pC packets
of charge onto the integration capacitors. If TEST is kept
HIGH through at least two conversions (that is, a rise and fall
of CONV), all four integrators will be charged with a 13pC
packet. At the end of each conversion, the voltage at the
output of the integrators is digitized as discussed in the
Continuous and Non-Continuous Operational Modes section
of this data sheet. The test mode is exited when TEST is
LOW and a CONV edge occurs.
Continuous and Non-Continuous
Operational Modes
The state diagram of the DDC112 is shown in Figure 9. In all,
there are 8 states. Table IV provides a brief explanation of
each of the states.
mbsy
1
2
CONV • mbsy
Ncont
Ncont
Once the test mode is entered as described above, TEST
can cycle as many times as desired. When this is done,
additional 13pC packets are added on the rising edge of
TEST to the existing charge on the integrator capacitors.
Multiple charge packets can be added in this way as long as
the TEST pin is not LOW when CONV toggles.
CONV
3
Int A
Cont
CONV • mbsy
CONV
4
5
CONV • mbsy
CONV • mbsy
Int B/Meas A
Cont
Int A/Meas B
Cont
DIGITAL ISSUES
The digital interface of the DDC112 provides the digital results
via a synchronous serial interface consisting of a data clock
(DCLK), a transmit enable pin (DXMIT), a valid data pin
(DVALID), a serial data output pin (DOUT), and a serial data
input pin (DIN). The DDC112 contains only one A/D converter,
so the conversion process is interleaved between the two
inputs (see Figure 2). The integration and conversion process
is fundamentally independent of the data retrieval process.
Consequently, the CLK frequency and DCLK frequencies
need not be the same. DIN is used when multiple converters
are cascaded. Cascading or daisy-chaining greatly simplifies
the interconnection and routing of the digital outputs in cases
where a large number of converters are needed. Refer to the
Cascading Multiple Converters section of this data sheet for
more detail.
CONV
6
CONV • mbsy
Int B
Cont
CONV
7
8
Ncont
Ncont
CONV • mbsy
mbsy
FIGURE 9. State Diagram.
STATE
MODE
DESCRIPTION
The conversion rate of the DDC112 is set by a combination of
the integration time (determined by the user) and the speed of
the A/D conversion process. The A/D conversion time is
primarily a function of the system clock (CLK) speed. One
A/D conversion cycle encompasses the conversion of two
signals (one from each input of the DDC112) and reset time
for each of the integrators involved in the two conversions. In
most situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC112 will
operate in the continuous mode. When the DDC112 is in the
continuous mode, the sensor output is continuously integrated
by one of the two sides of each input.
1
Ncont
Complete m/r/az of side A, then side B (if previous
state is state 4). Initial power-up state when CONV
is initially held HIGH.
2
3
4
5
6
7
8
Ncont
Cont
Prepare side A for integration.
Integrate on side A.
Cont
Integrate on side B; m/r/az on side A.
Integrate on side A; m/r/az on side B.
Integrate on side B.
Cont
Cont
Ncont
Ncont
Prepare side B for integration.
Complete m/r/az of side B, then side A (if previous
state is state 5). Initial power-up state when CONV
is initially held LOW.
TABLE IV. State Descriptions.
In the event that the A/D conversion takes longer than the
integration time, the DDC112 will switch into a noncontinu-
ous mode. In noncontinuous mode, the A/D converter is not
able to keep pace with the speed of the integration process.
Consequently, the integration process is periodically halted
until the digitizing process catches up. These two basic
modes of operation for the DDC112—continuous and non-
continuous modes—are described in the Continuous and
Noncontinuous Operational Modes section of this data sheet.
Four signals are used to control progression around the state
diagram: CONV and mbsy and their complements. The state
machine uses the level as opposed to the edges of CONV to
control the progression. mbsy is an internally-generated
signal not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in progress.
DDC112
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During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration. Con-
sequently, keeping track of the current status of CONV is all
that is needed to know the current state. Cont mode opera-
tion corresponds to states 3-6. Two of the states, 3 and 6,
only perform an integration (no m/r/az cycle).
Table V can be easily found for a given CLK. For example,
if CLK = 10MHz, then a CLK period = 0.1µs. t6 in Table V
would then be 479.4µs.
SYMBOL DESCRIPTION
VALUE (CLK periods)
t6
t7
Cont mode m/r/az cycle.
4794
Cont mode data ready.
4212
(tINT > 4794)
4212 ±3 (tINT = 4794)
mbsy becomes important when operating in the ncont mode;
states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy
is active, the DDC112 will enter or remain in either ncont
state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for integra-
tion. As mentioned above, in the ncont states, the inputs to
the DDC112 are grounded.
t8
t9
1st ncont mode data ready.
2nd ncont mode data ready.
Ncont mode m/r/az cycle.
4212 ±3
4548
t10
9108
TABLE V. Timing Specifications Generalized in CLK Periods.
Figure 10 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal is
CONV and is supplied by the user. The next line indicates the
current state in the state diagram. The following two traces
show when integrations and measurement cycles are under-
way. The internal signal mbsy is shown next. Finally, DVALID
is given. As described in the data sheet, DVALID goes active
LOW when data is ready to be retrieved from the DDC112.
It stays LOW until DXMIT is taken LOW by the user. In Figure
10 and the following timing diagrams, it is assumed that
DXMIT it taken LOW soon after DVALID goes LOW. The text
below the DVALID pulse indicates the side of the data and
arrows help match the data to the corresponding integration.
The signals shown in Figures 10 through 19 are drawn at
approximately the same scale.
One interesting observation from the state diagram is that the
integrations always alternate between sides A and B. This
relationship holds for any CONV pattern and is independent
of the mode. States 2 and 7 insure this relationship during the
ncont mode.
When power is first applied to the DDC112, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held HIGH at power-up, the beginning state is 1.
Conversely, for CONV held LOW at power-up, the beginning
state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6, and 4-5. Inverting
CONV results in the states progressing through their sym-
metrical match.
In Figure 10, the first state is ncont state 1. The DDC112
always powers up in the ncont mode. In this case, the first
state is 1 because CONV is initially HIGH. After the first two
states, cont mode operation is reached and the states begin
toggling between 4 and 5. From now on, the input is being
continuously integrated, either by side A or side B. The time
needed for the m/r/az cycle, t6, is the same time that
TIMING EXAMPLES
Cont Mode
A few timing diagrams will now be discussed to help illustrate
the operation of the state machine. These are shown in
Figures 10 through 19. Table V gives generalized timing
specifications in units of CLK periods. Values in µs for
CONV
State
1
2
3
4
5
4
Integration
Status
Integrate A
Integrate B
Integrate A
Integrate B
m/r/az
Status
m/r/az
t6
A
m/r/az
B
m/r/az A
mbsy
DVALID
t7
t = 0
Power-Up
Side A
Data
Side B
Data
Side A
Data
SYMBOL
DESCRIPTION
VALUE (CLK = 10MHz)
VALUE (CLK = 15MHz)
t6
t7
Cont mode m/r/az cycle.
Cont mode data ready.
479.4µs
319.6µs
421.2µs
(TINT > 479.4µs)
(TINT = 479.4µs)
280.8µs
(TINT > 319.6µs)
421.2 ±0.3µs
280.8 ±0.2µs (TINT = 319.6µs)
FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up).
DDC112
14
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determines the boundary between the cont and ncont modes
described earlier in the Overview section. DVALID goes
LOW after CONV toggles in time t7, indicating that data is
ready to be retrieved. As shown in Figure 10, there are two
values for t7, depending on TINT. The reason for this will be
discussed in the Special Considerations section.
Figure 11 shows the result of inverting the logic level of
CONV. The only difference is in the first three states. After-
wards, the states toggle between 4 and 5 just as in the
previous example. Figure 12 shows the timing diagram of the
internal operations occurring during continuous mode opera-
tion.
CONV
State
8
7
6
5
4
5
Integration
Status
Integrate B
Integrate A
Integrate B
Integrate A
m/r/az
Status
m/r/az
t6
B
m/r/az
A
m/r/az B
mbsy
DVALID
t7
t = 0
Power-Up
Side B
Data
Side A
Data
Side B
Data
FIGURE 11. Continuous Mode Timing (CONV LOW at power-up).
End Integration Side A
Start Integration Side B
End Integration Side B
Start Integration Side A
End Integration Side A
Start Integration Side B
TINT
CONV
TINT
Side A
t12
Side B
Side A
A/D Conversion
Input 1 (Internal)
Side A
t12
Side B
A/D Conversion
Input 2 (Internal)
t13
t14
DVALID
Side A
Side B
Data Ready
Data Ready
FIGURE 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC112.
CLK = 10MHz
TYP
CLK = 15MHz
SYMBOL
DESCRIPTION
MIN
MAX
MIN
TYP
MAX
UNITS
TINT
t12
Integration Period (continuous mode)
A/D Conversion Time (internally controlled)
A/D Conversion Reset Time (internally controlled)
500
1,000,000
333
1,000,000
µs
µs
µs
µs
202.2
13.2
61.8
134.8
8.8
t13
t14
Integrator and A/D Conversion Reset Time
(internally controlled)
41.2
TABLE VI. Timing for the Internal Operation in the Continuous Mode.
DDC112
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Ncont Mode
same time as in the cont mode. The second data will be
ready in time t9 after the first data is ready. One result of the
naming convention used in this application bulletin is that
when the DDC112 is operating in the ncont mode, it passes
through both ncont mode states and cont mode states. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1,
2, 3, 4...where 3 and 4 are cont mode states. Ncont mode
by definition means that for some portion of the time, neither
side A nor B is integrating. States that perform an integration
are labeled cont mode states while those that do not are
called ncont mode states. Since integrations are performed
in the ncont mode, just not continuously, some cont mode
states must be used in an ncont mode state pattern.
Figure 13 illustrates operation in the ncont mode. The
integrations come in pairs (that is, sides A/B or sides B/A)
followed by a time during which no integrations occur.
During that time, the previous integrations are being mea-
sured, reset and auto-zeroed. Before the DDC112 can
advance to states 3 or 6, both sides A and B must be
finished with the m/r/az cycle which takes time t10. When the
m/r/az cycles are completed, time t11 is needed to prepare
the next side for integration. This time is required for the
ncont mode because the m/r/az cycle of the ncont mode is
slightly different from that of the cont mode. After the first
integration ends, DVALID goes LOW in time t8. This is the
CONV
State
3
4
1
2
3
4
1
2
t11
Integration
Status
Int A
Int B
Int A
Int B
m/r/az
Status
m/r/az
A
m/r/az B
m/r/az
A
m/r/az B
t10
mbsy
t9
DVALID
t8
Side A
Data
Side B
Data
Side A
Data
Side B
Data
SYMBOL
DESCRIPTION
VALUE (CLK = 10MHz)
VALUE (CLK = 15MHz)
t8
t9
1st ncont mode data ready.
2nd ncont mode data ready.
Ncont mode m/r/az cycle.
Prepare side for integration.
421.2 ±0.3µs
454.8µs
280.8 ±0.2µs
303.2µs
t10
t11
910.8µs
607.2µs
≥ 24.0µs
≥ 24.0µs
FIGURE 13. Non-Continuous Mode Timing.
DDC112
16
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Start Integration Side A
End Integration Side A
Start Integration Side B
Start Integration Side A
End Integration Side B
Wait State
Release
State
TINT
t17
CONV
TINT
t16
A/D Conversion
Input 1
t12
A/D Conversion
Input 2
t12
t13
t15
DVALID
Side A
Side B
Data Ready
Data Ready
FIGURE 14. Conversion Detail for the Internal Operation of the Non-Continuous Mode with Side A Integrated First.
CLK = 10MHz
TYP
CLK = 15MHz
TYP
SYMBOL
DESCRIPTION
MIN
MAX
MIN
MAX
UNITS
TINT
t12
Integration Time (noncontinuous mode)
A/D Conversion Time (internally controlled)
A/D Conversion Reset Time (internally controlled)
50
1,000,000
50
1,000,000
µs
µs
µs
µs
202.2
13.2
37.8
134.8
8.8
t13
t15
Integrator and A/D Conversion Reset Time
(internally controlled)
25.2
t16
t17
Total A/D Conversion and Rest Time
(internally controlled)
910.8
607.2
µs
µs
Release Time
24
24
TABLE VII. Internal Timing for the DDC112 in the Non-Continuous Mode.
Start Integration Side B
Start Integration Side B
End Integration Side B
Start Integration Side A
End Integration Side A
Wait State
Release
State
TINT
CONV
TINT
t17
t16
A/D Conversion
t12
Input 1
A/D Conversion
Input 2
t12
t13
t15
DVALID
Side B
Side A
Data Ready
Data Ready
FIGURE 15. Internal Operation Timing Diagram of the Non-Continuous Mode with Side B Integrated First.
DDC112
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Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC112 remains in
those states until mbsy goes LOW, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 9). The top two signals are
different CONV patterns that produce the same state.
This feature can be a little confusing at first, but it does allow
flexibility in generating ncont mode CONV patterns. For
example, the DDC112 Evaluation Fixture operates in the
ncont mode by generating a square wave with pulse width
< t6. Figure 17 illustrates operation in the ncont mode using
a 50% duty cycle CONV signal with TINT = 1620 CLK
periods. Care must be exercised when using a square wave
to generate CONV. There are certain integration times that
must be avoided since they produce very short intervals for
state 2 (or state 7 if CONV is inverted). As seen in the state
diagram, the state progresses from 2 to 3 as soon as CONV
is HIGH. The state machine does not insure that the duration
of state 2 is long enough to properly prepare the next side
for integration (t11). This must be done by the user with
proper timing of CONV. For example, if CONV is a square
wave with TINT = 3042 CLK periods, state 2 will only be 18
CLK periods long, therefore, t11 will not be met.
CONV1
CONV2
mbsy
State
3
4
1
2
3
4
1
2
FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.
CONV
State
3
4
1
2
3
4
1
Integration
Status
Int A
Int B
Int A
Int B
mbsy
DVALID
Side A
Data
Side B
Data
Side A
Data
FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.
DDC112
18
SBAS085B
www.ti.com
Changing Between Modes
Changing from the ncont to cont mode occurs when TINT is
increased so that TINT is always ≥ t6 (see Figure 14). With a
longer TINT, the m/r/az cycle has enough time to finish before
the next integration begins and continuous integration of the
input signal is possible. For the special case of the very first
integration when changing to the cont mode, TINT can be
< t6. This is allowed because there is no simultaneous
m/r/az cycle on the side B during state 3—there is no need
to wait for it to finish before ending the integration on side A.
Changing from the cont to ncont mode occurs whenever
TINT < t6. Figure 18 shows an example of this transition.
In this figure, the cont mode is entered when the integration
on side A is completed before the m/r/az cycle on side B is
complete. The DDC112 completes the measurement on
sides B and A during states 8 and 7 with the input signal
shorted to ground. Ncont integration begins with state 6.
CONV
State
5
4
5
8
7
6
5
Continuous
Integrate B
Non-Continuous
Integration
Status
Integrate A
Int A
Int B Int A
m/r/az
Status
m/r/az
B
m/r/az
A
m/r/az
B
m/r/az
A
m/r/az B
mbsy
FIGURE 18. Changing from Continuous Mode to Non-Continuous Mode.
CONV
State
3
4
1
2
3
4
Non-Continuous
Continuous
Integrate A
Integration
Status
Int A
Int B
Integrate B
m/r/az
Status
m/r/az
A
m/r/az
B
m/r/az A
mbsy
FIGURE 19. Changing from Non-Continuous Mode to Continuous Mode.
DDC112
SBAS085B
19
www.ti.com
For TINT ≤ t6, the internal slow clock, is not allowed to shut
down and the synchronization never occurs. Therefore, the
time between CONV toggling and DVALID indicating data is
ready has uncertainty due to the random phase relationship
between CONV and the slow clock. This variation is
±1/(2fSLOWCLOCK) or ±3/fCLK. The timing to the second DVALID
in the ncont mode will not have a variation since it is
triggered off the first data ready (t9) and both are derived
from the slow clock.
SPECIAL CONSIDERATIONS
NCONT MODE INTEGRATION TIME
The DDC112 uses a relatively fast clock. For CLK = 10MHz,
this allows TINT to be adjusted in steps of 100ns since CONV
should be synchronized to CLK. However, for the internal
measurement, reset and auto-zero operations, a slower
clock is more efficient. The DDC112 divides CLK by six and
uses this slower clock with a period of 600ns to run the m/r/
az cycle and data ready logic.
Polling DVALID to determine when data is ready eliminates
any concern about the variation in timing since the readback
is automatically adjusted as needed. If the data readback is
triggered off the toggling of CONV directly (instead of poll-
ing), then waiting the maximum value of t7 or t8 insures that
data will always be ready before readback occurs.
Because of the divider, it is possible for the integration time
to be a non-integer number of slow clock periods. For
example, if TINT = 5000 CLK periods (500µs for CLK = 10MHz),
there will be 833 1/3 slow clocks in an integration period. This
non-integer relationship between TINT and the slow clock
period causes the number of rising and falling slow clock
edges within an integration period to change from integration
to integration. The digital coupling of these edges to the
integrators will in turn change from integration to integration
which produces noise. The change in the clock edges is not
random, but will repeat every 3 integrations. The coupling
noise on the integrators appears as a tone with a frequency
equal to the rate at which the coupling repeats.
Data Retrieval
In the continuous and noncontinuous modes of operation,
the data from the last conversion is available for retrieval with
the falling edge of DVALID (see Figure 22). The falling edge
of DXMIT in combination with the data clock (DCLK) will
initiate the serial transmission of the data from the DDC112.
Typically, data is retrieved from the DDC112 as soon as
DVALID falls and completed before the next CONV transition
from HIGH to LOW or LOW to HIGH occurs. If this is not the
case, care should be taken to stop activity on DCLK and
consequently DOUT by at least 10µs around a CONV tran-
sition. If this caution is ignored it is possible that the integra-
tion that is being initiated by CONV will have additional noise
introduced.
To avoid this problem in cont mode, the internal slow clock
is shut down after the m/r/az cycle is complete when it is no
longer needed. It starts up again just after the next integra-
tion begins. Since the slow clock is always off when CONV
toggles, the same number of slow clock edges fall within an
integration period regardless of its length. Therefore,
TINT ≥ 4794 CLK periods will not produce the coupling
problem described above.
The serial output data at DOUT is transmitted in Straight
Binary Code per Table VIII. An output offset has been built
into the DDC112 to allow for the measurement of input
signals near and below zero. Board leakage up to ≈ –0.4%
of the positive full-scale can be tolerated before the digital
output clips to all zeroes.
For the ncont mode however, the slow clock must always be
left running. The m/r/az cycle is not completed before an
integration ends. It is then possible to have digital coupling to
the integrators. The digital coupling noise depends heavily on
the layout of the printed circuit board used for the DDC112.
For solid grounds and power supplies with good bypassing,
it is possible to greatly reduce the coupling. However, for
ensuring the best performance in the ncont mode, the inte-
gration time should be chosen to be an integer multiple of
1/(2fSLOWCLOCK). For CLK = 10MHz, the integration time
should be an integer multiple of 300ns—TINT = 100µs is not.
A better choice would be TINT = 99µs.
CODE
INPUT SIGNAL
1111 1111 1111 1111 1111
1111 1111 1111 1111 1110
0000 0001 0000 0000 0001
0000 0001 0000 0000 0000
0000 0000 0000 0000 0000
FS
FS – 1LSB
+1LSB
Zero
–0.4% FS
TABLE VIII. Straight Binary Code Table.
DATA READY
Cascading Multiple Converters
The DVALID signal which indicates that data is ready is
generated using the internal slow clock. The phase relation-
ship between this clock and CLK is set when power is first
applied and is random. Since CONV is synchronized with
CLK, it will have a random phase relationship with respect to
the slow clock. When TINT > t6, the slow clock will temporarily
shut down as described above. This shutdown process
synchronizes the internal clock with CONV so that the time
between when CONV toggles to when DVALID goes LOW
(t7 and t8) is fixed.
Multiple DDC112 units can be connected in serial or parallel
configurations, as illustrated in Figures 20 and 21.
DOUT can be used with DIN to daisy-chain several DDC112
devices together to minimize wiring. In this mode of opera-
tion, the serial data output is shifted through multiple DDC112s,
as illustrated in Figure 20.
RPULLUP prevents DIN from floating when DXMIT is HIGH.
Care should be taken to keep the capacitive load on DOUT
as low as possible when running CLK=15MHz.
DDC112
20
SBAS085B
www.ti.com
Sensor “F”
Sensor “E” Sensor “D”
Sensor “C” Sensor “B”
Sensor “A”
IN1
IN2
IN1
IN2
IN1
IN2
DDC112
DDC112
DDC112
DCLK
DXMIT
DIN
DCLK
DXMIT
DIN
DCLK
DXMIT
DIN
DVALID
DOUT
DVALID
DOUT
DVALID
DOUT
RP
RP
RP
Data Retrieval
Outputs
“F” “E”
“D” “C”
“B” “A”
40 Bits
40 Bits
40 Bits
Data Retrievel
Inputs
FIGURE 20. Daisy-Chained DDC112s.
DDC112
DDC112
DDC112
DIN
DIN
DOUT
DXMIT
Data Output
DOUT
DXMIT
DOUT
DXMIT
DIN
Enable
FIGURE 21. DDC112 in Parallel Operation.
CLK
t18
DVALID
t19
DXMIT
t20
DCLK(1)
t22
t21
t23
Input 2
Bit 1
Input 2
Bit 20
Input 1
Bit 1
Input 1
Bit 20
DOUT
Output Disabled
Output Disabled
MSB
LSB
MSB
LSB
Output Enabled
NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH.
FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t18
t19
t20
t21
t22
t23
Propagation Delay from Rising Edge of CLK to DVALID LOW
Propagation Delay from DXMIT LOW to DVALID HIGH
Setup Time from DCLK LOW TO DXMIT LOW
30
30
ns
ns
ns
ns
ns
ns
ns
ns
20
30
Propagation Delay from DXMIT LOW to Valid DOUT
Hold Time that DOUT is Valid After Falling Edge of DCLK
Propagation Delay from DXMIT HIGH to DOUT Disabled
Propagation Delay from Falling Edge of DCLK to Valid DOUT
Propagation Delay from Falling Edge of DCLK to Valid DOUT
30
5
(1)
t22A
25
30
(2)
t22B
NOTES: (1) Applies to DDC112UK, YK only, with a maximum load of one DDC112UK, YK DIN (4pF typical) with an additional load of (5pF 100kΩ). (2) Applies
to DDC112U, Y only, with a maximum load of one DDC112U,Y DIN (4pF typical) with an additional load of (5pF 100kΩ).
TABLE IX. Timing for the DDC112 Data Retrieval.
DDC112
SBAS085B
21
www.ti.com
CLK
t18
t26
DVALID
t14
DXMIT
t20
DCLK(1)
t22
t24
t25
DIN
t22A, t22B
t23
t21
Input A
Bit 1
Input E
Bit 20
Input F
Bit 1
Input F
Bit 20
DOUT
Output Disabled
MSB
LSB
MSB
LSB
Output Disabled
Output Enabled
NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH.
FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112.
CLK = 10MHz
TYP
CLK = 15MHz
TYP
SYMBOL
DESCRIPTION
MIN
MAX
MIN
MAX
UNITS
t24
t25
t26
Set-Up Time From DIN to Rising Edge of DCLK
Hold Time For DIN After Rising Edge of DCLK
10
10
2
5
ns
ns
µs
10
Hold Time for DXMIT HIGH Before Falling
Edge of DVALID
1.33
TABLE X. Timing for the DDC112 Data Retrieval Using DIN.
RETRIEVAL BEFORE CONV TOGGLES
(CONTINUOUS MODE)
RETRIEVAL AFTER CONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the new
data is ready. Data retrieval must wait t29 after CONV toggles
before beginning. Figure 25 shows an example of this. The
maximum time available for retrieval is t27 – t29 – t26
This is the most straightforward method. Data retrieval be-
gins soon after DVALID goes LOW and finishes before
CONV toggles, see Figure 24. For best performance, data
retrieval must stop t28 before CONV toggles. This method is
the most appropriate for longer integration times. The maxi-
mum time available for readback is TINT – t27 – t28.
For DCLK and CLK = 10MHz, the maximum number of
DDC112s that can be daisy-chained together is:
(421.2µs – 10µs – 2µs for CLK = 10MHz), regardless of TINT
.
The maximum number of DDC112s that can be daisy-
chained together is:
409.2µs
40τDCLK
T
– 431.2µs
40τDCLK
INT
For DCLK = 10MHz, the maximum number of DDC112s is
102.
Where τDCLK is the period of the data clock. For example, if
INT = 1000µs and DCLK = 10MHz, the maximum number of
DDC112s is:
T
1000µs – 431.2µs
= 142.2 → 142 DDC112s
(40)(100ns)
DDC112
22
SBAS085B
www.ti.com
CONV
TINT
TINT
DVALID
t27
t28
DXMIT
DCLK
• • •
• • •
DOUT
• • •
• • •
Side B
Data
Side A
Data
CLK = 10MHz
TYP
CLK = 15MHz
TYP
SYMBOL
DESCRIPTION
MIN
MAX
MIN
MAX
UNITS
t27
t28
Cont Mode Data Ready
Data Retrieval Shutdown Before Edge of CONV
421.2
280.8
µs
µs
10
10
FIGURE 24. Readback Before CONV Toggles.
TINT
TINT
TINT
CONV
DVALID
t27
t29
t26
DXMIT
DCLK
• • •
• • •
• • •
• • •
• • •
• • •
DOUT
Side A
Data
Side B
Data
Side A
Data
CLK = 10MHz
CLK = 15MHz
TYP
SYMBOL
DESCRIPTION
MIN
TYP
MAX
MIN
MAX
UNITS
t26
Hold Time for DXMIT HIGH Before Falling Edge
of DVALID
2
1.33
µs
t27
t29
Cont Mode Data Ready
421.2
280.8
µs
µs
Data Retrieval Start-Up After Edge of CONV
10
10
FIGURE 25. Readback After CONV Toggles.
DDC112
SBAS085B
23
www.ti.com
RETRIEVAL BEFORE AND AFTER CONV
TOGGLES (CONTINUOUS MODE)
(available for download at www.ti.com), DVALID goes LOW
in time t30 after the first integration completes. If TINT is
shorter than this time, all of t31 is available to retrieve data
before the other side’s data is ready. For TINT > t30, the first
integration’s data is ready before the second integration
completes. Data retrieval must be delayed until the second
integration completes leaving less time available for retrieval.
The time available is t31 – (TINT – t30). The second integration’s
data must be retrieved before the next round of integrations
begin. This time is highly dependent on the pattern used to
generate CONV. As with the continuous mode, data retrieval
must halt before and after CONV toggles (t28 and t29) and be
completed before new data is ready (t26).
For the absolute maximum time for data retrieval, data can
be retrieved before and after CONV toggles. Nearly all of TINT
is available for data retrieval. Figure 26 illustrates how this is
done by combining the two previous methods. You must
pause the retrieval during CONV toggling to prevent digital
noise, as discussed previously, and finish before the next
data is ready. The maximum number of DDC112s that can
be daisy-chained together is:
T
– 20µs – 2µs
40τDCLK
INT
For TINT = 500µs and DCLK = 10MHz, the maximum number
of DDC112s is 119.
POWER-UP SEQUENCING
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed AVDD or DVDD. The level of CONV at power-
up is used to determine which side (A or B) will be integrated
first. Before integrations can begin though, CONV must
toggle; see Figure 28.
RETRIEVAL: NONCONTINUOUS MODE
Retrieving in noncontinuous mode is slightly different as
compared with the continuous mode. As shown in Figure 27
and described in detail in Application Bulletin SBAA024
CONV
TINT
TINT
TINT
t29
DVALID
t26
t28
DXMIT
DCLK
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
DOUT
Side B
Data
Side A
Data
CLK = 10MHz
TYP
CLK = 15MHz
TYP
SYMBOL
DESCRIPTION
MIN
MAX
MIN
MAX
UNITS
t26
Hold Time for DXMIT HIGH Before Falling
Edge of DVALID
2
1.33
µs
t28
t29
Data Retrieval Shutdown Before Edge of CONV
Data Retrieval Start-Up After dge of CONV
10
10
10
10
µs
µs
FIGURE 26. Readback Before and After CONV Toggles.
DDC112
24
SBAS085B
www.ti.com
TINT
TINT
CONV
TINT
TINT
DVALID
t30
t31
DXMIT
DCLK
• • •
• • •
• • •
• • •
DOUT
Side A
Data
Side B
Data
CLK = 10MHz
CLK = 15MHz
TYP
SYMBOL
DESCRIPTION
MIN
TYP
MAX
MIN
MAX
UNITS
t30
t31
1st Ncont Mode Data Ready (see SBAA024)
2nd Ncont Mode Data Ready (see SBAA024)
421.1 ±0.3
454.8
280.8
303.2
µs
µs
FIGURE 27. Readback in Noncontinuous Mode.
Release State
Power-Up
Start
Initialization
Integration
CONV
(HIGH at power-up)
t32
t33
Integrate Side A
Integrate Side B
CONV
(LOW at power-up)
Power Supplies
FIGURE 28. Timing Diagram at Power-Up of the DDC112.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t32
t33
Power-On Initialization Period
50
50
µs
µs
From Release Edge to Integration Start
TABLE XI. Timing for the DDC112 Power-Up Sequence.
shows the DVDD power supply derived from the AVDD supply
with a < 10Ω isolation resistor. In both cases, the 0.1µF
capacitors should be placed as close to the DDC112 pack-
age as possible.
LAYOUT
Power Supplies and Grounding
Both AVDD and DVDD should be as quiet as possible. It is
particularly important to eliminate noise from AVDD that is
non-synchronous with the DDC112 operation. Figure 29
illustrates two acceptable ways to supply power to the
DDC112. The first case shows two separate +5V supplies for
AVDD and DVDD. In this case, each +5V supply of the
DDC112 should be bypassed with 10µF solid tantalum ca-
pacitors and 0.1µF ceramic capacitors. The second case
Shielding Analog Signal Paths
As with any precision circuit, careful printed circuit layout will
ensure the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—
particularly at the analog input pins. Digital signals should be
kept as far from the analog input signals as possible on the
PC board.
DDC112
SBAS085B
25
www.ti.com
are used for the external integration capacitors should be
guarded by a ground plane when the external capacitors are
used.
Input shielding practices should be taken into consideration
when designing the circuit layout for the DDC112. The inputs
to the DDC112 are high impedance and extremely sensitive
to extraneous noise. Leakage currents between the PCB
traces can exceed the input bias current of the DDC112 if
shielding is not implemented. Figure 30 illustrates an accept-
able approach to this problem. A PC ground plane is placed
around the inputs of the DDC112. This shield helps minimize
coupled noise into the input pins. Additionally, the pins that
The approach above reduces leakage affects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather than
into the analog input stage of the DDC112.
IN1
IN2
Analog
Ground
VS+
AVDD
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Analog
Ground
Analog
Ground
10µF
0.1µF
0.1µF
DDC112
VDD
+
3
Shield
external
caps when
used
Shield
external
caps when
used
4
DVDD
10µF
5
6
Separate +5V Supplies
Analog
Power
7
DDC112U
Analog
Ground
8
VS+
9
AVDD
10µF
< 10Ω
10
11
12
13
14
0.1µF
0.1µF
DDC112
DVDD
One +5V Supply
Digital I/O
Digital I/O
and
and
Digital Power
Digital Power
FIGURE 30. Recommended Shield for DDC112U Layout
Design.
FIGURE 29. Power Supply Connection Options.
DDC112
26
SBAS085B
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DDC112U
DDC112U/1K
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
DW
DW
DW
DW
DW
DW
PJT
PJT
PJT
PJT
PJT
PJT
28
28
28
28
28
28
32
32
32
32
32
32
20
1000
1000
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
DDC112U/1KG4
DDC112UG4
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
DDC112UK
20
Green (RoHS
& no Sb/Br)
DDC112UKG4
DDC112Y/250
DDC112Y/250G4
DDC112Y/2K
20
Green (RoHS
& no Sb/Br)
250
250
2000
2000
250
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
DDC112Y/2KG4
DDC112YK/250
DDC112YK/250G4
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DDC112U/1K
DDC112Y/250
DDC112Y/2K
DDC112YK/250
SOIC
TQFP
TQFP
TQFP
DW
PJT
PJT
PJT
28
32
32
32
1000
250
330.0
330.0
330.0
330.0
32.4
16.4
16.4
16.4
11.35 18.67
3.1
1.5
1.5
1.5
16.0
12.0
12.0
12.0
32.0
16.0
16.0
16.0
Q1
Q2
Q2
Q2
9.6
9.6
9.6
9.6
9.6
9.6
2000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DDC112U/1K
DDC112Y/250
DDC112Y/2K
DDC112YK/250
SOIC
TQFP
TQFP
TQFP
DW
PJT
PJT
PJT
28
32
32
32
1000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
55.0
38.0
38.0
38.0
2000
250
Pack Materials-Page 2
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
PJT (S-PQFP–N32)
PLASTIC QUAD FLATPACK
0,45
0,30
0,80
M
0,20
0,20
0,09
Gage Plane
32
0,15
0,05
0,25
1
0°– 7°
7,00
9,00
SQ
SQ
0,75
0,45
1,05
0,95
Seating Plane
0,10
1,20
1,00
4203540/A 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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