DF1706 [TI]
Stereo, 24-Bit, 192kHz 8x Oversampling Digital Interpolation Filter; 立体声， 24位， 192kHz的8倍过采样数字插值滤波器
| 型号： | DF1706 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Stereo, 24-Bit, 192kHz 8x Oversampling Digital Interpolation Filter |
| 文件： | 总18页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DF1706
49%
FPO
DF1706
www.ti.com
Stereo, 24-Bit, 192kHz
8x Oversampling Digital Interpolation Filter
● SYSTEM CLOCK: 128fS, 192fS, 256fS,
FEATURES
● COMPANION DIGITAL FILTER FOR THE
384fS, 512fS, 768fS
● ON-CHIP CRYSTAL OSCILLATOR
PCM1704 24-BIT AUDIO DAC
● PROGRAMMABLE FUNCTIONS:
Hardware or Software Control Modes
Sharp or Slow Roll-Off Filter Response
Soft Mute
● HIGH PERFORMANCE FILTER:
Stopband Attenuation: –115dB
Passband Ripple: ±0.00005dB
● AUDIO INTERFACE:
Digital De-Emphasis
Independent Left/Right Digital Attenuation
Input Data Formats: Standard, Left-
Justified, and I2S
Input Word Length: 16, 20, or 24 Bits
Output Word Length: 16, 18, 20, or 24 Bits
Sampling Frequency: 32kHz to 192kHz
● +3.3V SINGLE-SUPPLY OPERATION
● SMALL SSOP-28 PACKAGE
selectable filter response, de-emphasis, attenuation,
and input/output data formats.
DESCRIPTION
The DF1706 is a high performance, stereo, 8X
oversampling digital interpolation filter designed for
high-end consumer and professional audio applica-
tions. The DF1706 supports 24-bit, 192kHz operation
and features user-programmable functions, including
The DF1706 is the ideal companion for Texas
Instruments’s PCM1704 24-bit audio Digital-to-Ana-
log (D/A) converter. This combination allows for the
construction of very high-performance audio systems
and components.
BCKO
BCKIN
Serial
LRCIN
Input
I/F
8X Oversampling
Digital Filter with
Function
WCKO
DIN
Output I/F
DOL
DOR
Controller
x4
MD/CKO
MC/LRIP
Mode
Control
I/F
ML/RESV
MODE
SCK
(MUTE)
RST
(DEM)
Crystal/OSC
Power Supply
VDD DGND
(SF0) (SF1) (SRO)
XTI
XTO
CLKO
Copyright © 2001, Texas Instruments Incorporated
SBAS182
Printed in U.S.A. January, 2001
SPECIFICATIONS
All specifications at TA = +25°C, VDD = 3.3V, fS = 44.1kHz, system clock = 256fS/384fS, 16-bit data, unless otherwise noted.
DF1706E
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
24
Bits
INPUT DATA FORMAT
Audio Data Interface Format
Audio Data Bit Length
Audio Data Format
Sampling Frequency
System Clock Frequency(1)
Standard, Left-Justified , I2S
16, 20, 24 Selectable
MSB First, Binary Two’s Complement
32 192
fS
kHz
fS
128/192/256/384/512/768
OUTPUT DATA FORMAT
Audio Data Interface Format
Audio Data Bit Length
Audio Data Format
Right-Justified
16, 20, 24 Selectable
MSB First, Binary Two’s Complement
DIGITAL INPUT/OUTPUT
CMOS Compatible
Input Logic Level: VIH
0.7VDD
V
V
V
V
VIL
Output Logic Level: VOH
VOL
0.3VDD
1.0
IOH = 2mA
IOL = 4mA
2.4
CLKO AC CHARACTERISTICS(2)
Rise Time
Fall Time
Duty Cycle(2)
tR
tF
20% to 80% VDD, 20pF
80% to 20% VDD, 20pF
20pF Load
4
3
50
ns
ns
%
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1 (Sharp Roll-Off)
Passband
±0.00005dB
0.454
0.493
fS
fS
–3dB
Stopband
Passband Ripple
Stopband Attenuation
Filter Characteristics 2 (Slow Roll-Off)
Passband Ripple
0.546
–115
fS
dB
dB
±0.00005
Stopband = 0.546fS
±0.0001dB
–3dB
0.254
0.460
fS
fS
Stopband
0.732
–100
fS
Passband Ripple
Stopband Attenuation
Delay Time
±0.0001
±0.004
dB
dB
sec
dB
Stopband = 0.748fS
45.125/fS
De-Emphasis Error
POWER-SUPPLY REQUIREMENTS
Voltage Range
Supply Current
VDD
VDD = 3.3V
DD = 3.3V
3.0
3.3
30
99
3.6
45
149
VDC
mA
mW
IDD
Power Dissipation
V
TEMPERATURE RANGE
Operation
Storage
–25
–55
+85
+125
°C
°C
°C
Thermal Resistance, θJA
SSOP-28
100
NOTES: (1) Refer to Table I. (2) Crystal resonator used.
DF1706
SBAS182
2
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN NAME
I/O
DESCRIPTION
Top View
SSOP
1
2
3
4
5
6
7
8
9
10
DIN
BCKIN
I2S
IN
IN
Serial Audio Data Input(1)
Bit Clock Input for Serial Audio Data(1)
Input Audio Data Format Select(2, 4)
Input Audio Data Word Select(2, 4)
Input Audio Data Word Select(2, 4)
Oscillator Input/External Clock Input
Oscillator Output
IN
IW0
IN
IW1
IN
XTI
IN
XTO
DGND
CLKO
MODE
OUT
—
DIN
BCKIN
I2S
1
2
3
4
5
6
7
8
9
28 LRCIN
27 SRO
26 BCKO
25 WCKO
24 DOL
23 DOR
22 VDD
Digital Ground
OUT
IN
Buffered System Clock Output
Mode Control Select (HIGH: Software Mode,
LOW: Hardware Mode)(3)
11 MD/CKO
IN
Mode Control, Data/Half External Clock Fre-
quency Select(3, 5)
Mode Control, Clock/Polarity of LRCIN Select(3, 5)
IW0
IW1
12 MC/LRIP
13 ML/RESV
IN
IN
IN
Mode Control, Latch Clock/Reserve(3, 5)
XTI
14
RST
Reset, Active LOW. When this pin is LOW the
DF and modulators are held in reset.(3)
Mute Control, Active LOW(4)
DF1706E
XTO
DGND
CLKO
15
16
17
18
19
20
21
MUTE
DEM
SF0
IN
IN
IN
IN
IN
IN
IN
De-Emphasis Control(2, 4)
21 x4
Sampling Rate Select for De-emphasis(2, 4)
Sampling Rate Select for De-emphasis(2, 4)
Output Audio Data Word Select(2, 4)
Output Audio Data Word Select(2, 4)
Oversampling Ratio Control. When this pin is
set HIGH, the ratio is 4 times.
Digital Power, +3.3V
20 OW1
19 OW0
18 SF1
SF1
OW0
OW1
x4
MODE 10
MD/CKO 11
MC/LRIP 12
ML/RSV 13
RST 14
17 SF0
22
23
24
25
26
27
28
VDD
DOR
—
16 DEM
15 MUTE
OUT
OUT
OUT
OUT
IN
R-Channel, Serial Audio Data Output
L-Channel, Serial Audio Data Output
Word Clock Output for Serial Audio Data Output
Bit Clock Output for Serial Audio Data Output
Filter Response Select(2, 4)
DOL
WCKO
BCKO
SRO
LRCIN
IN
L/R Clock Input (fS)(1)
NOTES: (1) Pins 1, 2, 28—Schmitt-Trigger input without pull-up and -down
resistor. (2) Pins 3-5, 16-21, 27—Schmitt-Trigger input without pull-up and
-down resistor. (3) Pins 10-15—Schmitt-Trigger input without pull-up and
-down resistor. (4) Pins 3-5, 15-20, 27—these pins are invalid when MODE
(pin 10) is HIGH. (5) Pins 11-13—these pins have different functions corre-
sponding to MODE (pin 10) HIGH/LOW.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Supply Voltage .................................................................................. +4.0V
Digital Input Voltage ..............................................................–0.2V to 4.5V
Input Current (any pins except supplies) ........................................ ±10mA
Operating Temperature Range ......................................... –25°C to +85°C
Ambient Storage Temperature ....................................... –40°C to +125°C
Junction Temperature ................................................................... +150°C
Lead Temperature (soldering, 5s)................................................. +260°C
Package Temperature (IR reflow, Peak, 10s) ................................ +235°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DF1706E
SSOP-28
324
–25°C to +85°C
DF1706E
DF1706E
Rails
"
"
"
"
"
DF1706E/2K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “DF1706E/2K” will get a single 2000-piece Tape and Reel.
DF1706
3
SBAS182
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = ±3.3V, fS = 44.1kHz, System Clock = 256fS/384fS, 16-bit data, unless otherwise noted.
DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz)
FREQUENCY RESPONSE (Sharp Roll-Off)
PASSBAND RIPPLE (Sharp Roll-Off)
20
0
0.00010
0.00008
0.00006
0.00004
0.00002
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–0.00002
–0.00004
–0.00006
–0.00008
–0.00010
0
1
2
3
4
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (fS)
Frequency (fS)
TRANSITION CHARACTERISTIC (Slow Roll Off)
FREQUENCY RESPONSE (Slow Roll Off)
0
–5
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–10
–15
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
1
2
3
4
Frequency (fS)
Frequency (fS)
DE-EMPHASIS AND DE-EMPHASIS ERROR
DE-EMPHASIS ERROR (fS = 32kHz)
DE-EMPHASIS (fS = 32kHz)
0
0.010
0.008
0.006
0.004
0.002
0
–2
–4
–0.002
–0.004
–0.006
–0.008
–0.010
–6
–8
–10
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
Frequency (kHz)
Frequency (kHz)
DF1706
SBAS182
4
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VDD = ±3.3V, fS = 44.1kHz, System Clock = 256fS/384fS, 16-bit data, unless otherwise noted.
DE-EMPHASIS (fS = 44.1kHz)
DE-EMPHASIS ERROR (fS = 44.1kHz)
0
–2
0.010
0.008
0.006
0.004
0.002
0
–4
–6
–0.002
–0.004
–0.006
–0.008
–0.010
–8
–10
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Frequency (kHz)
Frequency (kHz)
DE-EMPHASIS (fS = 48kHz)
DE-EMPHASIS ERROR (fS = 48kHz)
0
–2
0.010
0.008
0.006
0.004
0.002
0
–4
–0.002
–0.004
–0.006
–0.008
–0.010
–6
–8
–10
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
Frequency (kHz)
Frequency (kHz)
DF1706
5
SBAS182
SYSTEM CLOCK REQUIREMENTS
tSCKH
The system clock of the DF1706 can be supplied by either an
external clock signal at XTI (pin 6), or by the on-chip crystal
oscillator. The system clock rate must run at 128fS, 192fS,
256fS, 384fS, 512fS, or 768fS, where fS is the audio sampling
rate. When a 128fS or 192fS system clock is applied to
DF1706, the Over-Sampling Ratio (OSR) of the DF1706's
digital filter should be four times instead of eight times. The
OSR can be selected by the x4 pin (pin 21) in hardware mode
or x4 bit on MODE 2 register in software mode.
HIGH
2.0V
0.8V
System Clock
LOW
tSCKL
SYMBOL
PARAMETERS
MIN
MAX
UNITS
tSCKH
tSCKL
System Clock Pulse Width HIGH
System Clock Pulse Width LOW
12
12
ns(1)
ns(1)
NOTE: (1) For fS = 96kHz and SCK = 256fS, tSCKIH = 14ns (min)
SCKIL = 14ns (min)
For fS ≠ 96kHz and SCK = 256fS, tSCKIH = 20ns (min)
SCKIL = 20ns (min)
t
It should be noted that a 768fS system clock cannot be used
when fS is larger than 48kHz. Both 128fS and 192fS system
clock can be used when fS is larger than 96kHz. In addition,
the on-chip crystal oscillator is limited to a maximum fre-
quency of 24.0MHz. Table I shows the typical system clock
frequencies for selected sample rates.
t
FIGURE 1. System Clock Timing.
RESET
The DF1706 has both an internal power-on reset circuit and
a reset pin, RST (pin 14), for providing an external reset
signal. The internal power-on reset is performed automati-
cally when power is applied to the DF1706, as shown in
Figure 2. The RST pin can be used to synchronize the
DF1706 with a system reset signal, as shown in Figure 3.
The DF1706 includes a system clock detection circuit that
determines the system clock rate in use. The circuit compares
the system clock input (XTI) frequency with the LRCIN input
rate to determine the system clock multiplier. Ideally, LRCIN
and BCKIN should be derived from the system clock to
ensure proper synchronization. If the phase difference be-
tween the system clock and LRCIN is larger than ±4 bit clock
(BCKIN) periods, the synchronization of the system and
LRCIN clocks will be performed automatically by the DF1706.
During the power-on reset period (1024 system clocks), the
outputs of BCKO, DOL, and DOR are forced LOW and the
output of WCKO is forced HIGH. For an external forced reset,
the outputs of BCKO, DOL, and DOR are forced LOW and the
output of WCKO is forced HIGH during the initialization
period (1024 system clocks), which occurs after the LOW-to-
HIGH transition of the RST pin (see Figure 3).
Timing requirements for the system clock input are shown in
Figure 1.
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE FREQUENCY (fS)256fS
128fS
192fS
256fS
384fS
512fS
768fS
32kHz
44.1kHz
48kHz
N/A
N/A
N/A
N/A
8.192
11.2896
12.288
22.5792(1)
24.576
N/A
12.288
16.934
18.432
33.8688(1)
36.864(1)
N/A
16.384
22.5792
24.576(1)
N/A
24.576(1)
33.8688(1)
36.864(1)
N/A
N/A
N/A
88.2kHz
96kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
192kHz
22.5792(2)
24.576(1)(2)
33.8688(1)(2)
36.864(1)(2)
N/A
N/A
N/A
N/A
N/A
N/A
NOTES: (1) Crystal oscillator frequency using internal oscillator is not covered at frequency larger than 24.0MHz. (2) x4 (pin 21) should be set to HIGH.
TABLE I. Typical System Clock Frequencies.
2.8V
VCC/VDD 2.5V
1.8V
Reset
Reset Removal
Internal Reset
System Clock
1024 system clocks
FIGURE 2. Internal Power-On Reset Timing.
DF1706
SBAS182
6
External Reset
Reset
Reset Removal
Internal Reset
System Clock
1024 system clocks
FIGURE 3. External Forces Reset Timing.
AUDIO INPUT INTERFACE
clock, LRCIN, is used as a word latch for the audio input
data. BCKIN can run at 32fS, 48fS, or 64fS, where fS is the
audio sample frequency. LRCIN is run at the fS rate. Figures
4 (a) through (c) show the input data formats, which are sel-
ected by hardware or software controls.
The audio input interface is comprised of BCKIN (pin 2),
LRCIN (pin 28), and DIN (pin 1). BCKIN is the input bit
clock, which is used to clock data applied at DIN into the
DF1706’s input serial interface. Input data at DIN is clocked
into the DF1706 on the rising edge of BCKIN. The left/right
See Figure 5 for the audio input interface timing requirements.
(a) Standard Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
Lch
Rch
LRCIN
BCKIN
AUDIO DATA WORD = 16-BIT
DIN 14 15 16
1
2
15 16
19 20
23 24
1
2
15 16
19 20
23 24
MSB
LSB
LSB
LSB
AUDIO DATA WORD = 20-BIT
DIN 18 19 20
1
2
1
2
MSB
AUDIO DATA WORD = 24-BIT
DIN 22 23 24
1
2
1
2
MSB
MSB
LSB
(b) Left-Justified Format; L-Channel = HIGH, R-Channel = LOW
1/fS
Lch
Rch
LRCIN
BCKIN
AUDIO DATA WORD = 24-BIT
DIN
1
2
3
22 23 24
LSB
1
2
3
22 23 24
LSB
1
2
3
MSB
MSB
(c) I2S Data Format (Philips Format); L-Channel = LOW, R-Channel = HIGH
1/fS
Lch
Rch
LRCIN
BCKIN
AUDIO DATA WORD = 16-BIT
DIN
1
1
2
2
15 16
1
1
2
15 16
1
1
2
2
MSB
MSB
LSB
MSB
LSB
AUDIO DATA WORD = 24-BIT
DIN
23 24
2
23 24
LSB
MSB
LSB
FIGURE 4. Audio Data Input Formats.
DF1706
7
SBAS182
AUDIO OUTPUT INTERFACE
BCKO is fixed at 256fS for system clock rates of 256fS or
512fS.
The audio output interface includes BCKO (pin 26), WCKO
(pin 25), DOL (pin 24), and DOR (pin 23).
BCKO is fixed at 192fS for system clock rates of 384fS or
768fS.
BCKO is the output bit clock and is used to clock data into an
audio D/A converter, such as the PCM1704. DOL and DOR
are the left and right audio data outputs. WCKO is the output
word clock and is used to latch audio data words into an audio
D/A converter.
The output data format used by the DF1706 for DOL and
DOR is Binary Two’s Complement, MSB-first, right-justified
audio data. Figures 6(a), (b), (c), and (d) show the output data
formats for the DF1706. See Figure 7 the audio output timing.
WCKO runs at a fixed rate of 8fS (8x oversampling) for all
system clock rates.
BCKIN Pulse Cycle Time
BCKIN Pulse Width LOW
BCKIN Pulse Width HIGH
BCKIN Rising Edge to LRCIN Edge
LRCIN Edge to BCK Rising Edge
DIN Set-up Time
tBCY
tBCL
tBCH
tBL
82ns (min)
35ns (min)
35ns (min)
10ns (min)
10ns (min)
10ns (min)
10ns (min)
LRCKIN
50% of VDD
50% of VDD
tBCH
tBCL
tLB
BCKIN
tLB
tBCY
tBL
tDS
DIN Hold Time
tDH
DIN
50% of VDD
tDS
tDH
FIGURE 5. Audio Input Interface Timing.
(a) SYSTEM CLOCK: 256/512fS
1/8fS
WCKO
BCKO
AUDIO DATA WORD = 16-BIT
DOR
14 15 16
DOL
1
2
15 16
MSB
LSB
17 18
AUDIO DATA WORD = 18-BIT
DOR
16 17 18
DOL
1
2
MSB
LSB
AUDIO DATA WORD = 20-BIT
DOR
18 19 20
DOL
1
2
19 20
23 24
MSB
LSB
LSB
AUDIO DATA WORD = 24-BIT
DOR
22 23 24
DOL
1
2
MSB
(b) SYSTEM CLOCK: 384/768fS
1/8fS
WCKO
BCKO
AUDIO DATA WORD = 16-BIT
DOR
14 15 16
DOL
1
2
15 16
MSB
LSB
17 18
AUDIO DATA WORD = 18-BIT
DOR
16 17 18
1
2
DOL
MSB
LSB
AUDIO DATA WORD = 20-BIT
DOR
DOL
18 19 20
1
2
19 20
23 24
MSB
LSB
LSB
AUDIO DATA WORD = 24-BIT
DOR
DOL
22 23 24
1
2
1
2
MSB
FIGURE 6. Audio Output Data Format.
8
DF1706
SBAS182
(a) SYSTEM CLOCK: 128fS
1/4fS
WCKO
BCKO
AUDIO DATA WORD = 16-BIT
DOR
14 15 16
DOL
1
2
15 16
MSB
LSB
AUDIO DATA WORD = 18-BIT
DOR
16 17 18
DOL
1
2
17 18
19 20
23 24
MSB
LSB
LSB
LSB
AUDIO DATA WORD = 20-BIT
DOR
18 19 20
DOL
1
2
MSB
AUDIO DATA WORD = 24-BIT
DOR
22 23 24
DOL
1
2
MSB
(b) SYSTEM CLOCK: 192fS
1/4fS
WCKO
BCKO
AUDIO DATA WORD = 16-BIT
DOR
14 15 16
DOL
1
2
15 16
MSB
LSB
17 18
AUDIO DATA WORD = 18-BIT
DOR
16 17 18
DOL
1
2
MSB
LSB
AUDIO DATA WORD = 20-BIT
DOR
18 19 20
DOL
1
2
19 20
23 24
MSB
LSB
LSB
AUDIO DATA WORD = 24-BIT
DOR
22 23 24
DOL
1
2
1
2
MSB
(Cont.) FIGURE 6. Audio Output Data Format.
MODE CONTROL
MODE SETTING
MODE CONTROL SELECTION
The DF1706 may be configured using either software or
hardware control. The selection is made using the MODE
input (pin 10). See Table II for MODE selection.
MODE = H
MODE = L
Software Mode
Hardware Mode
TABLE II. MODE Selection.
tWCKP
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
WCKO
BCKO
0.5VDD
BCKO Period
tBCKP
1/96fS, 1/128fS, 1/192fS, 1/256fS,
BCKO Pulse Width HIGH/LOW (fS = 192kHz, 192fS
(fS = 192kHz, 128fS
)
)
tBCKH/tBCKL
10
14
20
–5
20
30
100
5
ns
ns
ns
ns
tBCKH
tBCKL
tCKWK
(other fS, 256/384/512/768fS
Delay Time BCKO Falling Edge to WCKO Valid
)
0.5VDD
tCKWK
tWCKP
tCKDO
tR
WCKO Period
1/4fS, 1/8fS
tBCKP
tCKDO
Delay Time BCKO Falling Edge to DOL, R Valid
Rising Time of All Signals
–5
7
5
ns
ns
ns
DOL, R
0.5VDD
Falling Time of All Signals
tF
7
NOTE: (1) Rising and falling time is measured from 10% to 90% of IN/OUT signal swing.
(2) Load capacitance of all signals are 20pF.
FIGURE 7. Audio Data Output Timing.
DF1706
9
SBAS182
Programmable Functions
PIN
PIN
NAME NUMBER
DESCRIPTION
The DF1706 includes a number of programmable features,
with most being accessible from either Hardware or Soft-
ware mode. Table III summarizes the user-programmable
functions for both modes of operation.
RSV
LRIP
13
12
Reserved, Not Used
LRCIN Polarity
LRIP = H: LRCIN= H = Left Channel, LRCIN= L = Right Channel
LRIP = L: LRCIN= L = Left Channel, LRCIN = H = Right Channel
CKO
11
CLKO Output Frequency
CKO = H: CLKO Frequency = XTI/2
CKO = L: CLKO Frequency = XTI
RESET
DEFAULT
(Software Mode)
SOFTWARE
(MODE = H)
HARDWARE
(MODE = L)
FUNCTION
MUTE
15
Soft Mute Control: H = Mute Off, L = Mute On
Input Data Format Controls
Input Data Format Selection
Input Word Length Selection
Output Word Length Selection
LRCIN Polarity Selection
Digital De-Emphasis
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
X
Standard Format
I2S
IW0
IW1
3
4
5
16 Bits
I2S
L
L
L
L
IW1 IW0
INPUT FORMAT
16 Bits
L
L
H
H
L
L
H
L
H
L
16-Bit, Standard, MSB-First, Right-Justified
20-Bit, Standard, MSB-First, Right-Justified
24-Bit, Standard, MSB-First, Right-Justified
24-Bit, MSB-First, Left-Justified
16-Bit, I2S
Left/Right = High/Low
OFF
Over Sample Ratio Control
Soft Mute
8x
OFF
H
H
L
H
24-Bit, I2S
Digital Attenuation
0dB, Independent L/R
SRO
27
Digital Filter Roll-Off: H = Slow, L = Sharp
Output Data Word Length Controls
Sample Rate for
De-Emphasis Function
OW0
OW1
19
20
O
O
O
O
O
O
44.1 kHz
OW1 OW0
OUTPUT FORMAT
16-Bit, MSB-First
18-Bit, MSB-First
20-Bit, MSB-First
24-Bit, MSB-First
Filter Roll-Off Selection
Sharp Roll-Off Selected
Same As XTI Input
L
L
H
H
L
H
L
CLKO Output-Frequency Selection
Legend:
O = User Programmable, X = Not Available.
H
SF0
SF1
17
18
Sample Rate Selection for the Digital De-Emphasis Control
TABLE III. User-Programmable Functions for Software and
Hardware Mode.
SF1
L
SF0
L
SAMPLING RATE
44.1kHz
L
H
H
L
Reserved, Not Used
48kHz
Hardware Mode Controls
H
H
32kHz
With MODE = L, the DF1706 may be configured by
utilizing several user-programmable pins. The following is a
brief summary of the pin functions. Table IV provides more
details on setting the hardware mode controls.
Pins I2S, IW0, and IW1 are used to select the audio data
input format and word length.
DEM
x4
16
21
Digital De-Emphasis: H = On, L = Off
Oversampling Rate Control: H = 4fS, L = 8fS
TABLE IV. Hardware Mode Controls.
Finally, the RESV pin is not used by the current DF1706
design, but is reserved for future use.
Pins OW0 and OW1 are used to select the output data word
length.
Software Mode Controls
The DEM pin is used to enable and disable the digital de-
emphasis function. De-emphasis is only available for 32kHz,
44.1kHz, and 48kHz sample rates.
With MODE = H, the DF1706 may be configured by
programming four internal registers in software mode. ML
(pin 13), MC (pin 12), and MD (pin 11) make up the 3-wire
software control port, and may be controlled using DSP or
microcontroller general purpose I/O pins, or a serial port.
Table V provides an overview of the internal registers,
labeled MODE0 through MODE3 (see Table V).
Pins SF0 and SF1 are used to select the sample rate for the
de-emphasis function.
The SRO pin is used to select the digital filter response,
either sharp or slow roll-off. Generally, sharp roll-off filter
is used.
See Figures 8 through 10 for more details regarding the
control port data format and timing requirements. The data
format for the control port is 16-bit, MSB-first, with Bit B15
being the MSB.
The MUTE pin is used to enable or disable the soft mute
function.
The CKO pin is used to select the clock frequency seen at
the CLKO pin, either XTI or XTI ÷ 2.
Register Addressing
A[1:0], bits B10 and B9 of the 16-bit control data word, are
used to indicate the register address to be written to by the
current control port write cycle. See Table VI for how to
address the internal registers using bits A[1:0] of registers
MODE0 through MODE3.
The LRIP pin is used to select the polarity used for the audio
input left/right clock, LRCIN.
The x4 pin is used to control the over sampling ratio of the
internal digital filter, either a 8x or 4x. For instance, when fs
is 192kHz or 176.4kHz, the over sampling ratio should be 4x.
DF1706
SBAS182
10
B15
res
B14
res
B13
res
B12
res
B11
res
B10
A1
B9
A0
B8
B7
B6
B5
B4
B3
B2
B1
B0
MODE0
MODE1
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
A1
A1
A1
A0
A0
A0
LDR
res
AR7
res
AR6
OW1
SF0
AR5
OW0
CKO
AR4
IW1
res
AR3
IW0
AR2
x4
AR1
AR0
MODE2
MODE3
DEM MUT
LRP
I2S
res
SF1
SRO
ATC
FIGURE 8. Internal Mode Control Registers.
ML
MC
MD
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 9. Software Interface Format.
tMLL
tMHH
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Hold Time
tMCY
tMCL
tMCH
tMDH
tMDS
tMLL
tMHH
tMLH
tMLS
100ns (min)
40ns (min)
40ns (min)
10ns (min)
10ns (min)
40ns
ML(1)
0.5VDD
0.5VDD
tMLH
tMLS
tMCH
tMCL
MD Set-Up Time
MC(2)
ML LOW Level Time
ML HIGH Level Time
ML Hold Time(1)
40ns
tMCY
20ns (min)
20ns (min)
ML Set-Up Time(2)
LSB
MD
0.5VDD
NOTES: (1) ML rising edge to the next MC rising edge.
(2) MC rising edge for LSB to ML rising edge.
tMDS
tMDH
FIGURE 10. Software Interface Timing Requirements.
A1
A0
REGISTER SELECTED
REGISTER
NAME
BIT
NAME
DESCRIPTION
0
0
1
1
0
1
0
1
MODE0
MODE1
MODE2
MODE3
MODE0
MODE1
MODE2
AL[7:0]
LDL
A[1:0]
res
Attenuation Data for the Left Channel
Attenuation Load Control for the Left Channel
Register Address
Reserved
AR[7:0]
LDL
A[1:0]
res
Attenuation Data for the Right Channel
Attenuation Load Control for the Right Channel
Register Address
TABLE VI. Internal Register Addressing.
Reserved
MUT
DEM
x4
IW[1:0]
OW[1:0]
A[1:0]
res
Soft Mute Control
Digital De-Emphasis Control
Oversampling Rate Control
Input Data Format and Word Length
Output Data Word Length
Register Address
Reserved
MODE3
I2S
LRP
Input Data Format (I2S or Standard/Left-Justified)
LRCIN Polarity
ATC
Attenuator Control, Dependent or Independent
Digital Filter Roll-Off Selection (sharp or slow)
CLKO Frequency Selection (XTI or XTI ÷ 2)
Sample Rate Selection for De-Emphasis Function
Register Address
SRO
CKO
SF[1:0]
A[1:0]
res
Reserved
NOTE: All reserved bits should be programmed to 0.
TABLE V. Internal Register Mapping.
DF1706
11
SBAS182
MODE0 Register
programmed data in bits AL[7:0] of register
MODE0.
The MODE0 register is used to set the attenuation data for
the left output channel, or DOL (pin 24).
When LDR = 0, the right channel output data
remains at its previously programmed level.
When ATC = 1 (Bit B2 of Register MODE3 = 1), the left
channel attenuation data AL[7:0] is used for both the left
and right channel attenuators.
MODE2 Register
The MODE2 register is used to program various functions:
When ATC = 0, (Bit B2 of Register MODE3 = 0), left
channel attenuation data is taken from AL[7:0] of register
MODE0, and right channel attenuation data is taken from
AR[7:0] of register MODE1.
MUT
Soft Mute Function.
When MUT = 0, Soft Mute is ON for both left
and right channels.
When MUT = 1, Soft Mute is OFF for both left
and right channels.
AL[7:0]
Left Channel Attenuator Data, where AL7 is the
MSB and AL0 is the LSB.
DEM
Digital De-Emphasis Function.
Attenuation Level is given by:
When DEM = 0, de-emphasis is OFF.
When DEM = 1, de-emphasis is ON.
x4 Oversampling Rate Selection
When x4 = 0, 8fS Sampling Rate Operation
When x4 = 1, 4fS Sampling Rate Operation
ATTEN = 0.5 • (DATA – 255)dB
For DATA = FFH, ATTEN = –0dB
For DATA = FEH, ATTEN = –0.5dB
For DATA = 01H, ATTEN = –127.5dB
For DATA = 00H, ATTEN = infinity = Mute
IW[1:0]
Input Data Format and Word Length.
LDL
Left Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenua-
tion levels of both the left and right channels.
I2S IW1
IW0
0
Description
0
0
16-Bit Data, Standard
Format (MSB-First,
Right-Justified)
When LDL = 1, the left channel output level is
set by the data in AL[7:0]. The right channel
output level is set by the data in AL[7:0], or the
most recently programmed data in bits AR[7:0]
of register MODE1.
0
0
0
0
1
1
1
0
1
20-Bit Data, Standard
Format
24-Bit Data, Standard
Format
When LDL = 0, the left channel output data
remains at its previously programmed level.
24-Bit Data, MSB-First,
Left-Justified
MODE1 Register
The MODE1 register is used to set the attenuation data for
the right output channel, or DOR (pin 23).
1
1
1
1
0
0
1
1
0
1
0
1
16-Bit Data, I2S Format
24-Bit Data, I2S format
Reserved
When ATC = 1 (Bit B2 of Register MODE3 = 1), the left
channel attenuation data AL[7:0] of register MODE0 is
used for both the left and right channel attenuators.
Reserved
OW[1:0] Output Data Word Length.
OW1 OW0 Description
When ATC = 0, (Bit B2 of Register MODE3 = 0), left
channel attenuation data is taken from AL[7:0] of register
MODE0, and right channel attenuation data is taken from
AR[7:0] of register MODE1.
0
0
1
1
0
1
0
1
16-Bit Data, MSB-First
18-Bit Data, MSB-First
20-Bit Data, MSB-First
24-Bit Data, MSB-First
AR[7:0] Right Channel Attenuator Data, where AR7 is
the MSB and AR0 is the LSB. Attenuation
Level is given by:
MODE3 Register
The MODE3 register is used to program various functions.
ATTEN = 0.5 • (DATA – 255)dB
For DATA = FFH, ATTEN = –0dB
I2S
Input Data Format.
When I2S = 0, standard or left-justified formats
are enabled.
For DATA = FEH, ATTEN = –0.5dB
For DATA = 01H, ATTEN = –127.5dB
For DATA = 00H, ATTEN = infinity = Mute
When I2S = 1, the I2S formats are enabled.
LDR
Right Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenua-
tion levels of both the left and right channels.
LRP
LRCIN Polarity Selection.
When LRP = 0, left channel is HIGH and right
channel is LOW.
When LDR = 1, the right channel output level
is set by the data in AR[7:0], or by the data in
bits AL[7:0] of register MODE0. The left chan-
nel output level is set to the most recently
When LRP = 1, left channel is LOW and right
channel is HIGH.
DF1706
SBAS182
12
For Figure 11(a), digital signals should be routed from the
DF1706 to the audio D/A converter(s) using short, direct
connections to reduce the amount of radiated high-fre-
quency energy. If necessary, series resistors may be placed
in the clock and data signal paths to reduce or eliminate any
overshoot or undershoot present on these signals. A value of
50Ω to 100Ω is recommended as a starting point, but the
designer should experiment with the resistor values in order
to obtain the best results.
ATC
Attenuator Control.
This bit is used to determine whether the Left
and Right channel attenuators operate with inde-
pendent data, or use common data (the Left
channel data in bits AL[7:0] of register MODE0).
When ATC = 0, the Left and Right channel
attenuator data is independent.
When ATC = 1, the Left and Right channel
attenuators use common data.
Figure 11(b) shows an improved method for high-perfor-
mance, mixed signal board layout. This method adds digital
isolation between the DF1706 and the audio D/A converter(s),
and provides complete isolation between the digital and
analog sections of the board. The ISO150 dual digital
coupler provides excellent isolation, and operates at speeds
up to 80Mbps.
SRO
CKO
Digital Filter Roll-Off Selection.
When SRO = 0, sharp roll-off is selected.
When SRO = 1, slow roll-off is selected.
CLKO Output Frequency Selection.
When CKO = 0, the CLKO frequency is the
same as the clock at the XTI input.
When CKO =1, the CLKO frequency is half of
the XTI input clock frequency.
POWER SUPPLIES AND BYPASSING
The DF1706 requires a single +5V power supply for opera-
tion. The power supply should be bypassed by a 10µF and
0.1µF parallel capacitor combination. The capacitors should
be placed as close as possible to VDD (pin 22). Aluminum
electrolytics or tantalum capacitors can be used for the 10µF
value, while ceramics may be used for the 0.1µF value.
SF[1:0]
Sampling Frequency Selection for the De-Em-
phasis Function.
SF1 SF0
Description
0
0
1
1
0
1
0
1
44.1 kHz
Reserved
48 kHz
32 kHz
BASIC CIRCUIT CONNECTIONS
See Figures 12 and 13 for basic circuit connections of the
DF1706. Figure 12 shows connections for Hardware mode
controls, while Figure 13 shows connections for Software
mode controls. Notice the placement of C1 and C2 in both
figures, as they are physically close to the DF1706.
APPLICATIONS INFORMATION
PCB LAYOUT GUIDELINES
In order to obtain the specified performance from the DF1706
and its associated D/A converters, proper printed circuit
board layout is essential. Figure 11 shows two approaches
for obtaining the best audio performance.
TYPICAL APPLICATIONS
The DF1706 will typically be used in high performance
audio equipment, in conjunction with high performance
audio D/A converters. Figure 14 shows a typical application
circuit example, employing the DF1706, a digital audio
receiver, and two PCM1704 24-bit, 192kHz audio D/A
converter(s).
Figure 11(a) shows a standard, mixed signal layout scheme.
The board is divided into digital and analog sections, each
with its own ground. The ground areas should be put on a
split-plane, separate from the routing and power layers. The
DF1706 and all digital circuitry should be placed over the
digital section, while the audio D/A converter(s) and analog
circuitry should be located over the analog section of the
board. A common connection between the digital and analog
grounds is required and is done at a single point as shown.
DF1706
13
SBAS182
(a) Layout Without Isolation
Common
Ground
Connection
Digital Power
Supplies
Analog Power
Supplies
WCKO
BCKO
DOL
DAC
DOR
DF1706
DAC
Digital Section
Analog Section
Split Ground Plane
(b) Layout With Isolation
Digital Power
Supplies
Analog Power
Supplies
WCKO
BCKO
DOL
ISO150
DAC
DOR
DF1706
DAC
ISO150
Digital Section
Analog Section
= DGND
= AGND
Split Ground Plane
FIGURE 11. PCB Layout Model.
DF1706
SBAS182
14
DF1706
1
2
3
4
5
6
7
8
9
DIN
LRCIN 28
SRO 27
BCKO 26
WCKO 25
DOL 24
DOR 23
VDD 22
BCKIN
I2S
Audio
Data
and
Clock
Source
D/A
Converters
or
Digital
Couplers
IW0
IW1
XTI
22pF
22pF
+3.3V
+
C1
0.1µF
C2
10µF
XTAL
XTO
VSS
x4 21
CLKO
OW1 20
OW0 19
SF1 18
(optional)
10 MODE
11 MD/CKO
12 MC/LRIP
13 ML/RESV
14 RST
SF0 17
DEM 16
MUTE 15
Digital
Logic
7
or
7
Manual
Controls
= DGND
NOTE: Do not allow pins 3-5, 11-20, and 27 to float. These pins should be manually
connected to VDD or DGND (hardwired, switch, jumper) or actively driven by logic.
FIGURE 12. Basic Circuit Connections, Hardware Control.
DF1706
Audio
Data
and
Clock
Source
1
2
3
4
5
6
7
8
9
DIN
LRCIN 28
SRO 27
BCKO 26
WCKO 25
DOL 24
DOR 23
VDD 22
BCKIN
I2S
D/A
Converters
or
Digital
Couplers
IWO
IW1
XTI
22pF
22pF
XTAL
XTO
VSS
+5V
+
C1
0.1µF
C2
10µF
x4 21
CLKO
OW1 20
OW0 19
SF1 18
(optional)
10 MODE
11 MD
12 MC
13 ML
+3.3V
Controller
or
Logic
SF0 17
DEM 16
MUTE 15
14 RST
= DGND
FIGURE 13. Basic Circuit Connection, Software Control.
DF1706
15
SBAS182
DIGITAL
SECTION
ANALOG
SECTION
WORD CLOCK
DF1706
Digital
Audio
Input
Digital
Audio
Receiver
DATA
PCM1704
1
2
3
4
5
6
7
8
9
DIN
LRCIN 28
SRO 27
BCKO 26
WCKO 25
DOL 24
DOR 23
VDD 22
BCLK
WCLK
DATA
BIT CLOCK
SYSTEM CLOCK
Left
Channel
Out
BCKIN
I2S
D/A
Converter
Post
Filter
I/V
IWO
IW1
XTI
XTO
VSS
x4 21
CLKO
OW1 20
OW0 19
SF1 18
PCM1704
10 MODE
11 MD
12 MC
13 ML
+3.3V
BCLK
WCLK
DATA
Micro
Controller
or
Right
Channel
Out
D/A
Converter
Post
Filter
Host
Interface
I/V
SF0 17
Logic
DEM 16
MUTE 15
14 RST
System
Reset
+
+5V
10µF
0.1µF
= DGND
+5V
FIGURE 14. DF1706 Typical Application Circuit.
DF1706
SBAS182
16
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
DF1706E
ACTIVE
ACTIVE
SSOP
SSOP
DB
DB
28
28
47
DF1706E/2K
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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