DIR9001IPWRQ1G4 [TI]
96-kHz, 24-Bit Digital Audio Interface Receiver; 96千赫， 24位数字音频接口接收器
| 型号： | DIR9001IPWRQ1G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 96-kHz, 24-Bit Digital Audio Interface Receiver |
| 文件： | 总35页 (文件大小：787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DIR9001-Q1
SLLS843A–JUNE 2007–REVISED FEBRUARY 2008
96-kHz, 24-Bit Digital Audio Interface Receiver
1
FEATURES
APPLICATIONS
•
•
Car Audio Head Units
Car Audio External Amplifiers
23
•
One-Chip Digital Audio Interface Receiver
(DIR) Including Low-Jitter Clock-Recovery
System
DESCRIPTION
•
Compliant With Digital Audio Interface
Standards: IEC60958 (former IEC958), JEITA
CPR-1205 (former EIAJ CP-1201, CP-340),
AES3, EBU tech3250
The DIR9001-Q1 is a digital audio interface receiver
that can receive a 28-kHz to 108-kHz sampling-
frequency, 24-bit-data-word, biphase-encoded signal.
The DIR9001-Q1 complies with IEC60958-3, JEITA
CPR-1205 (Revised version of EIAJ CP-1201), AES3,
EBUtech3250, and it can be used in various
applications that require a digital audio interface.
•
•
Clock Recovery and Data Decode From
Biphase Input Signal, Generally Called S/PDIF,
EIAJ CP-1201, IEC60958, AES/EBU
Biphase Input Signal Sampling Frequency (fS)
Range: 28 kHz to 108 kHz
The DIR9001-Q1 supports many output system clock
and output data formats and can be used flexibly in
many application systems. As the all functions which
the DIR9001-Q1 provides can be controlled directly
through control pins, it can be used easily in an
•
•
•
Low-Jitter Recovered System Clock: 50 ps
Jitter Tolerance Compliant With IEC60958-3
Selectable Recovered System Clock: 128 fS,
256 fS, 384 fS, 512 fS
Serial Audio Data Output Formats: 24-Bit I2S;
MSB-First, 24-Bit Left-Justified; MSB-First 16-,
24-Bit Right-Justified
application system that does not have
a
microcontroller. Also, as dedicated pins are provided
for the channel-status bit and user-data bit,
processing of their information can be easily
accomplished by connecting with a microcontroller,
DSP, etc.
•
•
User Data, Channel-Status Data Outputs
Synchronized With Decoded Serial Audio Data
The DIR9001-Q1 does not require an external clock
source or resonator for decode operation if the
internal actual-sampling-frequency calculator is not
used. Therefore, it is possible to reduce the cost of a
system.
•
•
No External Clock Required for Decode
Includes Actual Sampling Frequency
Calculator (Needs External 24.576-MHz Clock)
•
•
Function Control: Parallel (Hardware)
The operating temperature range of the DIR9001-Q1
is specified as –40°C to 85°C, which makes it
suitable for automotive applications.
Functions Similar and Pin Assignments
Equivalent to Those of DIR1703
•
•
Single Power Supply: 3.3 V (2.7 V to 3.6 V)
Wide Operating Temperature Range: –40°C to
85°C
•
•
5 V-Tolerant Digital Inputs
Package: 28-pin TSSOP, Pin Pitch: 0,65 mm
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SpAct is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
DIR9001-Q1
www.ti.com
SLLS843A–JUNE 2007–REVISED FEBRUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
VCC
Supply voltage
–0.3 to 4
V
VDD
VCC to VDD
AGND to DGND
Supply voltage differences
Ground voltage differences
±0.1
V
V
±0.1
–0.3 to 6.5
–0.3 to (VDD + 0.3) < 4
–0.3 to (VCC + 0.3) < 4
–0.3 to (VCC + 0.3) < 4
±10
Digital input
Digital output
XTI, XTO
FILT
Digital input voltage
Analog input voltage
V
V
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
mA
°C
–40 to 125
–55 to 150
150
°C
Junction temperature
°C
Lead temperature (soldering)
Package temperature (reflow, peak)
260
°C, 5 s
°C
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
3.3
MAX
3.6
UNIT
VDC
VDC
MHz
MHz
pF
VCC
VDD
Analog supply voltage
Digital supply voltage
2.7
3.3
3.6
XTI is connected to clock source
XTI is connected to DGND
24.576
Digital input clock frequency
Not required
Digital output load capacitance, except SCKO
Digital output load capacitance (SCKO)
Operating free-air temperature
20
10
85
pF
TA
–40
°C
2
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SLLS843A–JUNE 2007–REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.7 VDD
2
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT CHARACTERISTICS
VIH
VDD
0.3 VDD
5.5
Input logic level(1)
VIL
VDC
VDC
VDC
µA
VIH
Input logic level(2)
VIL
0.8
VOH
IO = 4 mA
IO = –4 mA
VIN = VDD
VIN = 0 V
VIN = VDD
VIN = 0 V
VIN = VDD
VIN = 0 V
0.85 VDD
Output logic level(3)
VOL
0.15 VDD
100
IIH
65
Input leakage current(4)
IIL
–10
–10
10
IIH
10
Input leakage current(5)
IIL
µA
–100
–10
–65
IIH
10
10
Input leakage current(6)
IIL
µA
–10
BIPHASE SIGNAL INPUT AND PLL
Input sampling frequency range
Jitter tolerance — (IEC60958-3)
28
108
100
kHz
ms
Bit
IEC60958-3 (2003-01)
Compliant
From biphase signal detection to error-out
release (ERROR = L)
PLL lock-up time
RECOVERED CLOCK AND DATA
Serial audio data width
16
3.584
7.168
10.752
14.336
1.792
28
24
13.824
27.648
41.472
55.296
6.912
128 fS
256 fS
384 fS
512 fS
64 fS
fS
SCKO frequency
MHz
BCKO frequency
LRCKO frequency
MHz
kHz
108
fS = 48 kHz, SCKO = 256 fS, measured
periodic
SCKO jitter
50
100 ps rms
55%
SCKO duty cycle
45%
XTI SOURCE CLOCK
XTI is connected to clock source
XTI is connected to DGND
24.576
XTI source clock frequency
MHz
Not required
Frequency accuracy
XTI is connected to clock source
XTI is connected to clock source
–100
45%
100
ppm
XTI input-clock duty cycle
55%
POWER SUPPLY AND SUPPLY CURRENT
VCC
2.7
2.7
3.3
3.3
6
3.6
3.6
8.3
Operation voltage range
VDD
VDC
mA
fS = 96 kHz, PLL locked, XTI connected
to DGND
ICC
Supply current(7)
fS = 96 kHz, PLL locked, XTI connected
to 24.576-MHz resonator
6
8.3
mA
RXIN = H or L, XTI = L, RST = L
130
µA
(1) CMOS compatible input: XTI (not 5-V tolerant)
(2) 5-V tolerant TTL inputs: RXIN, FMT0, FMT1, PSCK0, PSCK1, CKSEL, RST, RSV
(3) CMOS outputs: XTO, SCKO, BCKO, LRCKO, DOUT, UOUT, COUT, BFRAME, ERROR, CLKST, AUDIO, EMPH, FSOUT0, FSOUT1
(4) Internal pulldowns: FMT0, FMT1, PSCK0, PSCK1, CKSEL, RSV
(5) Internal pullup: RST
(6) No internal pullup and pulldown: RXIN, XTI
(7) No load connected to SCKO, BCKO, LRCKO, DOUT, COUT, VOUT, BFRAME, FSOUT0, FSOUT1, CLKST, ERROR, EMPH, AUDIO
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
8.3
UNIT
mA
fS = 96 kHz, PLL locked, XTI connected
to DGND
6
IDD
Supply current(7)
fS = 96 kHz, PLL locked, XTI connected
to 24.576-MHz resonator
9
12.4
mA
RXIN = H or L, XTI = L, RST = L
72
40
µA
fS = 96 kHz, PLL locked, XTI connected
to DGND
55
68
mW
PD
Power dissipation (7)
fS = 96 kHz, PLL locked, XTI connected
to 24.576-MHz resonator
50
mW
mW
RXIN = H or L, XTI = L, RST = L
28-pin T-SSOP
0.67
TEMPERATURE RANGE
TA
Operation temperature range
Thermal resistance
–40
85
°C
θJA
105
°C/W
PIN ASSIGNMENTS
DIR9001-Q1
(TOP VIEW)
1
2
3
4
5
6
7
8
9
CKSEL 28
ERROR 27
FMT1 26
AUDIO
FSOUT0
FSOUT1
SCKO
VDD
FMT0 25
VCC
24
DGND
XTO
AGND 23
FILT 22
XTI
21
RST
CLKST
RXIN 20
RSV 19
10 LRCKO
11 BCKO
12 DOUT
13 PSCK0
14 PSCK1
BFRAME 18
EMPH 17
UOUT 16
COUT 15
P0043-04
4
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SLLS843A–JUNE 2007–REVISED FEBRUARY 2008
TERMINAL FUNCTIONS
TERMINAL
PULL
UP/DOWN
I/O
REMARKS
DESCRIPTION
NAME
AGND
NO.
23
1
–
Analog ground
AUDIO
BCKO
BFRAME
CKSEL
CLKST
COUT
DGND
DOUT
EMPH
ERROR
FILT
OUT
OUT
OUT
IN
CMOS
CMOS
CMOS
Channel-status data information of non-audio sample word, active-low
Audio data bit clock output
11
18
28
9
Indication of top block of biphase input signal
Pulldown
5-V tolerant TTL Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock(1)
OUT
OUT
–
CMOS
CMOS
Clock change/transition signal output
15
6
Channel-status data serial output synchronized with LRCKO
Digital ground
12
17
27
22
25
26
2
OUT
OUT
OUT
–
CMOS
CMOS
CMOS
16-bit/24-bit decoded serial digital audio data output
Channel-status data information of pre-emphasis (50 µs/15 µs)
Indication of internal PLL or data parity error
External filter connection terminal; must connect recommended filter.
FMT0
IN
Pulldown
Pulldown
5-V tolerant TTL Decoded serial digital audio data output format selection 0 (1)
5-V tolerant TTL Decoded serial digital audio data output format selection 1 (1)
FMT1
IN
FSOUT0
FSOUT1
LRCKO
PSCK0
PSCK1
RST
OUT
OUT
OUT
IN
CMOS
CMOS
CMOS
Actual sampling frequency calculated result output 0
Actual sampling frequency calculated result output 1
Audio data latch enable output
3
10
13
14
21
19
20
4
Pulldown
Pulldown
Pullup
5-V tolerant TTL PLL source SCKO output frequency selection 0 (1)
5-V tolerant TTL PLL source SCKO output frequency selection 1(1)
IN
(2)
IN
5-V tolerant TTL Reset control input, active-low
RSV
IN
Pulldown
Reserved, must be connected to DGND(1)
RXIN
IN
5-V tolerant TTL Biphase digital data input(3)
SCKO
UOUT
VCC
OUT
OUT
–
CMOS
CMOS
System clock output
16
24
5
User data serial output synchronized with LRCKO
Analog power supply, 3.3-V
VDD
–
Digital power supply, 3.3-V
CMOS
Schmitt-trigger
XTI
8
7
IN
Oscillation amplifier input, or external XTI source clock input
Oscillation amplifier output
XTO
OUT
CMOS
(1) TTL Schmitt-trigger input with internal pulldown (51 kΩ typical), 5-V tolerant
(2) TTL Schmitt-trigger input with internal pullup (51 kΩ typical), 5-V tolerant
(3) TTL Schmitt-trigger input, 5-V tolerant.
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BLOCK DIAGRAM
FILT
XTI XTO
OSC
Sampling
Frequency
Calculator
FSOUT0
FSOUT1
SCKO
Clock and Data Recovery
Charge
Pump
Preamble
Detector
RXIN
VCO
Divider
PLL
BCKO
Divider
Clock
Decoder
LRCKO
Biphase
Data Decoder
ERROR
CLKST
ERROR
Detector
Decoder
CKSEL
DOUT
Serial
Audio Data
Formatter
FMT0
FMT1
Audio Data
MUTE Control
Function
Control
PSCK0
PSCK1
RSV
DGND
UOUT
Channel Status
and
User Data
Output
COUT
BFRAME
AUDIO
EMPH
Power Supply
RST
RESET
VDD
DGND
VCC
AGND
6
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SLLS843A–JUNE 2007–REVISED FEBRUARY 2008
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillation amplifier operating with crystal; 1-kHz, 0-dB, sine-wave data; no load
POWER SUPPLY CURRENT
SUPPLY CURRENT
SUPPLY CURRENT
vs
LOCKED SAMPLING FREQUENCY
vs
LOCKED SAMPLING FREQUENCY
20
18
16
14
12
10
8
20
18
16
14
12
10
8
V
= V = 3.3 V
DD
T
= 255C
CC
A
SCKO = 256 f
SCKO = 256 f
S
S
85°C
3.3 V
3.6 V
–40°C
50°C
25°C
–25°C
0°C
2.7 V
3 V
6
6
30
40
50
60
70
80
90
100
30
40
50
60
70
80
90
100
f
S
− Sampling Frequency − kHz
f
S
− Sampling Frequency − kHz
G001
G002
Figure 1.
Figure 2.
RECOVERED SYSTEM CLOCK (SCKO) JITTER
SCKO JITTER
vs
LOCKED SAMPLING FREQUENCY
200
180
160
140
120
100
80
V
= V = 3.3 V
DD
= 255C
CC
T
A
128 f
S
256 f
S
384 f
S
512 f
S
60
40
20
30
40
50
60
70
80
90
100
f
S
− Sampling Frequency − kHz
G003
Figure 3.
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DEVICE INFORMATION
ACCEPTABLE BIPHASE INPUT SIGNAL AND BIPHASE INPUT PIN (RXIN)
The DIR9001-Q1 can decode the biphase signal format which is specified in one of the following standards.
Generally, these following standards may be called Sony/Philips digital interface format (S/PDIF) or AES/EBU.
•
•
•
•
IEC60958 (revised edition of former IEC958)
JEITA CPR-1205 (revised edition of former EIAJ CP-1201, CP-340)
AES3
EBU tech3250
The sampling frequency range and data word length which DIR9001-Q1 can decode is as follows:
•
•
Sampling frequency range is 28 kHz to 108 kHz.
Maximum audio sample word length is 24-bit.
Note of others about the biphase input signal.
•
The capture ratio of the built-in PLL complies with level III of sampling frequency accuracy (12.5%), which is
specified in IEC60958-3.
•
•
The jitter tolerance of the DIR9001-Q1 complies with IEC60958-3.
The PLL may also lock in outside of the specified sampling-frequency range, but extended range is not
assured.
Notice about the signal level and transmission line of the biphase input signal.
•
•
•
•
The signal level and the transmission line (optical, differential, single-ended) are different in each standard.
The biphase input signal is connected to the RXIN pin of the DIR9001-Q1.
The RXIN pin has a 5-V tolerant TTL-level input.
An optical receiver module (optical to electric converter) such as TOSLINK, which is generally used in
consumer applications, is connected directly to the RXIN pin without added external components.
•
The output waveform of the optical receiver module varies depending on the characteristics of each product
type, so a dumping resistor or buffer amplifier might be required between the optical receiver module output
and the DIR9001-Q1 input. Careful handling is required if the optical receiver module and the DIR9001-Q1
are separated by a long distance.
•
•
The DIR9001-Q1 needs an external amplifier if it is connected to a coaxial transmission line.
The DIR9001-Q1 needs an external differential to single-ended converter, attenuator, etc., for general
consumer applications if non-optical transmission line is used.
8
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SYSTEM RESET
The DIR9001-Q1 reset function is controlled by and external reset pin, RST.
The reset operation must be performed during the power-up sequence as shown in Figure 4. Specifically, the
DIR9001-Q1 requires reset operation with a 100-ns period after the supply voltage rises above 2.7 V.
2.7 V
VDD
RST
DIR9001-Q1
Status
Reset
Operation
Unknown
Min. 100 ns
T0260-01
Figure 4. Required System Reset Timing
The state of each output pins during reset is shown in Table 1.
Table 1. Output-Pin States During Reset Period
CLASSIFICATION
PIN NAME
BCKO
WHILE RST = L
L
Clock
Data
LRCKO
SCKO
L
L
DOUT
L
AUDIO
BFRAME
CLKST
COUT
L
L
L
L
Flag and status
EMPH
L
ERROR
FSOUT0
FSOUT1
UOUT
H
L
L
L
Oscillation amplifier
XTO
Output
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OPERATION MODE AND CLOCK TRANSITION SIGNAL OUT
Operation Mode
The DIR9001-Q1 has the following three operation modes.
These modes are selected by the connection of the CKSEL pin.
•
•
•
PLL MODE: For demodulating a biphase input signal; always outputs PLL source clock
XTI MODE: For clock generator; always outputs XTI source clock
AUTO MODE: Automatic clock source selection; output source depends on ERROR pin.
Notes about operation mode selection:
•
•
Normally, the PLL mode: CKSEL = L is selected to decode a biphase input signal.
The XTI mode is a mode that supplies the XTI source clock to peripheral devices (A/D converters, etc);
therefore, recovered clock and decoded data is not output.
•
•
When the XTI source is not used, an XTI source is not required. In this case, clocks are not output in the XTI
mode.
At the time of XTI mode selection, biphase decode function continues to operate. Therefore, the biphase input
status (ERROR) and the result of the sampling frequency calculator (a required XTI source for operation), are
always monitored. That is, the following output pins: ERROR, BFRAME, FSOUT[1:0], CLKST, AUDIO and
EMPH are always enabled.
The details of these three modes are given in Table 2.
Table 2. Operation Mode and Clock Source
OPERATION
MODE
CKSEL PIN
SETTING
ERROR
PIN
STATUS
DOUT DATA
AUDIO
EMPH
FSOUT
[1:0]
BFRAME
COUT
UOUT
SCKO, BCKO, LRCKO
CLOCK SOURCE
H
PLL (VCO) free-running
clock(1)
MUTE (Low)
LOW
HL
LOW
LOW
PLL
L
L
H
L
PLL recovered clock
XTI clock
Decoded data
MUTE (Low)
MUTE (Low)
MUTE (Low)
Decoded data
OUT
LOW
OUT
LOW
OUT
OUT
HL
OUT
LOW
OUT
LOW
OUT
OUT
LOW
LOW
LOW
OUT
XTI
H
XTI clock
OUT
HL
H
L
XTI clock
Connected to
ERROR pin
AUTO
PLL recovered clock
OUT
(1) The VCO free-running frequency is not a constant frequency, because the VCO oscillation frequency is dependent on supply voltage,
temperature, and process variations.
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FILT
XTI XTO
OSC
Sampling
Frequency
Calculator
FSOUT0
FSOUT1
Clock and Data Recovery
SCKO
Charge
Pump
Preamble
Detector
RXIN
VCO
Divider
PLL
BCKO
Divider
Clock
Decoder
LRCKO
Biphase
Data Decoder
ERROR
CLKST
ERROR
Detector
Decoder
CKSEL
DOUT
Serial
Audio Data
Formatter
Audio Data
MUTE Control
DGND
Figure 5. Clock Source, Source Selector, and Data Path
Clock Transition Signal Out
The DIR9001-Q1 provides an output pulse that is synchronized with the PLL’s LOCK/UNLOCK status change.
The CLKST pin outputs the PLL status change between LOCK and UNLOCK. The CLKST output pulse depends
only on the status change of the PLL.
This clock change/transition signal is output through CLKST.
As this signal indicates a clock transition period due to a PLL status change, it can be used for muting or other
appropriate functions in an application.
A clock source selection caused by the CLKSEL pin does not affect the output of CLKST.
CLKST does change due to PLL status change even if CKSEL = H in the XTI source mode.
When DIR9001-Q1 is reset in the state where it is locked to the biphase input signal, the pulse signal of CLKST
is not output. That is, the priority of reset is higher than CLKST.
The relation among the lock-in/unlock process, the CLKST and ERROR outputs, the output clocks (SCKO,
BCKO, LRCKO), and data (DOUT) is shown in Figure 6.
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DIR9001-Q1 Status
RXIN
Non-Biphase
Unlock
Biphase
Non-Biphase
Unlock
Built-In PLL
Status
Lock
CLKST
tCLKST
tCLKST
ERROR
Lock Up Time
PLL Mode [CKSEL = Low]
XTO
XTI Source
SCKO, BCKO,
LRCKO
PLL Source
(Free-Run)
PLL Source
(Transition)
PLL Source
(Lock Frequency)
PLL Source
(Transition)
PLL Source
(Free-Run)
MUTE (Low)
MUTE (Low)
DOUT
Demodulated Data
XTI Mode [CKSEL = High]
XTO
XTI Source
SCKO, BCKO,
LRCKO
XTI Source
Always MUTE (Low)
DOUT
AUTO Mode [CKSEL = ERROR]
XTO
XTI Source
SCKO, BCKO,
LRCKO
XTI Source
PLL Source
XTI Source
MUTE (Low)
MUTE (Low)
DOUT
Demodulated Data
Note:
means clock source change.
T0261-01
PARAMETERS
CLKST pulse duration, high
MIN
TYP
MAX
UNIT
µs
tCLKST
4
20
Figure 6. Lock-In and Unlock Process
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CLOCK DESCRIPTION
System Clock Source
DIR9001-Q1 has the following two clock sources for the system clock.
•
•
PLL source (128 fS, 256 fS, 384 fS, 512 fS are available, recovered by built-in PLL)
XTI source (One 24.576-MHz resonator or external clock source is required.)
Two clock sources are used for the following purpose.
•
•
PLL source: Recovered system clock from the biphase input signal
XTI source: Clock source for peripheral devices (for example, A/D converter, microcontroller, etc.)
Measurement reference clock for the internal actual-sampling-frequency calculator
Description of PLL clock source
•
•
•
The PLL clock source is the output clock of built-in PLL (including VCO).
The PLL clock source frequency is selectable from 128 fS, 256 fS, 384 fS, 512 fS by PSCK[1:0].
When the PLL is in the locked condition, the PLL clock source is the clock recovered from the biphase input
signal.
•
•
When PLL is in the unlocked condition, the PLL clock source is the built-in free-running clock of the VCO.
The frequency of the PLL clock source in the unlocked condition is not constant.
(The VCO free-running frequency is dependent on supply voltage, temperature, and variations in the die’s
wafer.)
Description of XTI clock source
•
•
The XTI clock source is not used to recover the clock and decode data from the biphase input signal.
Therefore, if the DIR9001-Q1 is used only for recovering the clock and decoding data from the biphase input
signal, an XTI clock source is not required. In this case, the XTI pin must be connected to the DGND pin.
(The DIR9001-Q1 does not have a selection pin for using an XTI clock source or not using one.)
The selection method of clock source
•
•
•
•
•
The output clock is selected from two clock sources by the level of the CKSEL pin.
The selection of the system clock source depends only on the input level of CKSEL pin.
CKSEL = L setting is required for recovering the clock and decoding data from biphase input.
CKSEL = H setting is required for XTI clock source output.
The continuity of clock during the clock source transition between the XTI source and the PLL source is not
assured.
Method of automatic clock source selection (CLOCK SOURCE MODE: AUTO)
•
This method enables selection of the clock source automatically, using the DIR9001-Q1 ERROR status. The
PLL source clock is output when ERROR = L; the XTI source is output when ERROR = H.
•
•
•
To enable automatic clock source selection, the CKSEL pin must be connected to the ERROR pin.
If XTI clock source is needed during the ERROR period, this method is recommended.
Because the clock source during ERROR status is XTI, if an XTI clock source is not provided to the XTI pin,
then SCKO, BCKO, and LRCKO are not output during the ERROR period.
The relationship between the clock/data source and the combination of CKSEL pin and PLL status inputs is
shown in Table 2.
The clock tree system is shown in Figure 7.
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[PSCK1]
[PSCK0]
1/N
1/N
1/N
VCO
RXIN
CKSEL (I)
Built-in PLL
Clock Recovery
SCKO (O)
BCKO (O)
PLL Clock Source
XTI (I)
LRCKO (O)
1/4
XTO (O)
Oscillation Amplifier
Clock Source
Selector
1/64
XTI Clock Source
Figure 7. Clock Tree Diagram
PLL Clock Source (Built-In PLL and VCO) Description
The DIR9001-Q1 has on-chip PLL (including VCO) for recovering the clock from the biphase input signal.
The clock that is output from the built-in VCO is defined as the PLL clock source.
In the locked state, the built-in PLL generates a system clock that synchronizes with the biphase input signal.
In the unlocked state, the built-in PLL (VCO) generates a free-running clock. (The frequency is not constant.)
The PLL can support a system clock of 128 fS, 256 fS, 384 fS, or 512 fS, where fS is the sampling frequency of the
biphase input signal.
The system clock frequency of the PLL is selected by PSCK[1:0].
The DIR9001-Q1 can decode a biphase input signal through its 28 sampling-frequency range of kHz to 108 kHz,
independent of the setting of PSCK[1:0].
Therefore, the DIR9001-Q1 can decode a biphase input signal with a sampling frequency from 28 kHz to 108
kHz at all settings of PSCK[1:0]
The relationship between the PSCK[1:0] selection and the output clock (SCKO, BCKO, LRCKO) from the PLL
source is shown in Table 3.
Table 3. SCKO, BCKO, and LRCKO Frequencies Set by PSCK[1:0]
PSCK[1:0] SETTING
OUTPUT CLOCK FROM PLL SOURCE
PSCK1
PSCK0
SCKO
BCKO
64 fS
64 fS
64 fS
64 fS
LRCKO
L
L
L
H
L
128 fS
256 fS
384 fS
512 fS
fS
fS
fS
fS
H
H
H
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In PLL mode (CKSEL = L), output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock.
The relationship between frequencies of LRCKO, BCKO, and SCKO at different sampling frequencies fS of the
biphase input signal are shown in Table 4.
Table 4. Output Clock Frequency in PLL Locked State (CKSEL = L)
LRCKO
fS
BCKO
64 fS
SCKO (Depending on PSCK[1:0] Setting)
128 fS
256 fS
384 fS
512 fS
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
2.048 MHz
2.8224 MHz
3.072 MHz
5.6448 MHz
6.144 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
11.2896 MHz
12.288 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
22.5792 MHz
24.576 MHz
12.288 MHz
16.9344 MHz
18.432 MHz
33.8688 MHz
36.864 MHz
16.384 MHz
22.5792 MHz
24.576 MHz
45.1584 MHz
49.152 MHz
Required PLL Loop Filter Description
The DIR9001-Q1 incorporates a PLL for generating a clock synchronized with the biphase input signal.
The built-in PLL requires an external loop filter, which is specified as follows.
Operation and performance is assured for recommended filter components R1, C1, and C2.
Notes about Loop Filter Components and Layout
•
The resistor and capacitors which comprise the filter should be located and routed as close as possible to the
DIR9001-Q1.
•
•
•
A carbon film resistor or metal film resistor, with tolerance less than 5%, is recommended.
Film capacitors, with tolerance is less than 5%, is recommended.
If ceramic capacitors are used for C1 and C2, parts with a low voltage coefficient and low temperature
coefficient, such as CH or C0G, are recommended.
•
•
The external loop filter must be placed on FILT pins.
The GND node of the external loop filter must be directly connected with the AGND pin of the DIR9001-Q1; it
must be not combined with other signals.
The configuration of external loop filter and the connection with the DIR9001-Q1 is shown in Figure 8.
DIR9001-Q1
PLL Section
Charge
VCO
Pump
FILT
R1
AGND DGND
C2
C1
B0240-01
Figure 8. Loop Filter Connection
The recommended values of loop filter components is shown in Table 5.
Table 5. Recommended Value of Loop Filter Components
REF. NO.
RECOMMENDED VALUE
680 Ω
PARTS TYPE
TOLERANCE
≤5%
R1
C1
C2
Metal film or carbon
0.068 µF
Film or ceramic (CH or C0G)
Film or ceramic (CH or C0G)
≤5%
0.0047 µF
≤5%
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XTI Clock Source and Oscillation Amplifier Description
This clock, driven by the built-in oscillation amplifier or input into the XTI pin from an external clock, is defined as
the XTI source. A 24.576-MHz fundamental resonator or external 24.576-MHz clock is used as the XTI source.
The DIR9001-Q1 requires an XTI source for following purposes:
•
•
The measurement reference clock of actual-sampling-frequency calculator
The clock source for the XTI source mode (CKSEL = H setting)
(That is, the DIR9001-Q1 does not require an XTI source if it is only decoding the biphase input signal.)
The XTI clock source is supplied in one of the following two ways; the details are described in Figure 9.
•
•
Setting up an oscillation circuit by connecting a resonator with the built-in amplifier
Applying a clock from an external oscillator circuit or oscillator module
To set up an oscillation circuit by connecting a resonator with the built-in amplifier:
•
•
•
•
Connect a 24.576-MHz resonator between the XTI pin and XTO pin.
The resonator should be a fundamental-mode type.
A crystal resonator or ceramic resonator can be used.
The load capacitor CL1, CL2, and the current-limiting resistor Rd depend on the characteristics of the
resonator.
•
•
No external feedback resistor between the XTI pin and XTO pin is required, as an appropriate resistor is
incorporated in the device.
No load other than the resonator is allowed on the XTO pin.
To connect an external oscillator circuit or oscillator module:
•
•
•
Provide a 24.576-MHz clock on the XTI pin
Note that the XTI pin is not 5-V tolerant; it is simple CMOS input.
The XTO pin must be open.
Crystal
OSC
Circuit
Crystal
OSC
Circuit
24.576-MHz
Internal Clock
24.576-MHz
Internal Clock
Resonator
XTI
XTI
External
Clock
CL1
Rd
Must Be
Open
XTO
XTO
CL2
DIR9001-Q1
Resonator Connection
DIR9001-Q1
External Clock Input Connection
B0241-01
Figure 9. XTI and XTO Connection Diagram
Description of oscillation amplifier operation:
•
•
•
The built-in oscillation amplifier is always working.
If the XTI source clock is not used, then the XTI pin must be connected to DGND.
For reducing power dissipation, it is recommended to not use the XTI source clock.
In XTI mode (CKSEL = H), output clocks (SCKO, BCKO, LRCKO) are generated from XTI source clock.
The relation between output clock frequency (SCKO, BCKO, LRCKO) and the XSCK pin setting in XTI source
mode is shown in Table 6.
Table 6. SCKO, BCKO, LRCKO Output Frequency at XTI Mode
XTI FREQUENCY
OUTPUT CLOCK FREQUENCY IN XTI SOURCE MODE (CKSEL = H)
SCKO
BCKO
LRCKO
24.576 MHz
24.576 MHz
6.144 MHz
96 kHz
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DATA DESCRIPTION
Decoded Serial Audio Data Output and Interface Format
The DIR9001-Q1 supports following 4-data formats for the decoded data.
•
•
•
•
16-bit, MSB-first, right-justified
24-bit, MSB-first, right-justified
24-bit, MSB-first, left-justified
24-bit, MSB-first, I2S
Decoded data is MSB first and 2s-complement in all formats.
The decoded data is provided through the DOUT pin.
The format of the decoded data is selected by the FMT[1:0] pins.
The data formats for each FMT[1:0] pin setting are shown in Table 7.
Table 7. Serial Audio Data Output Format Set by FMT[1:0]
FMT[1:0] SETTINGS
DOUT SERIAL AUDIO DATA OUTPUT FORMAT
FMT1
FMT0
L
L
L
H
L
16-bit, MSB-first, right-justified
24-bit, MSB-first, right-justified
24-bit MSB-first, left-justified
24-bit, MSB-first, I2S
H
H
H
Biphase Signal (IN)
BFRAME (OUT)
B
0L
1L
W
0R
M
W
1R
tLATE
LRCKO (OUT)
(I2S)
LRCKO (OUT)
(Except I2S)
DOUT (OUT)
0L
0R
1L
1R
17 BCK
PARAMETERS
MIN
TYP
3/fS
MAX
UNIT
tLATE
LRCKO/DOUT latency
s
Figure 10. Latency Time Between Biphase Input and LRCKO/DOUT
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The relationships among BCKO, LRCKO, and DOUT for each format are shown in Figure 11.
Right Justified (MSB First, 24-bit, 16-bit)
1/fS
L-channel
R-channel
LRCKO
BCKO
Data Length: 16-bit
DOUT
14
1
2
16
15 16
15
LSB
1
2
15 16
LSB
MSB
MSB
Data Length: 24-bit
DOUT 22 23 24
1
2
23 24
LSB
1
2
23 24
LSB
MSB
MSB
Left Justified (MSB First)
1/fS
L-channel
R-channel
LRCKO
BCKO
Data Length: 24-bit
DOUT
1
2
23 24
1
2
23 24
MSB
LSB
MSB
LSB
I2S Format (MSB First)
1/fS
LRCKO
BCKO
L-channel
R-channel
Data Length: 24-bit
DOUT
1
2
23 24
LSB
1
2
1
23 24
LSB
MSB
MSB
Figure 11. Decoded Serial Audio Data Output Formats
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tSCY
tSCBC
SCKO
(OUT)
VDD/2
LRCKO
(OUT)
VDD/2
tBCH
tBCL
tCKLR
BCKO
(OUT)
VDD/2
tBCY
tBCDO
DOUT
(OUT)
VDD/2
PARAMETERS
System clock pulse cycle time
MIN
18
4
TYP
MAX
UNIT
tSCY
tSCBC
tCKLR
tBCY
tBCH
tBCL
tBCDO
tr
ns
ns
ns
s
Delay time of SCK rising edge to BCK rising edge
Delay time of BCKO falling edge to LRCKO valid
BCKO pulse cycle time
8
15
–5
0.5
0.5
1/64fS
BCKO pulse duration, HIGH
60
60
–5
ns
ns
ns
ns
ns
BCKO pulse duration, LOW
Delay time of BCKO falling edge to DOUT valid
Rising time of all signals
1
5
10
10
tf
Falling time of all signals
NOTE: Load capacitance of the LRCKO, BCKO, and DOUT pins is 20 pF. DOUT, LRCKO, and BCKO are synchronized with
SCKO.
Figure 12. Decoded Audio Data Output Timing
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Channel-Status Data and User Data Serial Outputs
The DIR9001-Q1 can output channel-status data and user data synchronized with audio data from the biphase
input signal.
Each output data has its own dedicated output pin.
•
•
Channel-status data (C, hereinafter) is output through COUT pin.
User data (U, hereinafter) is output through UOUT pin.
The C and U outputs are synchronized with LRCKO recovered from the biphase input signal.
The polarity of LRCKO recovered from the biphase input signal depends on FMT[1:0] setting.
For detecting the top of the block of channel-status data or user data, the BFRAME pin is provided.
The BFRAME pin outputs a high level for an 8-LRCK period if the preamble B is detected in the received biphase
signal.
In processing these data by a microcontroller or register circuit, LRCKO is used as the data input clock, and the
output pulse on the BFRAME pin is used as the top-of-block signal.
The relationship among LRCKO, BFRAME, DOUT, COUT, and UOUT is shown in Figure 13.
When in the XTI mode and the PLL-locked state, COUT and UOUT output L.
Recovered
LRCKO
(I2S)
Recovered
LRCKO
(Except I2S)
17 BCK
BFRAME
DOUT
COUT
UOUT
191R
0L
0R
1L
1R
2L
2R
3L
C191R
C0L
U0L
C0R
U0R
C1L
U1L
C1R
U1R
C2L
U2L
C2R
U2R
U191R
NOTE: The numbers 0 through 191 of DOUT, COUT, and UOUT indicate frame numbers of the biphase input.
Figure 13. LRCKO, DOUT, BFRAME, COUT, UOUT Output Timing
Channel-Status Data Information Output Terminal
The DIR9001-Q1 can output part of the channel-status information (bit 1, bit 3) through two dedicated pins,
AUDIO and EMPH.
The channel-status information which can be output from dedicated pins is limited to information from the
L-channel.
If channel-status information other than AUDIO or EMPH is required, or information from the R-channel, then the
channel-status data on the COUT pin, which is synchronized with biphase input signal, can be used.
These outputs are synchronized with the top of block.
The information that can be output through the dedicated pins is shown as follows.
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AUDIO Pin
This is the output pin for the audio sample word information of the channel-status data bit 1.
Table 8. Audio Sample Word Information
AUDIO
DESCRIPTION
Audio sample word represents linear PCM samples.
Audio sample word is used for other purposes.
L
H
EMPH Pin
This is the output pin for the emphasis information of the channel-status data bit 3.
Table 9. Pre-Emphasis Information
EMPH
DESCRIPTION
Two audio channels without pre-emphasis
Two audio channels with 50 µs / 15 µs pre-emphasis
L
H
LRCKO
(I2S)
LRCKO
(Except I2S)
DOUT
191R
0L
0R
1L
1R
2R
3L
2L
Bit 1 of Previous Block
Bit 3 of Previous Block
AUDIO
EMPH
NOTE: The numbers 0 through 191 of DOUT indicate frame numbers of the biphase input.
Figure 14. AUDIO and EMPH Output Timing
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ERRORS AND ERROR PROCESSING
Error Output Description
Error detection and data error processing for PLL errors
•
PLL responds with unlock for data in which the rule of biphase encoding is lost (biphase error and
frame-length error).
•
PLL responds with unlock for data in which the preamble B, M, W can not be detected.
Error processing function and error output pins
•
•
•
•
The DIR9001-Q1 has a data error detect function and an error output pin, ERROR.
The ERROR pin is defined as the logical OR of data error and parity error detection.
The ERROR rising edge is synchronized with CLKST.
The ERROR falling edge is synchronized with LRCK.
The relationship between data error and detected parity error is shown in Figure 15.
DIR9001-Q1
Data Error
ERROR Output
Detected Parity Error
B0242-01
Figure 15. ERROR Output
The state of the ERROR pin and the details of error are shown in Table 10.
Table 10. State of ERROR Output Pin
ERROR
DESCRIPTION
Lock state of PLL and nondetection of parity error
Unlock state of PLL or detection of parity error
L
H
Parity Error Processing
Error detection and error processing for parity errors
•
•
For PCM data, interpolation processing by previous data is performed.
For non-PCM data, interpolation is not performed and data is directly output with no processing. (Non-PCM
data is data with channel-status data bit 1 = 1.)
The processing for parity error occurrence is shown in Figure 16.
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[AUDIO = L]
Internal LOCK
AUDIO
LRCKO (I2S)
ERROR
DOUT
MUTE (Low)
L
R
L
R
L
R
L
R
n+3
n
n
n+1
n+1
n+1
n+2
n+3
Interpolation Processing
by Previous Data
[AUDIO = H]
Parity Error
Internal LOCK
AUDIO
LRCKO (I2S)
ERROR
DOUT
MUTE (Low)
L
R
L
R
L
R
L
R
n+3
n
n
n+1
n+1
n+2
n+2
n+3
Parity Error
Figure 16. Processing for Parity Error Occurrence
Other Error
Error for sampling frequency change: A rapid continuous change or a discontinuous change of the input sampling
frequency causes the PLL to lose lock.
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CALCULATION OF ACTUAL SAMPLING FREQUENCY
The DIR9001-Q1 calculates the actual sampling frequency of the biphase input signal and outputs its result
through dedicated pins.
To use this function, a 24.576-MHz clock source must be supplied to the XTI pin. The 24.576-MHz clock is used
as a measurement reference clock to calculate the actual sampling frequency.
If the XTI pin is connected to DGND, calculation of the actual sampling frequency is not performed.
If there is an error in the XTI clock frequency, the calculation result and range are shifted correspondingly.
This output is the result of calculating the sampling frequency, it is not the sampling frequency information of the
channel-status data (bit 24–bit 27).
The sampling frequency information of the channel-status data (bit 24–bit 27) is not output through these pins.
The calculation result is decoded into 2-bit data, which is output on the FSOUT[1:0] pins.
If the PLL is locked but the sampling frequency is out-of-range, or if the PLL is unlocked, FSOUT[1:0] = HL is
output to indicate an abnormality.
When the XTI source clock is not supplied before power on, FSOUT [1:0] always outputs LL.
When the XTI source clock is stopped, the fS calculator holds the last value of the fS calculator result.
If XTI source clock is supplied, the fS calculator resumes operation.
The calculated value is held until reset.
The relationship between the FSOUT[1:0] outputs and the range of sampling frequencies is shown in Table 11.
Table 11. Calculated Sampling Frequency Output
NOMINAL fS
ACTUAL SAMPLING FREQUENCY
RANGE
CALCULATED SAMPLING FREQUENCY OUTPUT
FSOUT1
FSOUT0
Out of range
32 kHz
Out of range or PLL unlocked
31.2 kHz–32.8 kHz
H
H
L
L
H
L
44.1 kHz
48 kHz
43 kHz–45.2 kHz
46.8 kHz–49.2 kHz
L
H
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TYPICAL CIRCUIT CONNECTION
Figure 17 illustrates typical circuit connection.
For Automatic Clock Source Selection
1
CKSEL 28
ERROR 27
FMT1 26
AUDIO
2
FSOUT0
FSOUT1
SCKO
Actual Sampling
Frequency Output
3
Decoded Data Format
Setting
4
FMT0 25
V
V
3.3-V VCC
+
3.3-V VDD
5
6
7
8
9
24
CC
DD
+
C
C
C
8
6
7
C
5
DGND
XTO
AGND 23
FILT 22
C
C
2
1
R
R
1
2
XTI
Reset (active LOW)
Receiver Circuit
21
RST
X1
C3
CLKST
RXIN 20
RSV 19
C
4
10 LRCKO
11 BCKO
12 DOUT
13 PSCK0
14 PSCK1
BFRAME 18
EMPH 17
UOUT 16
COUT 15
To Microcontroller
System Clock
Frequency Setting
(128, 256,
384, 512 fS)
Audio Data
Processor
NOTES: R1: Loop filter resistor, 680 Ω
R2: Current-limiting resistor; generally, a 100 Ω–500 Ω resistor is used, but it depends on the crystal resonator.
C1: Loop filter capacitor, 0.068 µF.
C2: Loop filter capacitor, 0.0047 µF.
C3, C4: OSC load capacitor; generally, a 10-pF–30-pF capacitor is used, but it depends on the crystal resonator and
PCB layout.
C5, C8: 10-µF electrolytic capacitor typical, depending on power-supply quality and PCB layout.
C6, C7: 0.1-µF ceramic capacitor typical, depending on power-supply quality and PCB layout.
X1: Crystal resonator, use a 24.576-MHz fundamental resonator when XTI clock source is needed.
Figure 17. Typical Circuit Connection Diagram
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DIR9001-Q1
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SLLS843A–JUNE 2007–REVISED FEBRUARY 2008
APPLICATION INFORMATION
Differences From DIR1703
The DIR9001-Q1 has many improved functions compared to the DIR1703.
The DIR9001-Q1 functions are similar to those of the DIR1703.
The DIR9001-Q1 pin assignment is equivalent to that of the DIR1703.
The DIR9001-Q1 biphase input signal decoding function is almost equivalent to that of the DIR1703.
The differences between the DIR9001-Q1 and DIR1703 are shown in Table 12.
Table 12. Main Differences Between DIR1703 and DIR9001-Q1
DIFFERENCE
Operational supply-voltage range
Operation temperature range
Package
DIR1703
DIR9001-Q1
3 V to 3.6 V
2.7 V to 3.6 V
–25°C to 85°C
–40°C to 85°C
SSOP-28P, pin pitch: 0.65 mm
SpAct™ feature
TSSOP-28P, pin pitch: 0.65 mm
Conventional PLL
Clock recovery architecture
IEC60958-3 jitter tolerance
IEC60958 sampling frequency accuracy
Acceptable sampling frequency
Biphase input signal level
Connection of loop filter
Not compliant
Compliant
Level II (±1000 ppm)
32/44.1/48/88.2/96 kHz, 1500 ppm
CMOS level
Level III (±12.5%)
28 kHz to 108 kHz continuous
5-V tolerant TTL level
Between FILT pin and AGND
Between FILT pin and VCC
XTI source clock frequency
One of the following clock sources or
Optional 24.576-MHz (24.576-MHz clock is
only required to use the internal
actual-sampling-frequency calculator or use
the DIR9001-Q1 as a 24.576-MHz clock
generator.)
resonators must be connected to the XTI pin:
4.069/5.6448/6.144/ 8.192/11.2896/12.288/
16.384/16.9344/18.432/ 22.5792/24.576-MHz
BFRAME H period
32/fS
8/fS
Channel status and user data
Latest tracked frequency hold
PLL mode clock at error
Clock transition signal out
Oscillation amplifier
Synchronous with LRCK transition
Available
17-BCK delay from LRCK transition
Not available
Latest tracked frequency
CKTRNS pin, active H
External feedback resistor (typ. 1 MΩ)
VCO free-running frequency
CLKST pin, active-high
Internal feedback resistor
26
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s) :DIR9001-Q1
DIR9001-Q1
www.ti.com
SLLS843A–JUNE 2007–REVISED FEBRUARY 2008
The differences between the DIR1703 and DIR9001-Q1 I/O pins are shown in Table 13.
Table 13. The Differences Between DIR1703 and DIR9001-Q1 in All I/O Pin
PIN NO.
DIR1703
DIR9001-
Q1
DIFFERENCES
DESCRIPTIONS OF DIR9001-Q1
1
ADFLG
BRATE0
BRATE1
SCKO
VDD
AUDIO
FSOUT0
FSOUT1
SCKO
VDD
Pin name only
Pin name only
Pin name only
Same function
Same function
Same function
Same function
Same function
Channel-status data information of non-audio sample word, active-low
Actual-sampling-frequency calculated result output 0
Actual-sampling-frequency calculated result output 1
System clock output
2
3
4
5
Digital power supply, 3.3-V
6
DGND
XTO
DGND
XTO
Digital ground
7
Oscillation amplifier output
8
XTI
XTI
Oscillation amplifier input, or external XTI source clock input
9
CKTRNS
LRCKO
BCKO
DOUT
SCF0
CLKST
LRCKO
BCKO
DOUT
PSCK0
PSCK1
COUT
UOUT
EMPH
BFRAME
RSV
CLKST is active-high Clock change/transition signal output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Same function
Same function
Same function
Pin name only
Pin name only
Pin name only
Pin name only
Pin name only
Same function
Reserved
Audio data latch enable output
Audio data bit clock output
16 bit–24 bit decoded serial digital audio data output
SCKO output frequency selection 0
SCF1
SCKO output frequency selection 1
CSBIT
URBIT
EMFLG
BFRAME
BRSEL
DIN
Channel-status data serial output synchronized with LRCKO
User data serial output synchronized with LRCKO
Channel-status data Information of pre-emphasis (50 µs/15 µs)
Indication of top block of biphase input signal
Reserved, must be connected to DGND
RXIN
Pin name only
Same function
Same function
Same function
Same function
Same function
Same function
Pin name only
Same function
Biphase digital data input
RST
RST
Reset control input, active-low
FILT
FILT
External filter connection terminal. Recommended filter must be connected.
Analog ground
AGND
VCC
AGND
VCC
Analog power supply, 3.3-V
FMT0
FMT0
FMT1
ERROR
CKSEL
Decoded serial digital audio data output format selection 0
Decoded serial digital audio data output format selection 1
Indication of internal PLL or data parity error
Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock
FMT1
UNLOCK
CKSEL
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s) :DIR9001-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DIR9001IPWQ1
DIR9001IPWRQ1
DIR9001IPWRQ1G4
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
PW
PW
PW
28
28
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DIR9001-Q1 :
Catalog: DIR9001
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2010
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DIR9001IPWRQ1
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
DIR9001IPWRQ1
2000
Pack Materials-Page 2
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