DIT4192_15_技术文档

DIT4192

SBOS229B – DECEMBER 2001 – REVISED JUNE 2003

192kHz Digital Audio Transmitter

FEATURES

● COMPLIANT WITH AES-3, IEC-60958, AND EIAJ

APPLICATIONS

● DIGITAL MIXING CONSOLES

CP1201 INTERFACE STANDARDS

● DIGITAL MICROPHONES

● SUPPORTS SAMPLING RATES UP TO 192kHz

● SUPPORTS MONO-MODE OPERATION

● ON-CHIP DIFFERENTIAL LINE DRIVER

● DIGITAL AUDIO WORKSTATIONS

● BROADCAST STUDIO EQUIPMENT

● EFFECTS PROCESSORS

● FLEXIBLE AUDIO SERIAL INTERFACE:

-Master or Slave Mode Operation

-Supports I²S, Left-Justified, and Right-Justified

Data Formats

●

SURROUND-SOUND DECODERS AND ENCODERS

● A/V RECEIVERS

● DVD, CD, DAT, AND MD PLAYERS

● AUDIO TEST EQUIPMENT

● SOFTWARE MODE VIA SERIAL CONTROL

INTERFACE:

-Block Sized Buffer for Channel Status Data

-Auto Increment Mode for Block Sized Write and

Read Operations

DESCRIPTION

The DIT4192 is a digital audio transmitter designed for use

in both professional and consumer audio applications. Trans-

mit data rates up to 192kHz are supported. The DIT4192

supports both software and hardware operation, which makes

it suitable for applications with or without a microcontroller. A

flexible serial audio interface is provided, supporting stan-

dard audio data formats and easy interfacing to audio DSP

serial ports.

● HARDWARE MODE ALLOWS OPERATION

WITHOUT A MICROCONTROLLER

● CRC CODE GENERATION FOR PROFESSIONAL

MODE

● MASTER CLOCK RATE: 128f_S, 256f_S, 384f_S, or 512f_S

● +5V CORE SUPPLY (V_DD

)

● +2.7V TO V_DDLOGIC I/O SUPPLY (V_IO)

● PACKAGE: TSSOP-28

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

Power-Supply Voltage, V_DD.............................................................. +6.5V

DISCHARGE SENSITIVITY

V

_IO............................................................... +6.5V

Input Current ................................................................................... ±10mA

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Digital Input Voltage .......................................................... –0.2V to +5.5V

Digital Output Voltage ............................................ –0.2V to (V_DD+ 0.2V)

Power Dissipation .......................................................................... 300mW

Operating Temperature Range ...................................... –40°C to + 85°C

Storage Temperature .....................................................–55°C to +125°C

Lead Temperature (soldering, 5s) ................................................. +260°C

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

Package Temperature (IR re-flow, 10s)........................................ +235°C

NOTE: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability. These are stress ratings only, and functional operation of the

device at these or any other conditions beyond those specified is not implied.

PACKAGE/ORDERING INFORMATION

SPECIFIED

PACKAGE

DESIGNATOR⁽¹⁾

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

DIT4192

TSSOP-28

PW

–40°C to +85°C

DIT4192IPW

Rails, 50

"

DIT4192IPWR

Tape and Reel, 2000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

DIT4192

2

SBOS229B

www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications at T_A= +25°C, V_DD= +5V, and V_IO= 3.3V unless otherwise noted.

DIT4192IPW

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

DIGITAL CHARACTERISTICS

Applies to All Digital I/O Except TX+ and TX–

High-Level Input Voltage, V_IH

Low-Level Input Voltage, V_IL

High-Level Output Voltage, V_OH

Low-Level Output Voltage, V_OL

Input Leakage Current

0.7 • V_IO

V_IO

0.2 • V_IO

V

µA

0

0.8 • V_IO

0

I_O= –4mA

I_O= +4mA

0.1 • V_IO

10

1

OUTPUT DRIVER CHARACTERISTICS

Applies Only to TX+ and TX–

High-Level Output Voltage, V_OH

Low-Level Output Voltage, V_OL

I_O= –30mA

I_O= +30mA

V_DD– 0.7

0

V_DD– 0.4

0.4

V_DD

0.7

V

SWITCHING CHARACTERISTICS

Master Clock and Reset

Master Clock (MCLK) Frequency

Master Clock (MCLK) Duty Cycle

Reset (RST) Active Low Pulse Width

Serial Control Port Timing

CCLK Frequency

25

60

MHz

%

ns

40

500

Stereo Mode

Mono Mode

f_S= Sampling Frequency

128 • f_S

64 • f_S

MHz

ns

Serial Control Data Setup Time, t_SDS

Serial Control Data Hold Time, t_SDH

CS Falling to CCLK Rising, t_CSCR

CCLK Falling to CS Rising, t_CFCS

CCLK Falling to CDOUT Data Valid, t_CFDO

CS Rising to CDOUT High Impedance, t_CSZ

Audio Serial Interface Timing

SYNC Frequency (or Frame Rate)

SYNC Clock Period t_SYNCP

SYNC High/Low Pulse Width, t_SYNCHL

SCLK Frequency

SCLK Clock Period, t_SCLKP

SCLK High/Low Pulse Width, t_SCLKHL

SYNC Edge to SCLK Edge, t_SYSK

Audio Data Setup Time, t_ADS

Audio Data Hold Time, t_ADH

C, U, and V Input Timing

12

8

15

12

10

195.3050

25

kHz

µs

MHz

ns

5.12

2.56

40

18

15

C/U/V Data Setup Time, t_CUVS

C/U/V Data Hold Time, t_CUVH

15

ns

POWER-SUPPLY

Operating Voltage

V_DD

V_IO

+4.5

+2.7

+5

+5.5

V_DD

V

Supply Current

I_DD, Quiescent

V_DD= +5V

V_IO= +3.3V

V_IO= +5V

25

2

µA

mA

µA

mA

µA

mA

I

_DD, Power-Down Mode

_DD, Dynamic (at 192kHz operation)

_IO, Quiescent

_IO, Power-Down Mode

_IO, Dynamic (at 192kHz operation)

_IO, Power-Down Mode

30

15

1.5

250

3

_IO, Quiescent

_IO, Dynamic (at 192kHz operation)

Power Dissipation

PD, Quiescent

PD, Power-Down Mode

PD, Dynamic (at 192kHz operation)

V_DD= +5V

100

175

µW

mW

TEMPERATURE RANGE

Operating Range

Storage Range

–40

–55

+85

+125

°C

DIT4192

SBOS229B

3

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PIN CONFIGURATION: Software Mode (MODE = 0)

PIN CONFIGURATION: Hardware Mode (MODE = 1)

Top View

TSSOP

Top View

TSSOP

NC

MODE

U

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CSS

MODE

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CDOUT

CCLK

CDIN

CS

COPY/C

L

U

NC

3

V

3

BLS

NC

4

CLK1

CLK0

MCLK

V_IO

BLS

4

5

BLSM

EMPH

AUDIO

MONO

MDAT

V_DD

5

MCLK

V_IO

NC

6

DIT4192

INT

NC

7

DIT4192

7

DGND

RXP

8

DGND

FMT0

FMT1

SCLK

SYNC

SDATA

M/S

8

NC

9

NC

V_DD

TX+

TX–

DGND

RST

10

11

12

13

14

10

11

12

13

14

SCLK

SYNC

SDATA

NC

TX+

TX–

DGND

RST

PIN DESCRIPTIONS: Software Mode

PIN DESCRIPTIONS: Hardware Mode

NAME

PIN DESCRIPTION

NAME

PIN DESCRIPTION

1

2

3

4

5

6

7

NC

CDOUT

CCLK

CDIN

CS

No Connection

1

2

CSS

Channel Status Data Mode Input

Copy Protect Input or Channel Status Se-

rial Data Input

Control Port Data Output, Tri-State

Control Port Data Clock Input

Control Port Serial Data Input

COPY/C

3

4

5

6

7

L

Generation Status Input

CLK1

CLK0

MCLK

V_IO

Master Clock Rate Selection Input

Control Port Chip Select Input, Active LOW

Master Clock Input

Master Clock Rate Selection Input

Master Clock Input

MCLK

V_IO

Digital I/O Power Supply, +2.7V to V_DD

Nominal

Digital I/O Power Supply, +2.7V to V_DD

Nominal

8

DGND

RXP

NC

Digital Ground

8

DGND

FMT0

FMT1

SCLK

SYNC

SDATA

M/S

Digital Ground

9

AES-3 Encoded Data Input

No Connection

9

Audio Data Format Control Input

Audio Serial Port Data Clock I/O

Audio Serial Port Frame SYNC Clock I/O

Audio Serial Port Data Input

10

11

12

13

14

15

16

17

18

19

20

21

22

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SCLK

SYNC

SDATA

NC

Audio Serial Port Data Clock I/O

Audio Serial Port Frame SYNC Clock I/O

Audio Serial Port Data Input

No Connection

Audio Serial Port Master/Slave Control Input

Reset Input, Active LOW

RST

DGND

TX–

Reset Input, Active LOW

Digital Ground

RST

DGND

TX–

Digital Ground

Transmitter Line Driver Output

Digital Core Power Supply, +5V Nominal

No Connection

Transmitter Line Driver Output

Digital Core Power-Supply, +5V Nominal

Mono Mode Channel Data Selection Input

Mono Mode Enable Input, Active HIGH

Audio Data Valid Control Input, Active LOW

Pre-Emphasis Status Input, Active LOW

Block Start Mode Control Input

Block Start I/O

TX+

V_DD

VDD

NC

MDAT

MONO

AUDIO

EMPH

BLSM

BLS

NC

No Connection

INT

Open Drain Interrupt Output, Active LOW.

Requires 10kΩ pull-up resistor to V_IO

.

23

24

25

26

27

28

NC

No Connection

Block Start I/O

BLS

NC

No Connection

V

Validity Data Input

U

User Data Input

U

User Data Input

MODE

Control Mode Input. Set MODE = 0 for

Software Mode operation.

MODE

Control Mode Input. Set MODE = 1 for

Hardware Mode Operation.

DIT4192

4

SBOS229B

www.ti.com

Analog-to-Digital (A/D) converters, Digital Signal Processors

(DSPs), and audio decoders. Support for Left-Justified, Right-

Justified, and I²S data formats is provided.

GENERAL DESCRIPTION

The DIT4192 is a complete digital audio transmitter, suitable

for both professional and consumer audio applications. Sam-

pling rates up to 192kHz are supported. The DIT4192 com-

plies with the requirements for the AES-3, IEC-60958, and

EIAJ CP1201 interface standards.

The AES-3 encoder creates a multiplexed bit stream, con-

taining audio, status, and user data. See Figure 3 for the

multiplexed data format. The data is then Bi-Phase Mark

encoded and output to a differential line driver. The line driver

outputs are connected to the transmission medium, be it

cable or fiber optics. In the case of twisted-pair or coaxial

cable, a transformer is commonly used to couple the driver

outputs to the transmission line. This provides both isolation

and improved common-mode rejection. For optical transmis-

sion, the TX+ (pin 18) driver output is connected to an optical

transmitter module. See the Applications Information section

of this data sheet for details regarding output driver circuit

configurations.

Figures 1 and 2 show the block diagrams for the DIT4192

when used in Software and Hardware control modes. The

MODE input (pin 28) determines the control model used to

configure the DIT4192 internal functions. In Software mode,

a serial control port is used to write and read on-chip control

registers and status buffers. In Hardware mode, dedicated

control pins are provided for configuration and status inputs.

The DIT4192 includes an audio serial port, which is used to

interface to standard digital audio sources, such as

RXP

U

TX+

Line

SYNC

Audio

Driver

AES-3 Encoder

SCLK

Serial

Port

TX–

SDATA

Serial Control Interface,

Control Registers,

and Channel Status

Data Buffers

MCLK

Clock

Generator

Reset

Logic

RST

Control Port

BLS

INT

FIGURE 1. Software Mode Block Diagram.

SYNC

SCLK

SDATA

TX+

Audio

Serial

Port

Line

Driver

AES-3 Encoder

M/S

FMT0

FMT1

TX–

MCLK

CLK0

CLK1

Clock

Generator

Reset

Logic

CUV

Data Buffer

RST

CSS

COPY/C

L

BLSM

BLS

MONO

MDAT

AUDIO

EMPH

U

V

FIGURE 2. Hardware Mode Block Diagram.

DIT4192

SBOS229B

5

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Start of Channel Status Block

Frame 191

Frame 0

Frame 1

X

Channel A

Channel B

Z

Channel A

Y

Channel B

X

Channel A

Y

Channel B

One Sub-Frame

Bits: 0

3

4

7 8

27 28 29 3031

Preamble

Aux Data

LSB

Audio Data

MSB V U C P

Validity Data

User Data

Channel Status Data

Parity Bit

FIGURE 3. AES-3 Frame Format.

MASTER CLOCK

RESET AND POWER-DOWN

OPERATION

The DIT4192 requires a master clock for operation. This

clock must be supplied at the MCLK input (pin 6). The

maximum master clock frequency that may be supplied to

MCLK is 25MHz. Table I shows master clock rates for

common input sampling frequencies.

The DIT4192 includes a reset input, RST (pin 15), which is

used to force a reset sequence. When the DIT4192 is first

powered up, the user must assert RST low in order to start

the reset sequence. The RST input must be low for a

minimum of 500ns. The RST input is then forced high to

enable normal operation. For software mode, the reset se-

quence will force all internal registers to their default settings.

In addition, the reset sequence will force all channel status

bits to 0 in Software mode.

SAMPLING

MASTER CLOCK FREQUENCY (MHz)

FREQUENCY (kHz) 128 • f_S

256 • f_S

384 • f_S

512 • f_S

22.05

24

32

44.1

48

88.2

96

n/a

22.5792

24.576

5.6448

6.144

8.192

11.2896

12.288

22.5792

24.576

n/a

8.4672

9.216

12.288

16.9344

18.432

n/a

11.2896

12.288

16.384

22.5792

24.576

n/a

While the RST input is low, the transmitter outputs,

TX– (pin 17) and TX+ (pin 18), are forced to ground.

Upon setting RST high, the TX– and TX+ outputs will remain

low until the rising edge of the SYNC clock is detected at

pin 12. Once this occurs, the TX– and TX+ outputs will

become active and be driven by the output of the AES-3

encoder.

176.4

192

n/a

TABLE I. Master Clock Frequencies for Common Sampling

Rates.

In Software mode, the DIT4192 also includes software reset

and power-down bits, located in control register 02_H. The

software reset bit, RST, and the software power-down bit,

PDN, are both active high.

For Software mode, the master clock frequency selection is

programmed using the CLK0 and CLK1 bits in Control

Register 02_H. For Hardware mode, the CLK0 (pin 5) and

CLK1 (pin 4) inputs are used to select the master clock

frequency. Table II shows the available MCLK frequency

selections.

AUDIO SERIAL PORT

The audio serial port is a 3-wire interface used to connect the

DIT4192 to an audio source, such as an A/D converter or

DSP. The port supports sampling frequencies up to 192kHz.

The port signals include SDATA (pin 13), SYNC (pin 12), and

SCLK (pin 11). The SDATA pin is the serial data input for the

port. The SCLK pin may be either an input or output, and is

used to clock serial data into the port. The SYNC pin may be

either an input or output, and provides the frame synchroni-

CONTROL BITS OR INPUT PINS

CLK1

CLK0

MASTER CLOCK (MCLK) SELECTION

0

1

0

1

0

1

128 • f_S

256 • f_S

384 • f_S

512 • f_S

TABLE II. Master Clock Rate Selection for Software and

Hardware Modes.

DIT4192

6

SBOS229B

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SYNC AND SCLK FREQUENCIES

zation clock for the port. The SYNC pin is also used as a data

latch clock for the channel status, user, and validity data

inputs in Hardware mode, and the user data input in Software

mode.

The SYNC clock rate is the same as the sampling frequency,

or f_S. This holds true for both Slave and Master modes. The

DIT4192 supports SYNC frequencies up to 192kHz.

The SCLK frequency in Slave mode must provide at least

one clock cycle for each data bit that is input at SDATA. The

maximum SCLK frequency is 128 • f_S, or 24.576MHz for

f_S= 192kHz. The SCLK frequency in Master mode is set by

the DIT4192 itself. For Software mode operation, the SCLK

rate may be programmed to either 64 • f_Sor 128 • f_S, using

the SCLKR bit in Control Register 03_HEX. In Hardware mode,

the SCLK frequency is fixed at 64 • f_Sfor Master mode.

SLAVE OR MASTER MODE OPERATION

The audio serial port supports both Slave and Master mode

operation. In Slave mode, both SYNC and SCLK are config-

ured as inputs. The audio source device must generate both

the SYNC and SCLK clocks in Slave mode. In Master mode,

both SYNC and SCLK are configured as outputs. The audio

serial port generates the SYNC and SCLK clocks in Master

mode, deriving both from the master clock (MCLK) input.

AUDIO DATA FORMATS

In Software mode, Master/Slave mode selection is per-

formed using the M/S bit in Control Register 03_H(defaults to

Slave mode). In Hardware mode, the M/S input (pin 14) is

used to select the audio serial port mode. This is shown in

Table III.

The DIT4192 supports standard audio data formats, includ-

ing Philips I²S, Left-Justified, and Right-Justified data.

Software mode provides the most flexible format selection,

while Hardware mode supports a limited subset of the

Software mode formats. Linear PCM audio data at the

SDATA input is typically presented in Binary Two’s Comple-

ment, MSB first format. Encoded or non-audio data may be

provided as required by the encoding scheme in use. Figure

4 shows the common data formats used by the audio serial

port.

CONTROL BITS OR INPUT PIN

M/S

0

MASTER/SLAVE MODE SELECTION

Slave Mode, both SYNC and SCLK

are inputs.

Master Mode, both SYNC and SCLK

are outputs.

1

TABLE III. Master/Slave Mode Selection for Software or

Hardware Mode.

Left Channel

Right Channel

SYNC

(ISYNC = 0)

SYNC

(ISYNC = 1)

MSB

LSB

MSB

LSB Right Justified

SDATA

Left Justified

0 SCLK Delay

MSB

LSB

MSB

LSB

Left Justified

MSB

LSB

MSB

LSB

SDATA

1 SCLK Delay (I²S)

SCLK

(ISCLK = 0)

SCLK

(ISCLK = 1)

t_SYNCHL

SYNC

SCLK

t_SYSK

t_SCLKHL

t_SCLKP

t_SYSKHL

SDATA

t_ADH

t_ADS

FIGURE 4. Audio Data Formats and Timing.

DIT4192

SBOS229B

7

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falling edge of SYNC when the ISYNC bit is set to 1. If BLS

is high when it is sampled, then a block start condition is

indicated. When BLS is configured as an output and the

ISYNC bit is set to 0, BLS will go high at every 192nd falling

edge of SYNC for Stereo mode, or every 384th falling edge

of SYNC for Mono mode. BLS will then go low on the

following falling edge. If the ISYNC bit is set to 1, then BLS

transitions on the rising edge of SYNC.

For Software mode, Control Register 03_His used to set the

audio data format selection. Data word length may be set to

16, 18, 20, or 24 bits using the WLEN0 and WLEN1 bits.

Several format parameters, including SCLK sampling edge,

data delay from the start of frame, and SYNC polarity may be

programmed using this register. Table IV shows examples of

register bit settings for three standard audio formats. SCLK

sampling edges and SYNC polarity may differ from one

system implementation to the next. Consult the audio source

device data sheet or technical reference for details regarding

the output data formatting.

Hardware mode operation is similar to Software mode opera-

tion, with the exception that there are only a limited number

of data formats available for the audio serial port. For Left-

and Right-Justified formats, BLS behaves as it would in

Software mode with ISYNC = 0. For the I²S data format, BLS

behaves as it would in Software mode with ISYNC = 1.

For Hardware mode, the FMT0 (pin 9) and FMT1 (pin 10)

inputs are utilized to select one of four audio data formats.

Refer to Table V for the available format selections.

INPUT PINS

CHANNEL STATUS DATA INPUT

FMT1

FMT0

FORMAT SELECTIONS

24-Bit Left-Justified

24-Bit I²S

24-Bit Right-Justified

16-Bit Right-Justified

Channel status data input is determined by the control mode

in use. In Software mode, the channel status data buffer is

accessed through the serial control port. Buffer operations

are described in detail in the section of this data sheet

entitled Channel Status Buffer Operation (Software Mode

Only). In Hardware mode, channel status data input is

accomplished by one of two user-selectable methods.

0

1

0

1

0

1

TABLE V. Audio Data Format Selection for Hardware Mode.

AES-3 ENCODER OPERATION

The AES-3 encoder performs the multiplexing of audio,

channel status, user, and validity data. It also performs Bi-

Phase Mark encoding of the multiplexed data stream. This

section describes how channel status, user, and validity data

are input to the encoder function.

THE CSS INPUT

In Hardware mode, the state of the CSS input (pin 1)

determines the function of dedicated channel status inputs.

When CSS = 0, the COPY (pin 2), L (pin 3), AUDIO (pin 22),

and EMPH (pin 23) inputs are used to set associated

channel status data bits. The COPY and L inputs are used to

set up copy protection for consumer operation, or indicate

that the transmitter is operating in professional mode, without

copy protection. The AUDIO input is utilized to indicate

whether the data being transmitted is PCM audio data, or

non-audio data. The EMPH input is used to indicate whether

the PCM audio data has been pre-emphasized using the

50/15µs standard. See Table VI for the available options for

these dedicated channel status inputs.

BLOCK START INPUT/OUTPUT

The block start is used to indicate the start of a channel status

data block, which starts with Frame 0 for the AES-3 data

stream. For the DIT4192, the block start signal BLS

(pin 25), may be either an input or output. In Software mode,

the direction of BLS is set using the BLSM bit in control register

01_H(defaults to input). In Hardware mode, the direction of BLS

is set by the BLSM input (pin 24). If BLSM = 0, the BLS pin is

an input. If BLSM = 1, the BLS pin is an output.

When CSS = 1, the channel status data is input in a serial

fashion at the C input (pin 2). Data is clocked on the rising

and falling edges of the SYNC input (pin 12). All channel

status data bits can be written in this mode, allowing greater

flexibility than the previous Hardware mode case with

CSS = 0. See Figure 5 for the C input timing diagram.

For Software mode operation, the block start signal is syn-

chronized to the audio serial port frame sync clock, SYNC

(pin 12). When BLS is configured as an input pin, it is

sampled on the rising edge of SYNC when the ISYNC bit in

control register 03_His set to 0. Otherwise, it is sampled on the

CONTROL REGISTER 03_HBIT SETTINGS

Bit Name

JUS

Function

Bit Name

DELAY

Function

Bit Name

ISCLK

Function

Bit Name

ISYNC

Function

Phase

AUDIO DATA

FORMATS

Justification

SCLK Delay

Sampling Edge

Philips I²S

Left-Justified

Right-Justified

0

1

Left-Justified

Right-Justified

1

0

1 SCLK Delay

0 SCLK Delay

0

Rising Edge

1

0

Inverted

Noninverted

TABLE IV. Audio Data Format Selection in Software Mode.

DIT4192

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INPUT

COPY

L

FUNCTION

Copy Status

Generation Status

COPY

L

0

1

0

1

Status

0

1

Consumer Mode, PRO = 0, COPY = 0, L = 0

Consumer Mode, PRO = 0, COPY = 0, L = 1

Consumer Mode, PRO = 0, COPY = 1, L = 0

Professional Mode, PRO = 1, No Copy Protection

AUDIO

EMPH

Audio Data Status

AUDIO

Status

0

1

Digital (or Linear PCM) Audio Data

Non-Audio or Encoded Audio Data

Pre-Emphasis Status

EMPH

Status

0

1

Pre-emphasis bits are set to indicate 50/15µs Pre-emphasis has been applied.

Pre-emphasis bits are set to indicate that no Pre-emphasis has been applied.

TABLE VI. Channel Status Data Input for Hardware Mode with CSS = 0.

Block Start

Frame 191 or 383

Frame 0

SYNC⁽¹⁾

BLS

(Input)

BLS

(Output)

192nd or 384th

Falling Edge⁽¹⁾

C, U, or V

Data

Ch B

Data

Ch A

Data

Ch B

Data

Ch A

Data

t_CUVS

t_CUVH

NOTE: (1) Assumes ISYNC = 0.

FIGURE 5. C, U, and V Data Timing.

USER AND VALIDITY DATA INPUT

for further processing. In Software mode, the VAL bit in

control register 01_His utilized to write the validity data. In

Hardware mode, the V input (pin 26) is used to input the

validity data in serial fashion. Refer to Figure 5 for V input

timing for Hardware Mode.

The user data bits in the AES-3 data stream allow for a

convenient way to transfer user-defined or application spe-

cific data to another device containing an AES-3 receiver.

The U input (pin 27) is used in both Software and Hardware

mode to input the user data in a serial fashion. Figure 5

shows the U input timing diagram.

When VAL or V = 0, this indicates that the audio data is valid

and suitable for further processing. When VAL or V = 1, then

the audio sample is defective and should not be used.

Validity data is used to indicate that a sample is error-free

audio data, or that the sample is defective and is not suitable

DIT4192

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CCLK is the data clock for the serial control interface. Data

is clocked in at CDIN on the rising edge of CCLK, while data

is clocked out at CDOUT on the falling edge of CCLK. Data

is clocked MSB first for both CDIN and CDOUT.

LINE DRIVER OUTPUTS

The DIT4192 includes a balanced line driver. The line driver

outputs are TX– (pin 17) and TX+ (pin 18). In Software mode,

the line driver input is taken from either the output of the on-

chip AES-3 encoder, or from an external AES-3 encoded

source input at RXP (pin 9). The input source is selected

using the BYPASS bit in control register 01_H(defaults to the

on-chip AES-3 encoder). In Hardware mode, the line driver

source is always the on-chip AES-3 encoder.

WRITE OPERATION

Figure 6 illustrates the write operation for the control port.

You may write one register or buffer address at a time, or use

the auto-increment capability built into the control port to

perform block writes. The register or buffer data is preceded

by a 16-bit header, with the first byte being used to configure

control port operation and set the starting register or buffer

address. The second byte of the header is comprised of

“don’t care” bits, which can be set to either 0 or 1 without

affecting port operation.

The outputs of the line driver will follow the AES-3 encoded

data source in normal operation. During a hardware or

software reset, or when the device is in power-down mode,

the line driver outputs will be forced to ground. The outputs

can also be forced to ground at any time in Software mode

by setting the TXOFF bit to 1 in control register 01_H.

The first byte of the header contains two control bits, R/W

and STEP, followed by a 6-bit address. For write operations,

R/W = 0. The STEP bit determines the address step size for

the auto-increment operation. When STEP = 0, the address

is incremented by 1. When STEP = 1, the address is

incremented by 2. Incrementing by 1 is useful when writing

multiple control registers in sequence, or when writing both

left and right channel status data in sequence. Incrementing

by 2 is useful when writing just one channel of status data in

sequence.

CONTROL PORT OPERATION

(SOFTWARE MODE ONLY)

For Software mode operation, the DIT4192 includes a serial

control port, which is used to write and read control registers

and the channel status data buffer. Port signals include CS

(pin 5), CDIN (pin 4), CDOUT (pin 2), and CCLK (pin 3).

CS is the active low chip select. This signal must be driven

low in order to write or read control registers and the channel

status data buffer.

The third byte contains the 8-bit data for the register or buffer

address pointed to by the first byte of the header. To write a

single address location, CS is brought high after the least

significant bit of the third byte is clocked into the port. For

auto increment mode, CS is kept low to write successive

register or buffer addresses.

CDIN is the serial data input, while CDOUT serves as the

serial data output. The CDOUT pin is a tri-state output, which

is set to a high-impedance state when not performing a Read

operation, or when CS = 1.

Set CS = 1 here to write one register or buffer location.

Keep CS = 0 to enable auto-increment mode.

CS

Header

Register or Buffer Data

Byte 2 Byte 3

Byte 0

Byte 1

Byte N

CDIN

CCLK

BYTE DEFINITION

MSB

LSB

A0

BYTE 0:

R/W STEP A5

A4

A3

A2

A1

Register or Buffer Address

Auto-Increment Address Step Size: 0 = Increment Address by 1

1 = Increment Address by 2

Read/Write Control: Set to 1 for Read Operation

Byte 1: All 8 bits are Don’t Care. Set 0 or 1.

Bytes 2 through N: 8-Bit Register or Buffer data.

FIGURE 6. Write Operation Format.

DIT4192

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READ OPERATION

the auto-increment operation. When STEP = 0, the address

is incremented by 1. When STEP = 1, the address is

incremented by 2. Incrementing by 1 is useful when reading

multiple control registers in sequence, or when reading both

left and right channel status data in sequence. Incrementing

by 2 is useful for reading just one channel of status data in

sequence.

Figure 7 shows an illustration of the read operation for the

control port. You may read one register or buffer address at

a time, or use the auto-increment capability built into the

control port to perform block reads. A 16-bit header is first

written to the port, with the first byte being used to configure

control port operation and set the starting register or buffer

address. The second byte of the header is comprised of

“don’t care” bits, which can be set to either 0 or 1 without

affecting port operation.

The first output data byte occurs immediately after the 16-bit

header has been written. This byte contains the 8-bit data for

the register or buffer address pointed to by the first byte of

the header. To read a single address location, CS is brought

high after the least significant bit of the first data byte is

clocked out of the port. For auto-increment mode, CS is kept

low to read successive register or buffer addresses.

The first byte of the header contains two control bits, R/W

and STEP, followed by a 6-bit address. For read operations,

R/W = 1. The STEP bit determines the address step size for

Set CS = 1 here to read one register or buffer location.

Keep CS = 0 to enable auto-increment mode.

Ignore Until Next High-to-Low Transition of CS

CS

Header

Byte 0

Byte 1

CDIN

Register or Buffer Data

Byte 0 Byte 1

Byte N

High Impedance

CDOUT

CCLK

BYTE DEFINITION

MSB

LSB

A0

BYTE 0:

R/W STEP A5

A4

A3

A2

A1

Register or Buffer Address

Auto-Increment Address Step Size: 0 = Increment Address by 1

1 = Increment Address by 2

Read/Write Control: Set to 1 for Read Operation

Byte 1: All 8 bits are Don’t Care. Set 0 or 1.

Bytes 2 through N: 8-Bit Register or Buffer data.

FIGURE 7. Read Operation Format.

CS

CCLK

t_CSCR

t_CFCS

t_SDS

t_SDH

CDIN

CDOUT

t_CSZ

t_CFDO

FIGURE 8. Serial Port Timing.

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When MONO = 1 and MCSD = 0, the MDAT bit

is used to select the source for Audio data.

CONTROL REGISTER DEFINITIONS

(SOFTWARE MODE ONLY)

This section defines the control registers used to configure

the DIT4192, as well as the status register used to indicate

an interrupt source.

When MONO = 1 and MCSD = 1, the MDAT bit

is used to select the source for both Audio and

Channel Status data.

MCSD

Channel Status Data Selection (Defaults to 0)

Register 00_H: Reserved for Factory Use

When set to 0, Channel A data is used for the A

sub-frame, while Channel B data is used for the

B sub-frame.

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

Bit 0 (LSB)

0

When set to 1, use the same channel status data

for both A and B sub-frames. Channel status data

source is selected using the MDAT bit.

BLSM

Block Start Mode (Defaults to 0)

When set to 0, BLS (pin 25) is configured as an

input pin.

TXOFF

Transmitter Output Disable (Defaults to 0)

When set to 0, the line driver outputs, TX–

(pin 17) and TX+ (pin 18) are enabled.

When set to 1, BLS (pin 25) is configured as an

output pin.

When set to 1, the line driver outputs are forced

to ground.

VAL

Audio Data Valid (Defaults to 0)

When set to 0, valid Linear PCM audio data is

indicated.

Register 02_H: Power-Down and Clock Control Register

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

When set to 1, invalid audio data or non-PCM

data is indicated.

0

RST

CLK1

CLK0

PDN

Register 01_H: Transmitter Control Register

PDN

Power-Down (Defaults to 1)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

VAL

Bit 0 (LSB)

BLSM

When set to 0, the DIT4192 operates normally.

TXOFF

MCSD

MDAT

MONO

BYPAS

MUTE

When set to 1, the DIT4192 is powered down,

with the line driver outputs forced to ground.

MUTE

Transmitter Mute (Defaults to 0)

CLK[1:0]

MCLK Rate Selection

When set to 0, the mute function is disabled.

These bits are used to select the master clock

frequency applied to the MCLK input (pin 6).

When set to 1, the mute function is enabled,

with Channel A and B audio data set to all 0’s.

CLK1 CLK0

MCLK Rate

128 • f_S

BYPASS

Transmitter Bypass—AES-3 Data Source for

the Output Driver (Defaults to 0)

0

1

0

1

0

1

256 • f_S(default)

384 • f_S

When set to 0, AES-3 encoded data is taken

from the output of the on-chip encoder.

512 • f_S

When set to 1, RXP (pin 9) is used as the

source for AES-3 encoded data.

RST

Software Reset (Defaults to 0)

When set to 0, the DIT4192 operates normally.

When set to 1, the DIT4192 is reset.

MONO

MDAT

Mono Mode Control (Defaults to 0)

When set to 0, the transmitter is set to Stereo

mode.

Register 03_H: Audio Serial Port Control Register

When set to 1, the transmitter is set to Mono

mode.

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

M/S

ISYNC

ISCLK

DELAY

JUS

WLEN1

WLEN0

SCLKR

Data Selection Bit (Defaults to 0)

(0 = Left Channel, 1 = Right Channel)

M/S

Master/Slave Mode (Defaults to 0)

When MONO = 0 and MCSD = 0, the MDAT bit

is ignored.

When set to 0, the audio serial port is set for

Slave operation.

When MONO = 0 and MCSD = 1, the MDAT bit

is used to select the source for Channel Status

data.

When set to 1, the audio serial port is set for

Master operation.

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BTI

Buffer Transfer Interrupt Status—Active

SCLKR

Master Mode SCLK Frequency (Defaults to 0)

High

When set to 0, the SCLK frequency is set to

When User Access (UA) to Transmitter Access

(TA) buffer transfers are enabled, and the BTI

interrupt is unmasked, this bit will go HIGH

when a UA to TA buffer transfer has com-

pleted. This will also cause the INT output

(pin 22) to be driven Low, indicating that an

interrupt has occurred.

64 • f_S.

When set to 1, the SCLK frequency is set to

128 • f_S.

WLEN[1:0] Audio Data Word Length

These bits are used to set the audio data word

length for both Left and Right channels.

TSLIP

Transmitter Source Data Slip Interrupt Sta-

tus—Active High

WLEN1 WLEN0

Length

0

1

24 Bits (default)

This bit will go HIGH when either a Data Slip or

Block Start condition is detected, and the TSLIP

interrupt is unmasked. This will also cause the

INT output (pin 22) to be driven LOW, indicat-

ing that an interrupt has occurred. The function

of this bit is selected using the BSSL bit in

control register 05_H(defaults Data Slip).

20 Bits

1

0

1

18 Bits

16 Bits

JUS

Audio Data Justification (Defaults to 0)

When set to 0, the audio data is Left-Justified

with respect to the SYNC edges.

The MBTI and MTSLIP bits are used to mask

the BTI and TSLIP interrupts. When masked,

these interrupt sources are disabled.

When set to 1, the audio data is Right-Justified

with respect to the SYNC edges.

Register 05_H: Interrupt Mask Register

DELAY

Audio Data Delay from the Start of Frame

(Defaults to 0)

This applies primarily to I²S and DSP frame

formats, which use Left-Justified audio data.

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

MBTI

0

BSSL

MTSLIP

When set to 0, audio data starts with the SCLK

period immediately following the SYNC edge

which starts the frame. This is referred to as a

zero SCLK delay.

MBTI

BTI Interrupt Mask. Set to ‘0’ to mask BTI

(Defaults to 0).

MTSLIP

TSLIP Interrupt Mask. Set to ‘0’ to mask

TSLIP (Defaults to 0).

When set to 1, the audio data starts with the

second SCLK period following the SYNC edge

which starts the frame. This is referred to as a

one SCLK delay. This is used primarily for the

I²S data format.

BSSL

TSLIP Interrupt Select (Defaults to 0)

When set to 0, the Data Slip condition is used

to trigger a TSLIP interrupt.

When set to 1, the Block Start condition is

used to trigger a TSLIP interrupt.

ISCLK

ISYNC

SCLK Sampling Edge (Defaults to 0)

When set to 0, audio serial data at SDATA

(pin 13) is sampled on rising edge of SCLK.

Register 06_H: Interrupt Mode Register

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

BTIM0

When set to 1, audio serial data at SDATA

(pin 13) is sampled on falling edge of SCLK.

0

TSLIPM1 TSLIPM0

BTIM1

SYNC Polarity (Defaults to 0)

When set to 0, Left channel data occurs when

the SYNC clock is HIGH.

BTIM[1:0]

BTI Interrupt Mode

TSLIPM[1:0] TSLIP Interrupt Mode

When set to 1, Left channel data occurs when

the SYNC clock is LOW.

These bits are used to select the active state

for interrupt operation.

For both cases, Left channel data always pre-

cedes the Right channel data in the audio frame.

BTIM1 or BTIM0 or

TSLIPM1 TSLIPM0 Interrupt Operation

Register 04_H: Interrupt Status Register

0

1

0

1

0

1

Rising Edge Active (default)

Falling Edge Active

Level Active

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

BTI

0

TSLIP

Reserved

DIT4192

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BTD

Buffer Transfer Disable (Defaults to 0)

The master clock input (MCLK) and the frame synchroniza-

tion clock input (SYNC) must be active in order to update the

channel status buffer in Software mode. When the DIT4192

is initially powered up, the device defaults to power-down

mode. When the PDN bit in Register 2 is set to 0 to power

up the device, there must be a delay between the time that

PDN is set to 0 and the first access to the channel status

buffer. This delay allows the SYNC clock to synchronize the

AES3 encoder block with the audio serial port. It is recom-

mended that Register 2 be the last control register written in

the initialization sequence, followed by a delay (10 millisec-

onds or longer) before attempting to access the channel

status buffer.

When set to 0, User Access (UA) to Transmit-

ter Access (TA) Buffer transfers are enabled.

When set to 1, User Access (UA) to Transmit-

ter Access (TA) Buffer transfers are disabled.

Register 07_H: Channel Status Buffer Control Register

bit 7 (MSB)

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0 (LSB)

0

BTD

CHANNEL STATUS DATA

BUFFER OPERATION

(SOFTWARE MODE ONLY)

The DIT4192 contains two buffers for the channel status data.

These are referred to as the Transmitter Access (TA) buffer

and the User Access (UA) buffer. Each buffer is 48 bytes long,

containing 24 bytes each for channels A and B. The 24 bytes

per channel correspond to the channel status block defined in

the AES-3 and IEC-60958 specifications. Channel A and B

data are interleaved within the buffers, see Tables VII and VIII.

UPDATING THE CHANNEL DATA STATUS BUFFER

Updating the channel status data buffer involves disabling

and enabling the UA to TA buffer transfer using the BTD bit

in control register 07_H. Figure 9 shows the proper flow for

updating the buffer.

The BTD bit is normally set to 0, which enables the UA to TA

buffer transfer. In order to update the channel status data, the

user must write to the UA buffer. To avoid UA to TA data

transfer while the UA buffer is being updated, the BTD bit is set

to 1, which disables UA to TA buffer transfers. While

BTD = 1, the user writes new channel status data to the UA

buffer via the control port. Once the UA buffer update is

complete, the BTD bit is reset to 0. A new UA to TA buffer

transfer will occur during one of the frames 184 through 191,

The AES-3 encoder internally accesses the TA buffer to

obtain the channel status data that is multiplexed into the

AES-3 data stream. The user accesses the UA buffer through

the control port in order to update the channel status data

when needed. The transfer of data from the UA buffer to the

TA buffer is managed internally by the DIT4192, but it may

be enabled or disabled by the user via a control register.

DISABLE UA TO TA BUFFER TRANSFER

Set BTD = 1

in Control Register 07_H

UPDATE THE CS DATA

Write Channel Status Data

to the UA Buffer

ENABLE UA TO TA BUFFER TRANSFER

Set BTD = 0

in Control Register 07_H

Is the

Buffer Transfer Interrupt (BTI)

Masked?

Assume that the Buffer Transfer has

completed and that the Channel Status

data has been updated.

NO

YES

Is the

NO

INT output LOW?

YES

Read Register 04_Hto verify that the

BTI bit is set to 1.

The Host has verified that the Buffer

Transfer is complete, which completes the

Channel Status Data update.

FIGURE 9. Flowchart for Updating the Channel Status Buffer.

DIT4192

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ADDRESS

(HEX)

08

CS

Byte

A0

BIT 0

MSB

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

LSB

PRO

AUDIO

CH MODE

AUX

EMPH

LOCK

f_S

09

B0

PRO

f_S

0A

0B

0C

0D

0E

0F

10

A1

CH MODE

AUX

CH MODE

AUX

CH MODE

WLEN

U BIT MGT

WLEN

U BIT MGT

WLEN

U BIT MGT

reserved

U BIT MGT

reserved

B1

A2

B2

AUX

WLEN

A3

reserved

REF

reserved

REF

reserved

B3

A4

11

B4

REF

12

A5

reserved

13

B5

14

A6

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A

Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A

Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B

Local Sample Address Code (32-Bit Binary) for Channel A

Local Sample Address Code (32-Bit Binary) for Channel B

Local Sample Address Code (32-Bit Binary) for Channel A

Local Sample Address Code (32-Bit Binary) for Channel B

Local Sample Address Code (32-Bit Binary) for Channel A

Local Sample Address Code (32-Bit Binary) for Channel B

Local Sample Address Code (32-Bit Binary) for Channel A

Local Sample Address Code (32-Bit Binary) for Channel B

Time of Day Code (32-Bit Binary) for Channel A

15

B6

16

A7

17

B7

18

A8

19

B8

1A

1B

1C

1D

1E

1F

20

A9

B9

A10

B10

A11

B11

A12

B12

A13

B13

A14

B14

A15

B15

A16

B16

A17

B17

A18

B18

A19

B19

A20

B20

A21

B21

A22

B22

A23

B23

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

Time of Day Code (32-Bit Binary) for Channel B

Time of Day Code (32-Bit Binary) for Channel A

Time of Day Code (32-Bit Binary) for Channel B

Time of Day Code (32-Bit Binary) for Channel A

31

Time of Day Code (32-Bit Binary) for Channel B

32

Time of Day Code (32-Bit Binary) for Channel A

33

Time of Day Code (32-Bit Binary) for Channel B

34

reserved

Rel Flags

35

36

CRC Check Character for Channel A

CRC Check Character for Channel B

37

TABLE VII. Channel Status Buffer Map for Professional Mode (PRO = 1).

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ADDRESS

CS

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

(HEX)

Byte

MSB

LSB

8

A0

B0

PRO = 0

CAT CODE

SOURCE

f_S

AUDIO

COPY

EMPH

MODE

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

A1

CAT CODE

SOURCE

f_S

CAT CODE

SOURCE

f_S

CAT CODE

SOURCE

f_S

CAT CODE

CH NUM

CLK ACC

reserved

CAT CODE

CH NUM

CLK ACC

reserved

CAT CODE

CH NUM

reserved

L

B1

L

A2

CH NUM

reserved

B2

A3

B3

f_S

A4

reserved

B4

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

B10

A11

B11

A12

B12

A13

B13

A14

B14

A15

B15

A16

B16

A17

B17

A18

B18

A19

B19

A20

B20

A21

B21

A22

B22

A23

B23

TABLE VIII. Channel Status Buffer for Consumer Mode (PRO = 0).

whichever is the first frame to occur after the BTD bit is reset

to 0. Once the UA to TA buffer transfer is completed, the buffer

transfer interrupt (BTI) will occur, as long as it is unmasked.

INTERRUPT SOURCES

(SOFTWARE MODE ONLY)

The transmitter will ignore any attempt to access the UA

buffer during a UA to TA buffer transfer. In addition, the BTD

bit may be set to 1 to stop a UA to TA buffer transfer that

maybe in progress, if so desired.

The DIT4192 can be programmed to generate interrupts for

up to three predefined conditions. The interrupt output, INT

(pin 22), is set low when a valid interrupt occurs. The interrupt

status register, 04_H, is then read to determine the source of

the interrupt. Status register bits and the INT output pin

remain active until the status register is read. Once read,

status bits are cleared and the INT pin is pulled high by an

external pull-up resistor to V_IO.

CHANNEL STATUS BUFFER MAP

The channel status buffer is organized in accordance with

the AES-3 and IEC-60958 standards. See Table VII for the

memory map for the UA channel status data buffer for

Professional mode. Table VIII shows the memory map for the

UA channel status data buffer for Consumer mode.

Interrupts may be masked using control register 05_H. When

masked, the interrupt mechanism associated with a particu-

lar status bit is disabled.

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CHANNEL STATUS BUFFER TRANSFER INTERRUPT

A block start condition occurs when a block start signal is

generated either internally by the DIT4192, or when an

external block start is received at the BLS input (pin 25).

This interrupt occurs when a channel status buffer transfer

has been completed. The buffer transfer process was de-

scribed in detail in the previous section of this data sheet.

This interrupt may be used by the host to trigger an event to

occur after a channel status buffer update. The BTI bit in

status register 04_His used to indicate the occurrence of the

buffer transfer. The BTI bit, like all other status bits, is active

high and remains set until the status register is read.

APPLICATIONS INFORMATION

This section provides practical information pertinent for de-

signing the DIT4192 into a target application. Circuit sche-

matics are provided as needed.

TYPICAL APPLICATION DIAGRAMS

DATA SLIP AND BLOCK START INTERRUPTS

Figures 10 and 11 illustrate the typical application schemat-

ics for the DIT4192 when used in Software and Hardware

modes. Figure 10 shows a typical Software mode applica-

tion, where a microprocessor or DSP interface is used to

communicate with the DIT4192 via the serial control port.

See Figure 11 for a typical Hardware mode configuration,

where the control pins are either hardwired or driven by

digital logic in a stand-alone application.

Unlike the BTI interrupt, which has only one function, the

TSLIP interrupt can be set to one of two modes. This is

accomplished using the BSSL bit in control register 05_H.

When BSSL = 0, the TSLIP interrupt is set to indicate a data

slip condition. When BSSL = 1, the TSLIP interrupt is set to

indicate a block start condition. The TSLIP bit, like all other

status bits, is active high and remains set until the status

register is read.

The recommended component values for power-supply by-

pass capacitors are shown in Figures 10 and 11. These

capacitors should be located as close to the DIT4192 power-

supply pins as physically possible.

A data slip condition may occur in cases where the master

clock, MCLK (pin 6), is asynchronous to the audio data

source. When BSSL = 0, the TSLIP bit will be set to 1 every

time a data sample is dropped or repeated.

From AES-3

Encoded Data

Source

(Optional)

DIT4192

9

11

12

13

RXP

18

SCLK

SYNC

SDATA

TX+

Digital Audio

Source

(A/D Converter,

DSP)

Cable or

Output

Fiber Optics

Circuit

17

TX–

(See Figs. 12-14)

5

3

CS

CCLK

CDIN

CDOUT

INT

4

2

µP or DSP

22

25

27

15

6

+2.7V to V_DD

C₁

BLS

7

U

V_IO

8

RST

DGND

+5V C₂

C₁= C₂= 0.1µF to 1µF

19

MCLK

MODE

V_DD

28

16

Audio Master

Clock

DGND

10kΩ

V_IO

FIGURE 10. Typical Circuit Configuration, Software Mode.

DIT4192

SBOS229B

17

www.ti.com

DIT4192

Digital Audio

Source

(A/D Converter,

DSP)

11

12

13

SCLK

SYNC

SDATA

18

17

TX+

Cable or

Fiber Optics

Output

Circuit

14

9

M/S

TX–

FMT0

FMT1

CSS

10

1

(See Figs. 12-14)

2

COPY/C

U

27

26

3

Hardwired

Control

or

V

L

Dedicated

Logic

or

Host

22

23

24

21

20

AUDIO

EMPH

BLSM

MONO

MDAT

+2.7V to V_DD

Controlled

C₁

7

15

25

V_IO

DGND

V_DD

RST

BLS

8

+5V C₂

19

C₁= C₂= 0.1µF to 1µF

6

5

MCLK

CLK0

CLK1

MODE

Audio Master

Clock Generator

16

DGND

4

28

V_IO

FIGURE 11. Typical Circuit Configuration, Hardware Mode.

The line driver outputs may be connected to cable or fiber

optic transmission media in the target application. Figures 12

and 13 show typical connections for driving either balanced

twisted-pair or unbalanced coaxial cable. Either of these

connections will support rates up to 192kHz.

Figure 14 illustrates the connection to an optical transmitter

module, used primarily in consumer applications, such as CD

or DVD players. The optical transmitter data rate is limited to

6Mb/s, so it will not support 192kHz data rates. The optical

interface is typically reserved for lower rate transmission,

such as 44.1kHz or 48kHz.

T1⁽¹⁾

110

18

17

1:1

TX+

XLR

18

17

4

1

5

8

TX+

2

3

Toshiba

TOTX173

Optical

1

DIT4192

0.1µF

4

TX–

Transmitter

TX–

NC

3

2

1

NOTE: (1) Scientific Conversion SC937-02 or equivalent.

8.2kΩ

TOSLINK

APF Interconnect

FIGURE 12. Recommended Transmitter Output Circuit for

+5V

Balanced, 110Ω Twisted-Pair Transmission.

FIGURE 14. Recommended Transmitter Output Circuit for

TOSLINK Optical Transmission Over All Plastic

Fiber (APF).

T1⁽¹⁾

2:1

RCA or BNC

0.1µF

300

18

17

TX+

1

4

5

8

DIT4192

DUAL-WIRE OPERATION USING MONO MODE

In order to support stereo 192kHz transmission for legacy

systems, which utilize AES-3 receivers that operate up to a

maximum of 96kHz, it is necessary to use two DIT4192

transmitters in what is referred to as a Dual-Wire configura-

tion. Each transmitter carries data for only one channel in this

configuration.

TX–

NOTE: (1) Scientific Conversion SC982-04 or equivalent.

FIGURE 13. Recommended Transmitter Output Circuit for

Unbalanced, 75Ω Coaxial Cable Transmission.

DIT4192

18

SBOS229B

www.ti.com

Dual-Wire operation requires that each DIT4192 operates in

Mono mode, which is supported in both Software and Hard-

ware control modes. In Mono mode, the DIT4192 transmits

two consecutive samples of a single channel for both the

Channel A and Channel B sub-frames, effectively doubling

the sampling rate. The audio serial port channel used for

sampling audio and channel status data is selectable in both

Software and Hardware control modes.

as the source channel for audio and channel status data.

Refer to the register definition for details regarding the setting

of these bits.

In Hardware mode, the MONO (pin 21) and MDAT (pin 20)

inputs are used to enable mono mode, as well as selecting

the source channel for audio and channel status data.

Table IX shows the available options for MONO and MDAT

selection. Figure 15 illustrates a simple Hardware mode

configuration for implementing Dual-Channel operation using

two DIT4192 transmitters.

In Software mode, the MONO, MDAT, and MCSD bits in

control register 01_Hare used to select mono mode, as well

INPUT

MONO

FUNCTION

Stereo/Mono Mode Selection

MONO

Status

0

1

Stereo Mode

Mono Mode

MDAT

Mono Mode Audio and Channel Status Data Selection

MDAT

Status

0

1

Source is Left Channel for Audio data, and Channel A for CS data.

Source is Right Channel for Audio data, and Channel B for CS data.

TABLE IX. Mono Mode Configuration Settings for Hardware Mode Operation.

V_IO

21

20

11

12

13

14

MONO MDAT

SCLK

SYNC

SDATA

M/S

18

17

TX+

Right

Channel

Output

Circuit

DIT4192

TX–

(See Figs. 12-14)

DATA

LRCK

BCK

ADC

13

12

11

14

SDATA

SYNC

SCLK

M/S

18

17

TX+

Left

Channel

Output

Circuit

DIT4192

TX–

Master Clock

Generator

To All Devices

(See Figs. 12-14)

MONO MDAT

21

V_IO

20

NOTE: To simplify the drawing, not all pins are shown here.

FIGURE 15. Hardware Mode Example for Dual-Channel Transmitter Operation.

DIT4192

SBOS229B

19

www.ti.com

PACKAGE DRAWING

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

DIT4192

20

SBOS229B

www.ti.com

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DIT4192IPWR

TSSOP

PW

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 28

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

DIT4192IPWR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DIT4192_15
厂家：	TEXAS INSTRUMENTS
描述：	192kHz Digital Audio Transmitter
文件：	总28页 (文件大小：981K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DIT4192_15 [TI]

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