DIX4192TPFBRQ1 [TI]
汽车类集成式数字音频接口接收器和变送器 | PFB | 48 | -40 to 105;
| 型号： | DIX4192TPFBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类集成式数字音频接口接收器和变送器 | PFB | 48 | -40 to 105 |
| 文件： | 总69页 (文件大小：1243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
DIX4192-Q1 集成数字音频接口接收器和发送器
1 特性
•
四个通用数字输出
通过控制寄存器实现多功能可编程性
超长掉电支持
可以单独禁用不使用的功能块
–
1
•
•
适用于汽车电子 应用
具有符合 AEC-Q100 标准的下列结果：
•
–
–
器件温度等级：
•
•
由 1.8V 内核和 3.3V I/O 电源供电
–
–
DIX4192I-Q1：3 级（–40°C 至 +85°C）
DIX4192T-Q1：2 级（–40°C 至 +105°C）
小型 TQFP-48 封装，兼容 SRC4382 和 SRC4392
–
–
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
2
2 应用
•
汽车信息娱乐系统
器件组件充电模式 (CDM) ESD 分类等级 C4B
•
•
数字音频接口发送器 (DIT)
3 说明
–
–
–
将 PCM/编码数据转换为 S/PDIF 数据
最高支持 216kHz 的采样率
DIX4192-Q1 器件是一款高度集成的 CMOS 器件，适
用于专业和广播数字音频系统。DIX4192-Q1 将数字音
频接口接收器 (DIR) 和发送器 (DIT)、两个音频串行端
口以及用于功能块数据和时钟互连的灵活分布逻辑完美
结合。
包含差分线路驱动器和
CMOS 缓冲输出
数字音频接口接收器 (DIR)
–
–
将 S/PDIF 转换为立体声 PCM/编码数据
锁相环 (PLL) 锁定范围包括介于 20kHz 到
216kHz 之间的采样率
DIR 和 DIT 兼容 AES3、S/PDIF、IEC 60958 和 EIAJ
CP-1201 接口标准。音频串行端口和 DIT 能够以高达
216kHz 的采样率运行。DIR 锁定范围包括介于 20kHz
到 216kHz 之间的采样率。
–
–
四个差分输入线路接收器和一个输入多路复用器
旁路多路复用器将线路驱动器输出路由至线路驱
动器和缓冲区输出
器件信息(1)
–
自动检测非 PCM 音频流（DTS CD/LD 和 IEC
61937 格式）
器件型号
DIX4192-Q1
封装
TQFP (48)
封装尺寸（标称值）
7.00mm × 7.00mm
–
–
音频 CD Q 通道子代码解码和数据缓冲
(1) 要了解所有可用封装，请参阅数据表末尾的封装选项附录。
低抖动恢复时钟输出
用户可选的串行主机接口： SPI™或 I2C 的 16 位
•
•
DIX4192-Q1 典型应用
调光控制
Head Unit
Tuner
–
–
–
提供片上寄存器和数据缓冲区的访问权限
标记条件和错误条件的状态寄存器和中断生成
通道状态和用户数据的块大小数据缓冲区
S/PDIF TX
I2S/PCM/TDM
PCM1864-Q1
Line/Mic Input ADC
Jacinto Processor
and DSP
两个音频串行端口（端口 A 和 B）
I2S/PCM
I2C
–
用于外部信号处理器、数据转换器和逻辑的同步
串行接口
External Trunk Amplifier
S/PDIF IN
DIX4192-Q1
S/PDIF RX
S/PDIF OUT
–
–
–
采样率高达 216kHz 的主/从模式操作
支持左对齐、右对齐和飞利浦 I2S™数据格式
Copyright © 2017, Texas Instruments Incorporated
支持高达
24 位的音频数据字长
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBFS041
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
目录
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 23
9.5 Register Maps ........................................................ 26
10 Application and Implementation........................ 51
10.1 Application Information.......................................... 51
10.2 Typical Application ................................................ 58
11 Power Supply Recommendations ..................... 59
12 Layout................................................................... 60
12.1 Layout Guidelines ................................................. 60
12.2 Layout Example .................................................... 60
13 器件和文档支持 ..................................................... 61
13.1 器件支持................................................................ 61
13.2 文档支持................................................................ 61
13.3 接收文档更新通知 ................................................. 61
13.4 社区资源................................................................ 61
13.5 商标....................................................................... 62
13.6 静电放电警告......................................................... 62
13.7 Glossary................................................................ 62
14 机械、封装和可订购信息....................................... 62
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
8.1 Absolute Maximum Ratings ...................................... 5
8.2 ESD Ratings.............................................................. 6
8.3 Recommended Operating Conditions....................... 6
8.4 Thermal Information.................................................. 6
8.5 Electrical Characteristics........................................... 6
8.6 Timing Requirements................................................ 7
8.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 12
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (July 2016) to Revision A
Page
•
•
•
已添加 新的 T 版 DIX4192-Q1 到数据表 ................................................................................................................................ 1
已更改 Q1 认证 特性 项目以便显示更多信息，并从最后一项移到第一项 .............................................................................. 1
已更改 DIX4192IPFBR-Q1 特定器件名称为 DIX4192-Q1 一般器件名称，因为添加了新的 T 版器件；一般器件名称同
时适用于 I 版和 T 版器件........................................................................................................................................................ 1
•
•
•
Added ambient temperature range for new T-version device to Absolute Maximum Ratings table ...................................... 5
Added ambient operating temperature to Recommended Operating Conditions table.......................................................... 6
Changed fMCLK max value From: 2.27 To: 27.7 ..................................................................................................................... 6
2
版权 © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
5 说明 （续）
DIX4192-Q1 器件通过四线串行外设接口 (SPI) 端口或双线 I2C 总线接口存取的片上控制寄存器和数据缓冲器进行
配置。通过状态寄存器，可以访问来自不同功能块的各种标记和错误位。该器件提供了开漏中断输出引脚，该引脚
通过控制寄存器设置由灵活的中断报告和屏蔽选项提供支持。该器件还提供了主复位输入引脚，以供通过主机处理
器或监测功能进行初始化。
DIX4192-Q1 器件不仅需要一个 3.3V 电源来为部分 DIR、DIT 以及线路驱动器和接收器功能供电，还需要一个
1.8V 内核逻辑电源。单独的逻辑 I/O 电源支持在 1.65V 到 3.6V 范围内运行，且兼容通常位于数字信号处理器和可
编程逻辑器件上的低电压逻辑接口。
DIX4192-Q1 器件采用无铅的 TQFP-48 封装。
6 Device Comparison Table
PART NUMBER
1.8-V I/O
MULTI-CH PCM
ADC
PCM PORTS
S/PDIF PORTS
4 differential line in and 1
differential line out
DIX4192-Q1
Yes
No
No
2
Up to 12 single-ended in
and up to 2 single-ended
out
Up to 3 in and up to 3
out
PCM9211
DIX9211
No
No
Yes
Yes
Yes
No
Up to 12 single-ended in
and up to 2 single-ended
out
Up to 3 in and up to 3
out
Copyright © 2016–2017, Texas Instruments Incorporated
3
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
7 Pin Configuration and Functions
PFB Package
48-Pin TQFP
Top View
RX1+
RX1œ
RX2+
RX2œ
RX3+
RX3œ
RX4+
RX4œ
VCC
1
36
35
34
33
32
31
30
29
28
27
26
25
SYNC
BLS
2
3
AESOUT
VDD33
TX+
4
5
6
TXœ
7
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
8
9
AGND
LOCK
RXCKO
10
11
12
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AESOUT
AGND
34
10
37
48
44
35
20
21
22
18
19
16
30
43
26
27
28
O
GND
I/O
I/O
GND
I/O
I
DIT buffered AES3-encoded data
DIR comparator and PLL power-supply ground
Audio serial port A bit clock
BCKA
BCKB
Audio serial port B bit clock
BGND
Substrate ground, connect to AGND (pin 10)
DIT block start clock
BLS
Serial data clock for SPI mode or I2C mode
CCLK/SCL
CDIN/A1
CDOUT/SDA
CPM
SPI port serial data input or programmable slave address for I2C mode
SPI port serial data output (tri-state output) or serial data I/O for I2C mode
Control port mode, 0 = SPI mode, 1 = I2C mode
Chip select (active low) for SPI mode or programmable slave address for I2C mode
Digital core ground
I
I/O
I
CS/A0
I
DGND1
DGND2
DGND3
GPO1
GND
GND
GND
O
DIR line receiver bias and DIT line driver digital ground
Logic I/O ground
General-purpose output 1
GPO2
O
General-purpose output 2
GPO3
O
General-purpose output 3
(1) I = Input, O = Output, PWR = Power, GND = Ground
4
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
GPO4
INT
NO.
29
O
General-purpose output 4
23
O
Interrupt flag (open-drain, active low)
DIR PLL lock flag (active low)
Audio serial Port A left/right clock
Audio serial Port B left/right clock
Master clock
LOCK
LRCKA
LRCKB
MCLK
NC
11
O
38
I/O
47
I/O
25
I
14, 15, 41
—
No internal signal connection, internally bonded to ESD pad
Reset (active low)
RST
24
1
I
RX1+
RX1–
RX2+
RX2–
RX3+
RX3–
RX4+
RX4–
RXCKI
RXCKO
SDINA
SDINB
SDOUTA
SDOUTB
SYNC
TX+
I
Line receiver 1, noninverting input
Line receiver 1, inverting input
2
I
3
I
Line receiver 2, noninverting input
Line receiver 2, inverting input
4
I
5
I
Line receiver 3, noninverting input
Line receiver 3, inverting input
6
I
7
I
Line receiver 4, noninverting input
Line receiver 4, inverting input
8
I
13
12
39
46
40
45
36
32
31
9
I
O
DIR reference clock
DIR recovered master clock (tri-state output)
Audio serial Port A data input
I
I
Audio serial Port B data input
O
Audio serial Port A data output
O
Audio serial Port B data output
O
DIT internal sync clock
O
DIT line driver noninverting output
DIT line driver inverting output
TX–
O
VCC
PWR
PWR
PWR
PWR
DIR comparator and PLL power supply, 3.3-V nominal
Digital core supply, 1.8-V nominal
DIR line receiver bias and DIT line driver supply, 3.3-V nominal
Logic I/O supply, 1.65 V to 3.6 V
VDD18
VDD33
VIO
17
33
42
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
VDD18
2
4
4
4
VDD33
Power supply
VIO
V
VCC
RXCKI, CPM, CS, CCLK, CDIN, CDOUT, INT, RST,
Digital input voltage: digital logic
MCLK, BLS, SYNC, BCKA, BCKB, LRCKA, LRCKB,
SDINA, SDINB
–0.3
(VIO + 0.3)
V
Line receiver input voltage (per pin)
RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–
(VDD33 + 0.3)
VPP
mA
Input current (all pins except power and ground)
±10
85
DIX4192I-Q1
DIX4192T-Q1
–40
–40
–65
Ambient operating temperature, TA
Storage temperature, Tstg
°C
°C
105
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2016–2017, Texas Instruments Incorporated
5
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 12, 13,
24, 25, 36, 37, and 48)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
3
NOM
1.8
MAX
1.95
3.6
UNIT
VDD18
VDD33
VCC
1.8-V power-supply voltage
V
V
V
V
3.3-V power-supply voltage
3.3
DIR comparator and PLL power-supply voltage
Logic I/O power-supply voltage
3
3.3
3.6
VIO
1.65
–40
–40
3.3
3.6
DIX4192I-Q1
DIX4192T-Q1
85
TA
Ambient operating temperature
°C
105
8.4 Thermal Information
DIX4192-Q1
PFB (TQFP)
48 PINS
62.0
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
12.8
27.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
ψJB
27.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
all specifications are at TA = 25°C, VDD18 = 1.8 V, VDD33 = 3.3 V, VIO = 3.3 V, and VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL I/O CHARACTERISTICS (ALL I/O PINS EXCEPT LINE RECEIVERS AND LINE DRIVER)
VIH
VIL
High-level input voltage
Low-level input voltage
0.7 × VIO
0
VIO
0.3 × VIO
30
V
V
IO = –4 mA, MUTE, SDINA, and SDINB pins
IO = –4 mA, all other pins
IO = 4 mA
0.5
0.5
0.5
IIH
High-level input current
μA
10
IIL
Low-level input current
High-level output voltage
Low-level output voltage
Input capacitance
10
μA
V
VOH
VOL
CIN
0.8 × VIO
0
VIO
0.2 × VIO
V
3
pF
LINE RECEIVER INPUTS (RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–)
VTH
VHY
Differential input sensitivity
Input hysteresis
150
200
mV
mV
Voltage across a given differential input pair
150
5.4
LINE DRIVER OUTPUTS (TX+, TX–)
VTXO Differential output voltage
MASTER CLOCK INPUT
RL = 110 Ω across TX+ and TX–
VPP
fMCLK
Master clock input (MCLK) frequency
Master clock input (MCLK) duty cycle
1
27.7
55%
MHz
fMCLKD
45%
DIGITAL AUDIO INTERFACE RECEIVER (DIR)
6
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
Electrical Characteristics (continued)
all specifications are at TA = 25°C, VDD18 = 1.8 V, VDD33 = 3.3 V, VIO = 3.3 V, and VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
20
216
PLL lock range
kHz
TA = 85°C or 105°C
24
216
fRXCKI
fRXCKID Reference clock input (RXCKI) duty cycle
fRXCKO Recovered clock output (RXCKO) frequency
Reference clock input (RXCKI) frequency
3.5
27.7
55%
27.7
55%
MHz
45%
3.5
MHz
fRXCKOD Recovered clock output (RXCKO) duty cycle
45%
Recovered clock output (RXCKO) intrinsic
jitter
Measured cycle-to-cycle
Measured cycle-to-cycle
250
200
ps RMS
ps RMS
DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)
Intrinsic output jitter
POWER SUPPLIES
All blocks powered down by default
VDD18 = 1.8 V
IDD18S
10
10
Supply current: initial startup
Supply current: quiescent
IDD33S
IIOS
VDD33 = 3.3 V
μA
mA
mA
mA
VIO = 3.3 V
300
10
ICCS
VCC = 3.3 V
All blocks powered up with no clocks applied
VDD18 = 1.8 V
IDD18Q
IDD33Q
IIOQ
2.3
0.6
0.3
6.3
VDD33 = 3.3 V
VIO = 3.3 V
ICCQ
VCC = 3.3 V
All blocks powered up, fS = 48 kHz
VDD18 = 1.8 V
IDD18D
IDD33D
IIOD(1)
ICCD
5.1
14.1
46
Supply current: dynamic
VDD33 = 3.3 V
VIO = 3.3 V
VCC = 3.3 V
7.4
All blocks powered up, fS = 192 kHz
VDD18 = 1.8 V
IDD18H
IDD33H
IIOH(1)
ICCH
6.7
15
Supply current: high sampling rate
VDD33 = 3.3 V
VIO = 3.3 V
47
VCC = 3.3 V
7.5
1
Total power dissipation: initial startup
Total power dissipation: quiescent
Total power dissipation: dynamic
All blocks powered down by default
All blocks powered up with no clocks applied
All blocks powered up, fS = 48 kHz
All blocks powered up, fS = 192 kHz
mW
mW
mW
mW
28
233
242
Total power dissipation: high sampling rate
(1) The typical VIO supply current is measured using the DIX4192-Q1EVM evaluation module with loading from the DAIMB motherboard
circuitry. VIO supply current is dependent upon the loading on the logic output pins.
8.6 Timing Requirements
MIN
NOM
MAX
216
UNIT
AUDIO SERIAL PORTS (PORT A AND PORT B)
fLRCK
tLRCKD
fBCK
LRCK clock frequency
0
kHz
LRCK clock duty cycle
50%
BCK clock frequency
0
10
10
10
10
13.824
MHz
ns
tBCKH
tBCKL
tAIS
BCK high pulse duration
BCK low pulse duration
ns
Audio data Input (SDIN) set-up time
Audio data input (SDIN) hold time
Audio data output (SDOUT) delay
ns
tAISH
tADD
ns
10
ns
Copyright © 2016–2017, Texas Instruments Incorporated
7
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
UNIT
Timing Requirements (continued)
MIN
NOM
MAX
HOST INTERFACE: SPI MODE
fCCLK
tCSCR
tCFCS
tCDS
Serial clock (CCLK) frequency
CS falling to CCLK rising
0
8
7
7
6
40
MHz
ns
CCLK falling to CS rising
ns
CDIN data set-up time
ns
tCDH
CDIN data hold time
ns
tCFDO
tCSZ
CCLK falling to CDOUT data valid
CS rising to CDOUT high-impedance
3
3
ns
ns
HOST INTERFACE: I2C STANDARD MODE(1)
fSCL
SCL clock frequency
0
4
100
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
pF
V
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Hold time repeated START condition
Low period of SCL clock
4.7
4
High period of SCL clock
Set-up time repeated START condition
Data hold time
4.7
0(2)
250
3.45(3)
Data set-up time
Rise time for both SDA and SDL
Fall time for both SDA and SDL
Set-up time for STOP condition
Bus free time between START and STOP
Capacitive load for each bus line
Noise margin at low level (including hysteresis)
Noise margin at high level (including hysteresis)
1000
300
tF
tSUSTO
tBUF
4
4.7
CB
400
400
VNL
0.1 × VIO
0.2 × VIO
VNH
V
HOST INTERFACE: I2C FAST MODE(1)
fSCL
SCL clock frequency
0
0.6
1.3
0.6
0.6
0(2)
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
ns
pF
V
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Hold time repeated START condition
Low period of SCL clock
High period of SCL clock
Set-up time repeated START condition
Data hold time
0.9(3)
Data set-up time
100(4)
(5)
Rise time for both SDA and SDL
Fall time for both SDA and SDL
Set-up time for STOP condition
Bus free time between START and STOP
Spike pulse duration suppressed by input filter
Capacitive load for each bus Line
Noise margin at low level (including hysteresis)
Noise margin at high level (including hysteresis)
20 + 0.2CB
300
300
(5)
tF
20 + 0.2CB
tSUSTO
tBUF
tSP
0.6
1.3
0
50
CB
400
VNL
0.1 × VIO
0.2 × VIO
VNH
V
(1) All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of this table.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum input level) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal.
(4) A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement that tSUDAT be 250 ns (minimum)
must then be met. For the DIX4192-Q1, this condition is automatically the case, because the device does not stretch the Low period of
the SCL signal.
(5) CB is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are
allowed.
8
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LRCK
tBCKH
BCK
tAIS
tBCKL
SDIN
tAIH
tAOD
SDOUT
Figure 1. Audio Serial Port Timing
tCFCS
CS
tCSCR
tCDS
CCLK
CDIN
tCDH
Hi Z
Hi Z
tCSZ
CDOUT
tCFDO
Figure 2. SPI Timing
tF
SDA
tSUDAT
tHDSTA
tSP
tR
tBUF
tLOW
tR
tF
SCL
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tHIGH
S
R
P
S
S = Start Condition
R = Repeated Start Condition
P = Stop Condition
Figure 3. I2C Standard and Fast Mode Timing
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8.7 Typical Characteristics
2
0
-10
-20
5
2
Input Jitter Amplitude
-30
1
-2
-40
Output Jitter Amplitude
500m
200m
100m
50m
20m
10m
5m
-4
-50
-60
-6
-70
-8
-80
-10
-12
-14
-16
-18
-20
-90
-100
-110
-120
-130
-140
-150
THD+N
2m
1m
100
101
102
Jitter Frequency (Hz)
103
104
105
106
20
100
1k
10k
100k
Sinusoidal Jitter Frequency (Hz)
Figure 5. DIR Jitter Tolerance Plot
Figure 4. DIR Jitter Attenuation Characteristics
10
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9 Detailed Description
9.1 Overview
The DIX4192-Q1 is an integrated digital audio interface receiver and transmitter (DIR and DIT). Two audio serial
ports, Port A and Port B, support input and output interfacing to external data converters, signal processors, and
logic devices. On-chip routing logic provides for flexible interconnection between the four functional blocks. The
audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR is specified for a PLL lock
range that includes sampling rates from 20 kHz to 216 kHz. All function blocks support audio data word lengths
up to 24 bits.
The DIX4192-Q1 requires an external host processor or logic for configuration control. The DIX4192-Q1 includes
a user-selectable serial host interface, which operates as either a 4-wire serial peripheral interface (SPI) port or a
2-wire Philips I2C bus interface. The SPI port operates at bit rates up to 40 MHz. The I2C bus interface may be
operated in standard or fast modes, supporting operation at 100 kbps and 400 kbps, respectively. The SPI and
I2C interfaces provide access to internal control and status registers, as well as the buffers used for the DIR and
DIT channel status and user data.
The digital interface receiver (DIR) includes four differential input line receiver circuits, suitable for balanced or
unbalanced cable interfaces. Interfacing to optical receiver modules and CMOS logic devices is also supported.
The outputs of the line receivers are connected to a 1-of-4 data selector, referred to as the receiver input
multiplexer, which is used to select one of the four line receiver outputs for processing by the DIR core. The
outputs of the line receivers are also connected to a second data selector, the bypass multiplexer, which may be
used to route input data streams to the DIT CMOS output buffer and differential line driver functions. This
configuration provides a bypass signal path for AES3-encoded input data streams.
The DIR core decodes the selected input stream data and separates the audio, channel status, user, validity, and
parity data. Channel status and user data is stored in block-sized buffers, which may be accessed through the
SPI or I2C serial host interface, or routed directly to the general-purpose output pins (GPO1 through GPO4). The
validity and parity bits are processed to determine error status. The DIR core recovers a low jitter master clock,
which may be used to generate word and bit clocks using on-chip or external logic circuitry.
The digital interface transmitter (DIT) encodes digital audio input data into an AES3-formatted output data
stream. Two DIT outputs are provided, including a differential line driver and a CMOS output buffer. Both the line
driver and buffer include 1-of-2 input data selectors, which are used to choose either the output of the DIT AES3
encoder, or the output of the bypass multiplexer. The line driver output is suitable for balanced or unbalanced
cable interfaces, while the CMOS output buffer supports interfacing to optical transmitter modules and external
logic or line drivers. The DIT includes block-sized data buffers for both channel status and user data. These
buffers are accessed through either the SPI or I2C host interface, or may be loaded directly from the DIR channel
status and user data buffers.
The DIX4192-Q1 includes four general-purpose digital outputs, or GPO pins. The GPO pins may be configured
as simple logic outputs, which may be programmed to either a low or high state. Alternatively, the GPO pins may
be connected to one of 13 internal logic nodes, allowing them to serve as functional, status, or interrupt outputs.
The GPO pins provide added utility in applications where hardware access to selected internal logic signals may
be necessary.
Functional Block Diagram shows a simplified functional block diagram for the DIX4192-Q1. Additional details for
each function block will be covered in respective sections of this data sheet.
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9.2 Functional Block Diagram
TI Device
CPM
SDINA
CS or A0
CCLK or SCL
CDIN or A1
CDOUT or SDA
INT
RST
GPO1
GPO2
GPO3
GPO4
Host
Interface
(SPI or I2C)
and
SDOUTA
LRCKA
BCKA
Audio Serial
Port A
General-
Purpose
Outputs
SDINB
SDOUTB
LRCKB
BCKB
Audio Serial
Port B
Control and Status
Registers
RXCKO
LOCK
DIR C and U
Data Buffers
RX1+
RX1-
RX2+
DIT C and U
Data Buffers
Digital
Interface
Receiver (DIR)
RX2-
RX3+
MCLK
Master
Clock
Distribution
RXCKI
From RXCKO
RX3-
RX4+
RX4-
TX+
TX-
Digital
Interface
Transmitter
(DIT)
AESOUT
VDD18
DGND1
VDD33
DGND2
VIO
BLS
SYNC
Power
DGND3
VCC
AGND
Internally Tied
to Substrate
BGND
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9.3 Feature Description
9.3.1 RESET Operation
The DIX4192-Q1 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize
the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The
reset low pulse duration must be a minimum of 500 ns in length. The user must not attempt a write or read
operation using either the SPI or I2C port for at least 500 μs after the rising edge of RST. See Figure 6 for the
reset timing sequence of the DIX4192-Q1.
In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby
all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the
RESET bit function.
Upon reset initialization, all functional blocks of the DIX4192-Q1 default to the power-down state, with the
exception of the SPI or I2C host interface and the corresponding control registers. The user may then program
the DIX4192-Q1 to the desired configuration, and release the desired function blocks from the power-down state
using the corresponding bits in control register 0x01.
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Feature Description (continued)
Write or Read
via
SPI or I2C
1
RST
0
500ns (min)
500ms (min)
Figure 6. Reset Sequence Timing
9.3.2 Master and Reference Clocks
The DIX4192-Q1 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically
used as the master clock source for the audio serial ports and/or the DIT. The MCLK may also be used as the
reference clock for the DIR. The RXCKI clock input is typically used for the DIR reference clock source, although
it may also be used as the master or reference clock source for the audio serial ports.
In addition to the MCLK and RXCKI clock sources, the DIR core recovers a master clock from the AES3-
encoded input data stream. This clock is suitable for use as a master or system clock source in many
applications. The recovered master clock output, RXCKO (pin 12), may be used as the master or reference clock
source for the audio serial ports and the DIT, as well as external audio devices.
The master clock frequency for the audio serial ports (Port A and Port B) depends on the Slave or Master mode
configuration of the port. In Slave mode, the ports do not require a master clock because the left/right word and
bit clocks are inputs, sourced from an external audio device serving as the serial bus timing master. In Master
mode, the serial ports derive the left/right word and bit clock outputs from the selected master clock source,
MCLK, RXCKI, or RXCKO. The left/right word clock rate is derived from the selected master clock source using
one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to Audio Serial Port Operation for
additional details.
The DIT always requires a master clock source, which may be either the MCLK input, or the DIR recovered clock
output, RXCKO. Like the audio serial ports, the DIT output frame rate is derived from the selected master clock
using one of four clock divider settings (divide-by-128, -256, -384, or -512). Refer to Digital Interface Transmitter
(DIT) Operation for additional details.
The DIR reference clock may be any frequency that meets the PLL1 set-up requirements, described in Control
Registers. Typically, a common audio system clock rate, such as 11.2896 MHz, 12.288 MHz, 22.5792 MHz, or
24.576 MHz, may be used for this clock.
TI recommends that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for
optimal performance. In general, phase-locked loop (PLL) clock synthesizers must be avoided, unless they are
designed or specified for low clock jitter.
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Feature Description (continued)
9.3.3 Audio Serial Port Operation
The DIX4192-Q1 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial
interfaces, supporting simultaneous input and output operation. Because each port has only one pair of left or
right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in
Figure 7.
The audio serial ports may be operated at sampling rates up to 216 kHz, and support audio data word lengths up
to 24 bits. Philips I2S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 8.
The left or right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either
Master or Slave mode operation. In Master mode, these clocks are outputs, derived from the selected master
clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio
input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave
mode the left or right word and bit clocks are inputs, and are sourced from an external audio device acting as the
serial bus master.
The LRCKA or LRCKB clocks operate at the input and output sampling rate, fS. The BCKA and BCKB clock rates
are fixed at 64 times the left or right word clock rate in Master mode. For Slave mode, the minimum BCKA and
BCKB clock rate is determined by the audio data word length multiplied by two, because there are two audio
data channels per left or right word clock period. For example, if the audio data word length is 24 bits, the bit
clock rate must be at least 48 times the left or right word clock rate, allowing one bit clock period for each data bit
in the serial bit stream.
Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port
on the falling edge of the bit clock. Refer to the Audio Serial Ports section of the Electrical Characteristics table
for parametric information and Figure 1 for a timing diagram related to audio serial port operation.
The audio serial ports are configured using control registers 0x03 through 0x06. Refer to Control Registers for
descriptions of the control register bits.
CLK[1:0]
M/S
DIV[1:0]
MCLK
RXCKI
Master
Master
Clock
Source
Mode
Clock
Generation
RXCKO
SDINA (pin 39) or SDINB (pin 46)
LRCKA (pin 38) or LRCKB (pin 47)
BCKA (pin 37) or BCKB (pin 48)
Audio Data
Serial
Input
Internal Clocks
Port A
Serial
Output
Data
Source
Port B
DIR
SDOUTA (pin 40) or SDOUTB (pin 45)
OUTS[1:0]
MUTE
FMT[1:0]
Figure 7. Audio Serial Port Block Diagram
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Feature Description (continued)
Channel 1 (Left Channel)
Channel 2 (Right Channel)
LRCKA
LRCKB
BCKA
BCKB
Audio
Data
MSB
LSB
MSB
LSB
(a) Left-Justified Data Format
LRCKA
LRCKB
BCKA
BCKB
Audio
Data
MSB
LSB
MSB
LSB
(b) Right-Justified Data Format
LRCKA
LRCKB
BCKA
BCKB
Audio
Data
MSB
LSB
MSB
LSB
(c) I2S Data Format
1/fs
Figure 8. Audio Data Formats
9.3.4 Overview of the AES3 Digital Audio Interface Protocol
This section introduces the basics of digital audio interface protocols pertaining to the transmitter (DIT) and
receiver (DIR) blocks of the DIX4192-Q1. Emphasis is placed upon defining the basic terminology and
characteristics associated with the AES3-2003 standard protocol, the principles of which may also be applied to
a number of consumer-interface variations, including S/PDIF, IEC-60958, and EIAJ CP-1201. It is assumed that
the reader is familiar with the AES3 and S/PDIF interface formats. Additional information is available from the
sources listed in the 开发支持 section.
The AES3-2003 standard defines a technique for two-channel linear PCM data transmission over 110-Ω shielded
twisted-pair cable. The AES-3id document extends the AES3 interface to applications employing 75-Ω coaxial
cable connections. In addition, consumer transmission variants, such as those defined by the S/PDIF, IEC
60958, and CP-1201 standards, use the same encoding techniques but with different physical interfaces or
transmission media. Channel status data definitions also vary between professional and consumer interface
implementations.
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Feature Description (continued)
For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and
status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio).
Figure 9 shows the AES3 frame and subframe formatting. Each subframe includes four bits for the preamble, up
to 24 bits for audio and/or auxiliary data, one bit indicating data validity (V), one bit for channel status data (C),
one bit for user data (U), and one bit for setting parity (P).
The 4-bit preamble is used for synchronization and identification of blocks and subframes. The X and Y preamble
codes are used to identify the start of the Channel 1 and Channel 2 subframes, as shown in Figure 9. However,
the X preamble for the first subframe of every 192 frames is replaced by the Z preamble, which identifies the
start of a new block of channel status and user data.
Block Start
Frame 191
Frame 0
Y
Frame 1
Y
X
Channel 1
Y
Channel 2
Z
Channel 1
Channel 2
X
Channel 1
Channel 2
One Sub Frame
Bits: 0
3 4
7 8
27 28 29 30 31
MSB
Audio or
Aux Data
Preamble
Audio Data
V U C P
Validity Bit
User Data
Channel Status Data
Parity Bit
Figure 9. AES3 Frame and Subframe Encoding
One block is comprised of 192 frames of data. This format translates to 192 bits each for channel status and
user data for each channel. The 192 bits are organized into 24 data bytes, which are defined by the AES3-2003
and consumer standards documents. The AES18 standard defines recommended usage and formatting of the
user data bits, while consumer applications may use the user data for other purposes. The DIX4192-Q1 also
includes block-sized transmitter and receiver channel status and user data buffers, which have 24 bytes each for
the channel status and user data assigned to audio Channels 1 and 2. Refer to Channel Status and User Data
Buffer Maps for the organization of the buffered channel status and user data for the receiver and transmitter
functions.
The audio data for Channel 1 and Channel 2 may be up to 24 bits in length, and occupies bits 4 through 27 of
the corresponding subframe. Bit 4 is the LSB while bit 27 is the MSB. If only 20 bits are required for audio data,
then bits 8 through 27 are used for audio data, while bits 4 though 7 are used for auxiliary data bits.
The validity (V) bit indicates whether or not the audio sample word being transmitted is suitable for digital-to-
analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity bit is 0,
then the audio sample is suitable for conversion or additional processing. If the validity bit is 1, then the audio
sample is not suitable for conversion or additional processing.
The parity (P) bit is set to either a 0 or 1, such that bits 4 through 31 carry an even number of ones and zeros for
even parity. The DIT block in the DIX4192-Q1 automatically manages the parity bit, setting it to a 0 or 1 as
required. The DIR block checks the parity of bits 4 though 31 and generates a parity error if odd parity is
detected.
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Feature Description (continued)
The binary non-return to zero (NRZ) formatted audio and status source data for bits 4 through 31 of each
subframe are encoded using a Biphase Mark format for transmission. This format allows for clock recovery at the
receiver end, as well as making the interface insensitive to the polarity of the balanced cable connections. The
preambles at the start of each subframe are encoded to intentionally violate the Biphase Mark formatting, making
their detection by the receiver reliable, as well as avoiding the possibility of audio and status data imitating the
preambles. Figure 10 shows the Biphase Mark and preamble encoding.
Although the AES3 standard originally defined transmission for sampling rates up to 48 kHz, the interface is
capable of handling higher sampling rates, given that attention is paid to cable length and impedance matching.
Equalization at the receiver may also be required, depending on the cable and matching factors. It is also
possible to transmit and decode more than two channels of audio data using the AES3 or related consumer
interfaces. Special encoding and compression algorithms are used to support multiple channels, including the
Dolby® AC-3, DTS, MPEG-1/2, and other data reduced audio formats.
Clock
(2x Source Bit Rate)
1
0
Source Data Coding
(NRZ)
Insert Preamble
Code Below
1
0
AES3 Channel Coding
(Biphase Mark)
Preamble Z (Block Start)
Preceding state, from the Parity bit of the previous frame.
Preamble Coding
Preceding state:
0
1
Preamble:
Channel coding:
11100010
11100100
Channel coding:
00011101
00011011
Description:
X
Y
Z
Channel 1 subframe
Channel 2 subframe
Channel 1 subframe and block start
11101000
00010111
Figure 10. Biphase Mark Encoding
9.3.5 Digital Interface Transmitter (DIT) Operation
The DIT encodes a given two-channel or data-reduced audio input stream into an AES3-encoded output stream.
In addition to the encoding function, the DIT includes differential line driver and CMOS-buffered output functions.
The line driver is suitable for driving balanced or unbalanced line interfaces, while the CMOS-buffered output is
designed to drive external logic or line drivers, as well as optical transmitter modules. Figure 11 shows the
functional block diagram for the DIT.
The input of the DIT receives the audio data for Channels 1 and 2 from one of three possible sources: Port A,
Port B, or the DIR. By default Port A is selected as the source. The DIT also requires a master clock source,
which may be provided by either the MCLK input (pin 25) or RXCKO (the DIR recovered master clock output). A
master clock divider is used to select the frame rate for the AES3-encoded output data. The TXDIV[1:0] bits in
control register 0x07 are used to select divide by 128, 256, 384, or 512 operation.
Channel status and user data for Channels 1 and 2 are input to the AES3 encoder through the corresponding
Transmitter Access (TA) data buffers. The TA data buffers are in turn loaded from the User Access (UA) buffers,
which are programmed through the SPI or I2C host interface, or loaded from the DIR Receiver Access (RA) data
buffers. The source of the channel status and user data is selected using the TXCUS[1:0] bits in control register
0x09. When the DIR is selected as the input source, the channel status and user data output from the DIT is
delayed by one block in relation to the audio data.
The validity (V) bit may be programmed using one of two sources. The VALSEL bit in control register 0x09 is
used to select the validity data source for the DIT block. The default source is the VALID bit in control register
0x07, which is written through the SPI or I2C host interface. The validity bit may also be transferred from the
AES3 decoder output of the DIR, where the V bit for the DIT subframes tracks the decoded DIR value frame by
frame.
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Feature Description (continued)
The Parity (P) bit will always be generated by the AES3 encoder internal parity generator logic, such that bits 4
through 31 of the AES3-encoded subframe are even parity.
The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers. As shown
in Figure 11, the source multiplexers allow the line driver or buffer to be driven by the AES3-encoded data from
the DIT, or by the bypass multiplexer, which is associated with the outputs of the four differential input line
receivers preceding the DIR core. The bypass multiplexer allows for one of the four line receiver outputs to be
routed to the line driver or buffer output, thereby providing a bypass mode of operation. Both the line driver and
CMOS output buffer include output disables, set by the TXOFF and AESOFF bits in control register 0x08. When
the outputs are disabled, they are forced to a low logic state.
The AES3 encoder includes an output mute function that sets all bits for both the Channel 1 and 2 audio and
auxiliary data to zero. The preamble, V, U, and C bits are unaffected, while the P bit is recalculated. The mute
function is controlled using the TXMUTE bit in control register 0x08.
TXDIV[1:0]
TXCLK
Master
Clock
Source
MCLK
AESMUX
AESOFF
RXCKO
AESOUT
(pin 34)
TXIS[1:0]
Port A
Port B
DIR
LDMUX
TXOFF
Data
Source
TX+ (pin 32)
AES3
Encoder
User Access
(UA) Buffers
Transmitter Access
(TA) Buffers
TX- (pin 31)
From Receiver
Access (RA) Buffer
To/From SPI or I2C
Host Interface
From
Bypass
Channel
Status
Channel
Status
Multiplexer
Output
From Receiver
Access (RA) Buffer
To/From SPI or I2C
Host Interface
BLS (pin 35)
SYNC (pin 36)
User
Data
User
Data
TXCUS[1:0] TXBTD
TXMUTE
BLSM
Figure 11. Digital Interface Transmitter (DIT) Functional Block Diagram
The AES3 encoder includes a block start input/output pin, BLS (pin 35). The BLS pin may be programmed as an
input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07.
By default, the BLS pin is configured as an input.
As an input, the BLS pin may be used to force a block start condition, whereby the start of a new block of
channel status and user data is initiated by generating a Z preamble for the next frame of data. The BLS input
must be synchronized with the DIT internal SYNC clock. This clock is output on SYNC (pin 36). The SYNC clock
rising edge is aligned with the start of each frame for the AES3-encoded data output by the DIT. Figure 12 shows
the format required for an external block start signal, as well as indicating the format when the BLS pin is
configured as an output. When the BLS pin is an output, the DIT generates the block start signal based upon the
internal SYNC clock.
For details regarding DIT control and status registers, as well as channel status and user data buffers, refer to
Control Registers and Channel Status and User Data Buffer Maps.
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Feature Description (continued)
Block Start
(Frame 0 starts here)
SYNC
BLS
(input)
BLS
(output)
Figure 12. DIT Block Start Timing
9.3.6 Digital Interface Receiver (DIR) Operation
The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The
lock range of the DIR includes frame and sampling rates from 20 kHz to 216 kHz. Figure 13 shows the functional
block diagram for the DIR.
Four differential line receivers are used for signal conditioning the encoded input data streams. The receivers can
be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with CMOS
logic level inputs from optical receivers or external logic circuitry. See Figure 14 for a simplified schematic for the
line receiver. External connections are discussed in Receiver Input Interfacing.
To SPI or I2C Host Interface
Reference
Clock
Source
MCLK
RXCKI
Channel
Status
User
Data
User Access
(UA) Buffers
PLL1
To
DIT
To
DIT
RXCLK
RX1+ (pin 1)
RXMUX[1:0]
Channel
Status
User
Data
AES3
Decoder
RX1- (pin 2)
Receiver
Access
(RA) Buffers
RX2+ (pin 3)
RX2- (pin 4)
RX3+ (pin 5)
RX3- (pin 6)
Pulse
Generator
Data Stream
De-Mux
Error and
Status Outputs
RX4+ (pin 7)
RX4- (pin 8)
To DIT Buffer
and Line Driver
BYPMUX[1:0]
PLL2
128fS
256fS
512fS
Ch.1
(Left) (Right)
Audio Audio
Ch.2
LOCK
(pin 11)
Clock
Receiver
Sync
Generator
RXCKO
(pin 12)
Divider
Divide by
1, 2, 4, or 8
RXCKOF[1:0]
RCV_SYNC
RXCKO
Figure 13. Digital Interface Receiver (DIR) Functional Block Diagram
Copyright © 2016–2017, Texas Instruments Incorporated
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Feature Description (continued)
VDD33
24 kꢀ
24 kꢀ
3 kꢀ
RX+
+
To Receiver Input
3 kꢀ
RXœ
and Bypass Multiplexers
œ
24 kꢀ
24 kꢀ
DGND2
Figure 14. Differential Line Receiver Circuit
The outputs of the four line receivers are connected to two 1-of-4 data selectors: the receiver input multiplexer
and the bypass multiplexer. The input multiplexer selects one of the four line receiver outputs as the source for
the AES3-encoded data stream to be processed by the DIR core. The bypass multiplexer is used to route a line
receiver output to either the DIT line driver or CMOS-buffered outputs, thereby bypassing all other internal
circuitry. The bypass function is useful for simple signal distribution and routing applications.
The DIR requires a reference clock, supplied by an external source applied at either the RXCKI (pin 13) or MCLK
(pin 25) clock inputs. PLL1 multiplies the reference clock to a higher rate, which is used as the oversampling
clock for the AES3 decoder. The decoder samples the AES3-encoded input stream in order to extract all of the
audio and status data. The decoded data stream is sent on to a de-multiplexer, where audio and status data are
separated for further processing and buffering. The pulse generator circuitry samples the encoded input data
stream and generates a clock that is 16 times the frame/sampling rate (or fS). The 16 fS clock is then processed
by PLL2, which further multiplies the clock rate and provides low-pass filtering for jitter attenuation. The available
PLL2 output clock rates include 512 fS, 256 fS, and 128 fS. The maximum available PLL2 output clock rate for a
given input sampling rate is estimated by internal logic and made available for readback through status register
0x13.
The output of PLL2 may be divided by a factor of two, four, or eight, or simply passed through to the recovered
master clock output, RXCKO (pin 12). The RXCKO clock may also be routed internally to other function blocks,
where it may be further divided to create left/right word and bit clocks. The RXCKO output may be disabled and
forced to a high-impedance state by means of a control register bit, allowing other tri-state buffered clocks to be
tied to the same external circuit node, if required. By default, the RXCKO output (pin 12) is disabled and forced
to a high-impedance state.
Figure 15 shows the frequency response of PLL2. Jitter attenuation starts at approximately 50 kHz. Peaking is
nominally 1 dB, which is within the 2 dB maximum allowed by the AES3 standard. The receiver jitter tolerance
plot for the DIR is shown in Figure 16, along with the required AES3 jitter tolerance template. The DIR jitter
tolerance satisfies the AES3 requirements, as well as the requirements set forth by the IEC60958-3 specification.
Figure 16 was captured using a full-scale 24-bit, two-channel, AES3-encoded input stream with a 48kHz frame
rate.
The decoded audio data, along with the internally-generated sync clocks, may be routed to other function blocks,
including Port A, Port B, and the DIT. The decoded channel status and user data are buffered in the
corresponding Receiver Access (RA) data buffers, then transferred to the corresponding User Access (UA) data
buffers, where it may be read back through either the SPI or I2C serial host interface. The contents of the RA
buffers may also be transferred to the DIT UA data buffers; this transfer is shown in Figure 11. The channel
status and user data bits may also be output serially through the general-purpose output pins, GPO[4:1].
Figure 17 shows the output format for the GPO pins when used for this purpose, along with the DIR block start
(BLS) and frame synchronization (SYNC) clocks. The rising edges of the DIR SYNC clock output are aligned with
the start of each frame for the received AES3 data.
20
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Feature Description (continued)
The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock
output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags
may be output at the general-purpose output (GPO) pins, or accessed through the status registers through the
SPI or I2C host interface. Refer to General-Purpose Digital Outputs and Control Registers for additional
information regarding the DIR status functions.
2
0
-10
-20
5
2
Input Jitter Amplitude
-30
-2
1
-40
Output Jitter Amplitude
-4
500m
200m
100m
50m
20m
10m
5m
-50
-60
-6
-70
-8
-80
-10
-12
-14
-16
-18
-20
-90
-100
-110
-120
-130
-140
-150
THD+N
2m
1m
100
101
102
103
104
105
106
20
100
1k
10k
100k
Jitter Frequency (Hz)
Sinusoidal Jitter Frequency (Hz)
Figure 15. DIR Jitter Attenuation Characteristics
Figure 16. DIR Jitter Tolerance Plot
Block Start
(Frame 0 Starts Here)
BLS
(output)
SYNC
(output)
C or U data
(output)
Ch. 1 Ch. 2 Ch. 1 Ch. 2 Ch. 1 Ch. 2 Ch. 1 Ch. 2
Bit 0
Bit 1
Bit 2
Bit 4
¼
Figure 17. DIR Channel Status and User Data Serial Output Format Through the GPO Pins
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Feature Description (continued)
9.3.7 General-Purpose Digital Outputs
The DIX4192-Q1 includes four general-purpose digital outputs, GPO1 through GPO4 (pins 26 through 29,
respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be
connected to one of 13 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal.
Control registers 0x1B through 0x1E are used to select the function of the GPO pins. For details regarding GPO
output configuration, refer to Control Registers. Table 1 summarizes the available output options for the GPO
pins.
Table 1. General-Purpose Output Pin Configurations
GPOn3
GPOn2
GPOn1
GPOn0
GPOn FUNCTION
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPOn is forced low (default)
GPOn is forced high
Reserved
DIT interrupt flag; active low
DIR interrupt flag; active low
DIR 50/15-μs emphasis flag; active low
DIR non-audio data flag; active high
DIR non-valid data flag; active high
DIR channel status data serial output
DIR user data serial output
DIR block start clock output
DIR COPY bit output
(0 = copyright asserted, 1 = copyright not asserted)
1
0
1
1
DIR L (or origination) bit output
(0 = 1st generation or higher, 1 = original)
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
DIR Parity error flag; active high
DIR internal sync clock output; may be used as the data clock for the channel
status and user data serial outputs.
DIT internal sync clock
9.3.8 Interrupt Output
The DIX4192-Q1 includes multiple internal status bits, many of which may be set to trigger an interrupt signal.
The interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a
pullup resistor to the VIO supply rail. The value of the pullup is not critical, but a 10-kΩ device must be sufficient
for most applications. Figure 18 shows the interrupt output pin connection. The open-drain output allows interrupt
pins from multiple DIX4192-Q1 devices to be connected in a wired OR configuration.
DIX4192-Q1
MCU, DSP,
or Logic
VIO
Interrupt
Logic
10 kΩ
INT 23
Interrupt
Input
To the INT outputs for
additional DIX4192-Q1 devices
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Interrupt Output Pin Connections
22
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9.4 Device Functional Modes
9.4.1 Host Interface Operation: Serial Peripheral Interface (SPI) Mode
The DIX4192-Q1 supports a 4-wire SPI port when the CPM input (pin 18) is forced low or tied to ground. The SPI
port supports high-speed serial data transfers up to 40 Mbps. Register and data buffer write and read operations
are supported.
The CS input (pin 19) serves as the active low chip select for the SPI port. The CS input must be forced low in
order to write or read registers and data buffers. When CS is forced high, the data at the CDIN input (pin 21) is
ignored, and the CDOUT output (pin 22) is forced to a high-impedance state. The CDIN input serves as the serial
data input for the port; the CDOUT output serves as the serial data output.
The CCLK input (pin 20) serves as the serial data clock for both the input and output data. Data is latched at the
CDIN input on the rising edge of CCLK, while data is clocked out of the CDOUT output on the falling edge of
CCLK.
Figure 19 shows the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant bit
(or MSB) is the read/write bit. For the R/W bit, a 0 indicates a write operation, while a 1 indicates a read
operation. The remaining seven bits of the command byte are used for the register address targeted by the write
or read operation. Byte 1 is a don’t care byte, and may be set to all zeroes. This byte is included in order to
retain protocol compatibility with earlier Texas Instruments digital audio interface and sample rate converter
products, including the DIT4096, DIT4192, the SRC418x series devices, and the SRC419x series devices.
The SPI port supports write and read operations for multiple sequential register addresses through the
implementation of an auto-increment mode. As shown in Figure 19, the auto-increment mode is invoked by
simply holding the CS input low for multiple data bytes. The register address is automatically incremented after
each data byte transferred, starting with the address specified by the command byte.
Refer to the SPI section of the Electrical Characteristics table and Figure 2 for specifications and a timing
diagram that highlight the key parameters for SPI operation.
Set CS = 1 here to write/read one register location.
Hold CS = 0 to enable auto-increment mode.
CS
Header
Register Data
Byte N
Byte 0
Hi Z
Byte 1
Hi Z
Byte 2
Byte 3
CDIN
Register Data
Data for A[6:0] Data for A[6:0]+1
Data for A[2:0]+N
CDOUT
CCLK
Byte Definition
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
Byte 0:
Register Address
Set to 0 for Write; Set to 1 for Read.
Byte 1: Don’t Care
Byte 2 through Byte N: Register Data
Figure 19. Serial Peripheral Interface (SPI) Protocol for the DIX4192-Q1
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Device Functional Modes (continued)
9.4.2 Host Interface Operation: PHILIPS I2C Mode
The DIX4192-Q1 supports a 2-wire Philips I2C bus interface when CPM (pin 18) is forced high or pulled up to the
VIO supply rail. The DIX4192-Q1 functions as a Slave-only device on the bus. Standard and Fast modes of
operation are supported. Standard mode supports data rates up to 100 kbps, while Fast mode supports data
rates up to 400 kbps. Fast mode is downward compatible with Standard mode, and these modes are sometimes
referred to as Fast/Standard, or F/S mode. The I2C Bus Specification (Version 2.1, January 2000), available from
Philips Semiconductor, provides the details for the bus protocol and implementation. It is assumed that the
reader is familiar with this specification. Refer to the I2C Standard and Fast Modes section of the Electrical
Characteristics table and Figure 3 for specifications and a timing diagram that highlight the key parameters for
I2C interface operation.
When the I2C mode is invoked, pin 20 becomes SCL (which serves as the bus clock) and pin 22 becomes SDA
(which carries the bi-directional serial data for the bus). Pins 19 and 21 become A0 and A1, respectively, and
function as the hardware configurable portion of the 7-bit slave address.
The DIX4192-Q1 uses a 7-bit Slave address; see Figure 20(a). Bits A2 through A6 are fixed and bits A0 and A1
are hardware programmable using pins 19 and 21, respectively. The programmable bits allow for up to four
DIX4192-Q1 devices to be connected to the same bus. The slave address is followed by the Register Address
Byte, which points to a specific register or data buffer location in the DIX4192-Q1 register map. The register
address byte is comprised of seven bits for the address, and one bit for enabling or disabling auto-increment
operation; see Figure 20(b). Auto-increment mode allows multiple sequential register locations to be written to or
read back in a single operation, and is especially useful for block write and read operations.
Figure 21 shows the protocol for Standard and Fast mode Write operations. When writing a single register
address, or multiple non-sequential register addresses, the single register write operation of Figure 21(a) may be
used one or more times. When writing multiple sequential register addresses, the auto-increment mode of
Figure 21(b) improves efficiency. The register address is automatically incremented by one for each successive
byte of data transferred.
Figure 22 shows the protocol for Standard and Fast mode Read operations. The current address read operation
of Figure 22(a) assumes the value of the register address from the previously executed write or read operation,
and is useful for polling a register address for status changes. Figure 22(b) and Figure 22(c) show read
operations for one or more random register addresses, with or without auto-increment mode enabled.
First Byte After the START/RESTART Condition
Slave Address
MSB
A6
1
LSB
A5
1
A4
1
A3
0
A2 A1
A1
A0
A0 R/W
0
Set by Pin 19
Set by Pin 21
(a) TI-Device Slave Address
MSB
LSB
A0
INC A6
A5
A4
A3
A2
A1
Auto-Increment
0 = Disabled
1 = Enabled
(b) Register Address Byte
Copyright © 2017, Texas Instruments Incorporated
Figure 20. DIX4192-Q1 Slave Address and Register Address Byte Definitions
24
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DIX4192-Q1
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Device Functional Modes (continued)
Byte 1
Slave Address
with R/W = 0
Byte 2
Register Address Byte
with INC = 0
Byte 3
Register
Data
S
A
A
A P
(a) Writing a Single Register
Byte 1
Slave Address
with R/W = 0
Byte 2
Register Address Byte
with INC = 1
Byte 4
Register Data
for Address + 1
Byte N
Register Data
for Address + N
Byte 3
Register Data
S
A
A
A
A
A P
(b) Writing Multiple Sequential Registers Using Auto-Increment Operation
Legend
S = START Condition
A = Acknowledge
P = STOP Condition
Transfer from Master to Slave
Transfer from Slave to Master
Figure 21. Fast and Standard Mode Write Operations
Byte 1
Slave Address
with R/W = 1
Byte 2
Register Data
S
A
A P
(a) Current Address Read, Assumes the Register Address of the Previous
Byte 1
Slave Address
with R/W = 0
Byte 2
Register Address Byte
with INC = 0
Byte 3
Slave Address
with R/W = 1
Byte 4
Register Data
A
A P
S
A
A R
(b) Random Read Operation, Auto-Increment Disabled
Byte 1
Slave Address
with R/W = 0
Byte 2
Register Address Byte
with INC = 1
Byte 3
Slave Address
with R/W = 1
Byte N
Register Data
for Address + N
Byte 4
Register Data
S
A
A R
A
A
A P
(c) Random Read Operation, Auto-Increment Enabled
Legend
S = START Condition
A = Acknowledge
Transfer from Master to Slave
Transfer from Slave to Master
A = Not Acknowledge
R = Repeated START
P = STOP Condition
Figure 22. Fast and Standard Mode Read Operations
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9.5 Register Maps
9.5.1 Register and Data Buffer Organization
The DIX4192-Q1 organizes the on-chip registers and data buffers into four pages. The currently active page is
chosen by programming the Page Selection Register to the desired page number. The Page Selection Register
is available on every register page at address 0x7F, allowing easy movement between pages. Table 2 indicates
the page selection corresponding to the Page Selection Register value.
Table 2. Register Page Selection
Page Selection Register Value (Hex)
Selected Register Page
00
01
02
03
Page 0, control and status registers
Page 1, DIR channel status and user data buffers
Page 2, DIT channel status and user data buffers
Page 3, reserved
Register Page 0 contains the control registers used to configure the various function blocks within the DIX4192-
Q1. In addition, status registers are provided for flag and error conditions, with many of the status bits capable of
generating an interrupt signal when enabled. See Table 3 for the control and status register map.
Register Page 1 contains the digital interface receiver (or DIR) channel status and user data buffers. These
buffers correspond to the data contained in the C and U bits of the previously received block of the AES3-
encoded data stream. The contents of these buffers may be read through the SPI or I2C serial host interface and
processed as required by the host system. See Table 35 for the DIR channel status buffer map, and Table 36 for
the DIR user data buffer map.
Register Page 2 contains the digital interface transmitter (or DIT) channel status and user data buffers. These
buffers correspond to the data contained in the C and U bits of the transmitted AES3-encoded data stream. The
contents of these buffers may be written through the SPI or I2C serial host interface to configure the C and U bits
of the transmitted AES3 data stream. The buffers may also be read for verification by the host system. See
Table 37 for the DIT channel status buffer map, and Table 38 for the DIT user data buffer map.
Register Page 3 is reserved for factory test and verification purposes, and cannot be accessed without an unlock
code. The unlock code remains private; the test modes disable normal operation of the device, and are not
useful in customer applications.
26
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9.5.2 Control Registers
See Table 3 for the control and status register map of the DIX4192-Q1. Register addresses 0x00 and 0x2D
through 0x7E are reserved for factory or future use. All register addresses are expressed as hexadecimal
numbers. The following pages provide detailed descriptions for each control and status register.
Table 3. Control and Status Register Map (Register Page 0)
ADDRESS
(Hex)
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
REGISTER GROUP
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
7F
RESET
0
PDALL
PDPA
PDPB
0
PDTX
TX
PDRX
RX
0
0
Power-down and reset
Global interrupt status
Port A control
0
0
0
0
0
AMUTE
AOUTS1
AOUTS0
AM/S
ACLK1
BM/S
BCLK1
TXIS0
TXBTD
0
AFMT2
ACLK0
BFMT2
BCLK0
BLSM
AESOFF
VALSEL
0
AFMT1
ADIV1
BFMT1
BDIV1
VALID
TXMUTE
TXCUS1
TSLIP
MTSLIP
TBTIM1
RXMUX1
RXCKOD0
J3
AFMT0
ADIV0
BFMT0
BDIV0
BSSL
TXOFF
TXCUS0
TBTI
0
0
0
0
Port A control
0
BMUTE
BOUTS1
BOUTS0
Port B control
0
0
0
0
Port B control
TXCLK
TXDIV1
TXDIV0
TXIS1
Transmitter control
BYPMUX1
BYPMUX0
AESMUX
LDMUX
Transmitter control
0
0
0
0
Transmitter control
0
0
0
0
0
DIT status
0
0
0
0
0
0
MTBTI
TBTIM0
RXMUX
RXCKOE
J2
DIT interrupt mask
0
0
0
0
TSLIPM1
RXCLK
RXAMLL
J5
TSLIPM0
0
DIT interrupt mode
0
0
0
RXBTD
Receiver control
0
0
0
LOL
RXCKOD1
J4
Receiver control
P3
P2
P1
P0
Receiver PLL configuration
Receiver PLL configuration
Receiver PLL configuration
Non-PCM audio detection
Receiver status
J1
J0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
DTS CD/LD
RXCKR1
QCRC
0
IEC61937
RXCKR0
RBTI
0
CSCRC
0
0
PARITY
0
0
0
0
0
VBIT
BPERR
QCHG
0
UNLOCK
0
Receiver status
0
MVBIT
0
0
OSLIP
MRBTI
MOSLIP
RBTIM0
BPERRM0
OSLIPM0
GPO10
GPO20
GPO30
GPO40
Q7
Receiver status
MCSCRC
0
MPARITY
0
MBPERR
MQCHG
0
MUNLOCK
0
MQCRC
0
Receiver interrupt mask
Receiver interrupt mask
Receiver interrupt mode
Receiver interrupt mode
Receiver interrupt mode
General-purpose out (GPO1)
General-purpose out (GPO2)
General-purpose out (GPO3)
General-purpose out (GPO4)
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
Audio CD Q-channel sub-code
PC burst preamble, high byte
PC burst preamble, low byte
PD burst preamble, high byte
PD burst preamble, low byte
Page selection
0
UNLOCKM0
PARITYM0
0
QCHGM1
CSCRCM1
0
QCHGM0
CSCRCM0
0
UNLOCKM1
PARITYM1
0
QCRCM1
VBITM1
0
QCRCM0
VBITM0
0
RBTIM1
BPERRM1
OSLIPM1
GPO11
GPO21
GPO31
GPO41
Q6
0
0
0
0
GPO13
GPO23
GPO33
GPO43
Q4
GPO12
GPO22
GPO32
GPO42
Q5
0
0
0
0
0
0
0
0
0
0
0
0
Q0
Q1
Q2
Q3
Q8
Q9
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
PC13
PC05
PD13
PD05
0
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
PC12
PC04
PD12
PD04
0
Q12
Q13
Q14
Q15
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
PC15
PC07
PD15
PD07
0
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
PC14
PC06
PD14
PD06
0
Q20
Q21
Q22
Q23
Q28
Q29
Q30
Q31
Q36
Q37
Q38
Q39
Q44
Q45
Q46
Q47
Q52
Q53
Q54
Q55
Q60
Q61
Q62
Q63
Q68
Q69
Q70
Q71
Q76
Q77
Q78
Q79
PC11
PC03
PD11
PD03
0
PC10
PC02
PD10
PD02
0
PC09
PC08
PC01
PC00
PD09
PD08
PD01
PD00
PAGE1
PAGE0
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Figure 23. Register 01: Power-Down and Reset
7 (MSB)
RESET
6
0
5
4
3
2
1
0 (LSB)
0
PDALL
PDPA
PDPB
PDTX
PDRX
Table 4. Register 01: Power-Down and Reset Field Descriptions
PDRX
Power-Down for the Receiver Function Block
This bit is used to power-down the DIR and associated functions. All receiver outputs are forced low.
PDRX
Receiver Power-Down Mode
0
1
Enabled (default)
Disabled; the Receiver function block will operate normally based upon the applicable control register settings.
PDTX
Power-Down for the Transmitter Function Block
This bit is used to power-down the DIT and associated functions. All transmitter outputs are forced low.
PDTX
Transmitter Power-Down Mode
0
1
Enabled (default)
Disabled; the Transmitter function block will operate normally based upon the applicable control register settings.
PDPB
PDPA
PDALL
RESET
Power-Down for Serial Port B
This bit is used to power-down the audio serial I/O Port B. All port outputs are forced low.
PDPB
Port B Power-Down Mode
0
1
Enabled (default)
Disabled; Port B will operate normally based upon the applicable control register settings.
Power-Down for Serial Port A
This bit is used to power-down the audio serial I/O Port A. All port outputs are forced low.
PDPA
Port A Power-Down Mode
0
1
Enabled (default)
Disabled; Port A will operate normally based upon the applicable control register settings.
Power-Down for All Functions
This bit is used to power-down all function blocks except the host interface port and the control and status registers.
PDALL
All Function Power-Down Mode
0
1
Enabled (default)
Disabled; all function blocks will operate normally based upon the applicable control register settings.
Software Reset
This bit is used to force a reset initialization sequence, and is equivalent to forcing an external reset through the RST input (pin 24).
RESET
Reset Function
0
1
Disabled (default)
Enabled; all control registers will be reset to the default state.
Figure 24. Register 02: Global Interrupt Status (Read-Only)
7 (MSB)
6
0
5
0
4
0
3
0
2
1
0 (LSB)
0
0
TX
RX
Table 5. Register 02: Global Interrupt Status (Read-Only) Field Descriptions
RX
TX
Receiver Function Block Interrupt Status (Active High)
When set to 1, this bit indicates an active interrupt from the DIR function block. This bit is active high. The user must then read status
registers 0x14 and 0x15 in order to determine which of the sources has generated an interrupt.
Transmitter Function Block Interrupt Status (Active High)
When set to 1, this bit indicates an active interrupt from the DIT function block. This bit is active high. The user must then read status
register 0x0A in order to determine which of the sources has generated an interrupt.
28
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Figure 25. Register 03: Port A Control Register 1
7 (MSB)
0
6
5
4
3
2
1
0 (LSB)
AFMT0
AMUTE
AOUTS1
AOUTS0
AM/S
AFMT2
AFMT1
Table 6. Register 03: Port A Control Register 1 Field Descriptions
AFMT[2:0]
Port A Audio Data Format
These bits are used to set the audio input and output data format for Port A. Refer to Audio Serial Port Operation for illustrations of the
supported data formats. Refer to the Audio Serial Ports section of the Electrical Characteristics table and Figure 1 for an applicable timing
diagram and parameters.
AFMT2
AFMT1
AFMT0
Audio Data Format
24-Bit Left-Justified (default)
24-Bit Philips I2S
Unused
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Unused
16-Bit Right-Justified
18-Bit Right-Justified
20-Bit Right-Justified
24-Bit Right-Justified
AM/S
Port A Slave and Master Mode
This bit is used to set the audio clock mode for Port A to either Slave or Master.
AM/S
Slave/Master Mode
0
1
Slave mode; the LRCK and BCK clocks are inputs generated by an external digital audio source. (default)
Master mode; the LRCK and BCK clocks are outputs, derived from the Port A master clock source.
AOUTS[1:0]
Port A Output Data Source
These bits are used to select the output data source for Port A. The data is output at SDOUTA (pin 40).
AOUTS1
AOUTS0
Output Data Source
0
0
1
0
1
Port A input, for data loop back. (default)
0
Port B input
DIR
1
1
Reserved
AMUTE
Port A Output Mute
This bit is used to mute the Port A audio data output.
AMUTE
Output Mute
0
1
Disabled; SDOUTA is driven by the output data source. (default)
Enabled; SDOUTA is forced low.
Figure 26. Register 04: Port A Control Register 2
7 (MSB)
0
6
0
5
0
4
0
3
2
1
0 (LSB)
ADIV0
ACLK1
ACLK0
ADIV1
Table 7. Register 04: Port A Control Register 2 Field Descriptions
ADIV[1:0]
Port A Master Clock Divider
These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation.
BCKA is always set to 64 times the LRCKA clock rate in Master mode.
ADIV1
ADIV0
Master Mode Clock Divider
Divide-by-128 (default)
Divide-by-256
0
0
1
0
1
0
1
Divide-by-384
1
Divide-by-512
ACLK[1:0]
Port A Master Clock Source
These bits are used to set the master clock source for Port A when configured for Master mode operation.
ACLK1
ACLK0
Master Clock Source
MCLK (default)
RXCKI
0
0
0
1
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Table 7. Register 04: Port A Control Register 2 Field Descriptions (continued)
1
1
0
1
RXCKO
Reserved
Figure 27. Register 05: Port B Control Register 1
7 (MSB)
0
6
5
4
3
2
1
0 (LSB)
BFMT0
BMUTE
BOUTS1
BOUTS0
BM/S
BFMT2
BFMT1
Table 8. Register 05: Port B Control Register 1 Field Descriptions
BFMT[2:0]
Port B Audio Data Format
These bits are used to set the audio input and output data format for Port B. Refer to Audio Serial Port Operation for illustrations of the
supported data formats. Refer to the Audio Serial Ports section of the Electrical Characteristics table and Figure 1 for an applicable timing
diagram and parameters.
BFMT2
BFMT1
BFMT0
Audio Data Format
24-Bit Left-Justified (default)
24-Bit Philips I2S
Unused
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Unused
16-Bit Right-Justified
18-Bit Right-Justified
20-Bit Right-Justified
24-Bit Right-Justified
BM/S
Port B Slave and Master Mode
This bit is used to set the audio clock mode for Port B to either Slave or Master.
BM/S
Slave and Master Mode
0
1
Slave mode; the LRCK and BCK clocks are generated by an external source. (default)
Master mode; the LRCK and BCK clocks are derived from the Port A master clock source.
BOUTS[1:0]
Port B Output Source
These bits are used to select the output data source for Port B. The data is output at SDOUTB (pin 45).
BOUTS1
BOUTS0
Output Data Source
0
0
1
0
1
Port B input, for data loop back. (default)
0
Port A input
DIR
1
1
Reserved
BMUTE
Port B Output Mute
This bit is used to mute the Port B audio data output.
BMUTE
Output Mute
0
1
Disabled; SDOUTB is driven by the output data source. (default)
Enabled; SDOUTB is forced low.
30
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Figure 28. Register 06: Port B Control Register 2
7 (MSB)
0
6
0
5
0
4
0
3
2
1
0 (LSB)
BDIV0
BCLK1
BCLK0
BDIV1
Table 9. Register 06: Port B Control Register 2 Field Descriptions
BDIV[1:0]
Port B Master Mode Clock Divider
These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation.
BCKB is always set to 64 times the LRCKB clock rate in Master mode.
BDIV1
BDIV0
Master Mode Clock Divider
Divide-by-128 (default)
Divide-by-256
0
0
1
0
1
0
1
Divide-by-384
1
Divide-by-512
BCLK[1:0]
Port B Master Clock Source
These bits are used to set the master clock source for Port B when configured for Master mode operation.
BCLK1
BCLK0
Master Clock Source
MCLK (default)
RXCKI
0
0
1
1
0
1
0
1
RXCKO
Reserved
Figure 29. Register 07: Transmitter Control Register 1
7 (MSB)
TXCLK
6
5
4
3
2
1
0 (LSB)
BSSL
TXDIV1
TXDIV0
TXIS1
TXIS0
BLSM
VALID
Table 10. Register 07: Transmitter Control Register 1 Field Descriptions
BSSL
Block Start or Asynchronous Data Slip Interrupt Trigger Selection
This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit.
BSSL
TSLIP Interrupt Trigger Source
Data slip condition (default)
Block start condition
0
1
VALID
Validity (V) Data Bit
This bit may be used to set the validity (or V) data bit in the AES3-encoded output. Refer to the VALSEL bit in control register 0x09 for V-
bit source selection.
VALID
Transmitted Validity (V) Bit Data
Indicates that the transmitted audio data is suitable for conversion to an analog signal or for further digital
processing. (default)
0
Indicates that the transmitted audio data is not suitable for conversion to an analog signal or for further
digital processing.
1
BLSM
Transmitter Block Start Input and Output Mode
This bit is used to select the input and output mode for the DIT block start pin, BLS (pin 35).
BLSM
BLS Pin Mode
Input (default)
Output
0
1
TXIS[1:0]
Transmitter Input Data Source
These bits are used to select the audio data source for the DIT function block.
TXIS1
TXIS0
Output Word Length
Port A (default)
Port B
0
0
1
1
0
1
0
1
DIR
Reserved
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Table 10. Register 07: Transmitter Control Register 1 Field Descriptions (continued)
TXDIV[1:0]
Transmitter Master Clock Divider
These bits are used to select the Transmitter master clock divider, which determines the output frame rate.
TXDIV1
TXDIV0
Clock Divider
0
0
1
0
1
Divide the master clock by 128. (default)
Divide the master clock by 256.
Divide the master clock by 384.
Divide the master clock by 512.
0
1
1
TXCLK
Transmitter Master Clock Source
This bit is used to select the master clock source for the Transmitter block.
TXCLK
Transmitter Master Clock Source
0
1
MCLK input (default)
RXCKO; the recovered master clock from the DIR function block.
Figure 30. Register 08: Transmitter Control Register 2
7 (MSB)
BYPMUX1
6
5
4
3
2
1
0 (LSB)
TXOFF
BYPMUX0
AESMUX
LDMUX
TXBTD
AESOFF
TXMUTE
Table 11. Register 08: Transmitter Control Register 2 Field Descriptions
TXOFF
Transmitter Line Driver Output Enable
This bit is used to enable or disable the TX+ (pin 32) and TX– (pin 31) line driver outputs.
TXOFF
Transmitter Line Driver
0
Enabled; the line driver outputs function normally. (default)
Disabled; the line driver outputs are forced low.
1
TXMUTE
AESOFF
TXBTD
Transmitter Audio Data Mute
This bit is used to set the 24 bits of audio and auxiliary data to all zeros for both Channels 1 and 2.
TXMUTE
Transmitter Audio Data Mute
0
Disabled (default)
1
Enabled; the audio data for both channels 1 and 2 are set to all zeros.
AESOUT Output Enable
This bit is used to enable or disable the AESOUT (pin 34) buffered AES3-encoded CMOS logic level output.
AESOFF
AESOUT Output
0
1
Enabled; the AESOUT pin functions normally. (default)
Disabled; the AESOUT pin is forced low.
Transmitter C and U Data Buffer Transfer Disable
This bit is used to enable and disable buffer transfers between the DIT User Access (UA) and DIT Transmitter Access (TA) buffers for both
channel status (C) and user (U) data.
Buffer transfers may be disabled, allowing the user to write new C and U data to the UA buffers through the SPI or I2C serial host
interface. Once updated, UA-to-TA buffer transfers may then be re-enabled, allowing the TA buffer to be updated and the new C and U
data to be transmitted at the start of the next block.
TXBTD
User Access (UA) to Transmitter Access (TA) Buffer Transfers
Enabled (default)
0
1
Disabled; allows the user to update DIT C and U data buffers.
Note: The TXCUS0 and TXCUS1 bits in control register 0x09 must be set to a non-zero value in order for DIT UA buffer updates to occur.
Transmitter Line Driver Input Source Selection
LDMUX
This bit is used to select the input source for the DIT differential line driver outputs.
LDMUX
Line Driver Input Source
0
1
DIT AES3 encoder output (default)
Bypass multiplexer output
AESMUX
AESOUT CMOS Buffer Input Source Selection
This bit is used to select the input source for the AESOUT CMOS logic level output.
AESMUX
AESOUT Buffer Input Source
DIT AES3 encoder output (default)
Bypass multiplexer output
0
1
32
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ZHCSFA7A –JULY 2016–REVISED APRIL 2017
Table 11. Register 08: Transmitter Control Register 2 Field Descriptions (continued)
BYPMUX[1:0]
Bypass Multiplexer Source Selection
These bits select the line receiver output to be used as the bypass multiplexer data source.
BYPMUX1
BYPMUX0
Line Receiver Output Selection
0
0
1
1
0
1
0
1
RX1 (default)
RX2
RX3
RX4
Figure 31. Register 09: Transmitter Control Register 3
7 (MSB)
0
6
0
5
0
4
0
3
0
2
1
0 (LSB)
VALSEL
TXCUS1
TXCUS0
Table 12. Register 09: Transmitter Control Register 3 Field Descriptions
TXCUS[1:0]
Transmitter Channel Status and User Data Source
These bits select the source of the channel status (or C) data and user (or U) data which is used to load the DIT User Access (UA) buffers.
TXCUS1
TXCUS0
DIT UA Buffer Source
0
0
1
0
1
0
The buffers will not be updated. (default)
The buffers are updated through the SPI or I2C host interface.
The buffers are updated through the DIR RA buffers.
The first 10 bytes of the buffers are updated through the SPI or I2C host, while the
remainder of the buffers are updated through the DIR RA buffers.
1
1
VALSEL
Transmitter Validity Bit Source
This bit is used to select the source for the validity (or V) bit in the AES3-encoded output data stream.
VALSEL
Validity (or V) Bit Source Selection
0
1
The VALID bit in control register 0x07.
The V bit is transferred from the DIR block with zero latency.
Figure 32. Register 0A: DIT Status (Read-Only)
7 (MSB)
0
6
5
0
4
0
3
0
2
0
1
0 (LSB)
TBTI
0
TSLIP
Table 13. Register 0A: DIT Status (Read-Only) Field Descriptions
TBTI
Transmitter Buffer Transfer Status, Active High
When DIT User Access (UA) to Transmitter Access (TA) buffer transfers are enabled (the TXBTD bit in control register 0x08 is set to
0), and the TBTI interrupt is unmasked (the MTBTI bit in control register 0x0B is set to 1), the TBTI bit will be set to 1 when the UA-to-
TA buffer transfer has completed. This configuration also causes the INT output (pin 23) to be driven low and the TX bit in status
register 0x02 to be set to 1, indicating that an interrupt has occurred.
TSLIP
Transmitter Source Data Slip Status, Active High
The TSLIP bit will be set to 1 when either an asynchronous data slip or block start condition is detected, and the TSLIP interrupt is
unmasked (the MTSLIP bit in control register 0x0B is set to 1). The BSSL bit in control register 0x07 is used to set the source for this
interrupt.
The TSLIP bit being forced to 1 will also cause the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set
to 1, indicating that an interrupt has occurred.
Figure 33. Register 0B: DIT Interrupt Mask Register
7 (MSB)
0
6
0
5
0
4
0
3
0
2
0
1
0 (LSB)
MTBTI
MTSLIP
Table 14. Register 0B: DIT Interrupt Mask Register Field Descriptions
MBTI
Transmitter Buffer Transfer Interrupt Mask
MTBI
BTI Interrupt Mask
0
1
BTI interrupt is masked. (default)
BTI interrupt is enabled.
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Table 14. Register 0B: DIT Interrupt Mask Register Field Descriptions (continued)
MTSLIP
Transmitter TSLIP Interrupt Mask
MTSLIP
TSLIP Interrupt Mask
0
1
TSLIP interrupt is masked. (default)
TSLIP interrupt is enabled.
Figure 34. Register 0C: DIT Interrupt Mode Register
7 (MSB)
6
0
5
0
4
0
3
2
1
0 (LSB)
TBTIM0
0
TSLIPM1
TSLIPM0
TBTIM1
Table 15. Register 0C: DIT Interrupt Mode Register Field Descriptions
TBTIM[1:0]
Transmitter Buffer Transfer Interrupt Mode
These bits are used to select the active trigger state for the BTI interrupt.
TBTIM1
TBTIM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
TSLIPM[1:0]
Transmitter Data Source Slip Interrupt Mode
These bits are used to select the active trigger state for the TSLIP interrupt.
TSLIPM1
TSLIPM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
Figure 35. Register 0D: Receiver Control Register 1
7 (MSB)
0
6
0
5
0
4
3
2
0
1
0 (LSB)
RXBTD
RXCLK
RXMUX1
RXMUX0
Table 16. Register 0D: Receiver Control Register 1 Field Descriptions
Receiver Input Source Selection
RXMUX[1:0]
These bits are used to select the output of the line receiver to be used as the input data source for the DIR core.
RXMUX1
RXMUX0
Input Selection
RX1 (default)
RX2
0
0
1
0
1
0
1
RX3
1
RX4
RXCLK
RXBTD
Receiver Reference Clock Source
This bit is used to select the reference clock source for PLL1 in the DIR core.
RXCLK
Receiver Reference Clock
RXCKI (default)
MCLK
0
1
Receiver C and U Data Buffer Transfer Disable
This bit is used to enable and disable buffer transfers between the Receiver Access (RA) and User Access (UA) buffers for both channel
status (C) and user (U) data.
Buffer transfers are typically disabled to allow the customer to read C and U data from the DIR UA buffer through the SPI or I2C serial host
interface. Once read, the RA-to-UA buffer transfer can be re-enabled to allow the RA buffer to update the contents of the UA buffer in real
time.
RXBTD
Receiver Access (RA) to User Access (UA) Buffer Transfers
Enabled (default)
0
1
Disabled; the user may read C and U data from the DIR UA buffers.
34
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Figure 36. Register 0E: Receiver Control Register 2
7 (MSB)
0
6
0
5
0
4
3
2
1
0 (LSB)
LOL
RXAMLL
RXCKOD1
RXCKOD0
RXCKOE
Table 17. Register 0E: Receiver Control Register 2 Field Descriptions
RXCKOE
RXCKOE Output Enable
This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled, the output is set to a high-impedance
state.
RXCKOE
RXCKO Output State
0
Disabled; the RXCKO output is set to high-impedance. (default)
Enabled; the recovered master clock is available at RXCKO.
1
RXCKOD[1:0]
RXCKO Output Clock Divider
These bits are used to set the clock divider at the output of PLL2. The output of the divider is the RXCKO clock, available internally or at
the RXCKO output (pin 12).
RXCKOD1
RXCKOD0
RXCKO Output Divider
0
0
1
1
0
1
0
1
Passthrough; no division is performed. (default)
Divide the PLL2 clock output by 2.
Divide the PLL2 clock output by 4.
Divide the PLL2 clock output by 8.
RXAMLL
Receiver Automatic Mute for Loss of Lock
This bit is used to set the automatic mute function for the DIR block when a loss of lock is indicated by both the AES3 decoder and PLL2.
RXAMLL
Receiver Auto-Mute Function
0
1
Disabled (default)
Enabled; audio data output from the DIR block is forced low for a loss of lock condition.
LOL
Receiver Loss of Lock Mode for the Recovered Clock (output from PLL2)
This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs.
LOL
Receiver PLL2 Operation
0
1
The PLL2 output clock is stopped for a loss of lock condition. (default)
The PLL2 output clock free runs when a loss of lock condition occurs.
Figure 37. Register 0F: Receiver PLL1 Configuration Register 1
7 (MSB)
P3
6
5
4
3
2
1
0 (LSB)
J2
P2
P1
P0
J5
J4
J3
Figure 38. Register 10: Receiver PLL1 Configuration Register 2
7 (MSB)
J1
6
5
4
3
2
1
0 (LSB)
D8
J0
D13
D12
D11
D10
D9
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Figure 39. Register 11: Receiver PLL1 Configuration Register 3
7 (MSB)
D7
6
5
4
3
2
1
0 (LSB)
D0
D6
D5
D4
D3
D2
D1
Table 18. Register 11: Receiver PLL1 Configuration Register 3 Field Descriptions
Registers 0x0F through 0x11 are used to program PLL1 in the DIR core. PLL1 multiplies the DIR reference clock source to an oversampling rate which is
adequate for AES3 decoder operation. PLL1 is programmed using the following relationship:
(CLOCK × K) / P = 98.304 MHz
where:
CLOCK = frequency of the DIR reference clock source.
K = J.D, where the integer part J = 1 to 63, and the fractional part D = 0 to 9999.
P = the pre-divider value, which may be set to any 4-bit value that meets the conditions stated below.
The following conditions must be met for the values of P, J, and D:
If D = 0, 2 MHz ≤ (CLOCK / P) ≤ 20 MHz and 4 ≤ J ≤ 55.
then:
If D ≠ 0, 10 MHz ≤ (CLOCK / P) ≤ 20 MHz and 4 ≤ J ≤11.
then:
Referring to registers 0x0F through 0x11:
P is programmed using bits P[3:0].
J is programmed using bits J[5:0].
D is programmed using bits D[13:0].
Table 19 shows values for P, J, and D for common
DIR reference clock rates.
Table 19. PLL1 Register Values for Common Reference Clock Rates
REFERENCE CLOCK RATE (MHz)
P
1
1
1
1
2
2
2
J
12
8
D
0
ERROR (%)
0.0000
0.0002
0.0000
0.0000
0.0002
0.0000
0.0003
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
27.0000
7075
0
8
6
0
8
7075
0
8
7
2818
Figure 40. Register 12: Non-PCM Audio Detection Status Register (Read-Only)
7 (MSB)
0
6
0
5
0
4
0
3
0
2
0
1
0 (LSB)
DTS CD/LD
IEC61937
Table 20. Register 12: Non-PCM Audio Detection Status Register (Read-Only) Field Descriptions
IEC61937
This bit is used to indicate the detection of an IEC 61937 data reduced audio format (includes Dolby AC-3, DTS, etc.) for DVD playback
or general transmission purposes.
IEC61937
Status
0
Data is not an IEC61937 format.
Data is an IEC61937 format. Refer to the PC and PD preamble registers (addresses 0x29
through 0x2C) for data type and burst length.
1
DTS CD/LD
This bit is used to indicate the detection of a DTS encoded audio compact disc (CD) or Laserdisc (LD) playback.
DTS CD/LD
Status
0
1
The CD/LD is not DTS-encoded.
DTS CD/LD playback detected.
36
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Figure 41. Register 13: Receiver Status Register 1 (Read-Only)
7 (MSB)
0
6
0
5
0
4
0
3
0
2
0
1
0 (LSB)
RXCKR1
RXCKR0
Table 21. Register 13: Receiver Status Register 1 (Read-Only) Field Descriptions
RXCKR[1:0]
Maximum Available Recovered Clock Rate
These two bits indicate the maximum available RXCKO clock rate based upon the DIR detection circuitry, which determines the frame rate
of the incoming AES3-encoded bit stream. Based upon the estimated frame rate, a maximum rate for the recovered clock output (RXCKO)
is determined and output from PLL2, as well as being loaded into the RXCKR0 and RXCKR1 status bits.
The status of the RXCKR0 and RXCKR1 bits may be used to determine the programmed value for the PLL2 output clock divider, set by the
RXCKOD0 and RXCKOD1 bits in control register 0x0E.
RXCKR1
RXCKR0
Maximum Available RXCKO Rate
0
0
1
1
0
1
0
1
Clock rate not determined.
128fS
256fS
512fS
Figure 42. Register 14: Receiver Status Register 2 (Read-Only)
7 (MSB)
CSCRC
6
5
4
3
2
1
0 (LSB)
RBTI
PARITY
VBIT
BPERR
QCHG
UNLOCK
QCRC
Note: Status bits must be unmasked in control register 0x16 in order for the status interrupts to be generated.
Table 22. Register 14: Receiver Status Register 2 (Read-Only) Field Descriptions
CSCRC
PARITY
VBIT
Channel Status CRC Status
CSCRC
CRC Status
No error
0
1
CRC error detected
Parity Status
PARITY
Parity Status
No error
0
1
Parity error detected
Validity Bit Status
VBIT
Validity Bit
0
Valid audio data indicated
Non-valid data indicated
1
BPERR
QCHG
Biphase Encoding Error Status
BPERR
Biphase Encoding Status
No error
0
1
Biphase encoding error detected
Q-Channel Sub-Code Data Change Status
QCHG
Q-Channel Data Status
0
No change in Q-channel sub-code data.
Q-channel data has changed. May be used to trigger a read of the Q-channel sub-code data,
registers 0x1F through 0x28.
1
UNLOCK
QCRC
RBTI
DIR Unlock Error Status
UNLOCK
DIR Lock Status
0
No error; the DIR AES3 decoder and PLL2 are locked.
DIR lock error; the AES3 decoder and PLL2 are unlocked.
1
Q-Channel Sub-Code CRC Status
QCRC
Q-Channel CRC Status
No error
0
1
Q-channel sub-code data CRC error detected.
Receiver Buffer Transfer Interrupt Status
RBTI
DIR RA Buffer-to-UA Buffer Transfer Status
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Table 22. Register 14: Receiver Status Register 2 (Read-Only) Field Descriptions (continued)
0
1
Buffer transfer incomplete, or no Buffer transfer interrupt indicated
Buffer transfer completed
Figure 43. Register 15: Receiver Status Register 3 (Read-Only)
7 (MSB)
0
6
0
5
0
4
0
3
0
2
0
1
0
0 (LSB)
OSLIP
Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated.
Table 23. Register 15: Receiver Status Register 3 (Read-Only) Field Descriptions
OSLIP
Receiver Output Data Slip Error Status
OSLIP
Receiver OSLIP Error Status
No error
0
1
DIR output data Slip or Repeat error detected
An OSLIP interrupt is possible when the DIR output is used as the source for either the Port A or Port B audio serial port and the port is configured to operate in
slave mode. Figure 44 shows the timing associated with the OSLIP interrupt.
When only one audio serial port (Port A or Port B) is sourced by the DIR output, then the OSLIP status bit and interrupt applies to that port. If both Port A and
Port B are sourced by the DIR output, then the OSLIP status bit and interrupt applies to Port A only.
AES3 Bit Stream
Y
X
Y
X
DIR SYNC
R
L
L
L
R
R
R
L
L
L
R
R
LRCK, Left- or Right-
Justified Formats (input)
LRCK, I2S Format (input)
±5%
±5%
Data Slip or Repeat may occur when the LRCK edges indicated are within the ±5% window.
Figure 44. DIR Output Slip and Repeat (OSLIP) Behavior
38
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Figure 45. Register 16: Receiver Interrupt Mask Register 1
7 (MSB)
6
5
4
3
2
1
0 (LSB)
MRBTI
MCSCRC
MPARITY
MVBIT
MBPERR
MQCHG
MUNLOCK
MQCRC
Table 24. Register 16: Receiver Interrupt Mask Register 1 Field Descriptions
MCSCRC
MPARITY
MVBIT
Channel Status CRC Error Interrupt Mask
MCSCRC
CRC Interrupt
Masked (default)
Enabled
0
1
Parity Error Interrupt Mask
MPARITY
Parity Error Interrupt
Masked (default)
Enabled
0
1
Validity Error Interrupt Mask
MVBIT
Validity Error Interrupt
Masked (default)
Enabled
0
1
MBPERR
MQCHG
MUNLOCK
MQCRC
MRBTI
Biphase Encoding Error Interrupt Mask
MBPERR
Biphase Error Interrupt
Masked (default)
Enabled
0
1
Q-Channel Sub-Code Data Change Interrupt Mask
MQCHG
Q-Channel Data Change Interrupt
0
Masked (default)
Enabled
1
DIR Unlock Error Interrupt Mask
MUNLOCK
DIR Unlock Interrupt
Masked (default)
Enabled
0
1
Q-Channel Sub-Code CRC Error Interrupt Mask
MQCRC
Q-Channel CRC Error Interrupt
0
Masked (default)
Enabled
1
Receiver Buffer Transfer Interrupt Mask
MRBTI
Receiver Buffer Transfer Interrupt
Masked (default)
0
1
Enabled
Figure 46. Register 17: Receiver Interrupt Mask Register 2
7 (MSB)
0
6
0
5
0
4
0
3
0
2
0
1
0
0 (LSB)
MOSLIP
Table 25. Register 17: Receiver Interrupt Mask Register 2 Field Descriptions
MOSLIP
Receiver Output Data Slip Error Mask
MOSLIP
Receiver OSLIP Error Interrupt
Masked (default)
0
1
Enabled
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Figure 47. Register 18: Receiver Interrupt Mode Register 1
7 (MSB)
6
5
4
3
2
1
0 (LSB)
RBTIM0
QCHGM1
QCHGM0
UNLOCKM1
UNLOCKM0
QCRCM1
QCRCM0
RBTIM1
Table 26. Register 18: Receiver Interrupt Mode Register 1 Field Descriptions
QCHGM[1:0]
UNLOCKM[1:0]
QCRCM[1:0]
RBTIM[1:0]
Q-Channel Sub-Code Data Change Interrupt Mode
QCHGM1
QCHGM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
0
1
0
1
1
Reserved
DIR Unlock Error Interrupt Mode
UNLOCKM1
UNLOCKM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
Q-Channel Sub-Code CRC Error Interrupt Mode
QCRCM1
QCRCM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
Receive Buffer Transfer Interrupt Mode
RBTIM1
RBTIM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
40
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Figure 48. Register 19: Receiver Interrupt Mode Register 2
7 (MSB)
6
5
4
3
2
1
0 (LSB)
CSCRCM1
CSCRCM0
PARITYM1
PARITYM0
VBITM1
VBITM0
BPERRM1
BPERRM0
Table 27. Register 19: Receiver Interrupt Mode Register 2 Field Descriptions
CSCRCM[1:0]
PARITYM[1:0]
VBITM[1:0]
Channel Status CRC Error Interrupt Mode
CSCRCM1
CSCRCM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
0
1
0
1
1
Reserved
Parity Error Interrupt Mode
PARITYM1
PARITYM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
0
1
0
1
1
Reserved
Validity Error Interrupt Mode
VBITM1
VBITM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
BPERRM[1:0]
Biphase Encoding Error Interrupt Mode
BPERRM1
BPERRM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
Figure 49. Register 1A: Receiver Interrupt Mode Register 3
7 (MSB)
0
6
0
5
0
4
0
3
0
2
0
1
0 (LSB)
OSLIPM1
OSLIPM0
Table 28. Register 1A: Receiver Interrupt Mode Register 3 Field Descriptions
OSLIPM[1:0]
Receiver Output Data Slip Error Interrupt Mode
OSLIPM1
OSLIPM0
Interrupt Active State
Rising edge active (default)
Falling edge active
Level active
0
0
1
1
0
1
0
1
Reserved
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Figure 50. Register 1B: General-Purpose Output 1 (GPO1) Control Register
7 (MSB)
0
6
0
5
0
4
0
3
2
1
0 (LSB)
GPO10
GPO13
GPO12
GPO11
Table 29. Register 1B: General-Purpose Output 1 (GPO1) Control Register Field Descriptions
GPO[13:10]
General-Purpose Output 1 (GPO1) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO1.
GPO13
GPO12
GPO11
GPO10
GPO1 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO1 is forced low (default)
GPO1 is forced high
Reserved
Transmitter interrupt, active low
Receiver interrupt, active low
Receiver 50/15-μs pre-emphasis, active low
Receiver non-audio data, active high
Receiver non-valid data, active high
Receiver channel status bit
Receiver user data bit
Receiver block start clock
Receiver COPY bit
(0 = copyright asserted, 1 = copyright not asserted)
1
1
0
1
1
0
1
0
Receiver L-bit
(0 = first generation or higher, 1 = original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver parity error, active high
Receiver internal sync clock
Transmitter internal sync clock
Figure 51. Register 1C: General-Purpose Output 2 (GPO2) Control Register
7 (MSB)
0
6
0
5
0
4
0
3
2
1
0 (LSB)
GPO20
GPO23
GPO22
GPO21
Table 30. Register 1C: General-Purpose Output 2 (GPO2) Control Register Field Descriptions
GPO[23:20]
General-Purpose Output 2 (GPO2) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO2.
GPO23
GPO22
GPO21
GPO20
GPO2 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO2 is forced low (default)
GPO2 is forced high
Reserved
Transmitter interrupt, active low
Receiver interrupt, active low
Receiver 50/15-μs pre-emphasis, active low
Receiver non-audio data, active high
Receiver non-valid data, active high
Receiver channel status bit
Receiver user data bit
Receiver block start clock
Receiver COPY bit
(0 = copyright asserted, 1 = copyright not asserted)
1
1
0
1
1
0
1
0
Receiver L-bit
(0 = first generation or higher, 1 = original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver parity error, active high
Receiver internal sync clock
Transmitter internal sync clock
42
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Figure 52. Register 1D: General-Purpose Output 3 (GPO3) Control Register
7 (MSB)
0
6
0
5
0
4
0
3
2
1
0 (LSB)
GPO30
GPO33
GPO32
GPO31
Table 31. Register 1D: General-Purpose Output 3 (GPO3) Control Register Field Descriptions
GPO[33:30]
General-Purpose Output 3 (GPO3) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO3.
GPO33
GPO32
GPO31
GPO30
GPO3 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO3 is forced low (default)
GPO3 is forced high
Reserved
Transmitter interrupt, active low
Receiver interrupt, active low
Receiver 50/15-μs pre-emphasis, active low
Receiver non-audio data, active high
Receiver non-valid data, active high
Receiver channel status bit
Receiver user data bit
Receiver block start clock
Receiver COPY bit
(0 = copyright asserted, 1 = copyright not asserted)
1
1
0
1
1
0
1
0
Receiver L-bit
(0 = first generation or higher, 1 = original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver parity error, active high
Receiver internal sync clock
Transmitter internal sync clock
Figure 53. Register 1E: General-Purpose Output 4 (GPO4) Control Register
7 (MSB)
0
6
0
5
0
4
0
3
2
1
0 (LSB)
GPO40
GPO43
GPO42
GPO41
Table 32. Register 1E: General-Purpose Output 4 (GPO4) Control Register Field Descriptions
GPO[43:40]
General-Purpose Output 4 (GPO4) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO4.
GPO43
GPO42
GPO41
GPO40
GPO4 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO4 is forced low (default)
GPO4 is forced high
Reserved
Transmitter interrupt, active low
Receiver interrupt, active low
Receiver 50/15-μs pre-emphasis, active low
Receiver non-audio data, active high
Receiver non-valid data, active high
Receiver channel status bit
Receiver user data bit
Receiver block start clock
Receiver COPY bit
(0 = copyright asserted, 1 = copyright not asserted)
1
1
0
1
1
0
1
0
Receiver L-bit
(0 = first generation or higher, 1 = original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver parity error, active high
Receiver internal sync clock
Transmitter internal sync clock
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9.5.2.1 Registers 1F through 28: Q-Channel Sub-Code Data Registers
Registers 0x1F through 0x28 comprise the Q-channel sub-code buffer, which may be accessed for audio CD
playback. The Q-channel data provides information regarding the playback status for the current disc. The buffer
data is decoded by the DIR block.
Figure 54. Register 1F: Q-Channel Sub-Code Data Register 1 (Read-Only), Bits[7:0], Control and Address
7 (MSB)
Q0
6
5
4
3
2
1
0 (LSB)
Q7
Q1
Q2
Q3
Q4
Q5
Q6
Figure 55. Register 20: Q-Channel Sub-Code Data Register 2 (Read-Only), Bits[15:8], Track
7 (MSB)
Q8
6
5
4
3
2
1
0 (LSB)
Q15
Q9
Q10
Q11
Q12
Q13
Q14
Figure 56. Register 21: Q-Channel Sub-Code Data Register 3 (Read-Only), Bits[23:16], Index
7 (MSB)
Q16
6
5
4
3
2
1
0 (LSB)
Q23
Q17
Q18
Q19
Q20
Q21
Q22
Figure 57. Register 22: Q-Channel Sub-Code Data Register 4 (Read-Only), Bits[31:24], Minutes
7 (MSB)
Q24
6
5
4
3
2
1
0 (LSB)
Q31
Q25
Q26
Q27
Q28
Q29
Q30
Figure 58. Register 23: : Q-Channel Sub-Code Data Register 5 (Read-Only), Bits[39:32], Seconds
7 (MSB)
Q32
6
5
4
3
2
1
0 (LSB)
Q39
Q33
Q34
Q35
Q36
Q37
Q38
Figure 59. Register 24: : Q-Channel Sub-Code Data Register 6 (Read-Only), Bits[47:40], Frame
7 (MSB)
Q40
6
5
4
3
2
1
0 (LSB)
Q47
Q41
Q42
Q43
Q44
Q45
Q46
Figure 60. Register 25: Q-Channel Sub-Code Data Register 7 (Read-Only), Bits[55:48], Zero
7 (MSB)
Q48
6
5
4
3
2
1
0 (LSB)
Q55
Q49
Q50
Q51
Q52
Q53
Q54
Figure 61. Register 26: Q-Channel Sub-Code Data Register 8 (Read-Only), Bits[63:56], AMIN
7 (MSB)
Q56
6
5
4
3
2
1
0 (LSB)
Q63
Q57
Q58
Q59
Q60
Q61
Q62
Figure 62. Register 27: Q-Channel Sub-Code Data Register 9 (Read-Only), Bits[71:64], ASEC
7 (MSB)
Q64
6
5
4
3
2
1
0 (LSB)
Q71
Q65
Q66
Q67
Q68
Q69
Q70
Figure 63. Register 28: Q-Channel Sub-Code Data Register 10 (Read-Only), Bits[79:72], AFRAME
7 (MSB)
Q72
6
5
4
3
2
1
0 (LSB)
Q79
Q73
Q74
Q75
Q76
Q77
Q78
44
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9.5.2.2 Registers 29 through 2C: IEC61937 PC/PD Burst Preamble
The PC and PD burst preambles are part of the IEC61937 standard for transmission of data reduced, non-PCM
audio over a standard two-channel interface (IEC60958). Examples of data-reduced formats include Dolby AC-3,
DTS, various flavors of MPEG audio (including AAC), and Sony ATRAC. The PA and PB preambles provide
synchronization data, and are fixed values of 0xF872 and 0x4E1F, respectively. The PC preamble indicates the
type of data being carried by the interface and the PD preamble indicates the length of the burst, given as
number of bits.
Registers 0x29 through 0x2C contain the PC and PD preambles as decoded by the DIR block.
Figure 64. Register 29: Burst Preamble PC High-Byte Status Register (Read-Only)
7 (MSB)
PC15
6
5
4
3
2
1
0 (LSB)
PC08
PC14
PC13
PC12
PC11
PC10
PC09
Figure 65. Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only)
7 (MSB)
PC07
6
5
4
3
2
1
0 (LSB)
PC00
PC06
PC05
PC04
PC03
PC02
PC01
Table 33. Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only) Field Descriptions
PC[4:0], Hex
Data Type
00
Null
01
Dolby AC-3
02
Reserved
03
Pause
04
MPEG-1 layer 1
05
MPEG-1 layer 2 or 3, or MPEG-2 without extension
06
MPEG-2 Data with extension
MPEG-2 AAC ADTS
MPEG-2 layer 1 low sample rate
MPEG-2 layer 2 or 3 low sample rate
Reserved
07
08
09
0A
0B
DTS type 1
0C
DTS type 2
0D
DTS type 3
0E
ATRAC
0F
10-1F
ATRAC2/3
Reserved
Bits PC[6:5] are both set to 0.
Bit PC[7] is an Error Flag, where: 0 = A valid burst-payload; 1 = Burst-payload may contain errors.
Bits PC[12:8] are data-type dependent.
Bits PC[15:13] indicate the stream number, which is set to 0.
Figure 66. Register 2B: Burst Preamble PD High-Byte Status Register (Read-Only)
7 (MSB)
PD15
6
5
4
3
2
1
0 (LSB)
PD08
PD14
PD13
PD12
PD11
PD10
PD09
Figure 67. Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only)
7 (MSB)
PD07
6
5
4
3
2
1
0 (LSB)
PD00
PD06
PD05
PD04
PD03
PD02
PD01
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Figure 68. Register 7F: Page Selection Register
7 (MSB)
0
6
0
5
0
4
0
3
0
2
0
1
0 (LSB)
PAGE0
PAGE1
Table 34. Register 7F: Page Selection Register Field Descriptions
PAGE[1:0]
Page Selection
These bits are used to select one of three register pages for write and/or read access through the SPI or I2C serial host interface. The
Page Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary.
PAGE1
PAGE0
Register/Buffer Page Selection
0
0
1
1
0
1
0
1
Page 0, control and status registers (default)
Page 1, DIR channel status and user data buffers
Page 2, DIT channel status and user data buffers
Page 3, reserved
9.5.3 Channel Status and User Data Buffer Maps
Table 35 through Table 38 show the buffer maps for the DIR and DIT channel status and user data buffers.
For Table 35, the channel status byte definitions are dependent on the transmission mode, either Professional or
Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode.
This is applicable for Table 35 and Table 36.
For Table 37, the channel status byte definitions are dependent on the transmission mode, either Professional or
Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. In
Professional mode, Byte 23 for each channel is reserved for CRC data, which is automatically calculated and
encoded by the DIT. There is no requirement to program Byte 23 for either channel in Professional mode.
46
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Table 35. DIR Channel Status Data Buffer Map (Register Page 1)
ADDRESS
(Hex)
CHANNEL
BYTE
BIT 0 (MSB)
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
0
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
2
1
3
1
4
2
5
2
6
3
7
3
8
4
9
4
A
5
B
5
C
6
D
6
E
7
F
7
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
Copyright © 2016–2017, Texas Instruments Incorporated
47
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
Table 36. DIR User Data Buffer Map (Register Page 1)
ADDRESS
(Hex)
CHANNEL
BYTE
0
BIT 0 (MSB)
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
BIT 1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
BIT 2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
BIT 5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
48
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
Table 37. DIT Channel Status Data Buffer Map (Register Page 2)
ADDRESS
(Hex)
CHANNEL
BYTE
0
BIT 0 (MSB)
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
BIT 1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
BIT 2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
BIT 5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
0
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
2
1
3
1
4
2
5
2
6
3
7
3
8
4
9
4
A
5
B
5
C
6
D
6
E
7
F
7
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
Copyright © 2016–2017, Texas Instruments Incorporated
49
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
Table 38. DIT User Data Buffer Map (Register Page 2)
ADDRESS
(Hex)
CHANNEL
BYTE
0
BIT 0 (MSB)
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
BIT 1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
BIT 2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
BIT 5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
50
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Typical application diagrams and power-supply connections are presented in this section to aid the customer in
hardware designs employing the DIX4192-Q1 device.
Figure 69 shows typical application connections for the DIX4192-Q1 using an SPI host interface. The SPI host
will typically be a microcontroller, digital signal processor, or programmable logic device. In addition to providing
the SPI bus master, the host may be used to process interrupt and flag outputs from the DIX4192-Q1. The audio
serial ports are connected to external digital audio devices, which may include data converters, digital signal
processors, digital audio interface receivers or transmitters, or other logic devices. The DIR inputs and DIT
outputs are connected to line, optical, or logic interfaces (see Receiver Input Interfacing and Transmitter Output
Interfacing). Master and DIR reference clock sources are also shown.
Figure 70 shows typical application connections for the DIX4192-Q1 using an I2C bus interface. The I2C bus
master will typically be a microcontroller, digital signal processor, or programmable logic device. In addition to
providing the I2C bus master, the host may be used to process interrupt and flag outputs from the DIX4192-Q1.
Pullup resistors are connected from SCL (pin 20) and SDA (pin 22) to the VIO supply rail. These resistors are
required for the open drain outputs of the I2C interface. All other connections to the DIX4192-Q1 are the same as
the SPI host case discussed previously.
Figure 71 shows the recommended power-supply connections and bypassing for the DIX4192-Q1. In this case, it
is assumed that the VIO, VDD33, and VCC supplies are powered from the same 3.3-V power source. The
VDD18 core supply is powered from a separate supply, or derived from the 3.3-V supply using a linear voltage
regulator, as shown with the optional regulator circuitry of Figure 71.
The 0.1-μF bypass capacitors are surface-mount X7R ceramic, and must be located as close to the device as
possible. These capacitors must be connected directly between the supply and corresponding ground pins of the
DIX4192-Q1. The ground pin is then connected directly to the ground plane of the printed circuit board (PCB).
The larger value capacitors, shown connected in parallel to the 0.1-μF capacitors, are recommended. At a
minimum, there must at least be footprints on the PCB for installation of these larger capacitors, so that
experiments can be run with and without the capacitors installed, in order to determine the effect on the
measured performance of the DIX4192-Q1. The larger value capacitors can be surface-mount X7R multilayer
ceramic or tantalum chip.
The substrate ground, BGND (pin 44), must be connected by a PCB trace to AGND (pin 10). The AGND pin is
then connected directly to the ground plane. This connection helps to reduce noise in the DIR section of the
device, aiding the overall jitter and noise tolerance for the receiver.
A series resistor is shown between the 3.3-V supply and VCC (pin 9) connection. This resistor combines with the
bypass capacitors to create a simple RC filter to remove higher frequency components from the VCC supply. The
series resistor must be a metal film type for best filtering characteristics. As a substitute for the resistor, a ferrite
bead can be used, although it may have to be physically large in order to contribute to the filtering.
Copyright © 2016–2017, Texas Instruments Incorporated
51
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
Application Information (continued)
TI Device
37
38
39
40
41
42
43
44
45
46
47
48
36
35
34
33
32
31
30
29
28
27
26
25
BCKA
LRCKA
SDINA
SDOUTA
NC
VIO
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
SYNC
BLS
AESOUT
VDD33
TX+
Audio
I/O
Device
To Host or External Logic
To Digital Outputs
(Line, Optical, Logic)
TX-
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
Audio
I/O
Device
To Host or External Logic
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
RST
INT
SDA
A1
SCL
From Digital Inputs
(Line, Optical, Logic)
SPI
Host
A0
CPM
VDD18
DGND1
NC
NC
RXCKI
Controller
10
11
12
AGND
LOCK
RXCKO
DIR Recovered Clock
Master
Clock
10 kW
VIO
DIR
Ref Clock
Copyright © 2017, Texas Instruments Incorporated
Figure 69. Typical Application Diagram Using SPI Host Interface
(See Figure 71 for Power-Supply Connections)
TI Device
37
38
39
40
41
42
43
44
45
46
47
48
36
35
34
33
32
31
30
29
28
27
26
25
BCKA
SYNC
BLS
AESOUT
VDD33
TX+
Audio
I/O
Device
To Host or External Logic
LRCKA
SDINA
SDOUTA
NC
To Digital Outputs
(Line, Optical, Logic)
VIO
TX-
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
Audio
I/O
Device
To Host or External Logic
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
RST
INT
SDA
A1
SCL
From Digital Inputs
(Line, Optical, Logic)
I2C
Host
A0
CPM
VDD18
DGND1
NC
NC
RXCKI
Controller
Tie
LO or HI
10
11
12
AGND
LOCK
RXCKO
DIR Recovered Clock
Master
Clock
10 kΩ
2.7 kΩ
VIO
DIR
Ref Clock
Copyright © 2017, Texas Instruments Incorporated
Figure 70. Typical Application Diagram Using I2C Host Interface
(See Figure 71 for Power-Supply Connections)
52
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
Application Information (continued)
3.3 V
10 µF
+
R may be set from 2 Ω to 10 Ω,
or replaced by a ferrite bead.
44
0.1 µF
R
43
42
TI Device
9
33
30
+
+
0.1 µF
10 µF
10 µF
0.1 µF
10
Connect pin 44 to pin 10.
Pin 10 is then connected to
the ground plane.
3.3 V
TPS79318DBVR
16
17
0.1 µF
1
3
5
4
C may be set to 10 µF,
or not installed when using
the optional regulator circuit.
IN
EN
OUT
NR
GND
2
C
+
0.01 µF
0.1 µF
2.2 µF
1.8 V
Copyright © 2017, Texas Instruments Incorporated
Optional Regulator Circuit
Figure 71. Recommended Power-Supply Connections
10.1.1 Digital Audio Transformer Vendors
Transformers are shown in this data sheet for both receiver and transmitter balanced and unbalanced line
interface implementations. For the Texas Instruments Pro Audio evaluation modules, transformers from Scientific
Conversion are used. In addition to Scientific Conversion, there are other vendors that offer transformer products
for digital audio interface applications. Please refer to the following manufacturer websites for details regarding
their products and services. Other transformer vendors may also be available by searching catalog and/or
Internet resources.
•
•
•
Scientific Conversion: http://scientificonversion.com
Schott Corporation: http://schottcorp.com
Pulse Engineering: http://pulseeng.com
10.1.2 Receiver Input Interfacing
This section details the recommended interfaces for the DIX4192-Q1 line receiver inputs. Balanced and
unbalanced line interfaces, in addition to optical receiver and external logic interfacing, are discussed.
For professional digital audio interfaces, 110-Ω balanced line interfaces are either required or preferred.
Transformer coupling is commonly employed to provide isolation and to improve common-mode noise rejection.
Figure 72 shows the recommended transformer-coupled balanced line receiver interface for the DIX4192-Q1.
The transformer is specified for a 1:1 turn ratio, and must exhibit low inter-winding capacitance for best
performance. Due to the DC bias on the line receiver inputs, 0.1-μF capacitors are used for AC-coupling the
transformer to the line receiver inputs. On the line side of the transformer, an optional 0.1-μF capacitor is shown
for cases where a DC bias may be applied at the transmitter side of the connection. The coupling capacitors
must be surface-mount ceramic chip type with an X7R or C0G dielectric.
Copyright © 2016–2017, Texas Instruments Incorporated
53
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
Application Information (continued)
C(1)
0.1mF
1:1
To RX+
3
2
Digital Input
110W Balanced
1
110W
To RX-
XLR
0.1mF
(1) Insert a 0.1mF capacitor when blocking common-mode DC voltage.
Figure 72. Transformer-Coupled Balanced Input Interface
Unbalanced 75-Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio
applications. Designs with and without transformer line coupling may be used. Figure 73(a) shows the
recommended 75-Ω transformer-coupled line interface, which shares many similarities to the balanced design
shown in Figure 72. Once again, the transformer provides isolation and improved noise rejection. Figure 73(b)
shows the transformer-free interface, which is commonly used for S/PDIF consumer connections.
C(1)
0.1mF
1:1
To RX+
Digital Input
75W Unbalanced
(RCA or BNC Connector)
75W
To RX-
0.1mF
(a) Transformer-Coupled Unbalanced Line Interface
0.1mF
To RX+
Digital Input
75W Unbalanced
(RCA or BNC Connector)
75W
To RX-
0.1mF
(b) Unbalanced Line Interface Without Transformer
(1) Insert a 0.1mF capacitor when blocking common-mode DC components.
Figure 73. Unbalanced Line Input Interfaces
Optical interfaces using all-plastic fiber are commonly employed for consumer audio equipment where
interconnections are less than 10 m in length. Optical receiver modules used for a digital audio interface operate
from either a single 3.3-V or 5-V supply and have a TTL–, CMOS-, or low-voltage CMOS-compatible logic output.
Interfacing to 3.3-V optical receivers is straightforward when the optical receiver supply is powered from the
DIX4192-Q1 VDD33 power source, as shown in Figure 74. For the 5-V optical receivers, the output high logic
level may exceed the DIX4192-Q1 line receiver absolute maximum input voltage. A level translator is required,
placed between the optical receiver output and the DIX4192-Q1 line receiver input. Figure 75 shows the
recommended input circuit when interfacing a 5-V optical receiver to the DIX4192-Q1 line receiver inputs. The
Texas Instruments SN74LVC1G125 single buffer IC is operated from the same 3.3-V supply used for DIX4192-
Q1 VDD33 supply. This buffer includes a 5-V tolerant digital input, and provides the logic level translation
required for the interface.
VDD33
All-Plastic
(5 or 10 meters maximum)
Optical
Receiver(1)
To RX+
To RX-
0.1mF
(1) Toshiba TORX141 or equivalent.
Figure 74. Interfacing to a 3.3-V Optical Receiver Module
54
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
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ZHCSFA7A –JULY 2016–REVISED APRIL 2017
Application Information (continued)
SN74LVC1G125
or Equivalent
+5V
VDD33
5
2
4
All-Plastic
(5 or 10 meters maximum)
Optical
Receiver(1)
To RX+
To RX-
1
3
0.1mF
(1) Toshiba TORX173, TORX176, TORX179, or equivalent.
Figure 75. Interfacing to a 5-V Optical Receiver Module
The DIX4192-Q1 line receivers may also be driven directly from external logic or line receiver devices with TTL
or CMOS outputs. If the logic driving the line receiver is operated from 3.3 V, then logic level translation will not
be required. However, if the external logic is operated from a power-supply voltage that exceeds the maximum
VDD33 supply voltage of the DIX4192-Q1, or operates from a supply voltage lower than 3.3 V, then level
translation is required. Figure 76 shows the recommended logic level translation methods, using buffers and level
translators available from Texas Instruments.
SN74LVC1G125
or Equivalent
VDD33
5
2
4
From +5V Logic
(TTL or CMOS)
To RX+
To RX-
1
3
0.1mF
SN74AVC1T45
or Equivalent
+1.8V or +2.5V
VDD33
1
5
6
3
4
From +1.8V or +2.5V
CMOS Logic
To RX+
To RX-
2
0.1mF
Figure 76. CMOS and TTL Input Logic Interface
10.1.3 Transmitter Output Interfacing
This section details the recommended interfaces for the DIX4192-Q1 transmitter line driver and CMOS-buffered
outputs. Balanced and unbalanced line interfaces, in addition to optical transmitter and external logic interfacing,
will be discussed.
For professional digital audio interfaces, 110-Ω balanced line interfaces are either required or preferred.
Transformer coupling is commonly employed to provide isolation and to improve common-mode noise
performance. Figure 77 shows the recommended transformer-coupled balanced line driver interface for the
DIX4192-Q1. The transformer is specified for a 1:1 turn ratio, and must exhibit low inter-winding capacitance for
best performance. To eliminate residual DC bias, a 0.1-μF capacitor is used for AC-coupling the transformer to
the line driver outputs. The coupling capacitor must be a surface-mount ceramic chip type with an X7R or C0G
dielectric.
Copyright © 2016–2017, Texas Instruments Incorporated
55
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
Application Information (continued)
1:1
110W
TX+
3
2
Digital Output
110W Balanced
1
TX-
XLR
0.1mF
Figure 77. Transformer-Coupled Balanced Output Interface
Unbalanced 75-Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio
applications. Designs with and without transformer line coupling may be used. Figure 78(a) shows the
recommended 75-Ω transformer-coupled line driver interface, which shares many similarities to the balanced
design shown in Figure 77. Figure 78(b) shows the transformer-free line driver interface, which is commonly used
for S/PDIF consumer connections.
1:1
0.1mF
R1
TX+
Digital Output
75W Unbalanced
(RCA or BNC connector)
R2
(a) Transformer-Coupled Unbalanced Output
0.1mF
R1
TX+
Digital Output
75W Unbalanced
(RCA or BNC connector)
R2
(b) Unbalanced Output Without Transformer
R1 and R2 are selected to achieve the desired output voltage level while maintaining the required 75W transmitter output impedance.
The TX+ output impedance is negligible.
Figure 78. Unbalanced Line Output Interfaces
Optical interfaces using all-plastic fiber are commonly employed for consumer audio equipment where
interconnections are less than 10 m in length. Most optical transmitter modules used for a digital audio interface
operate from a single 3.3-V or 5-V supply and have a TTL-compatible logic input. The CMOS-buffered transmitter
output of the DIX4192-Q1, AESOUT (pin 34), is capable of driving the optical transmitter with VIO supply
voltages down to 3 V. If the VIO supply voltage is less than 3 V, then level translation logic is required to drive
the optical transmitter input. A good choice for this application is the Texas Instruments SN74AVC1T45 single
bus transceiver. This device features two power-supply rails, one for the input side and one for the output side.
For this application, the input side supply is powered from the VIO supply, while the output side is powered from
a 3.3-V supply. This configuration will boost the logic high level to a voltage suitable for driving the TTL-
compatible input configuration. Figure 79 shows the recommended optical transmitter interface circuits.
56
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
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ZHCSFA7A –JULY 2016–REVISED APRIL 2017
Application Information (continued)
Optical
All-Plastic Fiber
(5 or 10 meters maximum)
Transmitter(1)
AESOUT
VIO
+3.3V
6
1
5
If VIO < +3.0V.
3
4
2
SN74AVC1T45
or Equivalent
(1) Toshiba TOTX141, TOTX173, TOTX176, TOTX179, or equivalent.
Figure 79. Interfacing to an Optical Transmitter Module
The AESOUT output may also be used to drive external logic or line driver devices directly. Figure 80 shows the
recommended logic interface techniques, including connections with and without level translation. Figure 81
shows an external line driver interface using the Texas Instruments SN75ALS191 dual differential line driver. If
the VIO supply of the DIX4192-Q1 is set from 3 V to 3.3 V, no logic level translation will be required between the
AESOUT output and the line driver input. If the VIO supply voltage is below this range, then the optional logic
level translation logic of Figure 81 will be required. The SN75ALS191 dual line driver is especially useful in
applications where simultaneous 75-Ω and 110-Ω line interfaces are required.
Direct to external logic
operating from the VIO supply.
+5V
AESOUT
5
2
4
To +5V Logic
(VIO supply = +3.0V to +3.3V)
3
1
SN74AHCT1G125
or Equivalent
Figure 80. CMOS or TTL Output Logic Interface
+5V
SN75ALS191
1
8
2
3
To Balanced or Unbalanced
Line Interface
AESOUT
7
VIO
1
+3.3V
6
6
5
5
If VIO < +3.0V.
To Balanced or Unbalanced
Line Interface
3
4
2
SN74AVC1T45
or Equivalent
1
Figure 81. External Line Driver Interface
Copyright © 2016–2017, Texas Instruments Incorporated
57
DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
10.2 Typical Application
PCM x1
x4
x1
IN
S/PDIF
DSP
GPO/INT
I2C
DIX4192-Q1
OUT
S/PDIF
PCM x1
PCM5242
TPA6120A2
Copyright © 2017, Texas Instruments Incorporated
Figure 82. DIX4192-Q1 Typical Application
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 39.
Table 39. Design Parameters
DESIGN PARAMETER
Audio input
EXAMPLE VALUE
PCM x2, differential S and PDIF x4
PCM x2, S and PDIF x4
Host 12C
Audio output
Control
RXCKI or MCLK
24.576 MHz
10.2.2 Detailed Design Procedure
10.2.2.1 Differential Line Inputs and Output
The DIX4192-Q1 has a total of 4 differential Line inputs and one Differential Line output. The 4 inputs are MUXed
to one port for decoding and the audio data is sent to the internal bus of the device. The differential line output
can choose from either the AES3 encoder or directly from one of the RX inputs. The AES3 encoder can encode
either of the serial ports or the DIR itself. User data and channel status data can be updated in registers.
10.2.2.2 Serial Ports
The DIX4192-Q1 has two serial ports which each support both input and output of PCM data. This allows a
device to receive data from one of the serial ports and then return audio to the DIX4192-Q1 to be routed to
another output of the DIX4192-Q1. For example in this application the DSP can receive audio from the DIX4192-
Q1 that was input to the DIX4192-Q1 over S/PDIF, then after processing the DSP can send audio back the
DIX4192-Q1 over the same serial port. This processed audio can then be sent back out the S/PDIF transmit port
of the DIX4192-Q1 or to the PCM5242 DAC on the other serial port.
58
Copyright © 2016–2017, Texas Instruments Incorporated
DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
10.2.3 Application Curves
2
0
-10
-20
5
2
Input Jitter Amplitude
-30
-2
1
-40
Output Jitter Amplitude
-4
500m
200m
100m
50m
20m
10m
5m
-50
-60
-6
-70
-8
-80
-10
-12
-14
-16
-18
-20
-90
-100
-110
-120
-130
-140
-150
THD+N
2m
1m
100
101
102
103
104
105
106
20
100
1k
10k
100k
Jitter Frequency (Hz)
Sinusoidal Jitter Frequency (Hz)
Figure 83. DIR Jitter Attenuation Characteristics
Figure 84. DIR Jitter Tolerance Plot
11 Power Supply Recommendations
The DIX4192-Q1 requires a 1.8-V and 3.3-V nominal supply rails. At least one 3.3-V supply is required for VCC,
VDD33. VIO can operate at 1.8 V or at 3.3 V. VDD18 requires a 1.8-V nominal supply rail. The decoupling
capacitors for the power supplies must be placed close to the device terminals.
Copyright © 2016–2017, Texas Instruments Incorporated
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DIX4192-Q1
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
TI recommends to use one ground plane for the DIX4192-Q1. While using one ground plane, it is best to ensure
that analog and digital circuitry be sufficiently partitioned on the PCB so that analog and digital return currents do
not cross.
•
•
Decoupling capacitors must be placed as close to power pins as possible (VCC, VDD33, VDD18, VIO).
Further guidelines can be found in Layout Example.
12.2 Layout Example
It is recommended to place a top layer ground pour for shielding around PCM9211 and
connect to lower main PCB ground plane by multiple vias
Series resistors between
50 ꢁ and 100 Ω
on PCM ports can reduce
reflections if necessary
Port A PCM
Port B PCM
Input and Output
Input and Output
VIO
10 µF
0.1 ꢀF
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
36
35
34
33
RX1+
SYNC
BLS
RX1œ
RX2+
AESOUT
VDD33
RX2œ
3.3 V
10 ꢀF
Differential
Line Inputs
0.1 ꢀF
32
RX3+
TX+
RX3œ
31
30
29
28
27
26
25
TXœ
DIX4192-Q1
RX4+
RX4œ
VCC
DGND2
GPO4
3.3 V
GPO to
Host
GPO3
GPO2
0.1 ꢀF
10 ꢀF
10 AGND
11 LOCK
GPO1
MCLK
RXCKO
12
13 14 15 16 17 18 19 20 21 22 23 24
INT pin must be pulled up to VIO
through 10-kΩ resistor
0.1 ꢀF
10 ꢀF
10 kΩ
VIO
Control Interface
1.8 V
Copyright © 2017, Texas Instruments Incorporated
Pad to top layer ground pour
Top Layer Ground Pour and PowerPad
Top Layer Signal Traces
Figure 85. DIX4192-Q1 Board Layout
60
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DIX4192-Q1
www.ti.com.cn
ZHCSFA7A –JULY 2016–REVISED APRIL 2017
13 器件和文档支持
13.1 器件支持
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 开发支持
相关开发支持请参阅以下文档：
•
•
•
•
•
•
•
•
AES 网站：http://www.aes.org
IEC 网站：http://www.iec.ch
ANSI 网站：http://www.ansi.org
日本电子与信息技术工业协会 (JEITA) 网站：http://www.jeita.or.jp/english
飞利浦网站：http://www.philips.com
Scientificonversion 网站：http://www.scientificonversion.com
Schott Magnetics 网站：http://www.schottcorp.com/
Pulse Electronics 网站：http://www.pulseelectronics.com/
13.2 文档支持
13.2.1 相关文档
相关文档如下：
•
•
•
•
•
•
•
DIT4096 96kHz 数字音频发送器 (SBOS225)
DIT4192 192kHz 数字音频发送器 (SBOS229)
SRC4184 4 通道异步采样率转换器 (SBFS026)
SRC419x 192kHz 立体声异步采样率转换器 (SBFS022)
具有三态输出的 SN74LVC1G125 单路总线缓冲器闸 (SCES223)
具有可配置电压转换和三态输出的 SN74AVC1T45 单比特双电源总线收发器 (SCES530)
SN75ALS191 双路差动线路驱动器 (SLLS032)
13.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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13.5 商标
E2E is a trademark of Texas Instruments.
Dolby is a registered trademark of Dolby Laboratories, Inc.
SPI is a trademark of Motorola.
I2S is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
62
版权 © 2016–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DIX4192IPFBRQ1
DIX4192TPFBRQ1
ACTIVE
ACTIVE
TQFP
TQFP
PFB
PFB
48
48
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
DIX4192I
DIX4192T
NIPDAU
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DIX4192IPFBRQ1
DIX4192TPFBRQ1
TQFP
TQFP
PFB
PFB
48
48
1000
1000
330.0
330.0
16.4
16.4
9.6
9.6
9.6
9.6
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DIX4192IPFBRQ1
DIX4192TPFBRQ1
TQFP
TQFP
PFB
PFB
48
48
1000
1000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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