DLP3030AFYJQ1 [TI]
DLP® 汽车类 0.3 英寸数字微镜器件 (DMD) | FYJ | 149 | -40 to 105;
| 型号： | DLP3030AFYJQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DLP® 汽车类 0.3 英寸数字微镜器件 (DMD) | FYJ | 149 | -40 to 105 |
| 文件： | 总37页 (文件大小：870K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
适用于汽车内部显示的 DLP3030-Q1 0.3 英寸 WVGA DMD
1 特性
3 说明
1
•
通过汽车认证
0.3 英寸对角线微镜阵列
DLP3030-Q1 汽车 DMD 主要针对具有很大视野或增
强现实功能（需要长焦距）的汽车抬头 显示 (HUD) 应
用 。该芯片组能够与 LED 或激光器配合使用，以生成
具有 125% 以上 NTSC 色域的深度饱和颜色并支持 24
位 RGB 视频输入。此外，该芯片组可以凭借宽动态范
围和快速开关功能（不随温度的变化而变化）实现高亮
度（15,000cd/m2 典型值）HUD 系统。当用于 TI 参考
设计中时，能够实现超过 5000:1 的极高动态范围，以
满足汽车 HUD 系统针对明亮的白昼和黑暗的夜晚驾驶
条件的工作范围要求。
•
–
–
–
7.6µm 微镜间距
±12° 微镜倾斜角（相对于平面）
采用侧面照明以提高效率
•
•
WVGA (864 × 480) 分辨率
偏振无关型空间光调制器
–
–
与 LED 或激光光源兼容
可通过偏光眼镜看到图像
•
•
•
•
•
•
低功耗：105mW（典型值）
工作温度范围：-40°C 至 105°C
具有 2.5°C/W 热效率的密封封装
可实现系统内验证的 JTAG 边界扫描
与 DLPC120-Q1 汽车 DMD 控制器兼容
78MHz DDR DMD 接口
器件信息(1)
封装
器件型号
封装尺寸（标称值）
DLP3030-Q1
FYJ (149)
22.30mm × 32.20mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
宽视场和增强现实平视显示 (HUD)
高分辨率前照灯
车内投影显示和照明
DLP®DLP3030-Q1 系统框图
Color & Dimming control
Flash
SPI
I2C
TMS320
F28023
Color
Controller
& Driver
Host
SPI
DLPC120-Q1
LEDs
Illumination
Control
& Feedback
Video
Processing &
DMD
real-time
optical
feedback
loop
24-bit RGB
& Syncs
Formatting
photo diode
LED Enable
Timing Control
Data & Control
DLP3030-Q1
Reset
.3" WLP(H) s450
DVSP DMD
Power Good
I2C
TMP411
-Q1
Data &
Address
DMD Power
DDR-2 DRAM
frame buffer
TPS65100
-Q1
Power Enable
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS076
DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
www.ti.com.cn
目录
7.4 Optical Performance ............................................... 27
7.5 DMD Image Quality Specification ........................... 28
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 Storage Conditions.................................................... 7
6.3 ESD Ratings.............................................................. 7
6.4 Recommended Operating Conditions....................... 8
6.5 Thermal Information................................................ 10
6.6 Electrical Characteristics......................................... 10
6.7 Timing Requirements.............................................. 12
6.8 Switching Characteristics........................................ 16
6.9 System Mounting Interface Loads .......................... 16
6.10 Physical Characteristics of the Micromirror Array. 17
6.11 Optical Characteristics of the Micromirror Array... 18
6.12 Window Characteristics......................................... 19
6.13 Chipset Component Usage Specification ............. 19
Detailed Description ............................................ 20
7.1 Overview ................................................................. 20
7.2 Functional Block Diagram ....................................... 20
7.3 Feature Description................................................. 20
7.6 Definition of Micromirror Landed-On/Landed-Off Duty
Cycle ........................................................................ 28
8
9
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Application .................................................. 29
8.3 Application Mission Profile Consideration............... 30
Power Supply Recommendations...................... 31
9.1 Power Supply Sequencing Requirements .............. 31
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Temperature Diode Pins....................................... 33
10.3 Layout Example .................................................... 33
11 器件和文档支持 ..................................................... 34
11.1 器件支持................................................................ 34
11.2 文档支持................................................................ 35
11.3 接收文档更新通知 ................................................. 35
11.4 社区资源................................................................ 35
11.5 商标....................................................................... 35
11.6 静电放电警告......................................................... 35
11.7 器件处理................................................................ 35
11.8 Glossary................................................................ 35
12 机械、封装和可订购信息....................................... 35
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2018) to Revision B
Page
•
•
•
Added illumination overfill maximum allowable heat load specifications, table notes, and figure in Recommended
Operating Conditions.............................................................................................................................................................. 9
Added calculation for array width and height with respect to number of active columns and rows in the Physical
Characteristics of the Micromirror Array table ...................................................................................................................... 17
Deleted axis-of-rotation specification from Optical Characteristics of the Micromirror Array table, as it was deemed
unnecessary for customer designs....................................................................................................................................... 18
•
•
Deleted illumination overfill row and corresponding table note in the Window Characteristics table................................... 19
Changed description of illumination overfill in the Illumination Overfill and Alignment section and added reference to
Recommended Operating Conditions overfill specification .................................................................................................. 27
•
已添加 器件处理 部分 ........................................................................................................................................................... 35
Changes from Original (November 2017) to Revision A
Page
•
•
•
•
•
•
•
•
已更改 将器件状态从高级信息 更改为生产数据...................................................................................................................... 1
已更改 将封装标识符从 CPGA 更改为 FYJ ............................................................................................................................ 1
Added comment to ground VCCH and VSSH pins .................................................................................................................... 6
Changed maximum DMD storage temperature from 105°C to 125°C in Storage Conditions table....................................... 7
Changed IOFFSET from 2.16 mA to 2.93 mA in Electrical Characteristics table..................................................................... 10
Changed IRESET from 1.5 mA to -2.00 mA in Electrical Characteristics table ....................................................................... 10
Changed POFFSET from 13.2 mW to 25.64 mW in Electrical Characteristics table................................................................ 11
Changed PBIAS from 37.3 mW to 37.95 mW in Electrical Characteristics table.................................................................... 11
2
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
•
•
•
•
Changed PRESET from 15.8 mW to 21.00 mW in Electrical Characteristics table................................................................. 11
Changed PTOTAL from 236.6 mW to 254.77 mW in Electrical Characteristics table ............................................................ 11
Added table note in Optical Parameters table...................................................................................................................... 18
已更改 更改了器件标记 部分中的器件标记编号.................................................................................................................... 34
Copyright © 2017–2019, Texas Instruments Incorporated
3
DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
www.ti.com.cn
5 Pin Configuration and Functions
FYJ Package
149-Pin CPGA
Bottom View
4
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
Pin Configurations and Functions
PIN
I/O
DESCRIPTION
TRACE, mm(1)
NAME
NO.
F18
F20
G20
G19
H19
G18
J20
DATA(0)
DATA(1)
DATA(2)
DATA(3)
DATA(4)
DATA(5)
DATA(6)
DATA(7)
DATA(8)
DATA(9)
DATA(10)
DATA(11)
DATA(12)
DATA(13)
DATA(14)
DCLK
Data bus. Synchronous to rising edge and falling edge
of DCLK.
H20
J19
8.059
K18
K19
L20
L18
K20
M18
N18
Data clock.
LVCMOS input
Parallel latch load enable. Synchronous to rising edge
and falling edge of DCLK.
LOADB
M20
N19
M19
A7
10.939
6.596
Serial control (sync). Synchronous to rising edge and
falling edge of DCLK.
SCTRL
Toggle rate control. Synchronous to rising edge and
falling edge of DCLK.
TRC
8.617
Reset control serial bus. Synchronous to rising edge of
SAC_CLK.
DAD_BUS
RESET_OEZ
RESET_STROBE
SAC_BUS
10.413
13.37
Active low. Output enable signal for internal reset
driver circuitry.
A5
Rising edge on RESET_STROBE latches in the
control signals.
A10
B9
13.329
12.586
Stepped address control serial bus. Synchronous to
rising edge of SAC_CLK.
SAC_CLK
TCK
A8
Stepped address control clock.
JTAG clock.
12.668
10.489
M2
JTAG data input. Synchronous to rising edge of TCK.
Bond pad connects to internal pull up resistor.
TDI
N3
M3
R5
11.04
JTAG data output. Synchronous to falling edge of
TCK. Tri-state failsafe output buffer.
TDO
TMS
LVCMOS output
LVCMOS input
10.067
10.413
JTAG mode select. Synchronous to rising edge of
TCK. Bond pad connects to internal pull up resistor.
TEMP_MINUS
TEMP_PLUS
T10
T11
N/A
N/A
Calibrated temperature diode used to assist accurate
temperature measurements of DMD die.
Analog Input
A3, A18, A19,
A20, B2, B10,
B18, B19, B20,
C1, C20, D18,
D19, D20, E18,
E19, E20, N20,
P20, R18, R19,
R20, T18, T19,
T20
No Connect (Unused)
N/A
N/A
N/A
(1) Propagation delay is 10.24 ps/mm for the DMD Series 450 ceramic package trace lengths.
Copyright © 2017–2019, Texas Instruments Incorporated
5
DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
www.ti.com.cn
Pin Configurations and Functions (continued)
PIN
I/O
DESCRIPTION
TRACE, mm(1)
NAME
NO.
Power supply for positive bias level of mirror reset
signal.
(2)
VBIAS
F3, K3, L3
N/A
A9, A12, A14,
A16, B13, B16,
R12, R13, R16,
R17, T13, T14,
T16
Power supply for low voltage CMOS logic. Power
supply for normal high voltage at mirror address
electrodes. Power supply for offset level of mirror reset
signal during power down.
Power
(2)
VCC
N/A
P3, R3, T3, T4,
T5, T6
VCCH
Connect to GND Reserved pin.
Power supply for high voltage CMOS logic. Power
N/A
N/A
supply for stepped high voltage at mirror address
electrodes. Power supply for offset level of mirror reset
signal.
(2)
VOFFSET
D1, E1, M1, N1
(2)
VREF
B11, B12
Power supply for low voltage CMOS DDR interface.
N/A
N/A
Power supply for negative reset level of mirror reset
signal.
(2)
VRESET
B3, C3, E3
A6, A11, A13,
A15, A17, B4,
B5, B8, B14,
B15, B17, C2,
C18, C19, F1,
F2, F19, H1,
H2, H3, H18,
J18, K1, K2,
L19, N2, P18,
P19, R4, R14,
R15, T7, T9,
T12, T15, T17
Power
(2)
VSS
Common return for all power.
N/A
N/A
P1, P2, R1, R2,
T1, T2
VSSH
Connect to GND Reserved pin.
RESERVED_BIM
RESERVED_DT
T8
R7
E2
G1
G2
G3
J1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Connect to GND Bond pad connects to internal pull down resistor.
RESERVED_RM
RESERVED_R(0)
RESERVED_R(1)
RESERVED_R(2)
RESERVED_R(3)
RESERVED_R(4)
RESERVED_R(5)
RESERVED_R(6)
RESERVED_R(7)
RESERVED_PFE
RESERVED_RA(0)
RESERVED_RA(1)
RESERVED_RA(2)
RESERVED_RS(0)
RESERVED_RS(1)
RESERVED_SO
RESERVED_TP(0)
RESERVED_TP(1)
RESERVED_TP(2)
Bond pad connects to 250k pull down resistor.
Manufacturing test.
Do not connect
J2
J3
L1
L2
R6
B6
D3
B7
A4
D2
R9
R8
R10
R11
Connect to GND Bond pad connects to internal pull down resistor.
Do not connect
Tri-state failsafe output buffer.
Connect to GND Manufacturing test.
(2) The following power supplies are required to operate the DMD: VBIAS, VCC, VOFFSET, VREF, VRESET, VSS
.
6
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
SUPPLY VOLTAGE
VREF
LVCMOS logic supply voltage(2)
LVCMOS logic supply voltage(2)
Mirror electrode and HVCMOS voltage(2)
Mirror electrode voltage
–0.5
–0.5
–0.5
–0.5
4
4
V
V
VCC
VOFFSET
VBIAS
|VBIAS – VOFFSET
VRESET
8.75
17
V
V
|
Supply voltage delta(3)
8.75
0.5
V
Mirror electrode voltage
–11
–0.5
60
V
(2)
Input voltage: other Inputs
fDCLK
See
VREF + 0.3
80
V
Clock frequency
MHz
µA
ITEMP_DIODE
Temperature diode current
500
ENVIRONMENTAL
Operating DMD array temperature (TARRAY
(monitored by TMP411-Q1 via DLPC120-Q1)
)
See (4) and Active Array Temperature
–40
105
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Unless otherwise
indicated, these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond
those indicated under Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may
affect device reliability.
(2) All voltage values are with respect to GND (VSS). VBIAS, VCC, VOFFSET, VREF, VRESET, and VSS are required to operate the DMD.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than or equal to 8.75 V.
(4) Contact TI application engineering for more details about the DMD modeled use profile.
6.2 Storage Conditions(1)
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
UNIT
Tstg
DMD storage temperature
–40
125
°C
(1) As a best practice, TI recommends storing the DMD in a temperature and humidity controlled environment.
6.3 ESD Ratings(1)
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
±2000
±500
±750
V(ESD) Electrostatic discharge
All pins
V
Charged-device model (CDM), per JESD22-C101(3)
Corner pins
(1) All CMOS devices require proper electrostatic discharge (ESD) handling procedures.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2017–2019, Texas Instruments Incorporated
7
DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
www.ti.com.cn
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE
VREF
LVCMOS interface power supply voltage(1)
LVCMOS logic power supply voltage(1)
Mirror electrode and HVCMOS voltage(1)
Mirror electrode voltage
1.65
2.25
8.25
15.5
1.8
2.5
8.5
16
1.95
2.75
V
V
VCC
VOFFSET
VBIAS
8.75
V
16.5
V
|VBIAS – VOFFSET
VRESET
VP VT+
VN VT–
VH ∆VT
IOH_TDO
IOL_TDO
|
Supply voltage delta(2)
8.75
V
Mirror electrode voltage
–9.5
0.4 × VREF
0.3 × VREF
0.1 × VREF
–10
–10.5
V
Positive going threshold voltage
0.7 × VREF
0.6 × VREF
0.4 × VREF
–2
V
Negative going threshold voltage
V
Hysteresis voltage (Vp – Vn)
V
High level output current @ Voh = 2.25 V, TDO, Vcc = 2.25 V
Low level output current @ Vol = 0.4 V, TDO, Vcc = 2.25 V
mA
mA
2
TEMPERATURE DIODE
ITEMP_DIODE
Max current source into temperature diode(3)
120
µA
ENVIRONMENTAL
2.0 mW/cm2
10 mW/cm2
(4)
ILLUV
Illumination, wavelength < 395 nm
Illumination, wavelength > 800 nm
0.68
ILLIR
Operating DMD array temperature (monitored by TMP411-Q1 via
DLPC120-Q1)(5)(6)(7)
TARRAY
–40
105
°C
(1) VBIAS, VCC, VOFFSET, VREF, VRESET, VSS are required to operate the DMD.
(2) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than or equal to 8.75 V.
(3) Temperature Diode is to allow accurate measurement of the DMD array temperature during operation.
(4) The maximum operation conditions for operating temperature and illumination UV shall not be implemented simultaneously.
(5) DMD active array temperature can be calculated as shown in Active Array Temperature section. Additionally, the DMD array
temperature is monitored in the system using the TMP411-Q1 and DLPC120-Q1 as shown in the system block diagram.
(6) For applications that are higher brightness (> 1000 lumens) or underfill the active array optically, the TMP411-Q1 and temperature
sensing diode are not sufficient to determine maximum array temperature. Contact TI Applications Engineering for array temperature
calculation methods for this application.
(7) TI assumes a normal automotive operating profile without continuous operation at either minimum or maximum temperatures. Operating
profile information for device duty cycle and temperature may be provided if requested.
8
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Illumination overfill maximum allowable heat load on left and bottom
26 mW/mm2
20 mW/mm2
sides of the aperture, TARRAY < 75°C(9)
(8)
ILLOVERFILL
Illumination overfill maximum allowable heat load on left and bottom
sides of the aperture, TARRAY > 75°C(9)
(8) See Illumination Overfill and Alignment section.
(9) Heat load outside the aperture in the red areas shown in the figure below should not exceed the values listed in the table. These values
assume a uniform distribution. For a non-uniform distribution, please contact TI Applications Engineering for additional information.
Limited illumination area
on window aperture
Window
Window
Aperture
Array
Window
0.50 mm
0.50 mm
Window
Aperture
Copyright © 2017–2019, Texas Instruments Incorporated
9
DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
www.ti.com.cn
6.5 Thermal Information
DLP3030-Q1
FYJ (CPGA)
149 PINS
2.5
THERMAL METRIC(1)
UNIT
Thermal resistance
Active area to test point 1 (TP1)(1)(2)
°C/W
(1) The total heat load on the DMD is a combination of the incident light absorbed by the active area and electrical power dissipation of the
array. See Active Array Temperature section. Optical systems should be designed to minimize the light energy falling outside the active
array area since any additional thermal load in this area can significantly degrade the reliability of the device.
(2) Thermal resistance assumes 16.3% optical overfill of the active array. Contact TI Applications Engineering for thermal resistance with an
optically underfilled array.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX
UNIT
VCC = 2.25 V
VOH
VOH2
VOL
High level output voltage
1.7
V
IOH = –8 mA
VREF = 1.8 V
IOH = –2 mA
VCC = 2.75 V
IOL = 8 mA
High level output voltage(3)
Low level output voltage
Low level output voltage(3)
1.44
V
V
V
0.4
VREF = 1.8 V
IOL = 2 mA
VOL2
0.36
VREF = 1.95 V
VOL = 0 V
–10
–5
IOZ
Output high impedance current
µA
VREF = 1.95 V
VOH = VREF
VREF = 1.95 V
VI = 0 V
10
6
IIL
Low level input current(4)
High level input current(4)
Low level input current(5)
High level input current(5)
Low level input current(6)
High level input current(6)
µA
µA
µA
µA
µA
µA
VREF = 1.95 V
VI = VREF
IIH
VREF = 1.95 V
VI = 0 V
IIL2
IIH2
IIL3
IIH3
–785
–5
VREF = 1.95 V
VI = VREF
6
VREF = 1.95 V
VI = 0 V
VREF = 1.95 V
VI = VREF
785
CURRENT
IREF
Current at VREF = 1.95 V
Current at VCC = 2.75 V
Current at VOFFSET = 8.75 V
Current at VBIAS = 16.5 V
Current at VRESET = –10.5 V
fDCLK = 80 MHz
fDCLK = 80 MHz
2.80
59.90
2.93
mA
mA
mA
mA
mA
Icc
IOFFSET
IBIAS
2.30
IRESET
–2.00
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) All voltage values are with respect to the ground pins (VSS).
(3) Specification is for LVCMOS JTAG output pin TDO.
(4) Specification is for LVCMOS input pins, which do not have pull up or pull down resistors. See Pin Configuration and Functions section.
(5) Specification is for LVCMOS input pins which do have pull up resistors (JTAG: TDI, TMS). See Pin Configuration and Functions section.
(6) Specification is for LVCMOS input pins which do have pull down resistors. See Pin Configuration and Functions section.
10
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
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ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX
UNIT
POWER(7)
PREF
Power at VREF = 1.95 V
fDCLK = 80 MHz
fDCLK = 80 MHz
5.46
164.73
25.64
mW
mW
mW
mW
mW
mW
PCC
Power at VCC = 2.75 V
POFFSET
PBIAS
Power at VOFFSET = 8.75 V
Power at VBIAS = 16.5 V
Power at VRESET = –10.5 V
Total power at nominal conditions
37.95
PRESET
PTOTAL
CAPACITANCE
CIN
21.00
fDCLK = 80 MHz
105
254.77
Input pin capacitance
ƒ = 1 MHz
ƒ = 1 MHz
ƒ = 1 MHz
20
65
20
pF
pF
pF
Analog pin capacitance (TEMP_PLUS
and TEMP_MINUS pins)
CA
Co
Output pin capacitance
(7) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also
required.
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6.7 Timing Requirements
Over Recommended Operating Conditions unless otherwise noted.
MIN
NOM
MAX
UNIT
DMD MIRROR AND SRAM CONTROL LOGIC SIGNALS
tSU
tH
tSU
tH
Setup time SAC_BUS low before SAC_CLK↑
Hold time SAC_BUS low after SAC_CLK↑
Setup time DAD_BUS high before SAC_CLK↑
Hold time DAD_BUS after SAC_CLK↑
1.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
tC
Cycle time SAC_CLK
12.5
5.0
16.67
tW
tR
Pulse width 50% to 50% reference points: SAC_CLK high or low
Rise time 20% to 80% reference points: SAC_CLK
Fall time 80% to 20% reference points: SAC_CLK
2.5
2.5
tF
DMD DATA PATH AND LOGIC CONTROL SIGNALS
tSU
tH
tSU
tH
tSU
tH
tSU
tH
tSU
tH
Setup time DATA(14:0) before DCLK↑ or DCLK↓
Hold time DATA(14:0) after DCLK↑ or DCLK↓
Setup time SCTRL before DCLK↑ or DCLK↓
Hold time SCTRL after DCLK↑ or DCLK↓
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
3.5
12.5
5.0
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time TRC before DCLK↑ or DCLK↓
Hold time TRC after DCLK↑ or DCLK↓
Setup time LOADB low before DCLK↑
Hold time LOADB low after DCLK↓
Setup time RESET_STROBE high before DCLK↑
Hold time RESET_STROBE after DCLK↑
tC
Cycle time DCLK
16.67
tW
Pulse width 50% to 50% reference points: DCLK high or low
Pulse width 50% to 50% reference points: LOADB low
Pulse width 50% to 50% reference points: RESET_STROBE high
Rise time 20% to 80% reference points: DCLK, DATA, SCTRL, TRC, LOADB
Fall time 80% to 20% reference points: DCLK, DATA, SCTRL, TRC, LOADB
tW(L)
tW(H)
tR
2.5
2.5
tF
JTAG BOUNDARY SCAN CONTROL LOGIC SIGNALS
fTCK
tC
Clock frequency TCK
10
MHz
ns
Cycle time TCK
100
10
5
tW
tSU
tH
Pulse width 50% to 50% reference points: TCK high or low
Setup time TDI valid before TCK↑
ns
ns
Hold time TDI valid after TCK↑
25
5
ns
tSU
tH
Setup time TMS valid before TCK↑
Hold time TMS valid after TCK↑
ns
25
ns
tR
Rise time 20% to 80% reference points: TCK, TDI, TMS
Fall time 80% to 20% reference points: TCK, TDI, TMS
2.5
2.5
ns
tR
ns
12
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tC
tW
tW
50%
50%
50%
50%
50%
50%
50%
SAC_CLK
tH
tSU
50%
50%
SAC_BUS
DAD_BUS
tSU
tH
50%
50%
VREF
80%
20%
Not To Scale.
SAC_CLK
VSS
tR
tF
Figure 1. DMD Mirror and SRAM Control Logic Timing Requirements
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tW
tW
tC
DCLK
50%
50%
50%
50%
50%
tH
tH
tSU
tSU
DATA
SCTRL
TRC
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
tSU
tH
50%
50%
LOADB
tW(L)
Not To Scale
tH
tSU
50%
50%
RESET_STROBE
tW(H)
VREF
80%
20%
DCLK, DATA, SCTRL, TRC, LOADB
VSS
tR
tF
Figure 2. DMD Data Path and Control Logic Timing Requirements
14
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tW
tW
tC
50%
50%
50%
50%
TCK
tH
tSU
TDI
50%
50%
50%
TMS
TDO
50%
tPD
50%
VREF
VSS
80%
TCK, TDI, TMS
20%
tR
tF
Figure 3. JTAG Boundary Scan Control Logic Timing Requirements
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6.8 Switching Characteristics(1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CL = 11 pF, from (Input) falling edge of
TCK to (Output) TDO. See Figure 3.
tPD
Output propagation, clock to Q (see Figure 3)
3
25
ns
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
Data Sheet Timing Reference Point
Device Pin
Tester Channel
Output Under Test
CL
See Micromirror Array section for more information.
Figure 4. Test Load Circuit for Output Propagation Measurement
6.9 System Mounting Interface Loads
PARAMETER
MIN NOM
MAX
UNIT
Condition 1:
Uniformly distributed within the Thermal Interface Area shown in Figure 5
Uniformly distributed within the Electrical Interface Area shown in Figure 5
11.30
11.34
kg
kg
Condition 2:
Uniformly distributed within the Thermal Interface Area shown in Figure 5
Uniformly distributed within the Electrical Interface Area shown in Figure 5
0
kg
kg
22.64
Figure 5. System Interface Loads
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6.10 Physical Characteristics of the Micromirror Array
PARAMETER
VALUE
684
UNIT
micromirrors
micromirrors
µm
N Number of active columns
M Number of active rows
See Figure 6
See Figure 6
608
ε
Micromirror (pixel) pitch – diagonal
See Figure 7
7.6
P Micromirror (pixel) pitch – horizontal and vertical
Micromirror active array width
See Figure 7
10.8
6.5718
3.699
10
µm
P × M + P / 2; see Figure 6
(P × N) / 2 + P / 2; see Figure 6
Pond of micromirror (POM)(1)
mm
Micromirror active array height
mm
Micromirror active border
micromirrors/side
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
(0,0)
Illumination
Border Mirrors (POM) are Omitted for Clarity
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Illumination
On-State
Off-State
Tilt Direction
Tilt Direction
DMD Active Mirror Array
Col 676
Col 677
Col 678
Col 679
Col 680
Col 681
Col 682
Col 683
6.5718 mm
DMD Periphery
Figure 6. Micromirror Array Physical Characteristics
P (um)
Figure 7. Mirror (Pixel) Pitch
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6.11 Optical Characteristics of the Micromirror Array
Table 1. Optical Parameters(1)
PARAMETER
MIN
NOM
MAX
UNIT
(2)
α
β
Micromirror Tilt Angle, landed (on-state or off-state) (see
and Figure 8)
12
°
°
Micromirror Tilt Angle Variation, device to device (see (2) and Figure 8)
–1
1
(3)
DMD Efficiency, 420 nm – 680 nm (see
)
66%
(1) Optical parameters are characterized at 25°C.
(2) Mirror Tilt: Limits on variability of mirror tilt are critical in the design of the accompanying optical system. Variations in tilt angle within a
device may result in apparent non-uniformities, such as line pairing and image mottling, across the projected image especially at higher
system F/#. Variations in the average tilt angle between devices may result in colorimetry, brightness, and system contrast variations.
(3) DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection
apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the efficiency
numbers are measured with 100% electronic mirror duty cycle and do not include system optical efficiency or overfill loss. Note that this
number is measured under conditions described above and deviations from these specified conditions could result in a different
efficiency value in a different optical sytem. The factors that can incluence the DMD efficiency related to system application include: light
source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as LEDs or
lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well as the
DMD efficiency factors that are not system dependent are described in detail in the DMD Optical Efficiency Application Note, which can
be accessed by contacting TI Applications Engineering.
e
t
h
a
t
St
-
Pa
f
f
t
h
O
g
i
L
. ± ꢀ
Å. ± ꢀ
Silicon Substrate
OnœState
Micromirror
OffœState
Micromirror
Figure 8. Micromirror Tilt Angle
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6.12 Window Characteristics
PARAMETER
MIN
NOM
Corning Eagle XG
1.5119
MAX UNIT
Window material designation
Window refractive index
Window aperture(1)
at wavelength 546.1 nm
(1)
See
(1) See the package mechanical ICD for details regarding the size and location of the window aperture.
6.13 Chipset Component Usage Specification
The DLP3030-Q1 DMD is a component of the DLP® chipset including the DLPC120-Q1 DMD controller. Reliable
function and operation of the DMD requires that it be used in conjunction with DLPC120-Q1 controller.
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously
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7 Detailed Description
7.1 Overview
The DLP3030-Q1 DMD has a resolution of 608 × 684 mirrors configured in a diamond format that results in an
aspect ratio of 16:9, which combined with the DLPC120-Q1 image processing creates an effective resolution of
864 × 480 square pixels. By configuring the pixels in a diamond format, the illumination input to the DMD enters
from the side allowing for smaller mechanical packaging of the optical system. Additionally, side illumination can
also enable increased optical efficiency compared to a corner illuminated square pixel design.
7.2 Functional Block Diagram
DLP303X-Q1
DMD Data Path and Logic Control
JTAG
Controller
(0,0)
Illumination
TEMP_PLUS
Off-State
Tilt Direction
On-State
Tilt Direction
TEMP_MINUS
0.3 WVGA 16:9 Aspect Ratio
SRAM & Micromirror Array
(607,683)
DMD Mirror & SRAM Voltage Control
RESERVE PINS
(TI Internal Use)
DMD Mirror & SRAM Control Logic
7.3 Feature Description
To ensure reliable operation, the DLP3030-Q1 DMD must be used with the DLPC120-Q1 DMD Display
controller.
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Feature Description (continued)
7.3.1 Micromirror Array
The DLP3030-Q1 DMD consists of a two-dimensional array of 1-bit CMOS memory cells that determine the state
of the each of the 608 × 684 micromirrors in the array. Refer to Physical Characteristics of the Micromirror Array
for a calculation of how the 608 × 684 micromirror array represents a 16:9 dimensional aspect ratio to the user.
Each micromirror is either “ON” (tilted +12°) or “OFF” (tilted –12°). Combined with appropriate projection optical
system the DMD can be used to create clear, colorful, and vivid digital images.
7.3.2 Double Data Rate (DDR) Interface
Each DMD micromirror and its associated SRAM memory cell is loaded with data from the DLPC120-Q1 via the
DDR interface (DATA(14:0), DCLK, LOADB, SCRTL, and TRC). These signals are low voltage CMOS nominally
operating at 1.8-V level to reduce power and switching noise. This high speed data input to the DMD allows for a
maximum update rate of the entire micromirror array to be nearly 5 kHz, enabling the creation of seamless digital
images using Pulse Width Modulation (PWM).
7.3.3 Micromirror Switching Control
Once data is loaded onto the DMD, the mirrors are caused to switch position (+12° or –12°) based on the timing
signal sent to the DMD Mirror and SRAM control logic. The DMD mirrors will be switched from OFF to ON or ON
to OFF, or stay in the same position based on control signals DAD_BUS, RESET_STROBE, SAC_BUS, and
SAC_CLK, which are coordinated with the data loading by the DLPC120-Q1. In general, the DLPC120-Q1 loads
the DMD SRAM memory cells over the DDR interface, and then commands to the micromirrors to switch
position.
At power down, the DMD Mirrors are commanded by the DLPC120-Q1 to move to a near flat (0°) position as
shown in Power Supply Recommendations section. The flat state position of the DMD mirrors are referred to as
the “Parked” state. To maintain long term DMD reliability, the DMD must be properly “Parked” prior to every
power down of the DMD power supplies. Refer to the DLPC120-Q1 Programmer's Guide for information about
properly parking the DMD.
7.3.4 DMD Voltage Supplies
The micromirrors switching requires unique voltage levels to control the mechanical switching. These voltages
levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET). The specification values for VBIAS
,
VOFFSET, and VRESET are shown in Recommended Operating Conditions.
7.3.5 Logic Reset
Reset of the DMD is required and controlled by the DLPC120-Q1.
7.3.6 Temperature Sensing Diode
The DMD includes a temperature sensing diode designed to be used with the TMP411-Q1 temperature
monitoring device. The DLPC120-Q1 monitors the DMD array temperature via the TMP411-Q1 and temperature
sense diode. The DLPC120-Q1 operation of the DMD is based in part on the DMD array temperature, and
therefore, this connection is essential to ensure reliable operation of the DMD.
Figure 9 shows the typical connection between the DLPC120-Q1, TMP411-Q1, and the DLP3030-Q1 DMD. The
signals to the temperature sense diode are sensitive to system noise, therefore, care should be taken in the
routing and implementation of this circuit. See the TMP411-Q1 Data Sheet for detailed PCB layout
recommendations.
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Feature Description (continued)
DLPC120-Q1
DLP303X-Q1
TEMP_PLUS
TEMP_MINUS
50 Ω
50 Ω
SCL
SCA
D +
100 pF
THERM1
THERM2
D œ
TMP411-Q1
Figure 9. Temperature Sense Diode Typical Circuit Configuration
The DLPC120-Q1 automatically controls the DMD parking based on the temperature measured from the
temperature sense diode; however, it is recommended that the host controller manage the parking via the proper
methods described in the DLPC120-Q1 Programmer's Guide.
7.3.6.1 Temperature Sense Diode Theory
A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.
The diode is formed by connecting the transistor base to the collector. Two different known currents flow through
the diode and the resulting diode voltage is measured in each case. The difference in their base-emitter voltages
is proportional to the absolute temperature of the transistor.
Refer to the TMP411-Q1 Data Sheet for detailed information about temperature diode theory and measurement.
Figure 10 and Figure 11 illustrate the relationship between the current and voltage through the diode.
IE1
IE2
+
VBE 1,2
-
Figure 10. Temperature Measurement Theory
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Feature Description (continued)
100uA
10uA
1uA
Temperature (°C)
Temperature (°C)
Figure 11. Example of Delta VBE vs Temperature
7.3.7 Active Array Temperature
NOTE
Calculation is not valid for a headlight application utilizing an optically underfilled active
array. Contact TI Applications Engineering for array temperature calculation methods for
headlight applications.
Active array temperature can be computed analytically from measurement points on the outside of the package,
the package thermal resistance, the electrical power, and the illumination heat load.
Relationship between array temperature and the reference ceramic temperature (thermocouple location TP1 in
Figure 12) is provided by the following equations.
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
QARRAY = QELECTRICAL+ QILLUMINATION
)
(1)
where
•
•
•
•
•
•
•
•
TARRAY = computed DMD array temperature (°C)
TCERAMIC = measured ceramic temperature (TP1 location in Figure 12) (°C)
RARRAY-TO-CERAMIC = DMD package thermal resistance from array to TP1 (°C/watt) (see Thermal Information)
QARRAY = total power, electrical plus absorbed, on the DMD array (watts)
QELECTRICAL = nominal electrical power dissipation by the DMD (watts)
QILLUMINATION = (CL2W × SL)
CL2W = conversion constant for screen lumens to power on the DMD (watts/lumen)
SL = measured screen lumens (lm)
(2)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies.
Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and
the intensity of the light source.
Equations shown previous are valid for a 1-Chip DMD system with total projection efficiency from DMD to the
screen of 87%.
The constant CL2W is based on the DMD array characteristics. It assumes a spectral efficiency of 300
lumens/watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the
array border.
Sample calculation:
•
•
•
SL = 50 lm
CL2W = 0.00293
QELECTRICAL = 0.105 W
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Feature Description (continued)
•
•
RARRAY-TO-CERAMIC = 2.5°C/W
TCERAMIC = 55°C
QARRAY = 0.105 W + (0.00293 × 50 lm) = 0.252 W
TARRAY = 55°C + (0.252 W × 2.5°C/W) = 55.6°C
(3)
(4)
Array
TP1
4.5
16.1
TP1
Figure 12. Thermocouple Locations
7.3.8 DMD JTAG Interface
The DMD uses 4 standard JTAG signals for sending and receiving boundary scan test data. TCK is the test clock
used to drive an IEEE 1149.1 TAP state machine and logic. TMS directs the next state of the TAP state
machine. TDI is the scan data input and TDO is the scan data output.
The DMD does not support IEEE 1149.1 signals TRST (Test Logic Reset) and RTCK (Returned Test Clock).
Boundary scan cells on the DMD are Observe-Only. To initiate the JTAG boundary scan operation on the DMD,
a minimum of 6 TCK clock cycles are required after TMS is set to logic high.
Refer to Figure 13 for a JTAG system board routing example. The DLPC120-Q1 can be enabled to perform an in
system boundary scan test. See DLPC120-Q1 Programmer's Guide for information about this test.
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Feature Description (continued)
DLPC120-Q1
DLP303X-Q1
DMD_JTCK
TCK
TMS
TDI
DMD_JTMS
DMD_JTDI
DMD_JTDO
TDO
Figure 13. System Interface Connection to DLPC120-Q1
The DMD Device ID can be read via the JTAG interface. The ID and 32-bit shift order is shown in Figure 14.
MSB
31
Version (4 Bits)
0000
28 27
Part Number (16 Bits)
1011-1011-0001-1011
12 11
Manufacturer ID (11 Bits)
0000-0010-111
1 0
LSB
1
TDI
TDO
Figure 14. DMD Device ID and 32-bit Shift Order
Refer to Figure 15 for a JTAG boundary scan block diagram for the DMD. These show the pins and the scan
order that are observed during the JTAG boundary scan.
(0,0)
Illumination
Not to Scale
JTAG Boundary Scan Cells Omitted For Clarity
SAC_BUS
SAC_CLK
DATA(0)
DATA(1)
DATA(2)
DATA(3)
DATA(4)
DATA(5)
DATA(6)
DATA(7)
DATA(8)
DATA(9)
DATA(10)
DATA(11)
DATA(12)
DATA(13)
DATA(14)
DAD_BUS
RESET_STROBE
RESET_OEZ
Illumination
DMD Active Mirror Array
DCLK
LOADB
SCTRL
TRC
Controller
Decoder
Registers
TCK
TMS
TDI
JTAG Boundary Scan Path
TDO
Figure 15. JTAG Boundary Scan Path
Refer to Figure 16 for a functional block diagram of the JTAG control logic.
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Feature Description (continued)
Not to Scale.
BSC = Boundary Scan Cell [Observe Only]
TAP = Test Access Port
Note 1: Signal Routing Omitted for Clarity.
BSC
BSC
BSC
BSC
BSC
BSC
BSC
.3 WVGA DDR
S450 œA1 DMD
BSC
BSC
Mirror Array & Core Logic
Device ID Register
Bypass Register
Note 1
Instruction Decoder
Instruction Register
TAP Controller
TDI
TCK
TMS
TDO
Figure 16. JTAG Functional Block Diagram
26
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7.4 Optical Performance
Optimizing system optical performance and image quality strongly relates to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described below.
7.4.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block flat-state and stray light from passing
through the projection lens. The mirror tilt angle defines DMD capability to separate the "On" optical path from
any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than
the illumination numerical aperture angle, contrast ratio can be reduced and objectionable artifacts in the image
border and/or active area could occur.
7.4.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils can create
objectionable artifacts in the image border and/or active area, which may require additional system apertures to
control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.4.3 Illumination Overfill and Alignment
Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and
other surfaces that surround the active array. These artifacts may be visible in the projected image. The
illumination optical system should be designed to minimize light flux incident outside the active array and on the
window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this amount
of overfill light on the area outside of the active array may still cause artifacts to be visible. Illumination light and
overfill can also induce undesirable thermal conditions on the DMD, especially if illumination light impinges
directly on the DMD window aperture or near the edge of the DMD window. Refer to Recommended Operating
Conditions for a specification on this maximum allowable heat load due to illumination overfill.
NOTE
TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD
FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING
LIMITS DESCRIBED ABOVE.
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7.5 DMD Image Quality Specification
PARAMETER(1)
Dark Blemishes(2)
MIN
NOM
MAX
UNIT
4
Light Blemishes(3)
4
Border Artifacts(4)
Allowed
Minor Blemishes(4)
Allowed
Bright Pixels(3)
Dark Pixels(5)(6)
Pixel Clusters (Dark)(6)
0
4
0
0
0
(6)(5)
Dark Pixels (Adjacent)
Unstable Pixels(4)
Optical Performance
Ambient Lighting Conditions
See Optical Performance
(7)
See
(1) Blemish counts do not include reflections or shadows of the same artifact. Gray 10 linear gamma graphic is the darkest screen that can
be used for IQ evaluation. Any artifact that is not specifically addressed in this table is acceptable unless mutually agreed to between
DLP® Products and the customer. Viewing distance must be > 48 inches. Screen size should be similar to application image size. All
values referenced are in linear gamma. Non-linear gamma curves may be running by default, and it should be ensured with a TI
applications engineer that the equivalent linear gamma value as specified is used to judge artifacts.
(2) Determined on Blue 60 linear gamma screen. Blemish cannot be darker than background.
(3) Determined on Gray 10 linear gamma screen. Blemish cannot be lighter than background.
(4) A Minor light blemish is any blemish that can be seen on a black screen but not a Gray 10 linear gamma screen. A Minor dark blemish
is any blemish that can be seen on a white screen but not a Blue 60 linear gamma screen. Border artifacts, unstable pixels, and Active
area shading are allowed unless visible on a screen brighter than Gray 10 linear gamma.
(5) Dark pixels must be at least fifty (50) mirrors apart.
(6) Determined on a White screen.
(7) The parameters stated in DMD Image Quality Specification assume that the viewed images are set with a nominally adjusted brightness
for ambient lighting condition. For example, if the ambient lighting conditions are very dark, such as night time conditions, then the
image brightness level will be matched to nominal expected value as used in the end application. Similarly, if the ambient lighting
conditions are very bright, such as day time viewing conditions, then the image brightness may be adjusted to the nominal brightness
level as would be expected in the end application.
7.6 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, assuming a fully-saturated white pixel, a landed duty cycle of 90/10 indicates that the referenced
pixel is in the ON state 90% of the time (and in the OFF state 10% of the time), whereas 10/90 would indicate
that the pixel is in the OFF state 90% of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time
and OFF 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
28
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DLP3030-Q1 DMD was designed to be used in automotive applications such as head-up display (HUD) .
The information shown in this section describes the HUD application based on the TI reference design. Contact
TI application engineer for information on this design.
8.2 Typical Application
The DLP3030-Q1 DMD combined with the DLPC120-Q1 are the primary devices that make up the reference
design for a HUD system as shown in the block diagram Figure 17.
Color & Dimming control
Flash
SPI
I2C
TMS320
F28023
Color
Controller
& Driver
Host
SPI
DLPC120-Q1
LEDs
Illumination
Control
& Feedback
Video
Processing &
DMD
real-time
optical
feedback
loop
24-bit RGB
& Syncs
Formatting
photo diode
LED Enable
Timing Control
Data & Control
DLP3030-Q1
Reset
.3" WLP(H) s450
DVSP DMD
Power Good
I2C
TMP411
-Q1
Data &
Address
DMD Power
DDR-2 DRAM
frame buffer
TPS65100
-Q1
Power Enable
Copyright © 2017, Texas Instruments Incorporated
Figure 17. HUD Reference Design Block Diagram
The DLPC120-Q1 accepts input video over the parallel RGB data interface up to 8 bits per color from a Video
Graphics processor. The DLPC120-Q1 then processes the video data (864 × 480 manhattan orientation) by
scaling the image to match the DMD resolution (608 × 684 diamond pixel), applies de-gamma correction, bezel
adjustment, and then formats the data into DMD bit plane information and stores the data into the DDR2 DRAM.
The DMD bit planes are read from DDR2 DRAM, and are then displayed on the DMD using Pulse Width
Modulation (PWM) timing. The DLPC120-Q1 synchronizes the DMD bit plane data with the RGB enable timing
for the LED color controller and Driver circuit. Finally, the DMD accepts the bit plane formatted data from the
DLPC120-Q1 and displays the data according to the timing controlled by the DLPC120-Q1.
Copyright © 2017–2019, Texas Instruments Incorporated
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DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
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Typical Application (continued)
Due to the mechanical nature of the micromirrors, the latency of the DLP3030-Q1 and DLPC120-Q1 chipset is
fixed across all temperature and operating conditions. The observed video latency is one frame, or 16.67 ms at
an input frame rate of 60 Hz. However, please note that the use of the DLPC120-Q1 bezel adjustment feature, if
enabled by the host controller, requires an additional frame of processing.
The DLPC120-Q1 is configured at power up by data stored in the flash file which stores configuration data, DMD
and sequence timing information, LED drive information, and other information related to the system functions.
See the DLPC120-Q1 Programmer's Guide for information about the this flash configuration data.
The HUD reference design from TI includes the TMS320F28023 Microcontroller (Piccolo) which is used to
control the color point by adjusting the RGB flux levels, and drives each RGB LED. This circuit also manages the
dimming function for the HUD system. The dimming level of a HUD system requires very large dynamic range of
over 5000:1. For example, on a bright day, the HUD system may require a brightness level as high as 15,000
cd/m2 and conversely at night time the minimum brightness level desired may only be 3 cd/m2.
8.2.1 HUD Reference Design and LED Controller Reference Design
The complete HUD reference design is available from TI, including electronics (Schematic) and PCB (Gerber)
design, opto-mechanical design (CAD and Zemax models), sample software, and other system reference design
documentation. Additionally, there are application notes describing the Piccolo LED driver and color control
circuit. Contact TI application engineering for access to these application notes and design information.
8.3 Application Mission Profile Consideration
Each application is anticipated to have different mission profiles, or number of operating hours at different
temperatures. To assist in evaluation, the Application Report Reliability Lifetime Estimates for the DLP3030-Q1
DMD in Automotive Applications may be provided if requested.
30
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
9 Power Supply Recommendations
9.1 Power Supply Sequencing Requirements
•
VBIAS, VCC, VOFFSET, VREF, VRESET, VSS are required to operate the DMD.
CAUTION
•
•
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to the prescribed power up and
power down procedures may affect device reliability.
The VCC, VREF, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated
during power up and power down operations. Failure to meet any of the below
requirements will result in a significant reduction in the DMD’s reliability and
lifetime. Refer to Figure 18. VSS must also be connected.
DMD Power Supply Power Up Procedure:
•
•
•
During power up, VCC and VREF must always start and settle before VOFFSET, VBIAS and VRESET voltages are
applied to the DMD.
During power up, VBIAS does not have to start after VOFFSET. However, it is a strict requirement that the delta
between VBIAS and VOFFSET must be within ±8.75 V (refer to Note 1 for Figure 18).
During power up, the DMD’s LVCMOS input pins shall not be driven high until after VCC and VREF have
settled at operating voltage.
•
•
During power up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
Power supply slew rates during power up are flexible, provided that the transient voltage levels follow the
requirements listed above and in Recommended Operating Conditions and in Figure 18.
DMD Power Supply Power Down Procedure
•
•
VCC and VREF must be supplied until after VBIAS, VRESET and VOFFSET are discharged to within 4 V of ground.
During power down it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that
the delta between VBIAS and VOFFSET must be within ± 8.75 V (refer to Note 1 for Figure 18).
•
•
During power down, the DMD’s LVCMOS input pins must be less than VREF + 0.3 V.
During power down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS
.
•
Power supply slew rates during power down are flexible, provided that the transient voltage levels follow the
requirements listed above in Recommended Operating Conditions and in Figure 18.
Copyright © 2017–2019, Texas Instruments Incorporated
31
DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
www.ti.com.cn
Power Supply Sequencing Requirements (continued)
9.1.1 Power Up and Power Down
Power
Off
VBIAS, VOFFSET, and VRESET
Disabled by DLPC120-Q1
VCC / VREF
Mirror Park Sequence
RESET_OEZ
VSS
VCC / VREF
VCC
/
VREF
VSS
VSS
VBIAS
VBIAS
ûV < 8.75 v
Note 1
ûV < 8.75 v
Note 1
VBIAS < 4 V
VSS
VSS
VOFFSET
VOFFSET
VSS
VSS
VOFFSET < 4 V
VSS
VSS
VRESET < 0.5 V
VRESET
VRESET > - 4 V
VRESET
VCC
LVCMOS
Inputs
VSS
VSS
(1) ±8.75-V delta, ∆V, shall be considered the max operating delta between VBIAS and VOFFSET. Customers may find that
the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power up and to remove VBIAS prior to
VOFFSET during power down.
Figure 18. Power Supply Sequencing Requirements (Power Up and Power Down)
32
Copyright © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
10 Layout
10.1 Layout Guidelines
Refer to DLPC120-Q1 Data Sheet for specific PCB layout and routing guidelines. For specific DMD PCB
guidelines, use the following:
•
•
VCC should have at least one 2.2-µF and four 0.1-µF capacitors evenly distributed among the 13 VCC pins.
A 0.1-µF, X7R rated capacitor should be placed near every pin for the VREF, VBIAS, VRSET, and VOFF
.
10.2 Temperature Diode Pins
The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411-Q1
temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411-Q1 are sensitive to
noise. See the TMP411-Q1 Data Sheet for specific routing recommendations.
Avoid routing the temperature diodes signals near other traces to avoid coupling of noise onto these signals.
10.3 Layout Example
Contact TI Application Engineering for access to the complete TI reference design PCB layout.
版权 © 2017–2019, Texas Instruments Incorporated
33
DLP3030-Q1
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
DLP3030 A FYJ Q1
Automotive
Package Type
Temperature Range
Device Descriptor
图 19. 器件型号 说明
11.1.2 器件标记
下面显示了器件标记。该标记将包括可读信息和一个二维矩阵码。
下面显示了可读信息。二维矩阵码是一个字母数字字符串，其中包含 DMD 部件号、序列号的第 1 部分和第 2
部分。
DMD 序列号（第 1 部分）的第一个字符为制造年份。DMD 序列号（第 1 部分）的第二个字符为制造月份。
DMD 序列号（第 2 部分）的最后一个字符为偏置电压二进制字母。
示例：*DLP3030AFYJQ1 GHXXXXX LLLLLLM
Part 2 of Serial Number
(7 characters)
Part 1 of Serial Number
(7 characters)
2-Dimension Matrix Code
(Part Number and Serial Number)
DMD Part Number
图 20. DMD 标记
下面显示了 DLP3030-Q1 器件的三维建模描述。
图 21. DLP3030-Q1的图像
34
版权 © 2017–2019, Texas Instruments Incorporated
DLP3030-Q1
www.ti.com.cn
ZHCSHX4B –NOVEMBER 2017–REVISED JUNE 2019
11.2 文档支持
11.2.1 相关文档
如需相关文档，请参阅：
•
•
•
DLPC120-Q1 产品文件夹，以获取 DLPC120-Q1 数据表
《TMS320F2802x Piccolo™ 微控制器》
《具有 N 因数和串联电阻校正的 TMP411-Q1 ±1°C 远程和本地温度传感器》
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 器件处理
DMD 是光学器件，故应注意避免损坏玻璃窗口。有关正确处理 DMD 的说明，请参阅《DMD 处理应用手册》。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
35
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP3030AFYJQ1
ACTIVE
CPGA
FYJ
149
33
RoHS & Green
Call TI
N / A for Pkg Type
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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