DLP650LE [TI]
DLP® 0.65 WXGA DMD;
| 型号： | DLP650LE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DLP® 0.65 WXGA DMD |
| 文件： | 总39页 (文件大小：1555K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP650LE
ZHCSN34A –NOVEMBER 2017 –REVISED FEBRUARY 2023
DLP650LE 0.65 WXGA 数字微镜器件
1 特性
3 说明
• 0.65 英寸对角线微镜阵列
TI DLP® DLP650LE 数字微镜器件 (DMD) 是一款数控
微机电系统 (MEMS) 空间照明调制器 (SLM)，可用于
实现明亮、经济实惠的 WXGA 显示解决方案。
DLP650LE DMD 通过与 DLPC4430 显示控制器、
DLPA100 电源和电机驱动器以及 DLPA200 DMD 微镜
驱动器配合使用，可提供实现高性能系统的能力，是需
要 16:10 纵横比、高亮度和系统简单性的显示应用的
理想之选。
– 具有超过100 万个微镜的WXGA (1280 × 800)
阵列
– 10.8µm 微镜间距
– ±12° 微镜倾斜角（相对于平面）
– 设计用于角落照明
• 2×LVDS 输入数据总线
• DLP650LE 芯片组包括：
器件信息
封装(1)
– DLP470TE DMD
– DLPC4430 控制器
封装尺寸（标称值）
器件型号
– DLPA100 控制器电源管理和电机驱动器IC
– DLPA200 DMD 电源管理IC
DLP650LE
FYL (149)
32.20mm × 22.30mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 智能照明
• 企业投影仪
• 教育投影仪
DLP650LE 简化应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS095
DLP650LE
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ZHCSN34A –NOVEMBER 2017 –REVISED FEBRUARY 2023
Table of Contents
7.3 Feature Description...................................................20
7.4 Device Functional Modes..........................................20
7.5 Optical Interface and System Image Quality
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings........................................ 8
6.2 Storage Conditions..................................................... 9
6.3 ESD Ratings............................................................... 9
6.4 Recommended Operating Conditions.........................9
6.5 Thermal Information..................................................12
6.6 Electrical Characteristics...........................................12
6.7 Capacitance at Recommended Operating
Conditions................................................................... 12
6.8 Timing Requirements................................................13
6.9 Window Characteristics............................................ 16
6.10 System Mounting Interface Loads.......................... 16
6.11 Micromirror Array Physical Characteristics............. 17
6.12 Micromirror Array Optical Characteristics............... 18
6.13 Chipset Component Usage Specification............... 18
7 Detailed Description......................................................19
7.1 Overview...................................................................19
7.2 Functional Block Diagram.........................................19
Considerations............................................................ 20
7.6 Micromirror Array Temperature Calculation.............. 21
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 23
8 Application and Implementation..................................26
8.1 Application Information............................................. 26
8.2 Typical Application.................................................... 26
9 Power Supply Recommendations................................29
9.1 DMD Power Supply Power-Up Procedure................29
9.2 DMD Power Supply Power-Down Procedure........... 29
10 Device and Documentation Support..........................31
10.1 第三方产品免责声明................................................31
10.2 Device Support....................................................... 31
10.3 Documentation Support.......................................... 31
10.4 接收文档更新通知................................................... 32
10.5 支持资源..................................................................32
10.6 Trademarks.............................................................32
10.7 静电放电警告.......................................................... 32
10.8 术语表..................................................................... 32
11 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
Changes from Revision * (November 2017) to Revision A (February 2023)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
• 更新了整个文档中的表格、图和交叉参考的编号格式将控制器更新为DLPC4430 更新了芯片组元件的链接.....1
• 将控制器更新为DLPC4430................................................................................................................................1
• Updated controller to DLPC4430......................................................................................................................19
• Updated controller to DLPC4430......................................................................................................................20
• Added a table for legacy part numbers and listed the mechanical ICD............................................................26
• Updated controller to DLPC4430......................................................................................................................26
• Updated controller to DLPC4430......................................................................................................................27
• Updated controller to DLPC4430......................................................................................................................27
• Updated controller to DLPC4430, updated the links.........................................................................................31
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5 Pin Configuration and Functions
1
3
5
7
9
11 13 15 17 19
12 14 16 18 20
2
4
6
8
10
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
图5-1. FYL Package 149-Pin CLGA Bottom View
表5-1. Pin Functions
PIN
NET LENGTH
SIGNAL
TYPE(1)
DESCRIPTION
(mils)
NAME
DATA INPUTS
NO.
D_AN(1)
D_AN(3)
D_AN(5)
D_AN(7)
D_AN(9)
D_AN(11)
D_AN(13)
D_AN(15)
D_AP(1)
D_AP(3)
D_AP(5)
D_AP(7)
D_AP(9)
D_AP(11)
D_AP(13)
D_AP(15)
G20
H19
F18
E18
C20
B18
A20
B19
H20
G19
G18
D18
D20
A18
B20
A19
711.64
711.60
711.60
711.60
711.60
711.60
711.60
711.58
711.66
711.61
711.59
711.60
711.59
711.58
711.59
711.59
LVDS
I
LVDS pair for Data Bus A
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表5-1. Pin Functions (continued)
PIN
NET LENGTH
(mils)
SIGNAL
TYPE(1)
DESCRIPTION
NAME
NO.
K20
J19
D_BN(1)
D_BN(3)
D_BN(5)
D_BN(7)
D_BN(9)
D_BN(11)
D_BN(13)
D_BN(15)
D_BP(1)
D_BP(3)
D_BP(5)
D_BP(7)
D_BP(9)
D_BP(11)
D_BP(13)
D_BP(15)
DCLK_AN
DCLK_AP
DCLK_BN
DCLK_BP
711.61
711.59
711.59
711.6
L18
M18
P20
R18
T20
R19
J20
711.6
711.59
711.59
711.59
711.61
711.6
LVDS
I
LVDS pair for Data Bus B
K19
K18
N18
N20
T18
R20
T19
D19
E19
N19
M19
711.58
711.58
711.6
711.61
711.59
711.6
711.59
711.59
711.6
I
I
LVDS pair for Data Clock A
LVDS pair for Data Clock B
711.61
DATA CONTROL INPUTS
SCTRL_AN
F20
E20
L20
M20
711.62
711.6
I
I
LVDS pair for Serial Control (Sync) A
LVDS pair for Serial Control (Sync) B
SCTRL_AP
SCTRL_BN
711.59
711.59
SCTRL_BP
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表5-1. Pin Functions (continued)
PIN
NET LENGTH
(mils)
SIGNAL
TYPE(1)
DESCRIPTION
NAME
NO.
MICROMIRROR BIAS RESET INPUTS
MBRST(0)
C3
D2
D3
E2
G3
E1
G2
G1
N3
M2
M3
L2
507.20
576.83
545.78
636.33
618.42
738.25
718.82
777.04
543.29
612.93
580.97
672.43
653.61
764.00
764.37
813.14
MBRST(1)
MBRST(2)
MBRST(3)
MBRST(4)
MBRST(5)
MBRST(6)
Nonlogic compatible Micromirror Bias Reset
signals. Connected directly to the array of
pixel micromirrors. Used to hold or release
the micromirrors. Bond Pads connect to an
internal pulldown resistor.
MBRST(7)
I
MBRST(8)
MBRST(9)
MBRST(10)
MBRST(11)
MBRST(12)
MBRST(13)
MBRST(14)
MBRST(15)
SCP CONTROL
J3
L1
J2
J1
Serial Communications Port Clock. Bond Pad
connects to an internal pulldown circuit.
SCPCLK
SCPDI
A8
A5
I
I
Serial Communications Port Data. Bond Pad
connects to an internal pulldown circuit.
Active low serial communications port
enable. Bond pad connects to an internal
pulldown circuit.
SCPENZ
B7
A9
I
SCPDO
O
Serial communications port output
OTHER SIGNALS
EVCC
A3
A4
P
I
Do not connect on the DLP system board.
Data Bandwidth Mode Select. Bond Pad
connects to an internal pulldown circuit.
Refer to Table 4 for DLP system board
connection information.
MODE_A
415.1
Active Low Device Reset. Bond Pad
connects to an internal pulldown circuit.
PWRDNZ
B9
110.38
I
POWER
B11, B12,
B13, B16,
R12, R13,
R16, R17
Power supply for low voltage CMOS logic.
Power supply for normal high voltage at
micromirror address electrodes
(2)
(2)
VCC
P
A12, A14,
A16, T12,
T14, T16
Power supply for low voltage CMOS LVDS
interface
VCCI
P
P
Power supply for high voltage CMOS logic.
Power supply for stepped high voltage at
micromirror address electrodes
C1, D1,
M1, N1
(2)
VOFFSET
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表5-1. Pin Functions (continued)
PIN
NET LENGTH
(mils)
SIGNAL
TYPE(1)
DESCRIPTION
NAME
NO.
A6, A11,
A13, A15,
A17, B4,
B5, B8,
B14, B15,
B17, C2,
C18, C19,
F1, F2,
F19, H1,
H2, H3,
VSS (Ground)(3)
P
Common Return for all power
H18, J18,
K1, K2,
L19, N2,
P18, P19,
R4, R9,
R14, R15,
T7, T13,
T15, T17
RESERVED SIGNALS
Connect to GND on the DLP system board.
Bond Pad connects to an internal pulldown
circuit.
RESERVED_FC
R7
R8
T8
B6
40.64
94.37
50.74
I
I
I
I
Connect to GND on the DLP system board.
Bond Pad connects to an internal pulldown
circuit.
RESERVED_FD
RESERVED_PFE
RESERVED_STM
Connect to ground on the DLP system board.
Bond Pad connects to an internal pulldown
circuit.
Connect to GND on the DLP system board.
Bond Pad connects to an internal pulldown
circuit.
RESERVED_TP0
RESERVED_TP1
RESERVED_TP2
RESERVED_BA
RESERVED_BB
RESERVED_RA1
RESERVED_RB1
RESERVED_TS
RESERVED_A(0)
RESERVED_A(1)
RESERVED_A(2)
RESERVED_A(3)
RESERVED_M(0)
RESERVED_M(1)
RESERVED_S(0)
RESERVED_S(1)
RESERVED_IRQZ
RESERVED_OEZ
RESERVED_RSTZ
RESERVED_STR
RESERVED_STR
R10
T11
R11
T10
A10
T9
93.3
I
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
263.74
281.47
148.85
105.28
I
I
O
O
O
O
O
A7
B10
T2
145.42
T3
NC
Do not connect on the DLP system board.
R3
T4
R2
P1
NC
NC
NC
NC
NC
NC
NC
NC
NC
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
Do not connect on the DLP system board.
T1
R1
T6
R5
R6
T5
T5
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表5-1. Pin Functions (continued)
PIN
NET LENGTH
(mils)
SIGNAL
TYPE(1)
DESCRIPTION
NAME
NO.
E3, F3,
K3, L3
RESERVED_VB
RESERVED_VR
NC
NC
Do not connect on the DLP system board.
Do not connect on the DLP system board.
B2, B3,
P2, P3
(1) I = Input, O = Output, G = Ground, A = Analog, P = Power, NC = No Connect.
(2) Power supply pins required for all DMD operating modes are VSS, VBIAS, VCC, VCCI, VOFFSET, and VRESET
(3) VSS must be connected for proper DMD operation.
.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).(1)
MIN
MAX
UNIT
SUPPLY VOLTAGES
VCC
Supply voltage for LVCMOS core logic(2)
Supply voltage for LVDS Interface(2)
Micromirror Electrode and HVCMOS voltage(2) (3)
Input voltage for MBRST(15:0)(2)
4
4
V
V
V
V
V
–0.5
–0.5
–0.5
–28
VCCI
VOFFSET
VMBRST
|VCCI –VCC
9
28
0.3
Supply voltage delta (absolute value)(4)
|
INPUT VOLTAGES
Input voltage for all other input pins(2)
VCC + 0.3
700
V
–0.5
|VID|
Input differential voltage (absolute value)(5)
mV
CLOCKS
ƒCLOCK
Clock frequency for LVDS interface, DCLK_A
Clock frequency for LVDS interface, DCLK_B
400
400
MHz
MHz
ƒCLOCK
ENVIRONMENTAL
Temperature, operating(6)
0
90
90
°C
°C
TARRAY and TWINDOW
Temperature, non–operating(6)
–40
Absolute Temperature delta between any point on the window edge and the
ceramic test point TP1(7)
|TDELTA
TDP
|
30
81
°C
°C
Dew point temperature, operating and non–operating (noncondensing)
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for all DMD
operating modes.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable voltage difference between VCC and VCCI may result in excessive current draw.
(5) The maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(6) The highest temperature of the active array (as calculated using 节7.6) or of any point along the window edge as defined in 图7-1.
The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-1 are intended to measure the highest window edge temperature.
If a particular application causes another point on the window edge to be at a higher temperature, then that point should be used.
(7) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst-case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, then that point should be used.
(8) VOFFSET supply transients must fall within specified voltages.
(9) Excludes micromirror Bias Reset inputs MBRST(15:0).
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6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
80
UNIT
°C
TDMD
DMD storage temperature
–40
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature (non-condensing)(1)
Elevated dew point temperature range (non-condensing)(2)
Cumulative time in elevated dew point temperature range
28
°C
28
36
°C
24 Months
(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
6.3 ESD Ratings
VALUE
±2000
< 250
UNIT
All pins except MBRST(15:0)
Pins MBRST(15:0)
Electrostatic
discharge
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in
this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is
implied when operating the device above or below these limits.
MIN NOM
MAX
UNIT
VOLTAGE SUPPLY
VCC
Supply voltage for LVCMOS core logic(1)
Supply voltage for LVDS interface(1)
3.0
3.0
3.3
3.3
8.5
3.6
3.6
V
V
V
V
V
VCCI
VOFFSET
VMBRST
|VCC –VCCI
Micromirror electrode and HVCMOS voltage(1) (2)
Micromirror bias / reset voltage(1)
8.25
–27
8.75
26.5
0.3
Supply voltage delta (absolute value)(3)
0
|
LVCMOS INTERFACE
VIH
Input high voltage
1.7
2.5
VCC + 0.3
0.7
V
V
VIL
Input low voltage
–0.3
IOH
High level output current
Low level output current
PWRDNZ pulse width(4)
mA
mA
ns
–20
IOL
15
tPWRDNZ
10
SCP INTERFACE
ƒSCPCLK
SCP clock frequency(5)
50
0
500
900
kHz
ns
Propagation delay, clock to Q, from rising-edge of SCPCLK to valid
SCPDO(6)
tSCP_PD
tSCP_DS
tSCP_DH
SCPDI clock setup time (before SCPCLK falling-edge)(6)
SCPDI hold time (after SCPCLK falling-edge)(6)
800
900
ns
ns
Time between falling-edge of SCPENZ and the rising-edge of
SCPCLK.(5)
tSCP_NEG_ENZ
1
1
us
us
s
Time between falling-edge of SCPCLK and the rising-edge of
SCPENZ
SCP_POS_ENZ
Time required for SCP output buffer to recover after SCPENZ
(from tristate)
tSCP_OUT_EN
192/ƒDCLK
tSCP_PW_ENZ
tr
SCPENZ inactive pulse width (high level)
1
1/ƒscpclk
Rise Time (20% to 80%). See (6)
.
200
ns
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6.4 Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in
this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is
implied when operating the device above or below these limits.
MIN NOM
MAX
UNIT
tf
Fall time (80% to 20%). See (6)
.
200
ns
LVDS INTERFACE
Clock frequency for LVDS interface (all channels), DCLK(7)
Input differential voltage (absolute value)(8)
Common mode voltage(8)
320
330
600
MHz
mV
mV
mV
ns
ƒCLOCK
|VID|
100
0
400
VCM
1200
VLVDS
LVDS voltage(8)
2000
10
tLVDS_RSTZ
Time required for LVDS receivers to recover from PWRDNZ
Internal differential termination resistance
Line differential impedance (PWB/trace)
ZIN
95
85
105
95
Ω
ZLINE
90
Ω
ENVIRONMENTAL
Array temperature, long-term operational(9) (10) (11)
Array temperature, short-term operational(10) (13)
10
0
40 to 70(12)
°C
°C
°C
TARRAY
10
90
85
Window temperature (all part numbers except *1280-6434B)(14) (15)
Window temperature (part number 1280-6434B)(14)
10
10
TWINDOW
T|DELTA |
Absolute temperature delta between any point on the window edge
and the ceramic test point TP1(16)
°C
26
TDP -AVG
TDP-ELR
CTELR
ILLUV
Average dew point average temperature (non-condensing)(17)
Elevated dew point temperature range (non-condensing)(18)
Cumulative time in elevated dew point temperature range
Illumination Wavelengths < 395 nm(9)
28
36
°C
°C
28
24 Months
2.00 mW/cm2
Thermally limited
mW/cm2
0.68
ILLVIS
ILLIR
Illumination Wavelengths between 395 nm and 800 nm
Illumination Wavelengths > 800 nm
10 mW/cm2
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for proper
DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI –VCC| must be less than the specified limit. See 节9, 图9-1, and 表9-2.
(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states
the SCPDO output pin.
(5) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(6) See 图6-2.
(7) See LVDS Timing Requirements in 节6.8 and 图6-6.
(8) See 图6-5 LVDS Waveform Requirements.
(9) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination will reduce device lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in 图7-1 and the package thermal resistance using 节7.6.
(11) Long-term is defined as the usable life of the device.
(12) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. See 节7.7 for a definition of micromirror landed duty cycle.
(13) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is
defined as cumulative time over the usable life of the device and is less than 500 hours.
(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-1 are intended to measure the highest window edge temperature.
For most applications, the locations shown are representative of the highest window edge temperature. If a particular application
causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(15) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta temperature. If a
particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
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(17) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
(18) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
80
70
60
50
40
30
0/100
100/0
5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
65/35
95/5
90/10
85/15
80/20
75/25
70/30
60/40
55/45
50/50
Micromirror Landed Duty Cycle
图6-1. Maximum Recommended Array Temperature—Derating Curve
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6.5 Thermal Information
DLP650LE
THERMAL METRIC
FYL Package
149 PINS
0.50
UNIT
Thermal resistance, active area to test point 1 (TP1)(1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the 节6.4.
The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other contributions include
light energy absorbed by the window aperture and electrical power dissipation of the array.
Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal
load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC = 3 V, IOH = –20 mA
VCC = 3.6 V, IOL = 15 mA
VCC = 3.6 V
MIN
TYP
MAX
UNIT
V
VOH
VOL
IOZ
High-level output voltage
Low-level output voltage
High-impedance output current
Low-level input current
High-level input current (1)
Supply current VCC (2)
Supply current VCCI (2)
Supply current VOFFSET (3)
Supply input power total
2.4
0.4
10
V
µA
µA
µA
mA
mA
mA
mW
IIL
VCC = 3.6 V, VI = 0
VCC = 3.6 V, VI = VCC
VCC = 3.6 V
–60
200
479
309
25
IIH
ICC
ICCI
IOFFSET
VCCI = 3.6 V
VOFFSET = 8.75 V
f = 1 MHz
3060
(1) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins.
(2) To prevent excess current, the supply voltage delta |VCCI –VCC| must be less than the specified limit in 节6.4.
(3) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than the specified limit in 节6.4.
6.7 Capacitance at Recommended Operating Conditions
over operating free-air temperature range, ƒ= 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
pF
CI
Input capacitance
CO
CIM
Output capacitance
10
pF
MBRST(15:0) input capacitance
1280 × 800 array all inputs interconnected
230
290
pF
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6.8 Timing Requirements
Over 节6.4 (unless otherwise noted).
PARAMETER DESCRIPTION
SIGNAL
MIN
TYP
MAX
UNIT
LVDS (1)
tC
Clock cycle duration for DCLK_A
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
3.03
3.03
1.36
1.36
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
–1.51
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC
Clock cycle duration for DCLK_B
tW
Pulse duration for DCLK_A
1.52
1.52
tW
Pulse duration for DCLK_B
tSU
tSU
tSU
tSU
tH
Setup time for D_A(15:0) before DCLK_A
Setup time for D_A(15:0) before DCLK_B
Setup time for SCTRL_A before DCLK_A
Setup time for SCTRL_B before DCLK_B
Hold time for D_A(15:0) after DCLK_A
Hold time for D_B(15:0) after DCLK_B
Setup time for SCTRL_A after DCLK_A
Setup time for SCTRL_B after DCLK_B
Channel B relative to Channel A(2) (3)
tH
tH
tH
tSKEW
1.51
(1) See 图6-6 for timing requirements for LVDS.
(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and
D_AP(15:0).
(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and
D_BP(15:0).
SCPCLK falling–edge capture for SCPDI.
tSCP_NEG_ENZ
tSCP_POS_ENZ
SCPCLK rising–edge launch for SCPDO.
50%
50%
SCPENZ
tSCP_DS
tSCP_DH
50%
50%
DI
SCPDI
tC
fSCPCLK = 1 / tC
50%
50%
50%
50%
SCPCLK
tSCP_PD
50%
DO
SCPDO
图6-2. SCP Timing Requirements
See 节6.4 for fSCPCLK, tSCP_DS, tSCP_DH, and tSCP_PD specifications.
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See 节6.4 for tr and tf specifications and conditions.
LVDS Interface
SCP Interface
1.0 * VCC
1.0 * V
ID
V
CM
0.0 * VCC
0.0 * V
ID
tr
tf
tr
tf
Not to scale.
Refer to the 节6.8.
Refer to 节5 for list of LVDS pins and SCP pins.
图6-3. Rise Time and Fall Time
Device pin
output under test
Tester channel
CLOAD
图6-4. Test Load Circuit for Output Propagation Measurement
For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
System designers should use IBIS or other simulation tools to correlate the timing reference load to a system
environment. See 图6-4.
Not to Scale
V
|
|
VID max
LVDS max = VCM max
1/2 *
+
tf
VCM
VID
tr
V
|
|
VID max
LVDS min = VCM min
1/2 *
œ
图6-5. LVDS Waveform Requirements
See 节6.4 for VCM, VID, and VLVDS specifications and conditions.
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t
c
Not to Scale
t
t
w
w
DCLK_P
DCLK_N
50%
t
h
t
h
t
t
t
su
su
D_P(0:?)
D_N(0:?)
50%
t
h
t
h
t
su
su
SCTRL_P
SCTRL_N
50%
t
t
skew
c
t
t
w
w
DCLK_P
DCLK_N
50%
t
h
t
h
t
t
t
t
su
su
D_P(0:?)
D_N(0:?)
50%
t
h
t
h
su
su
SCTRL_P
SCTRL_N
50%
图6-6. Timing Requirements
See 节6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(0:x) and D_N(0:x).
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6.9 Window Characteristics
表6-1. DMD Window Characteristics
PARAMETER
MIN
NOM
Corning Eagle
XG
Window material
Window Refractive Index at 546.1 nm
1.5119
Window Transmittance, minimum within the wavelength range 420–680 nm. Applies to all angles 0°–30°
97%
97%
AOI. (1) (2)
Window Transmittance, average over the wavelength range 420–680 nm. Applies to all angles 30°–45°
AOI. (1) (2)
(1) Single-pass through both surfaces and glass
(2) AOI—Angle of incidence is the angle between an incident ray and the normal to a reflecting or refracting surface.
6.10 System Mounting Interface Loads
表6-2. System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Condition 1:
Thermal Interface area(1)
Electrical Interface area(1)
Condition 2:
11.3
11.3
kg
kg
Thermal Interface area(1)
Electrical Interface area(1)
0
kg
kg
22.6
(1) Uniformly distributed within area shown in 图6-7
Electrical Interface Area
Thermal Interface Area
图6-7. System Mounting Interface Loads
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6.11 Micromirror Array Physical Characteristics
表6-3. Micromirror Array Physical Characteristics
PARAMETER DESCRIPTION
VALUE
1280
800
UNIT
Number of active columns(1)
Number of active rows(1)
M
N
P
micromirrors
Micromirror (pixel) pitch (1)
10.8
µm
Micromirror active array width(1)
Micromirror active array height(1)
Micromirror active border size(2)
Micromirror pitch × number of active columns
Micromirror pitch × number of active rows
Pond of Micromirror (POM)
13.824
8.640
10
mm
mm
micromirrors / side
(1) See 图6-8.
(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the Pond Of
Mirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or “on”state but still
require an electrical bias to tilt toward “off.”
0
1
2
3
Active Micromirror Array
N
M x N Micromirrors
N œ 4
N œ 3
N œ 2
N œ 1
M
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity.
Not to scale.
P
P
P
图6-8. Micromirror Array Physical Characteristics
Refer to 节6.11 table for M, N, and P specifications.
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6.12 Micromirror Array Optical Characteristics
表6-4. Micromirror Array Optical Characteristics
PARAMETER
MIN
NOM
MAX
13
UNIT
Mirror Tilt angle, variation device to device(1) (2) (3) (4)
11
12
degrees
Adjacent micromirrors
0
Number of out-of-specification micromirrors(5)
micromirrors
Non-adjacent
micromirrors
10
(1) Measured relative to the plane formed by the overall micromirror array
(2) Variation can occur between any two individual micromirrors located on the same device or located on different devices.
(3) Additional variation exists between the micromirror array and the package datums. See the package drawing.
(4) See 图6-9.
(5) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states.
备注
This number is specified under conditions described above and deviations from the specified
conditions could result in decreased efficiency.
Pond Of Micromirrors (POM) omitted for clarity.
Illumination
Details omitted for clarity. Not to scale.
0
1
2
3
On-State
Tilt Direction
45|
Off-State
Tilt Direction
N œ 4
N œ 3
N œ 2
N œ 1
图6-9. Micromirror Landed Orientation and Tilt
Refer to 节6.11 table for M, N, and P specifications.
6.13 Chipset Component Usage Specification
Reliable function and operation of the DLP650LE DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
control technology. TI DMD control technology consists of the TI technology and devices used for operating or
controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
The DMD is a 0.65 inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The
electrical interface is Low Voltage Differential Signaling (LVDS). The DMD consists of a two-dimensional array of
1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell rows.
Refer to 节 7.2. The positive or negative deflection angle of the micromirrors can be individually controlled by
changing the address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
The DLP650LE DMD is part of the chipset comprising of the DLP650LE DMD, the DLPC4430 display controller,
the DLPA100 power and motor driver and the DLPA200 micromirror driver. To ensure reliable operation, the
DLP650LE DMD must always be used with the DLPC4430 display controller, the DLPA100 power and motor
driver and the DLPA200 micromirror driver.
7.2 Functional Block Diagram
Channel A Interface
Column Read and Write
Control
Control
(0,0)
Voltages
Word Lines
Voltage
Generators
Micromirror Array
Row
(M-1, N-1)
Column Read and Write
Channel B Interface
Control
Control
Copyright © 2017, Texas Instruments Incorporated
For pin details on Channels A, B refer to 节5 and LVDS Interface section of 节6.8.
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7.3 Feature Description
7.3.1 Power Interface
The DMD requires 3 DC voltages: DMD_P3P3V, VOFFSET, and MBRST. DMD_P3P3V is created by the DLPA100
power and motor driver and the DLPA200 DMD micromirror driver. Both the DLPA100 and DLPA200 create the
main DMD voltages, as well as powering various peripherals (TMP411, I2C, and TI level translators).
DMD_P3P3V provides the VCC voltage required by the DMD. VOFFSET (8.5V) and MBRST are made by the
DLPA200 and are supplied to the DMD to control the micromirrors.
7.3.2 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. 图 6-4 shows an equivalent test load circuit for the output
under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS or
other simulation tools to correlate the timing reference load to a system environment. The load capacitance
value stated is only for characterization and measurement of AC timing signals. This load capacitance value
does not indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC4430 display controller. See the DLPC4430 display controller
data sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
System optical performance and image quality strongly relate to optical system design parameter trade offs.
Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any
other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle (and vice versa), contrast degradation, and objectionable artifacts
in the display’s border and/or active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display’s border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
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10% of the average flux level in the active area. Depending on the particular system’s optical architecture,
overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
Array
TP2
2X 12.0
TP5
TP4
2X 16.7
TP3
Window Edge
(4 surfaces)
TP3 (TP2)
TP1
TP5
TP4
4.5
16.1
TP1
图7-1. DMD Thermal Test Points
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Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test TP1 in 图7-1) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (CL2W × SL)
)
(1)
where
• TARRAY = computed array temperature (°C)
• TCERAMIC = measured ceramic temperature (°C) (TP1 location)
• RARRAY-TO-CERAMIC = thermal resistance of package (specified in 节6.5) from array to ceramic TP1 (°C/Watt)
• QARRAY = Total DMD power (electrical + absorbed) on the array (Watts)
• QELECTRICAL = Nominal Electrical Power
• CL2W = Conversion constant for screen lumens to power on DMD (Watts/Lumen)
• SL = measured screen Lumens
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 1.5 Watts.
Absorbed optical power from the illumination source is variable and depends on the operating state of the
micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with
total projection efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lm/Watt for the projected light and illumination distribution of 83.7% on the DMD active array,
and 16.3% on the DMD array border and window aperture.
Sample Calculations:
TCERAMIC = 55.0°C
SL = 3000 lm
QELECTRICAL = 1.5 W
CL2W = 0.00274 W/lm
QARRAY = 1.5 W + (0.00274 × 3000 lm) = 9.72 W
TARRAY = 55.0°C + (9.72 W × 0.50°C/W) = 59.9°C
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7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On state versus the amount of time the same
micromirror is landed in the Off state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On state 100% of the
time (and in the Off state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric
landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life. This is quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the Maximum Operating DMD Temperature at a given long-term average Landed
Duty Cycle.
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7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel will experience a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in 表7-1.
表7-1. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a
given primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
• Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_% × Blue_Scale_Value)
Where
• Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,
Green, and Blue are displayed (respectively) to achieve the desired white point. (1)
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,
and blue color intensities would be as shown in 表7-2 and 表7-3.
表7-2. Example Landed Duty Cycle for Full-Color, Color Percentage
RED CYCLE
GREEN CYCLE
BLUE CYCLE
50%
20%
30%
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表7-3. Example Landed Duty Cycle for Full-Color
RED SCALE
GREEN SCALE
BLUE SCALE
LANDED DUTY CYCLE
0%
0%
0%
0/100
50/50
20/80
30/70
6/94
100%
0%
0%
0%
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
7/93
0%
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
60%
60%
100%
12%
100%
0%
100%
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
Texas Instruments DLP® technology is a micro-electro-mechanical systems (MEMS) technology that modulates
light using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light
from an illumination source to one of two directions, either towards the projection optics, or the collection optics.
The large micromirror array size and ceramic package provides great thermal performance for bright display
applications. Typical applications using the DLP650LE include smart lighting, education projectors, and business
projectors. The following orderables have been replaced by the DLP650LE:
Device Information
PART NUMBER
DLP650LET
1280-6434B
1280-6438B
1280-6439B
1280-643AB
PACKAGE
FYL (149)
FYL (149)
FYL (149)
FYL (149)
FYL (149)
BODY SIZE (NOM)
32.20 mm × 22.30 mm
32.20 mm × 22.30 mm
32.20 mm × 22.30 mm
32.20 mm × 22.30 mm
32.20 mm × 22.30 mm
MECHANICAL ICD
2512372
2512372
2512372
2512372
2512372
8.2 Typical Application
The DLP650LE DMD combined with a DLPC4430 digital controller, DLPA100 power management device, and
DLPA200 micromirror driver provides WXGA resolution for bright, colorful display applications. A typical display
system using the DLP650LE and additional system components is shown in 图8-1.
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12V
12V
1.21V
1.8V
3.3V
5V
1.21V
1.8V
3.3V
5V
DLPA100
Controller
PMIC
DLPA100
Controller
PMIC
Flash
(23) (16)
CW Driver
CW Driver
ADDR
DATA
Wheel Motor #2
CTRL
Wheel Motor #1
CTRL
CW_INDEX1
CW_INDEX1
FE CTRL
DATA
3D L/R
CTRL
2xLVDS
SCP CTRL
DLPC4430
Controller
Front End Device
DLP DMD
1.8 V
USB CTRL
GPIO
1.15V
1.8V
3.3V
VBIAS
VOFFSET
VRESET
CTRL
3.3V
DMD PMIC
(Power Management IC)
(3)
I2C
EEPROM
TI DLP chipset
Third party component
图8-1. Typical DLPC4430 Application (LED - top, LPCW - bottom)
8.2.1 Design Requirements
The DLP 0.65 WXGA chipset can be used to create a powerful projection system. This chipset includes the
DLP650LE, DLPC4430, DLPA100, and the DLPA200. The DLP650LE is used as the core imaging device in the
display system and contains a 0.65-inch array of micromirrors. The DLPC4430 controller is the digital interface
between the DMD and the rest of the system. The controller drives the DMD by taking the converted source data
from the front end receiver and transmitting it to the DMD over a high speed interface. The DLPA100 power
management device provides voltage regulators for the controller and colorwheel motor control. The DLPA200
provides the power and sequencing to drive the DLP650LE. To ensure reliable operation, the DLP650LE DMD
must always be used with the DLPC4430 display controller, a DLPA100 PMIC driver, and a DLPA200 DMD
micromirror driver.
Other core components of the display system include an illumination source, an optical engine for the
illumination and projection optics, other electrical and mechanical components, and software. The illumination
source options include lamp, LED, laser, or laser phosphor. The type of illumination used and desired brightness
will have a major effect on the overall system design and size.
8.2.2 Detailed Design Procedure
For help connecting the DLPC4430 display controller and the DLP650LE DMD, see the reference design
schematic. For a complete DLP system, an optical module or light engine is required that contains the
DLP650LE DMD, associated illumination sources, optical elements, and necessary mechanical components.
The optical module is typically supplied by an optical OMM (optical module manufacturer) who specializes in
designing optics for DLP projectors.
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8.2.3 Application Curve
图8-2. Luminance vs Current
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VSS, VBIAS, VCC, VCCI, VOFFSET, and VRESET
.
DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.
备注
CAUTION: For reliable operation of the DMD, the following power supply sequencing requirements
must be followed. Failure to adhere to any of the prescribed power-up and power-down requirements
may affect device reliability. See 图9-1 - DMD Power Supply Sequencing Requirements.
VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies must be coordinated during power-up and
power-down operations. Failure to meet any of the below requirements will result in a significant
reduction in the DMD’s reliability and lifetime. Common ground VSS must also be connected.
9.1 DMD Power Supply Power-Up Procedure
• During power-up, VCC and VCCI must always start and settle before VOFFSET plus the first time delay period
(tD1) specified in 表9-2. VBIAS, and VRESET voltages are applied to the DMD.
• During power-up, it is a strict requirement that the voltage delta between VBIAS and VOFFSET must be within
the specified limit shown in 节6.4.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in 节6.1, in 节6.4, and in 图9-1.
• During power-up, LVCMOS input pins must not be driven high until after VCC and VCCI have settled at
operating voltages listed in 节6.4.
9.2 DMD Power Supply Power-Down Procedure
• During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to
within the specified limit of ground. See 表9-2.
• During power-down, it is a strict requirement that the voltage delta between VBIAS and VOFFSET must be within
the specified limit shown in 节6.4.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in 节6.1, in 节6.4, and in 图9-1.
• During power-down, LVCMOS input pins must be less than specified in 节6.4.
表9-1. DMD Power Supply Transition Points
TIME
t1
DESCRIPTION
DLP controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high
PG_OFFSET turns OFF after EN_OFFSET turns OFF per the tD2 specification in 表9-2.
DLP controller software initiates the global VBIAS command.
t1
t2
After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that
t3
t4
activates PWRDNZ and disables VBIAS, VRESET and VOFFSET
.
Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller
hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal should go high prior to PG_OFFSET
turning off to indicate the DMD micromirror has completed the emergency park procedures.
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VCC and
(2)
VCCI
VSS
VSS
ûV < Specification(3)
VOFFSET
(5)
tD1
VSS
VSS
VBIAS
ûV < Specification(4)
VRESET
EN_OFFSET
VSS
VSS
VSS
VSS
(5)
tD2
PG_OFFSET
RESET_OEZ
PWRDNZ
and RESETZ
t1
t2
t3 t4
1. Not to scale. Some details omitted for clarity. See 节6.4 for all specified limits and 节5 table for pin
descriptions.
2. To prevent excess current, the supply voltage difference |VCCI –VCC| must be less than the specified limit.
3. To prevent excess current, the supply voltage difference |VBIAS –VOFFSET| must be less than the specified
limit.
4. To prevent excess current, the supply voltage difference |VBIAS –VRESET| must be less than the specified
limit.
5. See 表9-2 for delay time descriptions.
6. See 表9-1 for transition time point descriptions.
图9-1. Power Supply Timing(1)
表9-2. Delay Times Requirements
DELAY TIME
tD1
tD2
DESCRIPTION
MIN
NOM
MAX
UNIT
Delay time period from VOFFSET settled at recommended operating
voltage to VBIAS and VRESET power up.
1
2
ms
Delay time period between PG_OFFSET hold time and when
EN_OFFSET goes low
100
ns
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10 Device and Documentation Support
10.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.2 Device Support
10.2.1 Device Nomenclature
DLP650LE FYL
Package Type
Device Descriptor
图10-1. Part Number Description
10.2.2 Device Markings
The device marking will include both human-readable information and a 2-dimensional matrix code. The human-
readable information is described in 图10-2. The 2-dimensional matrix code is an alpha-numeric character string
that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first character of
the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial Number
(part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias voltage bin
letter.
Example: *1280-643AB GHXXXXX LLLLLLM
TI Internal Numbering
Part 2 of Serial Number
(7 characters)
Part 1 of Serial Number
(7 characters)
2-Dimension Matrix Code
(Part Number and Serial Number)
DMD Part Number
图10-2. DMD Marking Locations
10.3 Documentation Support
10.3.1 Related Documentation
The following documents contain additional information related to the chipset components used with the
DLP650LE:
• DLPC4430 Display Controller Data Sheet
• DLPA100 Power and Motor Driver Data Sheet
• DLPA200 Micromirror Driver Data Sheet
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10.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP650LEFYL
ACTIVE
CLGA
FYL
149
33
RoHS & Green
NI-AU
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
DLP650TEA0FYP
0.65-inch, 4K UHD, HSSI DLP® digital micromirror device (DMD) | FYP | 149 | 0 to 70
TI
DLP660TEAAFYG
0.66-inch, 4K UHD, 2XLVDS DLP® digital micromirror device (DMD) | FYG | 350 | 0 to 70
TI
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