DLP780NEA0FYU [TI]
0.78 英寸 1080p DLP® 数字微镜器件 (DMD) | FYU | 350 | 0 to 70;
| 型号： | DLP780NEA0FYU |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.78 英寸 1080p DLP® 数字微镜器件 (DMD) | FYU | 350 | 0 to 70 |
| 文件： | 总44页 (文件大小：1743K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP780NE
ZHCSP00A –SEPTEMBER 2021 –REVISED SEPTEMBER 2022
DLP780NE 0.78 1080P DMD
1 特性
3 说明
• 0.78 英寸对角线微镜阵列
DLP780NE 数字微镜器件 (DMD) 是一款数控微机电系
统 (MEMS) 空间光调制器 (SLM)，可用于实现高亮度
Full HD 固态照明显示系统。TI DLP® 0.78-inch Full
HD 芯片组由 DMD、DLPC4430 display controller、
DLPA300 微镜驱动器和 DLPA100 电源和电机驱动器
组成。芯片组外形紧凑，可为体型小巧并采用固态照明
的Full HD 显示提供完整的系统解决方案。
– Full HD (1920 × 1080) 显示分辨率
– 9.0µm 微镜间距
– ±14.5° 微镜倾斜度（相对于平坦表面）
– 角落照明
• 2xLVDS 输入数据总线
• 支持高达120 Hz 的Full HD 分辨率
• DLPC4430 display controller、DLPA100 电源管理
和电机驱动器IC 为LED、激光荧光体和RGB 激光
提供支持
为了帮助缩短设计周期，DMD 生态系统包含现成的资
源，其中包括量产就绪型光学模块、光学模块制造商和
设计公司。
2 应用
要了解有关如何使用 DMD 开始进行设计的更多信息，
请访问TI DLP 显示技术入门页面。
• 激光电视
• 智能投影仪
• 企业投影仪
• 数字标牌
器件信息
器件型号(1)
DLP780NE
封装尺寸（标称值）
封装
FYU (350)
35.0 mm × 32.2 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
SCRTL_A
2xLVDS Bus A Data Pairs
16
DCLK_A
SCRTL_B
2xLVDS Bus B Data Pairs
16
DCLK_B
SPI
DLPC4430
Display Controller
DLP780NE
2xLVDS DMD
DLPA300 Control
DLPA300
MBRST
Micromirror
Driver
-16.5 V
15
12 V
10 V
VREG
DMD POWER En
I2C
1.8 V
VREG
3.3 V
Temperature
TMP411
2
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS188
DLP780NE
www.ti.com.cn
ZHCSP00A –SEPTEMBER 2021 –REVISED SEPTEMBER 2022
Table of Contents
7.6 Micromirror Array Temperature Calculation.............. 23
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24
8 Application and Implementation..................................28
8.1 Application Information............................................. 28
8.2 Typical Application.................................................... 28
8.3 Temperature Sensor Diode.......................................31
9 Power Supply Recommendations................................33
9.1 DMD Power Supply Requirements........................... 33
9.2 DMD Power Supply Power-Up Procedure................33
9.3 DMD Power Supply Power-Down Procedure........... 33
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 35
11 Device and Documentation Support..........................37
11.1 第三方产品免责声明................................................37
11.2 Device Support........................................................37
11.3 Device Markings......................................................37
11.4 Documentation Support.......................................... 38
11.5 接收文档更新通知................................................... 38
11.6 支持资源..................................................................38
11.7 Trademarks............................................................. 38
11.8 Electrostatic Discharge Caution..............................38
11.9 术语表..................................................................... 38
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings........................................ 8
6.2 Storage Conditions..................................................... 8
6.3 ESD Ratings............................................................... 8
6.4 Recommended Operating Conditions.........................9
6.5 Thermal Information..................................................11
6.6 Electrical Characteristics...........................................11
6.7 Timing Requirements................................................12
6.8 System Mounting Interface Loads............................ 16
6.9 Micromirror Array Physical Characteristics...............17
6.10 Micromirror Array Optical Characteristics............... 18
6.11 Window Characteristics...........................................19
6.12 Chipset Component Usage Specification............... 19
7 Detailed Description......................................................20
7.1 Overview...................................................................20
7.2 Functional Block Diagram.........................................21
7.3 Feature Description...................................................21
7.4 Device Functional Modes..........................................21
7.5 Optical Interface and System Image Quality
Considerations............................................................ 22
Information.................................................................... 38
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (September 2021) to Revision A (September 2022)
Page
• 更正了器件信息中的封装尺寸............................................................................................................................1
• Updated ILLVIS, added ILLBLU and ILLBLU1 in 节6.4 ......................................................................................... 8
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ZHCSP00A –SEPTEMBER 2021 –REVISED SEPTEMBER 2022
5 Pin Configuration and Functions
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
X
Y
Z
AA
25 23 21 19 17 15 13 11
26 24 22 20 18 16 14 12 10
9
7
5
3
1
8
6
4
2
图5-1. FYU Package (350-Pin) Bottom View
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表5-1. Pin Functions
PIN
SIGNAL
TYPE
TYPE(1)
PIN DESCRIPTION
TERMINATION
SIGNAL
LVDS BUS C
D_CN(0)
D_CP(0)
PGA_PAD
B18
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
Differential 100 Ω
B19
H24
G24
L23
K23
C18
C19
A19
A20
E24
D24
K25
J25
D_CN(1)
D_CP(1)
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
D_CN(2)
D_CP(2)
D_CN(3)
D_CP(3)
D_CN(4)
D_CP(4)
D_CN(5)
D_CP(5)
D_CN(6)
D_CP(6)
D_CN(7)
D_CP(7)
C26
D26
C21
B21
G25
F25
A24
B24
J26
D_CN(8)
D_CP(8)
LVDS
D_CN(9)
D_CP(9)
D_CN(10)
D_CP(10)
D_CN(11)
D_CP(11)
D_CN(12)
D_CP(12)
D_CN(13)
D_CP(13)
D_CN(14)
D_CP(14)
D_CN(15)
D_CP(15)
DCLK_CN
DCLK_CP
SCTRL_CN
SCTRL_CP
K26
D25
C25
E23
D23
B23
C23
K24
L24
H23
G23
F26
G26
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表5-1. Pin Functions (continued)
PIN
SIGNAL
TYPE
TYPE(1)
PIN DESCRIPTION
TERMINATION
SIGNAL
LVDS BUS D
D_DN(0)
D_DP(0)
PGA_PAD
Z18
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
High-speed differential pair
Differential 100 Ω
Z19
T24
U24
N23
P23
Y18
Y19
AA19
AA20
W24
X24
P25
R25
Y26
X26
Y21
Z21
U25
V25
AA24
Z24
R26
P26
X25
Y25
W23
X23
Z23
Y23
P24
N24
T23
U23
V26
U26
D_DN(1)
D_DP(1)
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
D_DN(2)
D_DP(2)
D_DN(3)
D_DP(3)
D_DN(4)
D_DP(4)
D_DN(5)
D_DP(5)
D_DN(6)
D_DP(6)
D_DN(7)
D_DP(7)
D_DN(8)
D_DP(8)
LVDS
D_DN(9)
D_DP(9)
D_DN(10)
D_DP(10)
D_DN(11)
D_DP(11)
D_DN(12)
D_DP(12)
D_DN(13)
D_DP(13)
D_DN(14)
D_DP(14)
D_DN(15)
D_DP(15)
DCLK_DN
DCLK_DP
SCTRL_DN
SCTRL_DP
SCP INTERFACE
SCPCLK
U2
T3
U4
U3
I
I
Serial Communications Port CLK
Serial Communications Data In
LVCMOS
LVCMOS
Internal pulldown
Internal pulldown
Internal pulldown
Internal pulldown
SCPDI
SCPENZ
I
Serial Communications Port Enable LVCMOS
Serial Communications Port Output LVCMOS
SCPDO
O
OTHER SIGNALS
DMD_PWRDNZ
G4
I
LVCMOS
Internal pulldown
Chip–Level ResetZ
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ZHCSP00A –SEPTEMBER 2021 –REVISED SEPTEMBER 2022
表5-1. Pin Functions (continued)
PIN
SIGNAL
TYPE
TYPE(1)
PIN DESCRIPTION
TERMINATION
SIGNAL
PGA_PAD
G1, H1, J1, J3,
J4, K3, P3, R1,
R3, R4, T1, U1,
V3, D17, X17,
K4, P4, F3, G2,
H3, W18, G3,
W6, W5, Y5,
Y4, W15, X15,
Z16, Z15, Y16,
Y17, Z13, Z12,
Y14, Y13,
AA10, AA9,
Z10, Y10, Z5,
Z6, Z9, Z8, W3,
X3, X6, Y6, X7,
X8, Y8, Y7, X4,
W4, Y3, Z3,
N/C
No Connect
W11, W10, D4,
E4, C3, B3,
E15, D15, B16,
B15, C16, C17,
B13, B12, C14,
C13, A10, A9,
B10, C10, B5,
B6, B9, B8, C4,
C5, E5, E6, D7,
D8, C8, C7, D3,
E3, C6, D6,
E11, E10, X16
TEMP_N
TEMP_P
W16
W17
I/O
I/O
MICROMIRROR BIAS RESET INPUTS
MBRST(0)
MBRST(1)
MBRST(2)
MBRST(3)
MBRST(4)
MBRST(5)
MBRST(6)
MBRST(7)
MBRST(8)
MBRST(9)
MBRST(10)
MBRST(11)
MBRST(12)
MBRST(13)
MBRST(14)
E14
D13
E13
C12
E12
C11
D16
C15
W14
X13
W13
Y12
W12
Y11
Y15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
Mirror actuation signal
POWERS AND GROUNDS
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SIGNAL
ZHCSP00A –SEPTEMBER 2021 –REVISED SEPTEMBER 2022
表5-1. Pin Functions (continued)
PIN
SIGNAL
TYPE
TYPE(1)
PIN DESCRIPTION
TERMINATION
PGA_PAD
A5, A6, B2, C1,
D10, D12, D19,
D22, E8, E19,
E20, E21, E22,
F1, F2, J2, K1,
L1, L25, M3,
M4, M25, N1,
N25, P1, R2,
V1, V2, W8,
W19, W20,
VDD
P
Low-voltage CMOS core supply
W21, W22,
X10, X12, X19,
X22, Y1, Z1,
Z2, AA2, AA5,
AA6
A7, A8, A11,
A16, A17, A18,
A21, A22, A23,
AA7, AA8,
AA11, AA16,
AA17, AA18,
AA21, AA22,
AA23
VDDI
P
P
I/O supply
A3, A4, A25,
B26, L26, M26,
N26, Z26, AA3,
AA4, AA25
VCC2
Memory array stepped-up voltage
B4, B7, B11,
B14, B17, B20,
B22, B25, C2,
C9, C20, C22,
C24, D1, D2,
D5, D9, D11,
D14, D18, D20,
D21, E1, E2,
E7, E9, E16,
E17, E18, E25,
E26, F4, F23,
F24, H2, H4,
H25, H26, J23,
J24, K2, L2, L3,
L4, M1, M2,
VSS
G
Global ground
M23, M24, N2,
N3, N4, P2,
R23, R24, T2,
T4, T25, T26,
V4, V23, V24,
W1, W2, W7,
W9, W25, W26,
X1, X2, X5, X9,
X11, X14, X18,
X20, X21, Y2,
Y9, Y20, Y22,
Y24, Z4, Z7,
Z11, Z14, Z17,
Z20, Z22, Z25
(1) I = Input, O = Output, P = Power, G = Ground, NC = No Connect
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ZHCSP00A –SEPTEMBER 2021 –REVISED SEPTEMBER 2022
6 Specifications
6.1 Absolute Maximum Ratings
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not
imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating
Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MIN
MAX UNIT
SUPPLY VOLTAGES
VDD
Supply voltage for LVCMOS core logic(1)
Supply voltage for LVDS Interface(1)
Micromirror Electrode and HVCMOS voltage(1) (2)
Input voltage for MBRST pins(1)
2.3
2.3
V
V
V
V
V
–0.5
–0.5
VDDI
VCC2
VMBRST
|VDDI –VDD
11
–0.5
22.5
0.3
–17.5
Supply voltage delta (absolute value)(3)
|
INPUT VOLTAGES
|VID|
Input differential voltage for LVDS pins (absolute value)
Input voltage for all other input pins(1)
500
mV
V
V_LVCMOS
VDDI + 0.3
–0.3
ENVIRONMENTAL
Temperature, operating(4)
0
90
90
81
°C
°C
°C
TARRAY
TDP
Temperature, nonoperating(4)
–40
Dew point temperature, operating and non–operating (noncondensing)
(1) All voltages are referenced to common ground VSS. VDD, VDDI, and VCC2 power supplies are all required for all DMD operating modes.
(2) VCC2 supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable voltage difference between VDD and VDDI may result in excessive current draw.
(4) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1), shown in Figure 7-1 using the 节7.6.
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system
MIN
MAX
80
UNIT
°C
TDMD
DMD storage temperature
–40
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature (noncondensing)(1)
Elevated dew point temperature range (noncondensing)(2)
Cumulative time in elevated dew point temperature range
28
°C
28
36
°C
24 months
(1) This is the average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation must be limited to less than a total cumulative
time of CTELR
.
6.3 ESD Ratings
SYMBOL
PARAMETER
DESCRIPTION
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
V(ESD)
V
Electrostatic
discharge (MBRST
PINS)
V(ESD)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
±150
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
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6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in
this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is
implied when operating the device above or below these limits.
MIN NOM
MAX
UNIT
VOLTAGE SUPPLY
VDD
Supply voltage for LVCMOS core logic(1)
Supply voltage for LVDS Interface(1)
1.65
1.65
9.5
1.8
1.8
10
1.95
1.95
10.5
21.5
0.3
V
V
V
V
V
VDDI
VCC2
VMBRST
Micromirror Electrode and HVCMOS voltage(1) (2)
Micromirror Bias / Reset Voltage(1)
–17
Supply voltage delta (absolute value)(3)
0
|VDD –VDDI
LVCMOS
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
IOH
|
Input High Voltage
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
VDD + 0.3
0.2 × VDD
2
V
V
Input Low Voltage
Input High Voltage
0.8 × VDD
–0.3
V
Input Low Voltage
V
High-level Output Current
Low-level Output Current
PWRDNZ pulse width(4)
mA
mA
ns
IOL
–2
tPWRDNZ
10
SCP INTERFACE
FSCPCLK
SCP clock frequency
50
500
kHz
SCPCLKDCDIN
LVDS INTERFACE
FCLOCK
SCP Clk Input duty cycle
40%
60%
Clock frequency for LVDS interface (all channels), DCLK(5)
Input CLK Duty Cycle Distortion tolerance
Input differential voltage (absolute value)(6)
Common mode voltage(6)
400
56%
440
MHz
DCDIN
44%
150
|VID|
300
mV
mV
mV
µs
VCM
1100 1200
1300
1520
VLVDS
LVDS voltage(6)
880
2
tLVDS_RSTZ
ZIN
Time required for LVDS receivers to recover from PWRDNZ
Internal differential termination resistance
Line differential impedance (PWB/trace)
80
90
100
100
120
110
Ω
ZLINE
Ω
ENVIRONMENTAL
Array temperature, long-term operational(7) (8) (9)
10
0
40 to 70(10)
°C
°C
°C
°C
TARRAY
Array temperature, short-term operational, 500 hr max(8) (11)
Average dew point average temperature (non–condensing)(12)
Elevated dew point temperature range (non-condensing)(13)
Cumulative time in elevated dew point temperature range
Window aperture illumination overfill(14) (15)
10
28
36
TDP -AVG
TDP-ELR
CTELR
28
24 Months
17 W/cm2
QAP-ILL
SOLID STATE ILLUMINATION
ILLUV
ILLBLU1
ILLBLU
ILLVIS
ILLIR
Illumination power at wavelengths < 410 nm(7)
10 mW/cm2
1
W/cm2
Illumination power at wavelengths ≥410 nm and ≤440 nm(16)
Illumination power at wavelengths ≥410 nm and ≤475 nm(16)
Illumination power at wavelengths ≥410 nm and ≤800 nm(16)
Ilumination power at wavelengths > 800 nm
5.5 W/cm2
18 W/cm2
10 mW/cm2
(1) All voltages are referenced to common ground VSS. VDD, VDDI, and VCC2 power supplies are all required for proper DMD operation.
VSS must also be connected.
(2) VCC2 supply transients must fall within specified max voltages.
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(3) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than the specified limit. See the DMD Power Supply
Requirements.
(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. The PWRDNZ input pin overrides the SCPENZ input pin and
tristates the SCPDO output pin.
(5) See LVDS clock timing requirements in Timing Requirements.
(6) See Figure 6-5 for the LVDS waveform requirements.
(7) Simultaneous exposure of the DMD to the maximum Recommend Operating Conditions for temperature and UV illumination reduces
device lifetime.
(8) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1), shown in Figure 7-1 using the Micromirror Array Temperature Calculation.
(9) Long-term is defined as the usable life of the device.
(10) Per Figure 6-1, the maximum operational array temperature is derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. See Micromirror Landed-on/Landed-off Duty Cycle for a definition of micromirror landed duty cycle.
(11) Short-term is the total cumulative time over the useful life of the device.
(12) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(13) Exposure to dew point temperatures in the elevated range during storage and operation is limited to less than a total cumulative time of
CTELR
.
(14) Applies to region defined in Figure 6-2
(15) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD
device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area
outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. Minimizing the
light flux incident outside the active array is a design requirement of the illumination optical system. Depending on the particular optical
architecture and assembly tolerances of the optical system, the amount of overfill light on the outside of the active array may
cause system performance degradation.
(16) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength
range specified and the micromirror array temperature (TARRAY).
80
70
60
50
40
30
0/100
100/0
5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
65/35
95/5
90/10
85/15
80/20
75/25
70/30
60/40
55/45
50/50
Micromirror Landed Duty Cycle
图6-1. Maximum Recommended Array Temperature—Derating Curve
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0.50 mm Critical area on window aperture
Window
Array
12.105 mm
Window
Aperture
18.613 Window Aperture
Window
图6-2. Illumination Overfill Diagram - Critical Area
6.5 Thermal Information
DLP780NE
FYU
THERMAL METRIC
UNIT
350 PINS
0.55
Thermal resistance, active area to test point 1 (TP1)(1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the DMD within the temperature range specified in the Recommended operating conditions.
The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other contributions include
light energy absorbed by the window aperture and electrical power dissipation of the array.
Minimizing the light energy falling outside the window clear aperture is a design requirement of the optical system because any
additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Information
(1)
IDD
Supply current VDD
Supply current VDDI
Supply current VCC2
800
170
40
mA
mA
(1)
IDDI
ICC2
PDD
mA
(1)
Supply power VDD
Supply power VDDI
Supply power VCC2
1560
332
420
mW
mW
mW
(1)
(1)
PDDI
PCC2
LVCMOS
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6.6 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
× VDD
× VDD
µA
VOH
High-level output voltage
Low-level output voltage
High impedance output current
Low-level input current
High-level input current(2)
IOH = 2 mA
0.8
VOL
IOL = 2 mA
0.2
10
IOZ
VDD = 1.95 V
IIL
VDD= 1.95 V, Vin = 0 V
VDD = 1.95 V, Vin = VDD
µA
–60
IIH
200
µA
Capacitances
CI
Input capacitance: LVDS pins
Input capacitance(2)
f = 1 MHz
f = 1 MHz
f = 1 MHz
20
15
pF
pF
pF
pF
CI
CO
CIM
Output capacitance(2)
15
Input capacitance for MBRST[0:14] pins f = 75 kHz
360
410
520
(1) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than the specified limit in Absolute Maximum Ratings.
(2) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins
6.7 Timing Requirements
Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER DESCRIPTION
MIN
NOM
MAX
UNIT
SCP
SCPDI clock setup time (before SCPCLK
tSCP_DS
800
900
1
ns
ns
µs
µs
ns
falling-edge)(1)
SCPDI hold time (after SCPCLK falling-edge)
tSCP_DH
(1)
Time between falling edge of SCPENZ and
the rising edge of SCPCLK(1)
tSCP_NEG_ENZ
tSCP_POS_ENZ
tSCP_OUT_EN
Time between falling edge of SCPCLK and
the rising edge of SCPENZ(1)
1
Time required for SCP output buffer to
recover after SCPENZ (from tri-state).(1)
960
tSCP_PW_ENZ
SCPENZ inactive pulse width (high-level)
Rise time (20% to 80%). See (2)
Fall time (80% to 20%). See (2)
1
1/Fscpclk
ns
tr
200
200
tf
ns
LVDS
tR_LVDS
tF_LVDS
Rise time (20% to 80%). See (3)
Fall time (80% to 20%). See (3)
500
500
ps
ps
Clock Cycle Duration for DCLK_C and
DCLK_D(4)
tC
2.5
1.19
350
ns
ns
ps
ps
ps
ps
ns
tW
Pulse Duration for DCLK_C/D(4)
Setup Time for High-speed data(15:0) before
DCLK(4)
tSU_data
tSU_sctrl
tH_data
tH_sctrl
tSKEW_C2D
Setup Time for SCTRL before DCLK(4)
330
Hold time for High-speed data(15:0) after
DCLK(4)
150
Hold Time for SCTRL after DCLK(4)
170
Skew tolerance between Channel C and
Channel D(5) (6) (7)
1.25
–1.25
(1) See Figure 6-3.
(2) See Figure 6-4.
(3) See Figure 6-6.
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(4) See Figure 6-7.
(5) See Figure 6-8.
(6) Channel C (Bus C) includes the following LVDS pairs: DCLK_C, SCTRL_C, and D_C.
(7) Channel D (Bus D) includes the following LVDS pairs: DCLK_D, SCTRL_D, and D_D.
tSCP_POS_ENZ
tSCP_NEG_ENZ
SCPCLK fallingœedge capture for SCPDI
SCPCLK risingœedge launch for SCPDO
SCPENZ
50%
tSCP_DS
tSCP_DH
50%
SCPDI
50%
SCPCLK
tSCP_PD
50%
SCPDO
图6-3. SCP Timing Parameters
SCPCLK, SCPDI,
SCPDO, SCPENZ
100%
80%
20%
0%
tf
tr
Time
图6-4. SCP Rise and Fall Times
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VLVDS max
VID
VCM
VLVDS min
图6-5. LVDS Waveform Parameters
DCLK_CN, DCLK_CP, D_CN(0:15), D_CP(0:15), SCRTL_CN, SCTRL_CP,
DCLK_DN, DCLK_DP, D_DN(0:15), D_DP(0:15), SCRTL_DN, SCTRL_DP
100%
80%
20%
0%
tf
tr
Time
图6-6. LVDS Rise and Fall Times
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tc
tW
tW
DCLK_P
50%
DCLK_N
tSU_data
tH_data
D_P(0:15)
50%
D_N(0:15)
tSU_scrtl
tH_scrtl
SCRTL_P
50%
SCRTL_N
图6-7. LVDS Timing Parameters
DCLK_CP
50%
DCLK_CN
D_CP(0:15)
50%
D_CN(0:15)
SCRTL_CP
50%
SCRTL_CN
tSKEW_C2D
DCLK_DP
50%
DCLK_DN
D_DP(0:15)
50%
D_DN(0:15)
SCRTL_DP
50%
SCRTL_DN
图6-8. LVDS Skew Parameters
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UNIT
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6.8 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
When loads are applied on both electrical and thermal interface areas
Maximum load to be applied to the electrical interface area(1)
Maximum load to be applied to the thermal interface area(1)
When load is applied on the electrical interface area only
Maximum load to be applied to the electrical interface area(1)
Maximum load to be applied to the thermal interface area(1)
111
111
N
N
222
0
N
N
(1) The load must be uniformly applied in the corresponding areas shown in Figure 6-9.
Electrical Interface Area
Thermal Interface Area
图6-9. System Mounting Interface Loads
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6.9 Micromirror Array Physical Characteristics
PARAMETER DESCRIPTION
VALUE
1920
1080
9.0
UNIT
micromirrors
micromirrors
µm
M
Number of active columns (1)
N
Number of active rows (1)
P
Micromirror (pixel) pitch(1)
Micromirror active array width(1)
Micromirror active array height(1)
Micromirror active border (top and bottom)(2)
Micromirror active border (right and left)(2)
Micromirror pitch x number of active columns
Micromirror pitch x number of active rows
Pond of micromirror (POM)
17.280
9.720
12
mm
mm
micromirrors/side
micromirrors/side
Pond of micromirror (POM)
12
(1) See Figure 6-10.
(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
Incident
Illumination
Light Path
0
1
2
3
Active Micromirror Array
N x P
M x N Micromirrors
N œ 4
N œ 3
N œ 2
N œ 1
Off-State
Light Path
M x P
P
P
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity.
Not to scale.
P
图6-10. Micromirror Array Physical Characteristics
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6.10 Micromirror Array Optical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
14.5 15.5
3
UNIT
Micromirror tilt angle(2) (3) (4) (5)
Micromirror crossover time(6)
Micromirror switching time(7)
Landed state(1)
typical performance
typical performance
Gray 10 screen(12)
Gray 10 screen(12)
White screen(13)
Any screen
13.5
degrees
µs
10
µs
Bright pixel(s) in active area(9)
Bright pixel(s) in the POM(9) (11)
Dark pixel(s) in the active area(10)
Adjacent pixel(s)(14)
0
1
4
0
0
Image
micromirrors
performance (8)
Unstable pixel(s) in active area(15)
Any screen
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(4) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations or system contrast variations.
(5) Refer to Figure 6-11.
(6) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(7) The minimum time between successive transitions of a micromirror.
(8) Conditions of Acceptance: all DMD image performance returns are evaluated using the following projected image test conditions:
Test set degamma shall be linear.
Test set brightness and contrast shall be set to nominal.
The diagonal size of the projected image shall be a minimum of 60 inches.
The projections screen shall be 1× gain.
The projected image shall be inspected from an 8-foot minimum viewing distance.
The image shall be in focus during all image performance tests.
(9) Bright pixel definition: a single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(10) Dark pixel definition: a single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(11) POM definition: rectangular border of off-state mirrors surrounding the active area
(12) Gray 10 screen definition: a full screen with RGB values set to R = 10/255, G = 10/255, B = 10/255
(13) White screen definition: a full screen with RGB values set to R=255/255, G = 255/255, B = 255/255
(14) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster.
(15) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The
unstable pixel appears to be flickering asynchronously with the image.
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Incident Light
Direction
Off-State Light
Direction
Landed Corner
Rotation Axis
A
Landed Corner
Landed Corne
A
R
Landed Corner
View A-A
图6-11. Micromirror Landed Orientation and Tilt
6.11 Window Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DESCRIPTION
Window Material
Window Refractive Index
Corning EagleXG
1.5119
546.1 nm
6.12 Chipset Component Usage Specification
Reliable function and operation of the DLP780NE DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
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control technology. TI DMD control technology consists of the TI technology and devices used for operating or
controlling a DLP DMD.
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
7 Detailed Description
7.1 Overview
The DMD is a 0.78-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system
(MOEMS). The fast switching speed of the DMD micromirrors combined with advanced DLP image processing
algorithms enables the micromirror array to display a full 1920 × 1080 pixel image at a 120 Hz frame rate. The
electrical interface is a low voltage differential signaling (LVDS) interface. The DMD consists of a two-
dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N
memory cell rows. Refer to the 节 7.2. The positive or negative deflection angle of the micromirrors can be
individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror
reset signals (MBRST).
The DLP 0.78-inch Full HD chipset is comprised of the DLP780NE DMD, DLPC4430 display controller, the
DLPA300 micromirror driver and the DLPA100 power management and motor driver. To ensure reliable
operation, the DLP780NE DMD must always be used with the DLP display controller and the power and motor
driver specified in the chipset.
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7.2 Functional Block Diagram
Channel C Interface
Column Read and
Write
Control
Control
Bit Lines
(0,0)
Electrode
Voltage
Generators
Word Lines
Row
Voltages
Micromirror Array
(M-1, N-1)
Bit Lines
Column Read and
Write
Control
Control
Channel D Interface
7.3 Feature Description
7.3.1 Power Interface
The DMD requires two DC voltages: 1.8-V source for VDD and VDDI, and a 10-V supply for VCC2. In a typical
configuration, 3.3 V is created by the DLPA100 power management and motor driver and is used on the DMD
board to create the 1.8 V. The DLPA300 micromirror driver takes in the 12 V and creates the micromirror reset
voltages.
7.3.2 Timing
The data sheet specifies timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be considered. Timing reference loads are not intended to be precise
representations of any particular system environment or depiction of the actual load presented by a production
test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing reference
load to a system environment. Use the specified load capacitance value for characterization and measurement
of AC timing signals only. This load capacitance value does not indicate the maximum load the device is capable
of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC4430 display controller. See the DLPC4430 display controller
data sheet or contact a TI applications engineer.
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7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
TI recommends that the light cone angle defined by the numerical aperture of the illumination optics is the same
as the light cone angle defined by the numerical aperture of the projection optics. This angle must not exceed
the nominal device micromirror tilt angle unless appropriate apertures are added in the illumination and
projection pupils to block out flat-state and stray light from the projection lens. The DLP780NE has a 14.5° tilt
angle which corresponds to the f/2.0 numerical aperture. The micromirror tilt angle defines DMD capability to
separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections from
the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens
surfaces. If the numerical aperture exceeds the micromirror tilt angle, or if the projection numerical aperture
angle is more than 2° larger than the illumination numerical aperture angle (and vice versa), contrast
degradation and objectionable artifacts in the display border or active area are possible.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border and active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. Design the illumination optical
system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the
average flux level in the active area. Depending on the particular system optical architecture, overfill light may
have to be further reduced below the suggested 10% level in order to be acceptable.
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7.6 Micromirror Array Temperature Calculation
Array
Window Edge
TP1
8.6
17.5
TP1
图7-1. DMD Thermal Test Point
Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from a
measurement point on the outside of the package, the package thermal resistance, the electrical power, and the
illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test TP1 in 图7-1 ) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
)
(1)
(2)
QARRAY = QELECTRICAL + QILLUMINATIOM
where
• TARRAY = Computed array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C) (TP1 location)
• RARRAY-TO-CERAMIC = Thermal resistance of package specified in 节6.5 from array to ceramic TP1 (°C/Watt)
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• QARRAY = Total DMD power on the array (W) (electrical + absorbed)
• QELECTRICAL = Nominal electrical power (W)
• QINCIDENT = Incident illumination optical power (W)
• QILLUMINATION = (DMD average thermal absorptivity × QINCIDENT) (W)
• DMD average thermal absorptivity = 0.55
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 1.0 W. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a single chip or multichip DMD
system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.
The sample calculation for a typical projection application is as follows:
QINCIDENT = 35 W (measured)
TCERAMIC = 55.0°C (measured)
(3)
(4)
QELECTRICAL = 1.0 W
(5)
QARRAY = 1.0 W + (0.55 × 35 W) = 20.25 W
(6)
(7)
TARRAY = 55.0°C + (20.25 W × 0.55°C/W) = 66.1°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the percentage of time that an
individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the
OFF state.
For example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the time
(and in the OFF state 0% of the time); whereas 0/100 indicates that the pixel is in the OFF state 100% of the
time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD useful life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect DMD useful life, and this interaction can
be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD useful life. This is
quantified in the derating curve shown in 图6-1.
The importance of this curve is that:
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• All points along this curve represent the same useful life.
• All points above this curve represent lower useful life (and the further away from the curve, the lower the
useful life).
• All points below this curve represent higher useful life (and the further away from the curve, the higher the
useful life).
In practice, this curve specifies the maximum operating DMD temperature for a given long-term average landed
duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the
pixel operates under a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.
表7-1. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a
given primary must be displayed in order to achieve the desired white point.
Use 方程式8 to calculate the landed duty cycle of a given pixel during a given time period.
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value)
(8)
+
(Blue_Cycle_%
×
Blue_Scale_Value)
where
• Red_Cycle_% represents the percentage of the frame time that red is displayed to achieve the desired white
point.
• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired
white point.
• Blue_Cycle_% represents the percentage of the frame time that blue is displayed to achieve the desired
white point.
For example, assume that the red, green, and blue color cycle times are 30%, 50%, and 20% respectively (to
achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue color
intensities are shown in 表7-2 and 表7-3.
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表7-2. Example Landed Duty Cycle for Full-Color,
Color Percentage
CYCLE PERCENTAGE
GREEN
RED
BLUE
30%
50%
20%
表7-3. Example Landed Duty Cycle for Full-Color
SCALE VALUE
GREEN
0%
LANDED DUTY
CYCLE
RED
0%
BLUE
0%
0/100
30/70
50/50
20/80
6/94
100%
0%
0%
0%
100%
0%
0%
0%
100%
0%
0%
12%
0%
0%
35%
0%
7/93
60%
0%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
35%
35%
0%
60%
60%
100%
0%
12%
100%
100%
The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the
DLPC4430 display controller, the gamma function affects the landed duty cycle.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC4430 display controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A
typical gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.
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100
90
80
70
60
50
40
30
20
10
0
Gamma = 2.2
0
10
20
30
40
50
60
Input Level (%)
70
80
90 100
D002
图7-2. Example of Gamma = 2.2
From 图 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale
value is 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact displayed
gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
Consideration must also be given to any image processing that occurs before the DLPC4430 display controller.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC4430
display controller. Typical applications using the DLP780NE DMD include laserTV, smart projectors, enterprise
projectors and digital signage.
DMD power-up and power-down sequencing is strictly controlled by the DLPC4430 display controller through the
DLPA300. Refer to 节 9.2 for power-up and power-down specifications. To ensure reliable operation, the
DLP780NE DMD must always be used with DLPC4430 display controller, a DLPA100 PMIC/Motor driver and a
DLPA300 Micromirror Driver.
8.2 Typical Application
The DLP780NE DMD combined with DLPC4430 display controller and a power management device provides
Full HD resolution for bright, colorful display applications. A typical display system using LED illumination
combines the DLP780NE DMD, DLPC4430 display controller, DLPA300 micromirror driver and DLPA100 PMIC
and motor driver. 图 8-1 shows a system block diagram for this configuration of the DLP 0.78-inch Full HD
chipset and additional system components needed. See 图 8-2 for a block diagram showing the system
components needed along with the laser phosphor of the DLP 0.78-inch Full HD chipset. The components
include DLP780NE DMD, DLPC4430 display controller and DLPA100 PMIC and motor driver and a DLPA300
micromirror driver.
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Flash
PWM (3)
LED_EN (3)
LED
Driver
(22) (16)
ADDR
DATA
1.1 V
1.8 V
3.3 V
1.1 V
12 V
1.8V
2.5V
3.3V
5V
DLPA100
(Controller
Voltages)
CNTRL (8)
FE CTRL
Front
End IC
Parallel
Data (30)
FIELD
OSC
TMP411
(Temp
Sensor)
DMD TEMP (2)
I2C (2)
DLPC4430
Controller
IR Rx
(2)
2Port 2xLVDS (68)
DMD Control (5)
DLP780NE
DMD
3.3-V to 1.8-V
Level Shifters
SSCP(4)
SSCP(4)
3D L/R
SSCP(4)
MBRST (15)
USB 1.0 (2)
GPIO
CNTRL (13)
12 V
-16.5 V
DLPA300
10 V
VCC2
1.2 V
VDD/VDDI
DLP Chipset Components
图8-1. Typical Full HD LED Application
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Flash
Laser
Driver
CNTRL
DLPA100
(22) (16)
ADDR
DATA
12 V
(Motor
1.1 V
1.8 V
3.3 V
CNTRL (8)
(4)
Wheel Motor 2
Wheel Motor 1
Control)
1.1 V
12 V
DLPA100
(Controller
Voltages and
Motor
1.8 V
2.5 V
3.3 V
5 V
FE CTRL
CNTRL (8)
Front
End IC
Parallel
Data (30)
CW Index 2
CW Index 1
Control)
(4)
FIELD
OSC
TMP411
(Temp
Sensor)
DMD TEMP (2)
I2C (2)
DLPC4430
Controller
IR Rx
(2)
2Port 2xLVDS (68)
DMD Control (5)
3.3-V to 1.8-V
Level Shifters
SSCP(4)
SSCP(4)
DLP780NE
DMD
3D L/R
USB 1.0 (2)
GPIO
SSCP(4)
MBRST (15)
CNTRL (13)
DLPA300
12 V
-16.5 V
10 V
VCC2
DLP Chipset Components
1.2 V
VDD/VDDI
图8-2. Typical Full HD Laser Phosphor Application
8.2.1 Design Requirements
Other core components of the display system include an illumination source, an optical engine for the
illumination and projection optics, other electrical and mechanical components, and software. The type of
illumination used and desired brightness has a major effect on the overall system design and size.
The display system uses the DLP780NE DMD as the core imaging device and contains a 0.78-inch array of
micromirrors. The DLPC4430 display controller is the digital interface between the DMD and the rest of the
system, taking digital input from front end receiver and driving the DMD over a high-speed LVDS interface. The
DLPA100 PMIC serves as a voltage regulator for the controller, and color filter wheel and phosphor wheel motor
control. The DLPA300 provides the DMD reset control.
8.2.2 Detailed Design Procedure
For a complete DLP system, an optical module or light engine is required that contains the DLP780NE DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DMD must always be used with DLPC4430 display controller, the DLPA300
micromirror driver and the DLPA100 PMIC and motor driver.
8.2.3 Application Curves
In a typical projector application, the luminous flux on the screen from the DMD depends on the optical design of
the projector. The efficiency and total power of the illumination optical system and the projection optical system
determines the overall light output of the projector. The DMD is inherently a linear spatial light modulator, so its
efficiency just scales the light output. 图 8-3 describes the relationship of laser input optical power to light output
for a laser-phosphor illumination system, where the phosphor is not at its thermal quenching limit.
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1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
Normalized Laser Power
0.75
0.8
0.85
0.9
0.95
1
norm
图8-3. Normalized Light Output vs. Normalized Laser Power for Laser Phosphor Illumination
8.3 Temperature Sensor Diode
The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside the
micromirror array. The thermal diode can be interfaced with the TMP411 temperature sensor as shown in 图8-4.
The software application contains functions to configure the TMP411 to read the DLP780NE DMD temperature
sensor diode. This data can be leveraged by the customer to incorporate additional functionality in the overall
system design such as adjusting illumination, fan speeds, etc. All communication between the TMP411 and the
DLPC4430 display controller happens over the I2C interface. The TMP411 connects to the DMD via pins outlined
in 节5.
Leave TEMP_N and TEMP_P pins unconnected (NC) if the temp sensor is not used.
3.3V
TMP411
DLP780NE
SCL
SDA
VCC
D+
R3
R5
TEMP_P
ALERT
THERM
GND
C1
R4
R6
D-
TEMP_N
GND
A. Details omitted for clarity.
B. See the TMP411 datasheet for system board layout recommendation.
C. See the TMP411 datasheet and the TI reference design for suggested component values for R1, R2, R3, R4, and C1.
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D. R5 = 0 Ω. R6 = 0 Ω. Place 0-Ωresistors close to the DMD package pins.
图8-4. TMP411 Sample Schematic
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9 Power Supply Recommendations
9.1 DMD Power Supply Requirements
The following power supplies are all required to operate the DMD: VDD, VDDI, and VCC2. VSS must also be
connected. DMD power-up and power-down sequencing is strictly controlled by the DLPC4430 display
controller.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power-up and power-down procedures may affect
device reliability. VDD, VDDI and VCC2 power supplies have to be coordinated during power-up and
power-down operations. VSS must also be connected. Failure to meet any of the below
requirements results in a significant reduction in the reliability and lifetime of the DMD. Refer to 图
9-1.
9.2 DMD Power Supply Power-Up Procedure
• During power-up, VDD and VDDI must always start and settle before VCC2 is are applied to the DMD.
• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements listed in 节6.1 and in 节6.4.
• During power-up, LVCMOS input pins must not be driven high until after VDD and VDDI have settled at
operating voltages listed in 节6.4 table.
9.3 DMD Power Supply Power-Down Procedure
• During power-down, VDD and VDDI must be supplied until after VCC2 is discharged to within the specified
limit of ground. Refer to 节6.4.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed in 节6.1 and in 节6.4.
• During power-down, LVCMOS input pins must be less than specified in 节6.4.
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Note A
VDD/VDDI
VSS
Note B
Note H
VCC2
VSS
Note F
Note G
VDD
Note C
TLVDS_RSTZ
Note D
PWRDNZ
Option 1
VSS
TPWRDNZ
VDD
VSS
PWRDNZ
Option 2
TLVDS_RSTZ
VDD
VSS
LVCMOS
Inputs
LVDS Inputs
VSS
图9-1. DMD Power Supply Sequencing Requirements
A. See Pin Configuration and Functions for pin functions.
B. VDD must be up and stable prior to VCC2 powering up.
C. PWRDNZ has two turn on options. Option 1: PWRDNZ does not go high until VDD and VCC2 are up and stable, or Option 2: PWRDNZ
must be pulsed low for a minimum of TPWRDNZ, or 10 ns after VDD and VCC2 are up and stable.
D. There is a minimum of TLVDS_ARSTZ, or 2 μs, wait time from PWRDNZ going high for the LVDS receiver to recover.
E. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates the
PWRDNZ and disables VCC2.
F. Under power-loss conditions, where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware,
PWRDNZ goes low.
G. VDD must remain high until after VCC2 goes low.
H. To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than specified limit in 节6.4.
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10 Layout
10.1 Layout Guidelines
The DLP780NE DMD is part of a chipset that is controlled by the DLPC4430 display controller in conjunction
with the DLP300 micromirror driver and the DLPA100 power and motor driver. These guidelines are targeted at
designing a PCB board with the DLP780NE DMD. The DLP780NE DMD board is a high-speed multi-layer PCB,
with primarily high-speed digital logic utilizing dual edge clock rates up to 400MHz for DMD LVDS signals. The
remaining traces are comprised of low speed digital LVTTL signals. Solid planes are required for DMD_P1P8V
and Ground. The target impedance for the PCB is 50 Ω ±10% with the LVDS traces being 100 Ω ±10%
differential. TI recommends using an 8-layer stack-up as described in 表10-1.
10.2 Layout Example
图10-1. Typical example for matching LVDS signal lengths by serpentine sections
10.2.1 Layers
The layer stack-up and copper weight for each layer is shown in 表10-1. Small sub-planes are allowed on signal
routing layers to connect components to major sub-planes on top/bottom layers if necessary.
表10-1. Layer Stack-Up
LAYER
NO.
LAYER NAME
Side A - DMD only
COPPER WT. (oz.)
COMMENTS
1
1.5
1
DMD, escapes, low frequency signals, power sub-planes.
Solid ground plane (net GND).
2
Ground
3
Signal
0.5
1
50 Ωand 100 Ωdifferential signals
Solid ground plane (net GND)
4
Ground
5
VDD and VDDI
Signal
1
+1.8-V power plane
6
0.5
1
50 Ωand 100 Ωdifferential signals
Solid ground plane (net GND).
7
Ground
8
Side B - All other Components
1.5
Discrete components, low frequency signals, power sub-planes
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10.2.2 Impedance Requirements
TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed
in 表10-2.
表10-2. Special Impedance Requirements
SIGNAL TYPE
SIGNAL NAME
IMPEDANCE (Ω)
DDCP(0:15), DDCN(0:15)
DCLKC_P, DCLKC_N
SCTRL_CP, SCTRL_CN
DDDP(0:15), DDDN(0:15)
DCLKD_P, DCLKD_N
SCTRL_DP, SCTRL_DN
100 ±10% differential across
each pair
C channel LVDS differential pairs
100 ±10% differential across
each pair
D channel LVDS differential pairs
10.2.3 Trace Width, Spacing
Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.005” design rule. Minimum
trace clearance from the ground ring around the PWB has a 0.1” minimum. An analysis of impedance and
stack-up requirements determine the actual trace widths and clearances.
10.2.3.1 Voltage Signals
表10-3. Special Trace Widths, Spacing Requirements
MINIMUM TRACE WIDTH TO
SIGNAL NAME
GND
LAYOUT REQUIREMENT
Maximize trace width to connecting pin
PINS (MIL)
15
15
15
15
15
3.3-V Supply Rail
VDD, VDDI
MBRST(0,14)
VCC2
Maximize trace width to connecting pin
Maximize trace width to connecting pin
Use 10 mil etch to connect all signals/voltages from DLPA300 to DLP780NE
Create mini plane from Voltage regulator to DLP780NE
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Device Support
11.2.1 Device Nomenclature
DLP780NE xc FYU
Package Type
TI Internal Numbering
Device Descriptor
图11-1. Part Number Description
11.3 Device Markings
The device marking includes both human-readable information and a 2-dimensional matrix code. The human-
readable information is described in 图 11-2. The 2-dimensional matrix code is an alpha-numeric string that
contains the DMD part number, Part 1 and Part 2 of the serial number.
Example:
TI Internal Numbering
2-Dimension Matrix Code
DMD Part Number
(Part Number and
YYYYYYY
Serial Number)
DLP780NE xc FYU
GHXXXXX LLLLLLM
Part 1 of Serial Number
(7 characters)
Part 2 of Serial Number
(7 characters)
图11-2. DMD Marking Locations
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11.4 Documentation Support
11.4.1 Related Documentation
For related documentation, see the following:
• DLPC4430 DLP Display Controller Data Sheet
• DLPA100 Power and Motor Driver Data Sheet
• DLPA300 DMD Micromirror Driver Data Sheet
11.5 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.6 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.7 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.9 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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1-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP780NEA0FYU
ACTIVE
CPGA
FYU
350
21
RoHS & Green
NI-AU
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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