DLP9500BFLN [TI]
DLP® 0.95 1080p 2xLVDS A 型 DMD | FLN | 355 | 20 to 70;型号: | DLP9500BFLN |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® 0.95 1080p 2xLVDS A 型 DMD | FLN | 355 | 20 to 70 商用集成电路 |
文件: | 总54页 (文件大小:1536K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
DLP9500 DLP® 0.95 1080p 2x LVDS A 型 DMD
1 特性
3 说明
•
•
•
0.95 英寸对角线微镜阵列
DLP9500 1080p 芯片组是 DLP® Discovery™4100 平
1
台的一部分,用于实现高分辨率、高性能的空间照明调
制。DLP9500 是 0.95 1080p 芯片组的基本款数字微
镜器件 (DMD)。DLP Discovery 4100 平台还提供具有
随机行寻址选项的最高级独立微镜控制。除了采用密封
封装外,DLP9500 具有独特的功能和价值,非常适合
支持各种工业、医疗和高级显示 应用的需求。
–
1920 × 1080 铝阵列,微米级微镜(1080p 分
辨率)
–
–
–
10.8µm 微镜间距
±12°微镜倾斜角(相对于平板状态)
设计用于边缘照明
专用于可见光
(400nm 至 700nm):
除了 DLP9500 DMD 以外,0.95 1080p 芯片组还包括
专用的 DLPC410 控制器(用于支持 23,148Hz(1 位
二进制)和 2,893Hz(8 位灰度)的)、一个
–
–
–
–
窗透射率 96%(单通,通过两个窗面)
微镜反射率 89%
阵列衍射效率 87%
DLPR410 单元(DLP Discovery 4100 配置 PROM)
和两个 DLPA200 单元(DMD 微镜驱动器)。
阵列填充因子 94%
四条 16 位低压差分信令 (LVDS)、双倍数据速率
(DDR) 输入数据总线
DLP9500 需要与芯片组的其他元件结合使用才能实现
可靠功能和操作。一套专用的芯片组能够使开发人员更
加轻松地访问 DMD 并使用高速而独立的微镜控制。
•
•
•
高达 400MHz 的输入数据时钟速率
42.2mm × 42.2mm × 7mm 封装尺寸
气密封装
DLP9500 是一款数控微光机电系统 (MEMS) 空间照明
调制器 (SLM)。当与适当的光系统成对使用
时,DLP9500 可用于调制入射光的振幅、方向和/或相
位。
2 应用
•
工业:
–
–
–
–
–
–
–
数字成像平版印刷
器件信息 (1)
激光打标
器件型号
DLP9500
封装
封装尺寸(标称值)
LCD 和 OLED 修复
计算机直接制版打印机
SLA 3D 打印机
LCCC (355)
42.16mm × 42.16mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
针对机器视觉和工厂自动化的 3D 扫描仪
平板印刷
简化原理图
•
医疗领域:
–
–
–
–
–
–
光照治疗器件
眼科学
直接制造
高光谱成像
3D 生物识别
共轭焦显微镜
•
显示:
–
–
–
3D 成像显微镜
自适应照明
增强现实和信息覆盖
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS025
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
目录
8.3 Feature Description................................................. 26
8.4 Device Functional Modes........................................ 32
8.5 Window Characteristics and Optics ....................... 34
8.6 Micromirror Array Temperature Calculation............ 35
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
(说明 (续))....................................................... 4
Pin Configuration and Functions......................... 4
Specifications....................................................... 13
7.1 Absolute Maximum Ratings .................................... 13
7.2 Storage Conditions.................................................. 13
7.3 ESD Ratings............................................................ 13
7.4 Recommended Operating Conditions..................... 14
7.5 Thermal Information................................................ 15
7.6 Electrical Characteristics......................................... 15
7.7 LVDS Timing Requirements ................................... 17
7.8 LVDS Waveform Requirements.............................. 18
7.9 Serial Control Bus Timing Requirements................ 19
7.10 Systems Mounting Interface Loads....................... 20
7.11 Micromirror Array Physical Characteristics........... 21
7.12 Micromirror Array Optical Characteristics ............. 22
7.13 Window Characteristics......................................... 23
7.14 Chipset Component Usage Specification ............. 23
Detailed Description ............................................ 23
8.1 Overview ................................................................. 23
8.2 Functional Block Diagram ....................................... 24
8.7 Micromirror Landed-On and Landed-Off Duty
Cycle ........................................................................ 38
9
Application and Implementation ........................ 40
9.1 Application Information............................................ 40
9.2 Typical Application ................................................. 41
10 Power Supply Recommendations ..................... 43
10.1 Power-Up Sequence (Handled by the DLPC410) 43
10.2 DMD Power-Up and Power-Down Procedures..... 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 46
12 器件和文档支持 ..................................................... 47
12.1 器件支持 ............................................................... 47
12.2 文档支持................................................................ 48
12.3 相关链接................................................................ 48
12.4 接收文档更新通知 ................................................. 48
12.5 社区资源................................................................ 48
12.6 商标....................................................................... 48
12.7 静电放电警告......................................................... 48
12.8 术语表 ................................................................... 48
13 机械、封装和可订购信息....................................... 48
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision D (March 2017) to Revision E
Page
•
•
•
•
•
•
已更改 窗透射率 .................................................................................................................................................................... 1
已更改 微镜反射率 ................................................................................................................................................................. 1
已更改 阵列衍射效率 ............................................................................................................................................................. 1
已更改 阵列填充因子 .............................................................................................................................................................. 1
已更改 高速图形速率 .............................................................................................................................................................. 1
Changed Recommended Operating Conditions table; split Environmental into 3 wavelength regions; simplified and
reorganized the table footnotes............................................................................................................................................ 14
•
•
•
•
•
•
•
•
•
•
•
Changed Thermal Metric text ............................................................................................................................................... 15
Changed Micromirror array optical efficiency ...................................................................................................................... 22
Changed Micromirror array fill factor ................................................................................................................................... 22
Changed Micromirror array diffraction efficiency ................................................................................................................. 22
Changed Micromirror surface reflectivity ............................................................................................................................. 22
Changed Window transmission ........................................................................................................................................... 22
Changed Window transmittance, Minimum ......................................................................................................................... 23
Changed Window transmittance, Average .......................................................................................................................... 23
Changed Micromirror Array Temperature Calculation to indicate that it is based on lumens.............................................. 36
Added Micromirror Array Temperature Calculation based on power ................................................................................... 37
已添加 接收文档更新通知 部分............................................................................................................................................. 48
2
版权 © 2012–2018, Texas Instruments Incorporated
DLP9500
www.ti.com.cn
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
Changes from Revision C (September 2015) to Revision D
Page
•
•
•
•
•
Removed '692' from Pin Configurations image ...................................................................................................................... 4
Added RH name for relative humidity in Absolute Maximum Ratings.................................................................................. 13
Clarified TGRADIENT footnote in Absolute Maximum Ratings.................................................................................................. 13
Changed Tstg to TDMD in Storage Conditions to conform to current nomenclature............................................................... 13
Changed typical micromirror crossover time to the time required to transition from mirror position to the other in
Micromirror Array Optical Characteristics............................................................................................................................. 22
•
•
•
Added typical micromirror switching time - 13 µs in Micromirror Array Optical Characteristics .......................................... 22
Changed "Micromirror switching time" to "Array switching time" for clarity in Micromirror Array Optical Characteristics.... 22
Added clarification to Micromirror switching time at 400 MHz with global reset in Micromirror Array Optical
Characteristics...................................................................................................................................................................... 22
•
•
更新了图 20 和图 21............................................................................................................................................................. 47
已添加 相关链接 表............................................................................................................................................................... 48
Changes from Revision B (July 2013) to Revision C
Page
•
添加了 ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、布局 部分、器件和文档
支持 部分以及机械、封装和可订购信息 部分 ......................................................................................................................... 1
在 特性 和 说明 部分进行了少量措辞更改 .............................................................................................................................. 1
Changed the name of Micromirror clocking pulse reset in Pin Functions ............................................................................ 11
Changed ESD Ratings table to match new standard........................................................................................................... 13
Added Max Recommended DMD Temperature – Derating Curve....................................................................................... 15
Moved Max Recommended DMD Temperature – Derating Curve to ................................................................................. 15
Replaced Figure 4. ............................................................................................................................................................... 19
Changed units from lbs to N................................................................................................................................................. 20
Added explanation for the15 MBRST lines to the DLP9500 from each DLPA200............................................................... 26
Changed Thermal Test Point Location graphic.................................................................................................................... 35
Added program interface to system interface list in Design Requirements.......................................................................... 42
Corrected number of banks of DMD mirrors to 15 in Device Description ............................................................................ 42
删除了 DLP Discovery 4100 芯片组数据表的链接................................................................................................................ 48
添加了 社区资源 部分 ........................................................................................................................................................... 48
•
•
•
•
•
•
•
•
•
•
•
•
•
Changes from Revision A (September 2012) to Revision B
Page
•
•
已添加 DLPR4101 增强型 PROM 至芯片组列表中的 DLPR410 ............................................................................................ 1
已添加 DLPR4101 增强型 PROM 至相关文档中的 DLPR410.............................................................................................. 48
Changes from Original (August 2012) to Revision A
Page
•
将器件状态从“产品预览”更改成了“生产” ................................................................................................................................. 1
版权 © 2012–2018, Texas Instruments Incorporated
3
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
5 (说明 (续))
电子方面,DLP9500 由 1 位 CMOS 存储器单元的两维阵列组成,其组织结构为 1920 存储器单元列乘以 1080 存
储器单元行的栅格。CMOS 存储器阵列通过四条 16 位低压差分信令 (LVDS) 双倍数据速率 (DDR) 总线逐行进行寻
址。寻址通过串行控制总线处理。特定的 CMOS 存储器访问协议由 DLPC410 数字控制器处理。
6 Pin Configuration and Functions
FLN Type A Package
355-Pin LCCC
Bottom View
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
A
C
E
G
J
B
D
F
H
K
M
P
T
L
N
R
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
4
Copyright © 2012–2018, Texas Instruments Incorporated
DLP9500
www.ti.com.cn
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
Pin Functions
(1)
PIN
TYPE
(I/O/P)
DATA
INTERNAL
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
RATE
TERM
NAME
NO.
DATA BUS A
Differentially
terminated – 100 Ω
D_AN(0)
D_AN(1)
D_AN(2)
D_AN(3)
D_AN(4)
D_AN(5)
D_AN(6)
D_AN(7)
D_AN(8)
D_AN(9)
D_AN(10)
D_AN(11)
D_AN(12)
D_AN(13)
D_AN(14)
D_AN(15)
D_AP(0)
D_AP(1)
D_AP(2)
D_AP(3)
D_AP(4)
D_AP(5)
D_AP(6)
D_AP(7)
D_AP(8)
D_AP(9)
D_AP(10)
F2
H8
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
512.01
158.79
471.24
159.33
585.41
551.17
229.41
300.54
346.35
782.27
451.52
74.39
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
E5
Differentially
terminated – 100 Ω
G9
Differentially
terminated – 100 Ω
D2
Differentially
terminated – 100 Ω
G3
Differentially
terminated – 100 Ω
E11
F8
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
C9
Differentially
terminated – 100 Ω
H2
Differentially
terminated – 100 Ω
B10
G15
D14
F14
C17
H16
F4
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
194.26
148.29
244.9
Input data bus A
(2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
73.39
Differentially
terminated – 100 Ω
509.63
152.59
464.09
152.39
591.39
532.16
230.78
300.61
338.16
773.17
449.57
Differentially
terminated – 100 Ω
H10
E3
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
G11
D4
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
G5
Differentially
terminated – 100 Ω
E9
Differentially
terminated – 100 Ω
F10
C11
H4
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
B8
(1) The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.
(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships.
(3) Refer to Electrical Characteristics for differential termination specification.
Copyright © 2012–2018, Texas Instruments Incorporated
5
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions (continued)
(1)
PIN
TYPE
(I/O/P)
DATA
RATE
INTERNAL
TERM
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
NAME
NO.
Differentially
terminated – 100 Ω
D_AP(11)
H14
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DCLK_A
DCLK_A
DCLK_A
DCLK_A
DCLK_A
71.7
Differentially
terminated – 100 Ω
D_AP(12)
D_AP(13)
D_AP(14)
D16
F16
C15
G17
DDR
DDR
DDR
DDR
198.69
143.72
240.14
74.05
Input data bus A
(2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
D_AP(15)
DATA BUS B
D_BN(0)
Differentially
terminated – 100 Ω
AH2
AD8
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
525.25
190.59
525.25
494.91
222.67
205.45
309.05
285.62
483.58
711.58
462.21
74.39
Differentially
terminated – 100 Ω
D_BN(1)
D_BN(2)
D_BN(3)
D_BN(4)
D_BN(5)
D_BN(6)
D_BN(7)
D_BN(8)
D_BN(9)
D_BN(10)
D_BN(11)
D_BN(12)
D_BN(13)
D_BN(14)
D_BN(15)
D_BP(0)
D_BP(1)
D_BP(2)
D_BP(3)
D_BP(4)
D_BP(5)
D_BP(6)
D_BP(7)
D_BP(8)
Differentially
terminated – 100 Ω
AJ5
Differentially
terminated – 100 Ω
AE3
Differentially
terminated – 100 Ω
AG9
AE11
AH10
AF10
AK8
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
AG5
AL11
AE15
AH14
AF14
AJ17
AD16
AH4
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Input data bus B
(2x LVDS)
Differentially
terminated – 100 Ω
194.26
156
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
247.9
Differentially
terminated – 100 Ω
111.52
525.02
190.61
524.22
476.07
222.8
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
AD10
AJ3
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
AE5
Differentially
terminated – 100 Ω
AG11
AE9
Differentially
terminated – 100 Ω
219.48
306.55
298.04
480.31
Differentially
terminated – 100 Ω
AH8
Differentially
terminated – 100 Ω
AF8
Differentially
terminated – 100 Ω
AK10
6
Copyright © 2012–2018, Texas Instruments Incorporated
DLP9500
www.ti.com.cn
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
Pin Functions (continued)
(1)
PIN
TYPE
(I/O/P)
DATA
RATE
INTERNAL
TERM
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
NAME
NO.
Differentially
terminated – 100 Ω
D_BP(9)
AG3
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
DCLK_B
727.18
Differentially
terminated – 100 Ω
D_BP(10)
D_BP(11)
D_BP(12)
D_BP(13)
D_BP(14)
AL9
DDR
DDR
DDR
DDR
DDR
DDR
461.02
71.35
Differentially
terminated – 100 Ω
AD14
AH16
AF16
AJ15
AE17
Input data bus B
(2x LVDS)
Differentially
terminated – 100 Ω
197.69
150.38
243.14
113.36
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
D_BP(15)
DATA BUS C
D_CN(0)
Differentially
terminated – 100 Ω
B14
E15
A17
G21
B20
F20
D22
G23
B26
F28
C29
G27
D26
H28
E29
J29
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
459.04
342.79
456.22
68.24
Differentially
terminated – 100 Ω
D_CN(1)
D_CN(2)
D_CN(3)
D_CN(4)
D_CN(5)
D_CN(6)
D_CN(7)
D_CN(8)
D_CN(9)
D_CN(10)
D_CN(11)
D_CN(12)
D_CN(13)
D_CN(14)
D_CN(15)
D_CP(0)
D_CP(1)
D_CP(2)
D_CP(3)
D_CP(4)
D_CP(5)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
362.61
163.07
204.16
105.59
450.51
302.04
429.8
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Input data bus C
(2x LVDS)
Differentially
terminated – 100 Ω
317.1
Differentially
terminated – 100 Ω
276.76
186.78
311.3
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
262.62
463.64
347.65
456.45
67.72
Differentially
terminated – 100 Ω
B16
E17
A15
H20
B22
F22
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
362.76
161.69
Differentially
terminated – 100 Ω
Copyright © 2012–2018, Texas Instruments Incorporated
7
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions (continued)
(1)
PIN
TYPE
(I/O/P)
DATA
RATE
INTERNAL
TERM
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
NAME
NO.
Differentially
terminated – 100 Ω
D_CP(6)
D20
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
DCLK_C
195.09
104.86
451.41
294.22
429.68
314.98
276.04
186.25
312.07
262.94
Differentially
terminated – 100 Ω
D_CP(7)
D_CP(8)
D_CP(9)
D_CP(10)
D_CP(11)
D_CP(12)
D_CP(13)
D_CP(14)
H22
B28
F26
C27
G29
D28
H26
E27
J27
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Input data bus C
(2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
D_CP(15)
DATA BUS D
D_DN(0)
Differentially
terminated – 100 Ω
AK14
AG15
AL17
AE21
AK20
AF20
AH22
AE23
AK26
AF28
AJ29
AE27
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
492.53
342.78
491.83
74.24
Differentially
terminated – 100 Ω
D_DN(1)
D_DN(2)
D_DN(3)
D_DN(4)
D_DN(5)
D_DN(6)
D_DN(7)
D_DN(8)
D_DN(9)
D_DN(10)
D_DN(11)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
356.23
163.07
204.16
105.59
450.51
302.04
429.8
Differentially
terminated – 100 Ω
Input data bus D
(2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
298.87
8
Copyright © 2012–2018, Texas Instruments Incorporated
DLP9500
www.ti.com.cn
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
Pin Functions (continued)
(1)
PIN
TYPE
(I/O/P)
DATA
RATE
INTERNAL
TERM
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
NAME
NO.
Differentially
terminated – 100 Ω
D_DN(12)
AH26
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
DCLK_D
276.76
Differentially
terminated – 100 Ω
D_DN(13)
D_DN(14)
D_DN(15)
D_DP(0)
D_DP(1)
D_DP(2)
D_DP(3)
D_DP(4)
D_DP(5)
D_DP(6)
D_DP(7)
D_DP(8)
D_DP(9)
D_DP(10)
D_DP(11)
D_DP(12)
D_DP(13)
D_DP(14)
D_DP(15)
AD28
AG29
AC29
AK16
AG17
AL15
AD20
AK22
AF22
AH20
AD22
AK28
AF26
AJ27
AE29
AH28
AD26
AG27
AC27
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
186.78
311.3
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
262.62
495.13
342.47
492.06
67.72
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
356.37
161.98
195.09
102.86
451.41
296.7
Differentially
terminated – 100 Ω
Input data bus D
(2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
429.68
302.74
276.04
186.25
312.07
262.94
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Copyright © 2012–2018, Texas Instruments Incorporated
9
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions (continued)
(1)
PIN
TYPE
(I/O/P)
DATA
RATE
INTERNAL
TERM
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
NAME
NO.
DATA CLOCKS
Differentially
terminated – 100 Ω
DCLK_AN
DCLK_AP
DCLK_BN
DCLK_BP
DCLK_CN
DCLK_CP
DCLK_DN
D10
D8
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
325.8
319.9
Input data bus A
Clock (2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
AJ11
AJ9
318.92
318.74
252.01
241.18
252.01
241.18
Input data bus B
Clock (2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
C23
C21
AJ23
AJ21
Input data bus C
Clock (2x LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Input data bus D
Clock (2x LVDS)
Differentially
terminated – 100 Ω
DCLK_DP
DATA CONTROL INPUTS
SCTRL_AN
Differentially
terminated – 100 Ω
J3
J5
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DCLK_A
DCLK_A
DCLK_B
DCLK_B
DCLK_C
DCLK_C
DCLK_D
DCLK_D
608.14
607.45
698.12
703.8
Serial control for
data bus A (2x
LVDS)
Differentially
terminated – 100 Ω
SCTRL_AP
SCTRL_BN
SCTRL_BP
SCTRL_CN
SCTRL_CP
SCTRL_DN
SCTRL_DP
Differentially
terminated – 100 Ω
AF4
AF2
E23
E21
AG23
AG21
Serial control for
data bus B (2x
LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
232.46
235.21
235.53
235.66
Serial control for
data bus C (2x
LVDS)
Differentially
terminated – 100 Ω
Differentially
terminated – 100 Ω
Serial control for
data bus D (2x
LVDS)
Differentially
terminated – 100 Ω
SERIAL COMMUNICATION AND CONFIGURATION
SCPCLK
SCPDO
SCPDI
AE1
AC3
AD2
AD4
B4
Input
Output
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
—
—
—
—
—
—
—
pull-down
—
—
SCP_CLK
SCP_CLK
SCP_CLK
—
Serial port clock
Serial port output
Serial port input
Serial port enable
Device reset
324.26
281.38
261.55
184.86
458.78
471.57
521.99
pull-down
pull-down
pull-down
pull-down
pull-down
SCPEN
PWRDN
MODE_A
MODE_B
J1
—
Data bandwidth
mode select
G1
—
10
Copyright © 2012–2018, Texas Instruments Incorporated
DLP9500
www.ti.com.cn
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
Pin Functions (continued)
(1)
PIN
TYPE
(I/O/P)
DATA
RATE
INTERNAL
TERM
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
NAME
NO.
MICROMIRROR CLOCKING PULSE (BIAS RESET)
MBRST(0)
MBRST(1)
MBRST(2)
MBRST(3)
MBRST(4)
MBRST(5)
MBRST(6)
MBRST(7)
MBRST(8)
MBRST(9)
MBRST(10)
MBRST(11)
MBRST(12)
MBRST(13)
MBRST(14)
MBRST(15)
MBRST(16)
MBRST(17)
MBRST(18)
MBRST(19)
MBRST(20)
MBRST(21)
MBRST(22)
MBRST(23)
MBRST(24)
MBRST(25)
MBRST(26)
MBRST(27)
MBRST(28)
MBRST(29)
POWER
L5
M28
P4
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
898.97
621.98
846.88
784.18
763.34
749.61
878.25
783.83
969.36
621.24
918.43
685.14
812.31
591.89
878.5
P30
L3
P28
P2
T28
M4
L29
T4
N29
N3
Micromirror clocking
pulse reset MBRST
signals clock
micromirrors into
state of LVCMOS
memory cell
L27
R3
V28
V4
660.15
848.64
796.31
715
associated with each
mirror.
R29
Y4
AA27
W3
W27
AA3
W29
U5
604.35
832.39
675.21
861.18
662.66
850.06
726.56
861.48
683.83
878.5
U29
Y2
AA29
U3
Y30
789.2
A3, A5, A7, A9,
A11, A13, A21,
A23, A25, A27,
A29, B2,
C1, C31, E31,
G31, J31, K2,
L31, N31, R31,
U31, W31,
Power for LVCMOS
logic
VCC
Power
Analog
—
—
—
—
AA31, AC1,
AC31, AE31,
AG1, AG31,
AJ31, AK2,
AK30, AL3, AL5,
AL7, AL19, AL21,
AL23, AL25,
AL27
H6, H12, H18,
H24, M6, M26,
P6, P26, T6, T26,
V6, V26,
Power supply for
LVDS Interface
VCCI
Power
Analog
—
—
—
—
Y6, Y26, AD6,
AD12, AD18,
AD24
Copyright © 2012–2018, Texas Instruments Incorporated
11
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions (continued)
(1)
PIN
TYPE
(I/O/P)
DATA
RATE
INTERNAL
TERM
TRACE
(MILS)
SIGNAL
CLOCK
DESCRIPTION
(2)
(3)
NAME
NO.
L1, N1, R1, U1,
W1, AA1
Power for high
voltage CMOS logic
VCC2
Power
Analog
—
—
—
—
A1, B12, B18,
B24, B30, C7,
C13, C19, C25,
D6, D12,
D18, D24, D30,
E1, E7, E13, E19,
E25, F6, F12,
F18, F24,
F30, G7, G13,
G19, G25, K4,
K6, K26, K28,
K30, M2, M30,
N5, N27, R5, T2,
T30, U27, V2,
V30, W5, Y28,
AB2, AB4,
Common return for
all power inputs
VSS
Power
Analog
—
—
—
—
AB6, AB26,
AB28, AB30,
AD30, AE7,
AE13, AE19,
AE25, AF6,
AF12, AF18,
AF24, AF30,
AG7, AG13,
AG19, AG25,
AH6, AH12,
AH18, AH24,
AH30, AJ1,
AJ7, AJ13, AJ19,
AJ25, AK6, AK12,
AK18, AL29
RESERVED SIGNALS (NOT FOR USE IN SYSTEM)
RESERVED_FC
RESERVED_FD
RESERVED_PFE
RESERVED_STM
RESERVED_AE
J7
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
—
—
—
—
—
pull-down
—
—
—
—
—
—
—
—
—
—
J9
pull-down
pull-down
pull-down
pull-down
Pins should be
connected to VSS
J11
AC7
C3
A19, B6, C5,
H30, J13, J15,
J17, J19, J21,
J23, J25, R27,
No connection (any
connection to these
terminals may result
in undesirable
AA5, AC11,
AC13, AC15,
AC17, AC19,
AC21, AC23,
NO_CONNECT
—
—
—
—
—
—
effects)
AC25, AC5, AC9,
AK24, AK4, AL13
12
Copyright © 2012–2018, Texas Instruments Incorporated
DLP9500
www.ti.com.cn
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted).
(1)
MIN
MAX
UNIT
ELECTRICAL
(2) (3)
VCC
Voltage applied to VCC
Voltage applied to VCCI
–0.5
–0.5
–0.5
4
4
9
V
V
V
(2) (3)
VCCI
VCC2
(2) (3) (4)
Voltage applied to VVCC2
Clocking pulse waveform voltage applied to MBRST[29:0] input pins (supplied
by DLPA200s)
VMBRST
–28
28
V
(4)
|VCC – VCCI
|
Supply voltage delta (absolute value)
0.3
V
V
(2)
Voltage applied to all other input terminals
–0.5
VCC + 0.3
Maximum differential voltage, damage can occur to internal termination resistor
if exceeded, see Figure 3
|VID
|
700
mV
Current required from a high-level output, VOH = 2.4 V
Current required from a low-level output, VOL = 0.4 V
–20
15
mA
mA
ENVIRONMENTAL
(5)
Array temperature – operational
20
70
80
°C
°C
TARRAY
(5)
Array temperature – non-operational
–40
Absolute temperature delta between the window test points (TP2, TP3) and the
ceramic test point TP1
TDELTA
RH
10
95
°C
%
(6)
Relative humidity (non-condensing)
(1) Stresses beyond those listed under may cause permanent damage to the device. These are stress ratings only, which do not imply
functional operation of the device at these or any other conditions beyond those indicated under . Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS (ground).
(3) Voltages VCC, VCCI, and VCC2 are required for proper DMD operation.
(4) Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw. The
difference between VCC and VCCI, |VCC – VCCI|, should be less than the specified limit.
(5) The worst-case temperature of any test point shown in Figure 17, or the active array as calculated by the Micromirror Array Temperature
Calculation - Lumens Based.
(6) As either measured, predicted, or both between any two points - measured on the exterior of the package, or as predicted at any point
inside the micromirror array cavity. Refer to Micromirror Array Temperature Calculation - Lumens Based.
7.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system
MIN
MAX
80
UNIT
°C
TDMD
RH
Storage temperature
–40
Storage humidity (non-condensing)
95
%
7.3 ESD Ratings
VALUE
±2000
±250
UNIT
All pins except
MBRST[29:0]
Electrostatic
VESD
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V
discharge
MBRST[29:0] pins
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
Copyright © 2012–2018, Texas Instruments Incorporated
13
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
(2) (3)
ELECTRICAL
VCC
Supply voltage for LVCMOS core logic
Supply voltage for LVDS receivers
3.0
3.0
3.3
3.3
8.5
3.6
3.6
V
V
V
VCC1
VCC2
Mirror electrode and HVCMOS supply voltage
8.25
8.75
Clocking Pulse Waveform Voltage applied to MBRST[29:0] Input Pins (supplied by
DLPA200s)
VMBRST
-27
26.5
0.3
V
V
(4)
|VCCI–VCC|
Supply voltage delta (absolute value)
ENVIRONMENTAL (5) For Illumination Source Between 420 nm and 700 nm
(6)(7) (8)(9)
(10)
Array temperature, Long–term operational
20
0
25-45
65
TARRAY
°C
(6)(7) (11)
Array temperature, Short–term operational
20
TWINDOW
|TDELTA
ILLVIS
Window temperature test points TP2 and TP3, Long-term operational(9)
.
10
70
10
°C
°C
Absolute temperature delta between the window test points (TP2, TP3) and the
ceramic test point TP1.(12)
|
Thermally
limited
Illumination(13)
W/cm2
ENVIRONMENTAL (5) For Illumination Source Between 400 nm and 420 nm
(6)(7) (8)(9)
TARRAY
Array temperature, Long–term operational
20
30
30
°C
°C
TWINDOW
Window temperature test points TP2 and TP3, Long-term operational(9)
Absolute temperature delta between the window test points (TP2, TP3) and the
ceramic test point TP1.(12)
|TDELTA
|
10
°C
W/cm2
W
11
ILL
Illumination(13)
26.6
ENVIRONMENTAL (5) For Illumination Source <400 nm and >700 nm
(6)(7) (8)(9)
(10)
Array temperature, Long–term operational
20
0
40
TARRAY
°C
(6)(7) (11)
Array temperature, Short–term operational
20
70
10
TWINDOW
ILL
Window temperature test points TP2 and TP3, Long-term operational(9)
Illumination(13)
10
°C
mW/cm2
(1) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
(2) Voltages VCC, VCC1, and VCC2 are required for proper DMD operation. VSS must also be connected.
(3) All voltages are referenced to common ground VSS
.
(4) Exceeding the recommended allowable absolute voltage difference between VCC and VCC1 may result in excess current draw. The
difference between VCC and VCC1, |VCC – VCC1|, should be less than the specified limit.
(5) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application
parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage
and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that
application-specific effects be considered as early as possible in the design cycle.
(6) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See Micromirror Array
Temperature Calculation for further details.
(7) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 17 and the package thermal resistance in Thermal Information using Micromirror Array Temperature Calculation.
(8) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will
reduce device lifetime.
(9) Long-term is defined as the usable life of the device.
(10) Per Figure 1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to Micromirror Landed-On and Landed-Off Duty Cycle for a definition of micromirror landed
duty cycle.
(11) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is
defined as cumulative time over the usable life of the device and is less than 500 hours.
(12) The temperature delta is the highest difference between the ceramic test point (TP1) and window test points (TP2) and (TP3) in
Figure 17.
(13) Total integrated illumination power density on the array in the indicated wavelength range.
14
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Figure 1. Max Recommended DMD Temperature – Derating Curve
7.5 Thermal Information
DLP9500
THERMAL METRIC
FLN (Package)
355 PINS
0.5
UNIT
(1)
Thermal resistance, active area to test point 1 (TP1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the Recommended Operating
Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other
contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should
be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can
significantly degrade the reliability of the device.
7.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
High-level output voltage
See Figure 11
,
VOH
VCC = 3 V, IOH = –20 mA
2.4
V
(1) Applies to LVCMOS pins only.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
Low-level output voltage
See Figure 11
,
VOL
VCC = 3.6 V, IOH = 15 mA
0.4
V
Clocking pulse waveform applied to
VMBRST MBRST[29:0] input pins (supplied by
–27
26.5
V
DLPA200s)
(1)
IOZ
IOH
IOL
High-impedance output current
VCC = 3.6 V
10
–20
–15
15
µA
VOH = 2.4 V, VCC ≥ 3 V
VOH = 1.7 V, VCC ≥ 2.25 V
VOL = 0.4 V, VCC ≥ 3 V
VOL = 0.4 V, VCC ≥ 2.25 V
(1)
High-level output current
mA
(1)
Low-level output current
mA
V
14
VCC
+
(1)
VIH
High-level input voltage
1.7
0.3
(1)
VIL
IIL
Low-level input voltage
–0.3
0.7
–60
60
V
µA
µA
mA
mA
mA
W
(1)
Low-level input current
VCC = 3.6 V, VI = 0 V
VCC = 3.6 V, VI = VCC
VCC = 3.6 V,
(1)
IIH
High-level input current
ICC
ICCI
ICC2
PD
Current into VCC pin
2990
910
25
(2)
Current into VOFFSET pin
VCCI = 3.6 V
Current into VCC2 pin
VCC2 = 8.75 V
Power dissipation
4.4
ZIN
ZLINE
CI
Internal differential impedance
Line differential impedance (PWB, trace)
95
90
105
110
10
Ω
100
Ω
(1)
Input capacitance
ƒ = 1 MHz
ƒ = 1 MHz
ƒ = 1 MHz
pF
pF
pF
(1)
CO
CIM
Output capacitance
10
Input capacitance for MBRST[29:0] pins
270
355
(2) Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw (See Absolute
Maximum Ratings for details).
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7.7 LVDS Timing Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 2
MIN
200
2.5
NOM
MAX
UNIT
MHz
ns
ƒDCLK_x
DCLK_x clock frequency (where x = [A, B, C, or D])
Clock cycle - DLCK_x
400
tc
tw
Pulse duration - DLCK_x
1.25
ns
ts
Setup time - D_x[15:0] and SCTRL_x before DCLK_x
Hold time, D_x[15:0] and SCTRL_x after DCLK_x
Skew between any two buses (A ,B, C, and D)
0.35
0.35
ns
th
ns
tskew
–1.25
1.25
ns
DCLK_AN
DCLK_AP
t
t
s
h
t
c
t
t
s
h
SCTRL_AN
SCTRL_AP
D_AN(15:0)
D_AP(15:0)
DCLK_BN
DCLK_BP
t
t
s
h
t
c
t
t
s
h
SCTRL_BN
SCTRL_BP
D_BN(15:0)
D_BP(15:0)
DCLK_CN
DCLK_CP
t
t
s
h
t
c
t
t
s
h
SCTRL_CN
SCTRL_CP
D_CN(15:0)
D_CP(15:0)
DCLK_DN
DCLK_DP
t
t
s
h
t
c
t
t
s
h
SCTRL_DN
SCTRL_DP
D_DN(15:0)
D_DP(15:0)
Figure 2. LVDS Timing Waveforms
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7.8 LVDS Waveform Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 3
MIN
NOM
400
MAX
UNIT
mV
mV
mV
ps
|VID
|
Input differential voltage (absolute difference)
Common mode voltage
100
600
VCM
1200
VLVDS
LVDS voltage
0
100
100
2000
400
tr
tr
Rise time (20% to 80%)
Fall time (80% to 20%)
400
ps
VLVDS max = VCM max + | 1/2 × VID max
|
tf
VID
VCM
tr
VLVDS min = VCM min | 1/2 × VID max
|
Figure 3. LVDS Waveform Requirements
18
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7.9 Serial Control Bus Timing Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 4 and Figure 5
MIN
NOM
MAX
500
300
960
UNIT
kHz
ns
ƒSCP_CLK
tSCP_SKEW
tSCP_DELAY
t SCP_EN
t_SCP
SCP clock frequency
50
Time between valid SCP_DI and rising edge of SCP_CLK
Time between valid SCP_DO and rising edge of SCP_CLK
Time between falling edge of SCP_EN and the first rising edge of SCP_CLK
Rise time for SCP signals
–300
ns
30
ns
200
200
ns
tƒ_SCP
Fall time for SCP signals
ns
t
f
= 1 / t
clock c
c
SCPCLK
50%
50%
tSCP_SKEW
SCPDI
50%
tSCP_DELAY
SCPD0
50%
Figure 4. Serial Communications Bus Timing Parameters
tf_SCP
tr_SCP
Input Controller VCC
SCP_CLK,
SCP_DI,
SCP_EN
VCC/2
0 v
Figure 5. Serial Communications Bus Waveform Requirements
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MAX UNIT
7.10 Systems Mounting Interface Loads
PARAMETER
MIN
NOM
Thermal interface area (see Figure 6)
156
1334
712
N
N
N
Maximum system mounting interface
load to be applied to the:
Electrical interface area (see Figure 6)
Datum A Interface area (see Figure 6)
Thermal Interface
Area
Electrical Interface
Area
Other Area
Datum ‘A’ Areas
Figure 6. System Interface Loads
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7.11 Micromirror Array Physical Characteristics
See 机械、封装和可订购信息 for additional details.
VALUE
1920
1080
10.8
UNIT
micromirrors
micromirrors
µm
(1)
M
N
P
Number of active micromirror columns
(1)
Number of active micromirror rows
(1)
Micromirror (pixel) pitch
(1)
Micromirror active array width
M × P
20.736
11.664
10
mm
(1)
Micromirror active array height
N × P
mm
(1) (2)
Micromirror array border
Pond of micromirrors (POM)
micromirrors/side
(1) See Figure 7.
(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
0
1
2
3
DMD Active Array
N x P
M x N Micromirrors
N œ 4
N œ 3
N œ 2
N œ 1
M x P
P
Border micromirrors omitted for clarity.
Details omitted for clarity.
P
Not to scale.
P
P
Refer to the Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 7. Micromirror Array Physical Characteristics
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7.12 Micromirror Array Optical Characteristics
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical
performance involves making trade-offs between numerous component and system design parameters. See the related
application reports (listed in 相关文档) for guidelines.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1) (2) (3)
DMD parked state
,
0
See Figure 12
a
Micromirror tilt angle
degrees
(1) (4) (5)
DMD landed state
See Figure 12
12
(1) (4) (6) (7) (8)
β
Micromirror tilt angle variation
See Figure 12
–1
56
44
1
degrees
µs
(9)
Micromirror crossover time
3
(10)
Micromirror switching time
13
22
µs
(11)
Array switching time at 400 MHz with global reset
µs
Non-adjacent micromirrors
Adjacent micromirrors
See Figure 12
10
0
(12)
Non-operating micromirrors
micromirrors
degrees
(13)
Orientation of the micromirror axis-of-rotation
45
46
400 to 700 nm, with all
micromirrors in the ON state
(14) (15)
Micromirror array optical efficiency
70%
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by
the overall micromirror array).
(3) When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.
(4) Additional variation exists between the micromirror array and the package datums, as shown in 机械、封装和可订购信息.
(5) When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS
memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in an nominal angular
position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.
(6) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations and/or system contrast variation.
(9) Micromirror crossover time is the transition time from landed to landed during a crossover transition and primarily a function of the
natural response time of the micromirrors.
(10) Micromirror switching time is the time after a micromirror clocking pulse until the micromirrors can be addressed again. It included the
micromirror settling time.
(11) Array switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal switching time depends
on the system implementation and represents the time for the entire micromirror array to be refreshed (array loaded plus reset and
mirror settling time).
(12) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.
(13) Measured relative to the package datums 'B' and 'C', shown in the 机械、封装和可订购信息.
(14) The minimum or maximum DMD optical efficiency observed in a specific application depends on numerous application-specific design
variables, such as:
(a) Illumination wavelength, bandwidth/line-width, degree of coherence
(b) Illumination angle, plus angle tolerance
(c) Illumination and projection aperture size, and location in the system optical path
(d) Illumination overfill of the DMD micromirror array
(e) Aberrations present in the illumination source and/or path
(f) Aberrations present in the projection path
The specified nominal DMD optical efficiency is based on the following use conditions:
(a) Visible illumination (400 to 700 nm)
(b) Input illumination optical axis oriented at 24° relative to the window normal
(c) Projection optical axis oriented at 0° relative to the window normal
(d) ƒ / 3 illumination aperture
(e) ƒ / 2.4 projection aperture
Based on these use conditions, the nominal DMD optical efficiency results from the following four components:
(a) Micromirror array fill factor: nominally 94%
(b) Micromirror array diffraction efficiency: nominally 87%
(c) Micromirror surface reflectivity: nominally 89%
(d) Window transmission: nominally 96% (single pass, through two surface transitions)
(15) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle
represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection
path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.
22
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7.13 Window Characteristics
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Window material designation
Window refractive index
Corning 7056
At wavelength 589 nm
1.487
(2)
Window flatness
Per 25 mm
4
fringes
µm
(3)
Window artifact size
Window aperture
Illumination overfill
Within the Window Aperture
400
(4)
See
Refer to Illumination Overfill
At wavelength 405 nm. Applies to 0° and 24° AOI only.
95%
96%
Minimum within the wavelength range 420 nm to 680 nm.
Applies to all angles 0° to 30° AOI.
Window transmittance, single–pass
(5)
through both surfaces and glass
Average over the wavelength range 420 nm to 680 nm.
Applies to all angles 30° to 45° AOI.
96%
(1) See Window Characteristics and Optics for more information.
(2) At a wavelength of 632.8 nm.
(3) See the 机械、封装和可订购信息 section at the end of this document for details regarding the size and location of the window aperture.
(4) For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical
ICD in the Mechanical, Packaging, and Orderable Information section.
(5) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP DMD Window.
7.14 Chipset Component Usage Specification
The DLP9500 is a component of one or more DLP chipsets. Reliable function and operation of the DLP9500
requires that it be used in conjunction with the other components of the applicable DLP chipset, including those
components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP DMD.
8 Detailed Description
8.1 Overview
Optically, the DLP9500 consists of 2,073,600 highly reflective, digitally switchable, micrometer-sized mirrors
(micromirrors), organized in a two-dimensional array of 1920 micromirror columns by 1080 micromirror rows ().
Each aluminum micromirror is approximately 10.8 microns in size (see the Micromirror Pitch in ) and is
switchable between two discrete angular positions: –12° and 12°. The angular positions are measured relative to
a 0° flat state, which is parallel to the array plane (see Figure 12). The tilt direction is perpendicular to the hinge-
axis, which is positioned diagonally relative to the overall array. The On State landed position is directed toward
row 0, column 0 (upper left) corner of the device package (see the Micromirror Hinge-Axis Orientation in ). In the
field of visual displays, the 1920 × 1080 pixel resolution is referred to as 1080p.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual
micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the
CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking
pulse will result in the corresponding micromirror switching to a 12° position. Writing a logic 0 into a memory cell
followed by a mirror clocking pulse will result in the corresponding micromirror switching to a –12° position.
Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the
CMOS memory. Second, application of a micromirror clocking pulse to all or a portion of the micromirror array
(depending upon the configuration of the system). Micromirror clocking pulses are generated externally by two
DLPA200s, with application of the pulses being coordinated by the DLPC410 controller.
Around the perimeter of the 1920 by 1080 array of micromirrors is a uniform band of border micromirrors. The
border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has
been applied to the device. There are 10 border micromirrors on each side of the 1920 by 1080 active array.
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Overview (continued)
Figure 8 shows a DLPC410 and DLP9500 chipset block diagram. The DLPC410 and DLPA200s control and
coordinate the data loading and micromirror switching for reliable DLP9500 operation. The DLPR410 is the
programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset
components, see Application and Implementation. For a typical system application using the DLP Discovery 4100
chipset including a DLP9500, see Figure 18.
8.2 Functional Block Diagram
Figure 8 shows a simplified system block diagram with the use of the DLPC410 with the following chipset
components:
DLPC410
Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control, and DLPA200
timing and control
DLPR410
DLPA200
DLP9500
[XCF16PFSG48C] serial flash PROM contains startup configuration information (EEPROM)
Two DMD micromirror drivers for the DLP9500 DMD
Spatial light modulator (DMD)
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USER INTERFACE
DLPC410
DLP9500
= LVDS Bus
DDC_DCLK_A
DVALID_A
DDC_DCLKOUT_A
DDC_SCTRL_A
DDC_DIN_A(15:0)
DDC_DOUT_A(15:0)
DDC_DCLK_B
DVALID_B
DDC_DCLKOUT_B
DDC_SCTRL_B
DDC_DIN_B(15:0)
DDC_DOUT_B(15:0)
DDC_DCLK_C
DVALID_C
DDC_DCLKOUT_C
DDC_SCTRL_C
DDC_DIN_C(15:0)
DDC_DOUT_C(15:0)
DDC_DCLK_D
DVALID_D
DDC_DCLKOUT_D
DDC_SCTRL_D
DDC_DIN_D(15:0)
DDC_DOUT_D(15:0)
COMP_DATA
NS_FLIP
SCPCLK
SCPDO
STEPVCC
SCPDI
WDT_ENBLZ
PWR_FLOAT
DMD_A_SCPENZ
DMD_B_SCPENZ
A_SCPENZ
ROWMD(1:0)
ROWAD(10:0)
RST2BLKZ
B_SCPENZ
DLPA200
BLKMD(1:0)
BLKAD(10:0)
A_STROBE
A_MODE(1:0)
A_SEL(1:0)
A_ADDR(3:0)
MBRST1_(15:0)
RST_ACTIVE
INIT_ACTIVE
A
ECP2_FINISHED
DMD_TYPE(3:0)
OEZ
INIT
DDC_VERSION(2:0)
DLPR410
PROM_CCK_DDC
PROGB_DDC
PROM_DO_DDC
DONE_DDC
DLPA200
TDI_JTAG
INTB_DDC
B_STROBE
B_MODE(1:0)
B_SEL(1:0)
B_ADDR(3:0)
MBRST2_(15:0)
CS_B_0
B
RDWR_B_0
HSWAPEN_0
TDO_XCF16DDC
TCK_JTAG
TCK_JTAG
TDO_DDC
VLED0
VLED1
DDC_M(2:0)
ECP2_M_TP(31:0)
DDCSPARE(1:0)
ARSTZ
DMD_A_RESET
DMD_B_RESET
CLKIN_R
OSC
50 Mhz
Figure 8. DLPC410, DLPA200, DLPR410, and DLP9500 Functional Block Diagram
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8.3 Feature Description
Table 1. DMD Overview
SINGLE BLOCK
MODE
(Patterns/s)
GLOBAL RESET
MODE
(Patterns/s)
DATA RATE
(Giga Pixels/s)
DMD
ARRAY
MIRROR PITCH
DLP9500 - 0.95" 1080p
1920 × 1080
23148
17857
48
10.8 μm
8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
The DLPC410 chipset includes the DLPC410 controller which provides a high-speed LVDS data and control
interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not
included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in
response to the inputs on the control interface.
For more information, see the DLPC410 data sheet (DLPS024).
8.3.2 DLPA200 - DMD Micromirror Drivers
DLPA200 micromirror drivers provide the micromirror clocking pulse driver functions for the DMD. Two drivers
are required for DLP9500.
The DLPA200 is designed to work with multiple DLP chipsets. Although the DLPA200 contains 16 MBSRT output
pins, only 15 lines are used with the DLP9500 chipset. For more information see and the DLPA200 data sheet
(DLPS015).
8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
The DLPC410 controller is configured at startup from the DLPR410 PROM. The contents of this PROM can not
be altered. For more information, see the DLPR410 data sheet (DLPS027) the DLPC410 data sheet (DLPS024).
8.3.4 DLP9500 - DLP 0.95 1080p 2xLVDS Type-A DMD 1080p DMD
8.3.4.1 DLP9500 1080p Chipset Interfaces
This section will describe the interface between the different components included in the chipset. For more
information on component interfacing, see Application and Implementation.
8.3.4.1.1 DLPC410 Interface Description
8.3.4.1.1.1 DLPC410 IO
Table 2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the
DLPC410 data sheet (DLPS024).
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Table 2. Input/Output Description
PIN NAME
DESCRIPTION
I/O
ARST
Asynchronous active low reset
I
I
I
CLKIN_R
Reference clock, 50 MHz
DIN_[A,B,C,D](15:0)
DCLKIN[A,B,C,D]
DVALID[A,B,C,D]
ROWMD(1:0)
ROWAD(10:0)
BLK_AD(3:0)
BLK_MD(1:0)
PWR_FLOAT
DMD_TYPE(3:0)
RST_ACTIVE
INIT_ACTIVE
VLED0
LVDS DDR input for data bus A,B,C,D (15:0)
LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D
LVDS input used to start write sequence for bus A, B, C, and D
DMD row address and row counter control
DMD row address pointer
I
I
I
I
DMD mirror block address pointer
I
DMD mirror block reset and clear command modes
Used to float DMD mirrors before complete loss of power
DMD type in use
I
I
O
O
O
O
O
Indicates DMD mirror reset in progress
Initialization in progress.
System “heartbeat” signal
VLED1
Denotes initialization complete
8.3.4.1.1.2 Initialization
The INIT_ACTIVE (Table 2) signal indicates that the DLP9500, DLPA200s, and DLPC410 are in an initialization
state after power is applied. During this initialization period, the DLPC410 is initializing the DLP9500 and
DLPA200s by setting all internal registers to their correct states. When this signal goes low, the system has
completed initialization. System initialization takes approximately 220 ms to complete. Data and command write
cycles should not be asserted during the initialization.
During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to
correctly align the data inputs to the data clock. For more information, see the interface training pattern
information in the DLPC410 data sheet.
8.3.4.1.1.3 DMD Device Detection
The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 2) is an output from the
DLPC410 that contains the DMD information.
8.3.4.1.1.4 Power Down
To ensure long term reliability of the DLP9500, a shutdown procedure must be executed. Prior to power removal,
assert the PWR_FLOAT (Table 2) signal and allow approximately 300 µs for the procedure to complete. This
procedure assures the mirrors are in a flat state.
8.3.4.1.2 DLPC410 to DMD Interface
8.3.4.1.2.1 DLPC410 to DMD IO Description
Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 3. DLPC410 to DMD I/O Pin Descriptions
PIN NAME
DDC_DOUT_[A,B,C,D](15:0)
DDC_DCLKOUT_[A,B,C,D]
DDC_SCTRL_[A,B,C,D]
DESCRIPTION
I/O
O
LVDS DDR output to DMD data bus A,B,C,D (15:0)
LVDS output to DMD data clock A,B,C,D
LVDS DDR output to DMD data control A,B,C,D
O
O
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8.3.4.1.2.2 Data Flow
Figure 9 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the
DLPC410 to allow best signal flow.
LVDS BUS D
sDIN_D(15:0)
sDCLK_D
LVDS BUS C
sDIN_C(15:0)
sDCLK_C
sDVALID_C
sDVALID_D
DLPC410
LVDS BUS D
sDOUT_D(15:0)
sDCLKOUT_D
sSCTRL_D
LVDS BUS A
sDOUT_A(15:0)
sDCLKOUT_A
sSCTRL_A
Figure 9. DLPC410 Data Flow
Four LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge
aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the
DLPC410 (DVALID).
Output LVDS buses transfer data from the DLPC410 to the DMD. Output buses LVDS C and LVDS D are used
in addition to LVDS A and LVDS B with the DLP9500.
8.3.4.1.3 DLPC410 to DLPA200 Interface
8.3.4.1.3.1 DLPA200 Operation
The DLPA200 DMD micromirror driver is a mixed-signal application-specific integrated circuit (ASIC) that
combines the necessary high-voltage power supply generation and micromirror clocking pulse functions for a
family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD
requirements.
The DLPA200 operates from a 12-V power supply input. For more detailed information on the DLPA200, see the
DLPA200 data sheet.
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8.3.4.1.3.2 DLPC410 to DLPA200 IO Description
The serial communications port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows
exchange of commands from the DLPC410 to the DLPA200s.
DLPA200
SCP bus
DLPC410
SCP bus
DLPA200
Figure 10. Serial Port System Configuration
Five signal lines are associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ.
Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 4. DLPC410 to DLPA200 I/O Pin Descriptions
PIN NAME
A_SCPEN
DESCRIPTION
Active-low chip select for DLPA200 serial bus
DLPA200 control signal strobe
DLPA200 mode control
I/O
O
O
O
O
O
O
O
O
O
O
A_STROBE
A_MODE(1:0)
A_SEL(1:0)
A_ADDR(3:0)
B_SCPEN
DLPA200 select control
DLPA200 address control
Active-low chip select for DLPA200 serial bus (2)
DLPA200 control signal strobe (2)
DLPA200 mode control
B_STROBE
B_MODE(1:0)
B_SEL(1:0)
B_ADDR(3:0)
DLPA200 select control
DLPA200 address control
The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0],
SEL[1:0] and reset group address A[3:0] (Table 4). The MODE[1:0] input determines whether a single output, two
outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected
by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the
selected voltage level after a break-before-make delay. Outputs will remain latched at the last micromirror
clocking pulse waveform level until the next micromirror clocking pulse waveform cycle.
8.3.4.1.4 DLPA200 to DLP9500 Interface
8.3.4.1.4.1 DLPA200 to DLP9500 Interface Overview
The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST
lines in various sequences through the micromirror clocking pulse driver function. VOFFSET is also supplied
directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by
regulators.
The function of the micromirror clocking pulse driver is to switch selected outputs in patterns between the three
voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several micromirror clocking pulse
waveforms. The order of these micromirror clocking pulse waveform events is controlled externally by the logic
control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the
DMD type to determine the appropriate micromirror clocking pulse waveform.
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A direct micromirror clocking pulse operation causes a mirror to transition directly from one latched state to the
next. The address must already be set up on the mirror electrodes when the micromirror clocking pulse is
initiated. Where the desired mirror display period does not allow for time to set up the address, a micromirror
clocking pulse with release can be performed. This operation allows the mirror to go to a relaxed state regardless
of the address while a new address is set up, after which the mirror can be driven to a new latched state.
A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as off
although the light is likely to be more than a mirror latched in the off state. System designers should carefully
evaluate the impact of relaxed mirror conditions on optical performance.
8.3.5 Measurement Conditions
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 11 shows an equivalent test load circuit for the
output under test. The load capacitance value stated is only for characterization and measurement of AC timing
signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise
and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH
MIN for output clocks.
LOAD CIRCUIT
R
L
From Output
Under Test
Tester
Channel
C
C
= 50 pF
L
L
= 5 pF for Disable Time
Figure 11. Test Load Circuit for AC Timing Measurements
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Package Pin
A1 Corner
DLP9500
Two Two
“On-State” “Off-State”
Micromirrors Micromirrors
For Reference
Flat-State
( “parked” )
Micromirror Position
a
b
-a
b
Silicon Substrate
Silicon Substrate
“On-State”
Micromirror
“Off-State”
Micromirror
Figure 12. Micromirror Landed Positions and Light Paths
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8.4 Device Functional Modes
The DLP9500 has only one functional mode; it is set to be highly optimized for low latency and high speed in
generating mirror clocking pulses and timings.
When operated with the DLPC410 controller in conjunction with the DLPA200 drivers, the DLP9500 can be
operated in several display modes. The DLP9500 is loaded as 15 blocks of 72 rows each. The first 64 bits of
pixel data and last 64 bits of pixel data for all rows are not visible. Below is a representation of how the image is
loaded by the different micromirror clocking pulse modes. Figure 13, Figure 14, Figure 15, and Figure 16 show
how the image is loaded by the different micromirror clocking pulse modes.
There are four micromirror clocking pulse modes that determine which blocks are reset when a micromirror
clocking pulse command is issued:
•
•
•
•
Single block mode
Dual block mode
Quad block mode
Global mode
8.4.1 Single Block Mode
In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset
to transfer the information to the mechanical state of the mirrors.
Figure 13. Single Block Mode
8.4.2 Dual Block Mode
In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5), (6-7), (8-9), (10-11), (12-13),
and (14). These pairs can be reset in any order. After data is loaded a pair can be reset to transfer the
information to the mechanical state of the mirrors.
Figure 14. Dual Block Mode
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Device Functional Modes (continued)
8.4.3 Quad Block Mode
In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-14). Each
quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the
information to the mechanical state of the mirrors.
Figure 15. Quad Block Mode
8.4.4 Global Block Mode
In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be
loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of
the mirrors.
Figure 16. Global Mode
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8.5 Window Characteristics and Optics
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
8.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
8.5.2 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination, projection pupils, or both to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
8.5.3 Pupil Match
TI recommends the exit pupil of the illumination is nominally centered within 2° (two degrees) of the entrance
pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border
and/or active area, which may require additional system apertures to control, especially if the numerical aperture
of the system exceeds the pixel tilt angle.
8.5.4 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical
operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the
window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical
system should be designed to limit light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the optical architecture of a
particular system, overfill light may have to be further reduced below the suggested 10% level to be acceptable.
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8.6 Micromirror Array Temperature Calculation
8.6.1 Thermal Test Points
The temperature of the DMD case can be measured directly. For consistency, thermal test point locations 1, 2,
and 3 are defined as shown in Figure 17.
TP2
TP2
27.80
TP3
TP3
TP3 (TP2)
TP1
21.08
Figure 17. Thermal Test Points
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Micromirror Array Temperature Calculation (continued)
8.6.2 Micromirror Array Temperature Calculation - Lumens Based
Micromirror array temperature cannot be measured directly; therefore, it must be computed analytically from:
•
•
•
•
the measurement points (Figure 17)
the package thermal resistance
the electrical power
the illumination heat load
The relationship between micromirror array temperature and the reference ceramic temperature (thermal test
point TP1 in Figure 17) is provided by the following equations:
TARRAY = T CERAMIC + (QARRAY × RARRAY-TO-CERAMIC
QARRAY = QELECTRICAL + QILLUMINATION
)
where
•
•
•
TARRAY = computed array temperature (°C)
TCERAMIC = measured ceramic temperature (°C) (TP1 location)
RARRAY-TO-CERAMIC = thermal resistance of DMD package (specified in Thermal Information) from array to
ceramic TP1 (°C/W)
•
•
•
•
•
QARRAY = total power (electrical + absorbed) on the array (Watts)
QELECTRICAL = nominal electrical power (Watts)
QILLUMINATION = (CL2W × SL) (Watts)
CL2W = conversion constant for screen lumens to power on DMD (Watts/lumen)
SL = measured screen lumens
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 4.4 Watts. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The conversion constant CL2W is based on the DMD input illumination
characteristics. It assumes a spectral efficiency of 300 lumens/Watt for the projected light and an illumination
distribution of 83.7% on the active array and 16.3% on the array border. The equations shown above are valid for
a system with a total projection efficiency through the projection lens from the DMD to the screen of 87%.
Sample calculation for typical application:
•
•
•
•
•
•
•
TCeramic = 55°C (measured)
SL = 2000 lm (measured)
QELECTRICAL = 4.4 Watts
RARRAY-TO-CERAMIC = 0.5 °C/W
CL2W = 0.00274 W/lm
QARRAY = 4.4 + (0.00274 W/lm × 2000 lm) = 9.88 W
TARRAY = 55°C + (9.88 W x 0.5 °C) = 59.9 °C
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Micromirror Array Temperature Calculation (continued)
8.6.3 Micromirror Array Temperature Calculation - Power Density Based
Micromirror array temperature cannot be measured directly; therefore, it must be computed analytically from:
•
•
•
•
the measurement points (Figure 17)
the package thermal resistance
the electrical power
the illumination heat load
The relationship between array temperature and the reference ceramic temperature (thermal test point TP1 in
Figure 17) is provided by the following equations:
TARRAY = T CERAMIC + (QARRAY × RARRAY-TO-CERAMIC
QARRAY = QELECTRICAL + (0.42 x QINCIDENT
)
)
where
•
•
•
TARRAY = computed array temperature (°C)
TCERAMIC = measured ceramic temperature (°C) (TP1 location)
RARRAY-TO-CERAMIC = thermal resistance of DMD package (specified in Thermal Information) from array to
ceramic TP1 (°C/W)
•
•
•
QARRAY = total power (electrical + absorbed) on the array (Watts)
QELECTRICAL = nominal electrical power (Watts)
QINCIDENT = total incident optical power on DMD (Watts)
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 4.4 watts. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for each DMD chip in a system. It
assumes an illumination distribution of 83.7% on the active array and 16.3% on the array border.
Sample Calculation for each DMD in a system with a measured illumination power density:
•
•
•
•
•
•
•
•
•
•
TCeramic = 20°C (measured)
ILLDENSITY = 11 Watts per cm2 (optical power on DMD per unit area) (measured)
Overfill = 16.3% (optical design)
QELECTRICAL = 4.4 Watts
RARRAY-TO-CERAMIC = 0.5 °C/W
Area of array = ( 2.0736 cm x 1.1664 cm ) = 2.419 cm2
ILLAREA = 2.419 cm2 / (83.7%) = 2.89 cm2
QINCIDENT =11 W/cm2 x 2.89 cm2 = 31.79 W
QARRAY = 4.4 W + (0.42 x 31.79 W) = 17.75 W
TARRAY = 20°C + (17.75 W x 0.5 °C) = 28.9 °C
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8.7 Micromirror Landed-On and Landed-Off Duty Cycle
8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On–state versus the amount of time the same
micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the
time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Because a micromirror can only be landed in one state or the other (on or off), the two numbers (percentages)
always add to 100.
8.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the usable life of the DMD.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
8.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD, and this
interaction can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD’s
usable life. This is quantified in the derating curve shown in Figure 1. The importance of this curve is that:
•
•
All points along this curve represent the same usable life.
All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
•
All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at
for a give long-term average landed duty.
8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel
will experience a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 5.
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Table 5. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_% × Blue_Scale_Value)
where:
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,
Green, and Blue are displayed (respectively) to achieve the desired white point.
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (to
achieve the desired white point), then the landed duty for various combinations of red, green, blue color
intensities would be as shown in Table 6.
Table 6. Example Landed Duty Cycle for Full-Color
RED CYCLE PERCENTAGE
50%
GREEN CYCLE PERCENTAGE
20%
BLUE CYCLE PERCENTAGE
30%
LANDED DUTY CYCLE
RED SCALE VALUE
GREEN SCALE VALUE
BLUE SCALE VALUE
0%
100%
0%
0%
0%
0%
0%
0/100
50/50
20/80
30/70
6/94
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
0%
7/93
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
0%
60%
60%
100%
12%
100%
100%
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DLP9500 devices must be coupled with the DLPC410 controller to provide a reliable solution for many
different applications. The DMDs are spatial light modulators which reflect incoming light from an illumination
source to one of two directions, with the primary direction being into a projection collection optic. Each application
is derived primarily from the optical architecture of the system and the format of the data coming into the
DLPC410. Applications of interest include 3D printing, lithography, medical systems, and compressive sensing.
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9.2 Typical Application
A typical embedded system application using the DLPC410 controller and DLP9500 is shown in Figure 18. In this configuration, the DLPC410 controller
supports input from an FPGA. The FPGA sends low-level data to the controller, enabling the system to be highly optimized for low latency and high
speed.
OPTICAL
SENSOR
(CAMERA)
LED
DRIVERS
LEDS
LED
SENSORS
LVDS BUS (A,B,[C,D])
DDC_DCLK, DVALID, DDC_DIN(15:0)
LVDS BUS (A,B,[C,D])
DDC_DCLKOUT, DDCSCTRL, DDC_DOUT(15:0)
USER
INTERFACE
SCP BUS
SCPCLK, SCPDO, SCPDI, DMD_SCPENZ, A_SCPENZ, B_SCPENZ
ROW and BLOCK SIGNALS
ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ
CONTROL SIGNALS
COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT
DLP9500
DLPA200 CONTROL
MBRST1_(15:0)
CONNECTIVITY
(USB, ETHERNET, ETC.)
A_MODE(1:0), A_SEL(1:0),
DLPA200
USER - MAIN
PROCESSOR / FPGA
DLPC410 INFO SIGNALS
RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED,
DMD_TYPE(3:0), DDC_VERSION(2:0)
A_ADDR(3:0), OEZ, INIT
A
DLPC410
PGM SIGNALS
PROM_CCK_DDC, PROGB_DDC,
PROM_DO_DDC, DONE_DDC, INTB_DDC
DLPA200 CONTROL
MBRST2_(15:0)
B_MODE(1:0), B_SEL(1:0),
VOLATILE
and
DLPR410
DLPA200
B_ADDR(3:0), OEZ, INIT
NON-VOLATILE
STORAGE
B
JTAG
VLED0
VLED1
ARSTZ
CLKIN_R
OSC
50 Mhz
DMD_RESET
POWER MANAGMENT
~
Figure 18. DLPC410 and DLP9500 Embedded Example Block Diagram
Copyright © 2012–2018, Texas Instruments Incorporated
41
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
9.2.1 Design Requirements
All applications using the DLP9500 1080p chipset require both the controller and the DMD components for
operation. The system also requires an external parallel flash memory device loaded with the DLPC410
configuration and support firmware. The chipset has several system interfaces and requires some support
circuitry. The following interfaces and support circuitry are required:
•
DLPC410 system interfaces:
–
–
–
–
–
–
Control interface
Trigger interface
Input data interface
Illumination interface
Reference clock
Program interface
•
DLP9500 interfaces:
–
–
–
–
–
DLPC410 to DLP9500 digital data
DLPC410 to DLP9500 control interface
DLPC410 to DLP9500 micromirror reset control interface
DLPC410 to DLPA200 micromirror driver
DLPA200 to DLP9500 micromirror reset
9.2.1.1 Device Description
The DLP9500 1080p chipset offers developers a convenient way to design a wide variety of industrial, medical,
telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data,
and light patterns.
The DLP9500 1080p chipset includes the following four components: DMD digital controller (DLPC410),
EEPROM (DLPR410), DMD micromirror driver (DLPA200), and a DMD (DLP9500).
DLPC410 Digital Controller for DLP Discovery 4100 chipset
•
•
•
•
Provides high speed 2XLVDS data and control interface to the user
Drives mirror clocking pulse and timing information to the DLPA200
Supports random row addressing
Controls illumination
DLPR410 PROM for DLP Discovery 4100 chipset
Contains startup configuration information for the DLPC410
DLPA200 DMD Micromirror Driver
•
•
Generates micromirror clocking pulse control (sometimes referred to as a reset) of 15 banks of DMD
mirrors. (Two are required for the DLP9500).
DLP9500 DLP 0.95 1080p 2xLVDS Type-A DMD
•
Steers light in two digital positions (+12° and –12°) using 1920 × 1080 micromirror array of aluminum
mirrors.
Table 7. DLP DLP9500 Chipset Configurations
QUANTITY
TI PART
DLP9500
DLPC410
DLPR410
DLPA200
DESCRIPTION
DLP 0.95 1080p 2xLVDS Type-A DMD
Digital Controller for DLP Discovery 4100 chipset
PROM for DLP Discovery 4100 chipset
DMD Micromirror Driver
1
1
1
2
42
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DLP9500
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ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
Reliable function and operation of DLP9500 1080p chipsets require the components be used in conjunction with
each other. This document describes the proper integration and use of the DLP9500 1080p chipset components.
The DLP9500 1080p chipset can be combined with a user programmable application FPGA (not included) to
create high performance systems.
9.2.2 Detailed Design Procedure
The DLP9500 DMD is well suited for visible light applications requiring fast, spatially programmable light patterns
using the micromirror array. See the block diagram in Figure 8 to see the connections between the DLP9500
DMD, the DLPC410 digital controller, the DLPR410 EEPROM, and the DLPA200 DMD micromirror drivers. An
example application block diagram can be found in Figure 18. Layout guidelines should be followed for reliability.
10 Power Supply Recommendations
10.1 Power-Up Sequence (Handled by the DLPC410)
The sequence of events for DMD system power-up is:
1. Apply logic supply voltages to the DLPA200 and to the DMD according to DMD specifications.
2. Place DLPA200 drivers into high impedance states.
3. Turn on DLPA200 bias, offset, or reset supplies according to driver specifications.
4. After all supply voltages are assured to be within the limits specified and with all micromirror clocking pulse
operations logically suspended, enable all drivers to either VOFFSET or VBIAS level.
5. Begin micromirror clocking pulse operations.
10.2 DMD Power-Up and Power-Down Procedures
Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. The
DLP9500 power-up and power-down procedures are defined by the DLPC410 data sheet (DLPS024). These
procedures must be followed to ensure reliable operation of the device.
Copyright © 2012–2018, Texas Instruments Incorporated
43
DLP9500
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11 Layout
11.1 Layout Guidelines
The DLP9500 is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These
guidelines are targeted at designing a PCB board with these components.
11.1.1 Impedance Requirements
Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs
(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn) which should be matched to 100 Ω ±10% across
each pair.
11.1.2 PCB Signal Routing
When designing a PCB board for the DLP9500 controlled by the DLPC410 in conjunction with the DLPA200s,
the following are recommended:
Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces
routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2
Memory, DMD (LVDS signals), then DLPA200 signals.
TI does not recommend signal routing on power or ground planes.
TI does not recommend ground plane slots.
High speed signal traces should not cross over slots in adjacent power and/or ground planes.
Table 8. Important Signal Trace Constraints
SIGNAL
CONSTRAINTS
P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle
<2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)
Trace width: 4 mil (0.1 mm)
Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)
Maximum recommended trace length <6 inches (150 mm)
LVDS (DMD_DAT_xnn,
DMD_DCKL_xn, and
DMD_SCTRL_xn)
Table 9. Power Trace Widths and Spacing
MINIMUM TRACE
MINIMUM TRACE
SPACING
SIGNAL NAME
LAYOUT REQUIREMENTS
WIDTH
GND
Maximize
5 mil (0.13 mm)
10 mil (0.25 mm)
15 mil (0.38 mm)
Maximize trace width to connecting pin as a minimum
VCC, VCC2
MBRST[14:0]
20 mil (0.51 mm)
11 mil (0.28 mm)
11.1.3 Fiducials
Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials
for optical auto insertion are placed on three corners of both sides of the PCB.
11.1.4 PCB Layout Guidelines
A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal
layers.
11.1.4.1 DMD Interface
The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data
is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS
signals should have 100 Ω differential impedance. The differential signals should be matched but kept as short
as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not
necessary.
44
Copyright © 2012–2018, Texas Instruments Incorporated
DLP9500
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ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
11.1.4.1.1 Trace Length Matching
The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of
100 Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair
uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all
signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal
DMD routing must be considered in this calculation.
11.1.4.2 DLP9500 Decoupling
General decoupling capacitors for the DLP9500 should be distributed around the PCB and placed to minimize
the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have
vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is
discouraged. The power and ground pads of the DLP9500 should be tied to the voltage and ground planes with
their own vias.
11.1.4.2.1 Decoupling Capacitors
Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and
ground pin of the component. TI recommends that the placement of and routing for the decoupling capacitors
meet the following guidelines:
•
The supply voltage pin of the capacitor should be located close to the device supply voltage pin or pins. The
decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to
the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be
tied to the voltage or ground plane through separate vias.
•
•
•
•
The trace lengths of the voltage and ground connections for decoupling capacitors and components should
be less than 0.1 inch to minimize inductance.
The trace width of the power and ground connection to decoupling capacitors and components should be as
wide as possible to minimize inductance.
Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance
and improve noise performance.
Decoupling performance can be improved by using low ESR and low ESL capacitors.
11.1.4.3 VCC and VCC2
The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should
be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each
decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND
pads of the DMD should be tied to the VCC and ground planes with their own vias.
The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the
distance from the DMD’s VCC2 and ground pads. Using wide etch from the decoupling capacitors to the DMD
connection will reduce inductance and improve decoupling performance.
11.1.4.4 DMD Layout
See the respective sections in this data sheet for package dimensions, timing and pin out information.
11.1.4.5 DLPA200
The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the
DLPA200 (MBRST[29:0] should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil.
The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum
trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet DLPS015 for
mechanical package and layout information.
Copyright © 2012–2018, Texas Instruments Incorporated
45
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
11.2 Layout Example
For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the
dashed lines, Figure 19 shows correct matching of signal pair lengths with serpentine sections to maintain the
correct impedance.
Figure 19. Mitering LVDS Traces to Match Lengths
46
版权 © 2012–2018, Texas Instruments Incorporated
DLP9500
www.ti.com.cn
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
12 器件和文档支持
12.1 器件支持
12.1.1 器件命名规则
图 20 提供了读取任一 DLP 器件完整器件名称的图例。
图 20. 器件命名规则
12.1.2 器件标记
图 21 显示了器件标记字段。
TI Internal Numbering
DMD Part Number
2-Dimensional Matrix Code
YYYYYYY
(DMD Part Number
and Serial Number)
DLP9500_FLN
GHXXXXX LLLLLLM
LLLLLL
Part 1 of Serial Number
(7 characters)
Part 2 of Serial Number
(7 characters)
TI Internal Numbering
图 21. DLP9500 器件标记
版权 © 2012–2018, Texas Instruments Incorporated
47
DLP9500
ZHCSA86E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
12.2 文档支持
12.2.1 相关文档
以下文档包含关于使用 DLP9500 器件的更多信息。
•
•
•
《适用于 DLP Discovery 4100 芯片组的 DLPC410 数字控制器数据表》
《DLPA200 DMD 微镜驱动器数据表》
《适用于 DLP Discovery 4100 芯片组的 DLPR410 PROM 数据表》
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的快速链
接。
表 10. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
DLP9500
DLPA200
DLPC410
DLPR410
12.4 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.6 商标
Discovery, E2E are trademarks of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
48
版权 © 2012–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP9500BFLN
ACTIVE
CLGA
FLN
355
12
RoHS & Green
NI-PD-AU
N / A for Pkg Type
20 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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