DLPC3426ZVB [TI]
DLP® display controller for DLP230NP (0.23 1080p) DMD
| ZVB | 176 | -30 to 85;型号: | DLPC3426ZVB |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® display controller for DLP230NP (0.23 1080p) DMD | ZVB | 176 | -30 to 85 |
文件: | 总69页 (文件大小:2193K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLPC3436
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
DLPC3436 和DLPC3426 显示控制器
1 特性
3 说明
• 适用于DLP230NP 或DLP230NPSE (0.23 1080p)
DMD 的显示控制器
DLPC3436 和 DLPC3426 显示控制器是 DLP230NP
或 DLP230NPSE .23 1080p 芯片组的组件,可为
DLP230NP/NPSE 数字微镜器件 (DMD) 的可靠运行提
供支持。DLPC34x6 控制器可在系统电子设备与 DMD
之间提供一个便捷的多功能接口,从而实现小外形尺寸
的低功耗全高清显示。
– 支持高达1080p 的输入分辨率
– 低功耗DMD 接口
• 输入帧速率高达240Hz(1080p 分辨率时为
60Hz)
• 像素数据处理,包括:
请访问 TI DLP® PicoTM 显示技术入门页面,了解有关
DMD 技术的更多信息。
– IntelliBright™ 图像处理算法套件
• 内容自适应照明控制(CAIC)
• 局部亮度增强(LABB)
– 1D 梯形校正
DLP230NP/NPSE .23 1080p 芯片组包含现成的资源,
可帮助用户加快设计周期。这些资源包括可直接用于生
产环境的光学模块、光学模块制造商和设计公司。
– 色彩坐标调整
器件兼容性
DMD
– 4:2:2 至4:4:4 色度插值
• 24 位输入像素接口支持:
– 并行接口协议
– 高达155MHz 的像素时钟
– 多个输入像素数据格式选项
• 支持外部闪存
控制器
说明
DLPC3436
DLPC3426
DLP230NP
DLP230NPSE
亮度更高
亮度更低
器件信息
封装(1)
封装尺寸(标称值)
7.00mm x 7.00mm
7.00mm x 7.00mm
器件型号
• 断电时自动DMD 停止
• 嵌入式帧存储器(eDRAM)
• 系统特性;包括:
DLPC3436
DLPC3426
NFBGA (176)
NFBGA (176)
– I2C 器件控制
– 可编程启动界面
– 可编程LED 电流控制
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
V
LED
• 与DLPA2000、DLPA2005、DLPA3000 或
DLPA3005 PMIC(电源管理集成电路)和LED 驱
动器配合使用
SYSPWR
1.8 V external
1.8 V
PROJ_ON
GPIO_8 SPI1
DLPA200x
2
I C
HOST_IRQ
R
LIM
RESETZ
PARKZ
2 应用
SPI (4)
Parallel
(28)
Parallel (28)
SUB_FRAME
ACT_SYNC
Illumination
optics
• DLP 标牌
• 移动投影仪
VDD
DLPC3436
FPGA
FPD-
Link
2
I C
V
, V ,
BIAS OFFSET
• 移动智能电视
• 平板电脑(多媒体)
• 增强现实眼镜
• 智能家居显示
• Pico 投影仪
SPI0
VCC_18
V
RESET
DAC_DATA,
DAC_CLK
1.8 V
Actuator
Drive
Circuit
DMD
CTRL
Sub-LVDS
1.8 V
VCC_INTF
VCC_FLSH
典型简化系统图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS156
DLPC3436
www.ti.com.cn
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
Table of Contents
6.17 DMD Parking Switching Characteristics................. 24
6.18 Chipset Component Usage Specification............... 24
7 Detailed Description......................................................26
7.1 Overview...................................................................26
7.2 Functional Block Diagram.........................................26
7.3 Feature Description...................................................27
7.4 Device Functional Modes..........................................40
7.5 Programming............................................................ 40
8 Application and Implementation..................................41
8.1 Application Information............................................. 41
8.2 Typical Application.................................................... 41
9 Power Supply Recommendations................................44
9.1 PLL Design Considerations...................................... 44
9.2 System Power-Up and Power-Down Sequence....... 44
9.3 Power-Up Initialization Sequence.............................48
9.4 DMD Fast Park Control (PARKZ)..............................49
9.5 Hot Plug I/O Usage...................................................49
9.6 Maximum Signal Transition Time..............................49
10 Layout...........................................................................50
10.1 Layout Guidelines................................................... 50
10.2 Layout Example...................................................... 58
11 Device and Documentation Support..........................59
11.1 Device Support........................................................59
11.2 Documentation Support.......................................... 62
11.3 Related Links.......................................................... 62
11.4 接收文档更新通知................................................... 62
11.5 支持资源..................................................................62
11.6 Trademarks............................................................. 62
11.7 静电放电警告...........................................................62
11.8 术语表..................................................................... 62
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
5.1 Test Pins and General Control....................................5
5.2 Parallel Port Input....................................................... 6
5.3 DSI Input Data and Clock........................................... 7
5.4 DMD Reset and Bias Control......................................7
5.5 DMD Sub-LVDS Interface...........................................7
5.6 Peripheral Interface.....................................................8
5.7 GPIO Peripheral Interface...........................................9
5.8 Clock and PLL Support.............................................10
5.9 Power and Ground....................................................10
6 Specifications................................................................ 12
6.1 Absolute Maximum Ratings...................................... 12
6.2 ESD Ratings............................................................. 12
6.3 Recommended Operating Conditions.......................13
6.4 Thermal Information..................................................13
6.5 Power Electrical Characteristics............................... 14
6.6 Pin Electrical Characteristics.................................... 15
6.7 Internal Pullup and Pulldown Electrical
Characteristics.............................................................17
6.8 DMD Sub-LVDS Interface Electrical
Characteristics.............................................................18
6.9 DMD Low-Speed Interface Electrical
Characteristics.............................................................19
6.10 System Oscillator Timing Requirements.................20
6.11 Power Supply and Reset Timing Requirements......20
6.12 Parallel Interface Frame Timing Requirements.......21
6.13 Parallel Interface General Timing Requirements.... 22
6.14 Flash Interface Timing Requirements..................... 22
6.15 Other Timing Requirements....................................24
6.16 DMD Sub-LVDS Interface Switching
Information.................................................................... 63
12.1 Package Option Addendum....................................64
Characteristics.............................................................24
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision D (March 2023) to Revision E (April 2023)
Page
• 为新型号器件 DLPC3426 和DLP230NPSE 添加了器件信息.............................................................................1
• Added the table of DLPC3426 DLPA compatibility...........................................................................................24
• Added new DLPC34x6 and NPSE info.............................................................................................................43
• Changed DLPC3436 to DLPC34x6.................................................................................................................. 44
• Added NPSE and 34x6 to parts name..............................................................................................................49
• Changed 3436 to 34x6..................................................................................................................................... 62
Changes from Revision C (October 2020) to Revision D (March 2023)
Page
• 添加了对 DLPA3005 的支持............................................................................................................................... 1
• Added missing I/O definition 10 .......................................................................................................................10
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS156
2
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Product Folder Links: DLPC3436
DLPC3436
www.ti.com.cn
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
• Added the DLPA3005 device to the supported configuration .......................................................................... 24
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: DLPC3436
English Data Sheet: DLPS156
DLPC3436
www.ti.com.cn
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
5 Pin Configuration and Functions
图5-1. ZVB Package 176-Pin NFBGA Bottom View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
P
CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PWM
SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0
A
B
C
D
E
F
LK
DATA
DATAH_P DATAG_P
DATAF_P
DATAE_P
DATAD_P
DATAC_P
DATAB_P
DATAA_P
DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
N
ARSTZ
DATA
DATAH_N DATAG_N
DATAF_N
DATAE_N
DATAD_N
DATAC_N
DATAB_N
DATAA_N
HWTEST_E
N
DD3P
DD3N
VDDLP12
VDD
VSS
VCC
VSS
VSS
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VCC
VDD
VSS
VCC
RESETZ SPI0_CSZ1
PARKZ
VDD
VSS
VDD
VSS
VDD
VSS
VCC
VDD
GPIO_00
GPIO_02
GPIO_04
GPIO_06
GPIO_08
GPIO_10
GPIO_12
GPIO_14
GPIO_16
GPIO_01
GPIO_03
GPIO_05
GPIO_07
GPIO_09
GPIO_11
GPIO_13
GPIO_15
GPIO_17
GPIO_19
TSTPT_7
TSTPT_5
TSTPT_3
DD2P
DCLKP
DD1P
DD2N
DCLKN
DD1N
VDD
VSS
VSS
VDD
VSS
VCC_FLSH
VDD
VCC
VCC
VSS
VSS
VDD
VSS
VDD
VSS
VDD
RREF
DD0P
DD0N
VSS_PLLM
G
H
J
PLL_REFCL
K_I
VDD_PLLM VSS_PLLD
PLL_REFCL
K_O
VDD_PLLD
PDATA_0
PDATA_2
PDATA_4
PDATA_6
VSS
VDD
PDATA_1
PDATA_3
PDATA_5
PDATA_7
VSYNC_WE
PDATA_8
K
L
VSS
VCC_INTF
VCC_INTF
PCLK
VSS
VDD
3DR
VCC_INTF
VSS
VDD
VDD
VCC
JTAGTMS1 GPIO_18
M
N
P
R
PDM_CVS_
TE
HSYNC_CS
VCC_INTF HOST_IRQ IIC0_SDA
IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1
TSTPT_6
TSTPT_4
TSTPT_2
DATEN_CM
D
PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK
JTAGTDI
TSTPT_1
PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22
IIC1_SDA
IIC1_SCL
TSTPT_0
Note: The lower image view is from the top.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS156
4
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Product Folder Links: DLPC3436
DLPC3436
www.ti.com.cn
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
5.1 Test Pins and General Control
PIN
I/O
TYPE(4)
DESCRIPTION
NAME
HWTEST_EN
NO.
Manufacturing test enable signal. Connect this signal directly to ground on the
PCB for normal operation.
C10
I
I
6
DMD fast park control (active low Input with a hysteresis buffer). This signal is
used to quickly park the DMD when loss of power is imminent. The longest
lifetime of the DMD may not be achieved with the fast park operation;
therefore, this signal is intended to only be asserted when a normal park
operation is unable to be completed. The PARKZ signal is typically provided
from the DLPAxxxx interrupt output signal.
PARKZ
C13
6
JTAGTCK
JTAGTDI
P12
P13
I
I
6
6
1
1
6
6
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
JTAGTDO1
JTAGTDO2
JTAGTMS1
JTAGTMS2
N13(1)
N12(1)
M13
O
O
I
N11
I
TI internal use.
This pin must be tied to ground, through an external resistor for normal
operation. Failure to tie this pin low during normal operation can cause start
up and initialization problems.(2)
JTAGTRSTZ
P11
C11
I
I
6
Power-on reset (active low input with a hysteresis buffer). Self-configuration
starts when a low-to-high transition is detected on RESETZ. All controller
power and clocks must be stable before this reset is deasserted. No signals
are in their active state while RESETZ is asserted. This pin is typically
connected to the RESETZ pin of the DLPA200x or RESET_Z of the
DLPA200x.
RESETZ
6
TSTPT_0
TSTPT_1
TSTPT_2
TSTPT_3
TSTPT_4
TSTPT_5
TSTPT_6
TSTPT_7
R12
R13
R14
R15
P14
P15
N14
N15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
1
1
1
1
1
1
1
Test pins (includes weak internal pulldown). Pins are tristated while RESETZ
is asserted low. Sampled as an input test mode selection control
approximately 1.5 µs after deassertion of RESETZ, and then driven as
outputs.(2) (3)
Normal use: reserved for test output. Leave open for normal use.
Note: An external pullup may put the DLPC34x36 in a test mode. See 节
7.3.8 for more information.
(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal
pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an
external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is
recommended to ensure a logic low.
(2) External resistor must have a value of 8 kΩor less to compensate for pins that provide internal pullup or pulldown resistors.
(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal
pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but
there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to
ensure a logic low.
(4) See 表5-3 for type definitions.
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Product Folder Links: DLPC3436
English Data Sheet: DLPS156
DLPC3436
www.ti.com.cn
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
5.2 Parallel Port Input
PIN(1) (2)
NAME
DESCRIPTION
I/O
TYPE(4)
NO.
PARALLEL RGB MODE
PCLK
P3
I
11
5
Pixel clock
Parallel data mask. Programable polarity with default of active high.
Optional signal.
PDM_CVS_TE
N4
I/O
VSYNC_WE
HSYNC_CS
DATAEN_CMD
P1
N5
P2
I
I
I
11
11
11
Vsync(3)
Hsync(3)
Data valid
(TYPICAL RGB 888)
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7
K2
K1
L2
Blue (bit weight 1)
Blue (bit weight 2)
Blue (bit weight 4)
Blue (bit weight 8)
Blue (bit weight 16)
Blue (bit weight 32)
Blue (bit weight 64)
Blue (bit weight 128)
L1
I
11
M2
M1
N2
N1
(TYPICAL RGB 888)
PDATA_8
PDATA_9
PDATA_10
PDATA_11
PDATA_12
PDATA_13
PDATA_14
PDATA_15
R1
R2
R3
P4
R4
P5
R5
P6
Green (bit weight 1)
Green (bit weight 2)
Green (bit weight 4)
Green (bit weight 8)
Green (bit weight 16)
Green (bit weight 32)
Green (bit weight 64)
Green (bit weight 128)
I
11
(TYPICAL RGB 888)
PDATA_16
PDATA_17
PDATA_18
PDATA_19
PDATA_20
PDATA_21
PDATA_22
PDATA_23
R6
P7
R7
P8
R8
P9
R9
P10
Red (bit weight 1)
Red (bit weight 2)
Red (bit weight 4)
Red (bit weight 8)
Red (bit weight 16)
Red (bit weight 32)
Red (bit weight 64)
Red (bit weight 128)
I
11
11
3D reference
•
For 3D applications: left or right 3D reference (left = 1, right = 0). To be
provided by the host. Must transition in the middle of each frame (no
closer than 1 ms to the active edge of VSYNC).
3DR
N6
I
•
If a 3D application is not used, pull this input low through an external
resistor.
(1) PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.
(2) Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩor less).
(3) VSYNC and HSYNC polarity can be adjusted by software.
(4) See 表5-3 for type definitions.
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Product Folder Links: DLPC3436
English Data Sheet: DLPS156
DLPC3436
www.ti.com.cn
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
5.3 DSI Input Data and Clock
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
DCLKN
DCLKP
E2
E1
I/O
10
Reserved - leave disconnected
DD0N
DD0P
DD1N
DD1P
DD2N
DD2P
DD3N
DD3P
G2
G1
F2
F1
D2
D1
C2
C1
I/O
10
Reserved - leave disconnected
Reserved - leave disconnected
RREF
F3
—
5.4 DMD Reset and Bias Control
PIN
I/O
TYPE(1)
DESCRIPTION
NAME
NO.
DMD driver enable (active high). DMD reset (active low). When
corresponding I/O power is supplied, the controller drives this signal low
after the DMD is parked and before power is removed from the DMD. If the
1.8-V power to the DLPC34x6 is independent of the 1.8-V power to the
DMD, then TI recommends including a weak, external pulldown resistor to
hold the signal low in case DLPC34x6 power is inactive while DMD power
is applied.
DMD_DEN_ARSTZ
B1
O
2
DMD_LS_CLK
A1
A2
B2
O
O
I
3
3
6
DMD, low speed (LS) interface clock
DMD, low speed (LS) serial write data
DMD, low speed (LS) serial read data
DMD_LS_WDATA
DMD_LS_RDATA
(1) See 表5-3 for type definitions.
5.5 DMD Sub-LVDS Interface
PIN
I/O
TYPE(1)
DESCRIPTION
NAME
NO.
DMD_HS_CLK_P
DMD_HS_CLK_N
A7
B7
O
4
DMD high speed (HS) interface clock
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
A3
B3
A4
B4
A5
B5
A6
B6
A8
B8
A9
B9
A10
B10
A11
B11
DMD sub-LVDS high speed (HS) interface write data lanes. The true
numbering and application of the DMD_HS_WDATA pins depend on the
software configuration. See 节7.3.9.
O
4
(1) See 表5-3 for type definitions.
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Product Folder Links: DLPC3436
English Data Sheet: DLPS156
DLPC3436
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ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
5.6 Peripheral Interface
PIN(1)
I/O
TYPE(3)
DESCRIPTION
NAME
NO.
Successive approximation ADC (analog-to-digital converter) comparator output (DLPC34x6
Input). To implement, use a successive approximation ADC with a thermistor feeding one
input of the external comparator and the DLPC34x6 controller GPIO_10 (RC_CHARGE) pin
driving the other side of the comparator. It is recommended to use the DLPAxxxx to achieve
this function. CMP_OUT must be pulled down to ground if this function is not used
(hysteresis buffer).
CMP_OUT
A12
I
6
CMP_PWM
A15
N8
O
O
1
9
TI internal use. Leave this pin unconnected.
Host interrupt (output)
HOST_IRQ indicates when the DLPC34x6 auto-initialization is in progress and most
importantly when it completes.
HOST_IRQ(2)
This pin is tristated during reset. An external pullup must be included on this signal.
I2C secondary (port 0) SCL (bidirectional, open-drain signal with input hysteresis): This pin
requires an external pullup resistor. The secondary I2C I/Os are 3.6-V tolerant (high-voltage-
input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C
pullups must be connected to a host supply with an equal or higher supply voltage, up to a
maximum of 3.6 V (a lower pullup supply voltage does not typically satisfy the VIH
specification of the secondary I2C input buffers).
IIC0_SCL(4)
IIC1_SCL
N10
R11
I/O
I/O
7
8
TI internal use. TI recommends an external pullup resistor.
I2C secondary (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): This pin
requires an external pullup resistor. The secondary I2C port is the control port of controller.
The secondary I2C I/O pins are 3.6-V tolerant (high-volt-input tolerant) and are powered by
VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to a
host supply with an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup
supply voltage does not typically satisfy the VIH specification of the secondary I2C input
buffers).
IIC0_SDA(4)
IIC1_SDA
N9
I/O
I/O
7
8
R10
TI internal use. TI recommends an external pullup resistor.
LED enable select. Automatically controlled by the DLPC34x6 programmable DMD
sequence.
LED_SEL(1:0)
Enabled LED
None
Red
Green
Blue
LED_SEL_0
B15
O
1
00
01
10
11
The controller drives these signals low when RESETZ is asserted and the corresponding I/O
power is supplied. The controller continues to drive these signals low throughout the auto-
initialization process. A weak, external pulldown resistor is recommended to ensure that the
LEDs are disabled when I/O power is not applied.
LED_SEL_1
SPI0_CLK
B14
A13
A14
O
O
O
1
SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to the flash
memory clock.
13
13
SPI port 0, chip select 0 (active low output). This pin is typically connected to the flash
memory chip select.
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device
during controller reset assertion.
SPI0_CSZ0
SPI port 0, chip select 1 (active low output). This pin typically remains unused.
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device
during controller reset assertion.
SPI0_CSZ1
C12
O
13
Synchronous serial port 0, receive data in. This pin is typically connected to the flash
memory data out.
SPI0_DIN
B12
B13
I
12
13
Synchronous serial port 0, transmit data out. This pin is typically connected to the flash
memory data in.
SPI0_DOUT
O
(1) External pullup resistor must be 8 kΩor less.
(2) For more information about usage, see 节7.3.2.
(3) See 表5-3 for type definitions.
(4) When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low which prevents communication
on this I2C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional secondary
devices on this bus.
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5.7 GPIO Peripheral Interface
表5-1. GPIO Peripheral Interface
PIN(1)
I/O TYPE(3)
DESCRIPTION(2)
NAME
NO.
General purpose I/O 19 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_19
M15
I/O
I/O
1
1
General purpose I/O 18 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_18
M14
General purpose I/O 17 (hysteresis buffer). ACT_SYNC (output): Output to FPGA, used for
synchronizing the actuator position with the controller data processing.
GPIO_17
GPIO_16
GPIO_15
GPIO_14
L15
L14
K15
K14
I/O
I/O
I/O
I/O
1
1
1
1
General purpose I/O 16 (hysteresis buffer). SUB_FRAME_2 (input): Input from FPGA, signaling sub-
frames.
General purpose I/O 15 (hysteresis buffer). SUB_FRAME_1 (input): Input from FPGA, signaling sub-
frames.
General purpose I/O 14 (hysteresis buffer). FPGA_RDY (input): Input from FPGA, indicating when the
FPGA initialization process is complete.
General purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_13
GPIO_12
J15
J14
I/O
I/O
1
1
General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
General purpose I/O 11 (hysteresis buffer). Options:
1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and
enabled.
GPIO_11
GPIO_10
H15
H14
I/O
I/O
1
1
2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
General Purpose I/O 10 (hysteresis buffer). Options:
1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.
2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
General purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_09
GPIO_08
G15
G14
I/O
I/O
1
1
General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven
by the PROJ_ON output of the host. A logic low on this signal causes the DLPC34x6 to PARK the
DMD, but it does not power down the DMD (the DLPAxxxx does that instead). At power-up, GPIO_08
must remain high until HOST_IRQ goes low (see 节9.3).
General purpose I/O 07 (hysteresis buffer). If unused TI recommends this pin be configured as a logic
zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to
avoid a floating GPIO input.
GPIO_07
GPIO_06
GPIO_05
F15
F14
E15
I/O
I/O
I/O
1
1
1
General purpose I/O 06 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
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表5-1. GPIO Peripheral Interface (continued)
PIN(1)
NAME
I/O TYPE(3)
DESCRIPTION(2)
NO.
General purpose I/O 04 (hysteresis buffer). Options:
1. 3D glasses control (output): Controls the shutters on 3D glasses (Left = 1, Right = 0).
2. SPI1_CSZ1 (active-low output): Optional SPI1 chip select 1 signal. Requires an external pullup
resistor to deactivate this signal during reset and auto-initialization processes.
3. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
GPIO_04
E14
I/O
1
General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal.
This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to
deactivate this signal during reset and auto-initialization processes.
GPIO_03
D15
I/O
1
General purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is
typically connected to the DLPAxxxx SPI_DIN pin.
GPIO_02
GPIO_01
GPIO_00
D14
C15
C14
I/O
I/O
I/O
1
1
1
General purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically
connected to the DLPAxxxx SPI_CLK pin.
General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is
typically connected to the DLPAxxxx SPI_DOUT pin.
(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or
more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as
open-drain.
(2) General purpose I/O for the DLPC34x6 controllers. These GPIO pins are software configurable.
(3) See 表5-3 for type definitions.
5.8 Clock and PLL Support
PIN
I/O
TYPE(1)
DESCRIPTION
NAME
NO.
Reference clock crystal input. If an external oscillator is used instead of a crystal, use
this pin as the oscillator input.
PLL_REFCLK_I
H1
I
12
5
Reference clock crystal return. If an external oscillator is used instead of a crystal,
leave this pin unconnected (floating with no added capacitive load).
PLL_REFCLK_O
J1
O
(1) See 表5-3 for type definitions.
5.9 Power and Ground
表5-2. Power and Ground
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
C5, D5, D7,
D12, J4,
J12, K3, L4,
L12, M6,
M9, D9,
D13, F13,
H13, L13,
M10, D3, E3
VDD
PWR
PWR
Core 1.1-V power (main 1.1 V)
—
—
VDDLP12
C3
Reserved. Tie to the VDD rail.
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表5-2. Power and Ground (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
C4, D6, D8,
D10, E4,
E13, F4, G4,
G12, H4,
H12, J3,
VSS
GND
Core ground (eDRAM, DSI, I/O ground, thermal ground)
—
J13, K4,
K12, L3, M4,
M5, M8,
M12, G13,
C6, C8
All 1.8-V I/O power:
C7, C9, D4,
E12, F12,
K13, M11
(1.8-V power supply for all I/O pins except the host or parallel interface
and the SPI flash interface. This includes RESETZ, PARKZ, LED_SEL,
CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins)
VCC18
PWR
—
M3, M7, N3,
N7
Host or parallel interface I/O power: 1.8 V (includes IIC0, PDATA, video
syncs, and HOST_IRQ pins)
VCC_INTF
VCC_FLSH
PWR
PWR
—
—
Flash interface I/O power: 1.8 V to 3.3 V
(dedicated SPI0 power pin)
D11
VDD_PLLM
VSS_PLLM
VDD_PLLD
VSS_PLLD
H2
G3
J2
PWR
RTN
PWR
RTN
MCG PLL (primary clock generator phase lock loop) 1.1-V power
MCG PLL return
—
—
—
—
DCG PLL (DMD clock generator phase lock loop) 1.1-V power
DCG PLL return
H3
表5-3. I/O Type Subscript Definition
I/O
SUPPLY REFERENCE
ESD STRUCTURE
SUBSCRIPT
DESCRIPTION
1
2
3
4
5
6
7
8
9
1.8-V LVCMOS I/O buffer with 8-mA drive
1.8-V LVCMOS I/O buffer with 4-mA drive
1.8-V LVCMOS I/O buffer with 24-mA drive
1.8-V sub-LVDS output with 4-mA drive
1.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA drive
1.8-V LVCMOS input
Vcc18
Vcc18
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
Vcc18
Vcc18
Vcc_INTF
Vcc18
Vcc_INTF
Vcc18
1.8-V, 2.5-V, 3.3-V I2C with 3-mA drive
1.8-V I2C with 3-mA drive
1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive
Vcc_INTF
VDD for high speed
transmit, high speed
receive, and low power
receive.
10
LVDS I/O
ESD diode to GND and supply rail
VDDLP12 for low power
transmit
11
12
13
1.8-V, 2.5-V, 3.3-V LVCMOS input
Vcc_INTF
Vcc_FLSH
Vcc_FLSH
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
1.8-V, 2.5-V, 3.3-V LVCMOS input
1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
MAX
UNIT
SUPPLY VOLTAGE(2)
V(VDD)
1.21
1.32
1.96
1.96
3.60
3.60
1.21
1.21
V
V
V
V
V
V
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V(VDDLP12)
V(VCC18)
DMD sub-LVDS interface (DMD_HS_CLK_x and DMD_HS_WDATA_x_y)
V(VCC_INTF)
V(VCC_FLSH)
V(VDD_PLLM) (MCG PLL)
V(VDD_PLLD) (DCG PLL)
VI2C buffer (I/O type 7)
GENERAL
See (3)
V
TJ
Operating junction temperature
Storage temperature
125
125
°C
°C
–30
–40
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to VSS (GND).
(3) I/O is high voltage tolerant; that is, VCC_INTF = 1.8 V, and the input is 3.3-V tolerant.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.045
1.045
NOM
1.10
1.10
MAX
1.155
1.155
UNIT
V
V(VDD)
Core power 1.1 V (main 1.1 V)
Reserved(4)
V(VDDLP12)
V
All 1.8-V I/O power:
(1.8-V power supply for all I/O pins except the host or
parallel interface and the SPI flash interface. This includes
RESETZ, PARKZ LED_SEL, CMP_OUT, GPIO, IIC1,
TSTPT, and JTAG pins.)
V(VCC18)
1.64
1.80
1.96
V
1.64
2.28
1.80
2.50
1.96
2.72
3.58
1.96
2.72
3.58
1.155
1.155
85
Host or parallel interface I/O power: 1.8 V (includes IIC0,
PDATA, video syncs, and HOST_IRQ pins)
V(VCC_INTF)
See (1)
See (1)
V
V
3.02
3.30
1.64
1.80
V(VCC_FLSH)
Flash interface I/O power: 1.8 V to 3.3 V
2.28
2.50
3.02
3.30
V(VDD_PLLM)
MCG PLL 1.1-V power
See (2)
See (2)
1.025
1.025
–30
–30
1.100
1.100
V
V
V(VDD_PLLD)
DCG PLL 1.1-V power
TA
TJ
Operating ambient temperature(3)
°C
°C
Operating junction temperature
105
(1) These supplies have multiple valid ranges.
(2) The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop
across the filter.
(3) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value
at 0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum
estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects RθJA
Thus, maximum operating ambient temperature varies by application.
.
•
•
Ta_min = Tj_min –(Pd_min × RθJA) = –30°C –(0.0 W × 30.3°C/W) = –30°C
Ta_max = Tj_max –(Pd_max × RθJA) = +105°C –(0.348 W × 30.3°C/W) = +94.4°C
(4) VDDLP12 must be tied to the VDD rail.
6.4 Thermal Information
DLPC34x6
ZVB (NFBGA)
176 PINS
11.2
THERMAL METRIC(1)
UNIT
°C/W
°C/W
RθJC
Junction-to-case top thermal resistance
at 0 m/s of forced airflow(2)
at 1 m/s of forced airflow(2)
at 2 m/s of forced airflow(2)
30.3
RθJA
Junction-to-air thermal resistance
27.4
26.6
Temperature variance from junction to package top center temperature, per unit power
dissipation(3)
0.27
°C/W
ψJT
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics Application Report.
(2) Thermal coefficients abide by JEDEC Standard 51. RθJA is the thermal resistance of the package as measured using a JEDEC
defined standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC34x6 PCB and thus the reported
thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different, it is
the best information available during the design phase to estimate thermal performance.
(3) Example: (0.5 W) × (0.2°C/W) ≈0.1°C temperature rise.
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6.5 Power Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3) (4) (5)
TEST CONDITIONS
MIN
TYP(1)
Frame rate = 50 Hz
Input = 1920 x 1080 to FPGA
210
327
mA
354
I(VDD)
I(VDD_PLLM)
I(VDD_PLLD)
+
+
1.1-V rails
Frame rate = 60 Hz
Input = 1920 x 1080 to FPGA
194
6
Frame rate = 50 Hz
Input = 1920 x 1080 to FPGA
I(VDD_PLLM)
I(VDD_PLLD)
I(VCC18)
MCG PLL 1.1-V current(6)
DCG PLL 1.1-V current(6)
mA
mA
Frame rate = 60 Hz
Input = 1920 x 1080 to FPGA
6
Frame rate = 50 Hz
Input = 1920 x 1080 to FPGA
6
Frame rate = 60 Hz
Input = 1920 x 1080 to FPGA
6
Frame rate = 50 Hz
Input = 1920 x 1080 to FPGA
28
28
2
48
All 1.8-V I/O current: (1.8-V power supply
for all I/O other than the host or parallel
interface and the SPI flash interface)
mA
48
Frame rate = 60 Hz
Input = 1920 x 1080 to FPGA
Frame rate = 50 Hz
Input = 1920 x 1080 to FPGA
Host or parallel interface I/O current: 1.8 V
(includes IIC0, PDATA, video syncs, and
HOST_IRQ pins)(6)
I(VCC_INTF)
mA
mA
Frame rate = 60 Hz
Input = 1920 x 1080 to FPGA
2
Frame rate = 50 Hz
Input = 1920 x 1080 to FPGA
1
I(VCC_FLSH)
Flash interface I/O current: 1.8 to 3.3 V(6)
Frame rate = 60 Hz
Input = 1920 x 1080 to FPGA
1
(1) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.
(2) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.
(3) Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum
nominal voltage (that is 1.8 V).
(4) Input image is 1920 × 1080 (1080p) 24 bits using reduced VESA timings on the parallel interface at the frame rate shown with the
0.23-in 1080p (DLP230NP/NPSE ) DMD. The controller has the CAIC and LABB algorithms turned off.
(5) The values do not take into account software updates or customer changes that may affect power performance.
(6) This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor,
30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells.
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6.6 Pin Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER(3)
MIN
TYP
MAX UNIT
CONDITIONS(4)
0.7 ×
VCC_INTF
I2C buffer (I/O type 7)
See
(1)
I/O type 1, 2, 3, 6, 8 except pins
noted in (2)
VCC18 = 1.8 V
1.17
3.6
I/O type 1, 6 for pins noted in (2)
VCC18 = 1.8 V
1.3
1.17
1.17
1.7
3.6
3.6
3.6
3.6
3.6
3.6
3.6
High-level input
threshold voltage
I/O type 5, 9, 11
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
VIH
V
I/O type 12, 13
I/O type 5, 9, 11
I/O type 12, 13
1.7
I/O type 5, 9, 11
2.0
I/O type 12, 13
2.0
0.3 ×
VCC_INTF
I2C buffer (I/O type 7)
–0.5
–0.3
I/O type 1, 2, 3, 6, 8 except pins
noted in (2)
VCC18 = 1.8 V
0.63
I/O type 1, 6 for pins noted in (2)
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
0.5
0.63
0.63
0.7
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
1.35
1.35
1.35
1.7
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
VCC18 = 1.8 V
Low-level input
threshold voltage
VIL
V
I/O type 5, 9, 11
I/O type 12, 13
0.7
I/O type 5, 9, 11
I/O type 12, 13
0.8
0.8
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
VCC_INTF > 2 V
High-level output
voltage
VOH
I/O type 5, 9, 11
I/O type 12, 13
V
1.7
I/O type 5, 9, 11
2.4
I/O type 12, 13
2.4
I2C buffer (I/O type 7)
0.4
0.2 ×
VCC_INTF
I2C buffer (I/O type 7)
VCC_INTF < 2 V
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
I/O type 5, 9, 11
I/O type 12, 13
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
0.45
0.45
0.45
0.7
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
Low-level output
voltage
VOL
V
0.7
0.4
0.4
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MAX UNIT
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6.6 Pin Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER(3)
MIN
TYP
CONDITIONS(4)
I/O type 2, 4
I/O type 5
VCC18 = 1.8 V
2
2
VCC_INTF = 1.8 V
VCC18 = 1.8 V
I/O type 1
3.5
3.5
3.5
10.6
5.4
10.8
10.8
7.8
15
I/O type 9
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC18 = 1.8 V
I/O type 13
I/O type 3
High-level output
current(5)
IOH
mA
I/O type 5
VCC_INTF = 2.5 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
I/O type 9, 13
I/O type 13
I/O type 5
I/O type 9
I/O type 13
I2C buffer (I/O type 7)
I/O type 2, 4
I/O type 5
15
3
VCC18 = 1.8 V
2.3
2.3
4.6
4.6
4.6
13.9
5.2
10.4
10.4
4.4
8.9
8.9
VCC_INTF = 1.8 V
VCC18 = 1.8 V
I/O type 1
I/O type 9
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC18 = 1.8 V
I/O type 13
I/O type 3
Low-level output
current(6)
IOL
mA
I/O type 5
VCC_INTF = 2.5 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
I/O type 9
I/O type 13
I/O type 5
I/O type 9
I/O type 13
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6.6 Pin Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER(3)
MIN
TYP
MAX UNIT
CONDITIONS(4)
VI2C buffer < 0.1 ×
VCC_INTF or
VI2C buffer > 0.9 ×
VCC_INTF
I2C buffer (I/O type 7)
10
–10
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
10
10
–10
–10
–10
–10
–10
–10
–10
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
High-impedance
leakage current
IOZ
µA
10
I/O type 5, 9, 11
I/O type 12, 13
10
10
10
10
5
I/O type 5, 9, 11
I/O type 12, 13
I2C buffer (I/O type 7)
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
2.6
2.6
2.6
2.6
2.6
2.6
2.6
3.5
3.5
3.5
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
I/O type 5, 9, 11
I/O type 12, 13
3.5
pF
Input capacitance
(including package)
CI
3.5
3.5
3.5
I/O type 5, 9, 11
I/O type 12, 13
Sub-LVDS –DMD high speed
(I/O type 4)
VCC18 = 1.8 V
3
(1) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.
(2) Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied VIH and VIL range from other 1.8-V
I/O.
(3) The I/O type refers to the type defined in 表5-3.
(4) Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O's supply
reference is set to.
(5) At a high level output signal, the given I/O will be able to output at least the minimum current specified.
(6) At a low level output signal, the given I/O will be able to sink at least the minimum current specified.
6.7 Internal Pullup and Pulldown Electrical Characteristics
over operating free-air temperature (unless otherwise noted) (2)
TEST
INTERNAL PULLUP AND PULLDOWN RESISTOR CHARACTERISTICS
MIN
MAX
UNIT
CONDITIONS(1)
VCCIO = 3.3 V
VCCIO = 2.5 V
VCCIO = 1.8 V
VCCIO = 3.3 V
VCCIO = 2.5 V
VCCIO = 1.8 V
29
38
56
30
36
52
63
90
Weak pullup resistance
kΩ
148
72
Weak pulldown resistance
101
167
kΩ
(1) The resistance is dependent on VCCIO, the pin's supply reference (see a given pins supply reference in 表5-3).
(2) An external 8-kΩpullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any
associated internal pullups or pulldowns.
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6.8 DMD Sub-LVDS Interface Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VCM
Common mode voltage
0.8
0.9
1.0
75
VCM (Δpp)(1)
VCM change peak-to-peak (during switching)
VCM change steady state
mV
mV
mV
mV
V
VCM (Δss)(1)
–10
170
10
(2)
|VOD
|
Differential output voltage magnitude
VOD change (between logic states)
Single-ended output voltage high
Single-ended output voltage low
Internal differential termination
250
350
10
VOD (Δ)
VOH
–10
0.825
0.625
80
1.025
0.775
100
1.175
0.975
120
VOL
V
Txterm
Ω
100-Ωdifferential PCB trace
(50-Ωtransmission lines)
Txload
0.5
6
in
(1) See 图6-1.
(2) VOD is the differential voltage measured across a 100-Ωtermination resistance connected directly between the transmitter differential
pins. VOD = VP –VN, where P and N are the differential output pins. |VOD| is the magnitude of the peak-to-peak voltage swing across
the P and N output pins (see 图6-2). VCM cancels out between signals when measured differentially, thus the reason VOD swings
relative to zero.
+V
OD
100
90
80
|VOD
|
70
60
V
(û
CM SS
)
V
(û )
CM P-P
V
CM
(0 V) 50
40
30
|VOD
|
20
10
0
œV
OD
tFALL
tRISE
图6-1. Common Mode Voltage
VCM is removed when the signals are viewed differentially.
图6-2. Differential Output Signal
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6.9 DMD Low-Speed Interface Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC output high voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.7 ×
VCC18
VOH(DC)
VOL(DC)
VOH(AC)
VOL(AC)
V
DC output low voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.3 ×
VCC18
V
V
V
AC output high voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.8 ×
VCC18
VCC18 +
0.5
(1)
(2)
AC output low voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.2 ×
VCC18
–0.5
VOL(DC) to VOH(AC) for rising edge
and VOH(DC) to VOL(AC) for rising
edge
DMD_LS_WDATA and DMD_LS_CLK
1.0
3.0
Slew rate
V/ns
DMD_DEN_ARSTZ
DMD_LS_RDATA
VOL(AC) to VOH(AC) for rising edge
0.25
0.5
(1) VOH(AC) maximum applies to overshoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries
termination resistor, the DMD operates within the LPSDR input AC specifications.
(2) VOL(AC) minimum applies to undershoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries
termination resistor, the DMD operates within the LPSDR input AC specifications.
(3) See 图6-3 for DMD_LS_CLK, and DMD_LS_WDATA rise and fall times. See 图6-4 for DMD_DEN_ARSTZ rise and fall times.
DMD_DEN_ARSTZ
LS_CLK, LS_WDATA
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
V
V
V
OH(AC)
OH(AC)
OH(DC)
V
OL(DC)
V
V
OL(AC)
OL(AC)
10
0
10
0
tRISE
tFALL
tRISE
tFALL
图6-3. LS_CLK and LS_WDATA Slew Rate
图6-4. DMD_DEN_ARSTZ Slew Rate
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6.10 System Oscillator Timing Requirements
MIN
23.998
41.663
NOM
24.000
41.667
MAX
UNIT
MHz
ns
fclk
tc
Clock frequency, MOSC (primary oscillator clock)(1)
Cycle time, MOSC (clock period)(1)
24.002
41.670
See 图6-5
50% to 50% reference
points (signal)
tw(H)
tw(L)
Pulse duration as percent of tc (2), MOSC, high
Pulse duration as percent of tc (2), MOSC, low
40%
40%
50%
50%
50% to 50% reference
points (signal)
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
tt
Transition time(2), MOSC
10
ns
Long-term, peak-to-peak, period jitter(2), MOSC
(that is the deviation in period from ideal period due
solely to high frequency jitter)
tjp
2%
(1) The frequency accuracy for MOSC is ±200 PPM. This includes impact to accuracy due to aging, temperature, and trim sensitivity. The
MOSC input does not support spread spectrum clock spreading.
(2) Applies only when driven by an external digital oscillator.
tt
tt
tc
tw(H)
tw(L)
80%
20%
80%
20%
50%
50%
MOSC
50%
图6-5. System Oscillators
6.11 Power Supply and Reset Timing Requirements
MIN
MAX
UNIT
µs
tw(L)
tr
Pulse duration, active low, RESETZ
Rise time, RESETZ(1)
50% to 50% reference points (signal)
20% to 80% reference points (signal)
80% to 20% reference points (signal)
1.25
0.5
0.5
µs
tf
Fall time, RESETZ(1)
µs
Rise time, VDD (during VDD ramp up at
turn-on)
trise
0.3 V to 1.045 V (VDD)
1
ms
(1) For more information on RESETZ, see 节5 .
DC Power Supplies
tf
tr
80%
50%
20%
80%
50%
20%
RESETZ
tw(L)
tw(L)
tw(L)
Time
图6-6. Power-Up and Power-Down RESETZ Timing
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6.12 Parallel Interface Frame Timing Requirements
See 节11.1.2.3 for additional information.
MIN
MAX
UNIT
tp_vsw
tp_vbp
50% reference points
50% reference points
1
lines
Pulse duration –default VSYNC_WE high
Vertical back porch (VBP) –time from the active edge of
VSYNC_WE to the active edge of HSYNC_CS for the first
active line(1)
2
1
lines
lines
Vertical front porch (VFP) –time from the active edge of the
HSYNC_CS following the last active line in a frame to the active
edge of VSYNC_WE(1)
tp_vfp
50% reference points
Total vertical blanking –the sum of VBP and VFP (tp_vbp
tp_vfp
+
tp_tvb
tp_hsw
tp_hbp
50% reference points
50% reference points
50% reference points
See (1)
lines
)
4
4
128
PCLKs
PCLKs
Pulse duration –default HSYNC_CS high
Horizontal back porch (HBP) –time from the active edge of
HSYNC_CS to the rising edge of DATAEN_CMD
Horizontal front porch (HFP) –time from the falling edge of
DATAEN_CMD to the active edge of HSYNC_CS
tp_hfp
50% reference points
8
PCLKs
(1) The minimum total vertical blanking is defined by the following equation: tp_tvb(min) = 6 + [8 × Max(1, Source_ALPF / DMD_ALPF)]
lines
where:
•
•
SOURCE_ALPF = Input source active lines per frame
DMD_ALPF = Actual DMD used lines per frame supported
1 Frame
tp_vsw
VSYNC_WE
(This diagram assumes the VSYNC
active edge is the rising edge)
tp_vbp
tp_vfp
HSYNC_CS
DATAEN_CMD
1 Line
tp_hsw
HSYNC_CS
(This diagram assumes the HSYNC
active edge is the rising edge)
tp_hbp
tp_hfp
DATAEN_CMD
PDATA(23/15:0)
PCLK
P
n-2
P
n-1
P0
P1
P2
P3
Pn
图6-7. Parallel Interface Frame Timing
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6.13 Parallel Interface General Timing Requirements
MIN
1.0
MAX
UNIT
MHz
ns
PCLK frequency
PCLK period
155.0
1000
ƒclock
tp_clkper
tp_clkjit
tp_wh
50% reference points
Max ƒclock
6.45
PCLK jitter
See (1)
PCLK pulse duration high
PCLK pulse duration low
50% reference points
50% reference points
2.43
2.43
ns
ns
tp_wl
Setup time –HSYNC_CS, DATAEN_CMD,
PDATA(23:0) valid before the active edge of PCLK
tp_su
tp_h
50% reference points
50% reference points
0.9
0.9
ns
ns
Hold time –HSYNC_CS, DATAEN_CMD,
PDATA(23:0) valid after the active edge of PCLK
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
tt
0.2
2.0
ns
Transition time –all signals
tsetup, 3DR
thold, 3DR
This is the setup time with respect to VSYNC(2)
This is the hold time with respect VSYNC(3)
50% reference points
50% reference points
1.0
1.0
ms
ms
(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock –5.76 ns]. Setup and hold times must be met even with clock jitter.
(2) In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes.
(3) In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes.
tp_clkper
tp_wh
tp_wl
PCLK
tp_h
tp_su
图6-8. Parallel Interface Pixel Timing
6.14 Flash Interface Timing Requirements
The DLPC34xx flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The
DLPC34x6 can support 1- to 128-Mb flash memories.(2) (3) (4)
MIN
MAX
36.0
704
UNIT
MHz
ns
fclock
SPI_CLK frequency
See (1)
1.4
tp_clkper
tp_wh
tp_wl
SPI_CLK period
50% reference points
50% reference points
50% reference points
27.8
352
352
SPI_CLK pulse duration high
SPI_CLK pulse duration low
ns
ns
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
tt
0.2
3.0
1.0
ns
Transition time –all signals
Setup time –SPI_DIN valid before SPI_CLK falling
edge
tp_su
tp_h
50% reference points
50% reference points
50% reference points
10.0
0.0
ns
ns
ns
Hold time –SPI_DIN valid after SPI_CLK falling edge
SPI_CLK clock falling edge to output valid time –
SPI_DOUT and SPI_CSZ
tp_clqv
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The DLPC34xx flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The
DLPC34x6 can support 1- to 128-Mb flash memories.(2) (3) (4)
MIN
MAX
UNIT
SPI_CLK clock falling edge output hold time –
SPI_DOUT and SPI_CSZ
tp_clqx
50% reference points
3.0
ns
–3.0
(1) This range include the ±200 ppm of the external oscillator (but no jitter).
(2) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC34x6 transmits
data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI devices
with long clock-to-Q timing. DLPC34xx hold capture timing has been set to facilitate reliable operation with standard external SPI
protocol devices.
(3) With the above output timing, DLPC34xx provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the
rising edge of SPI_CLK.
(4) For additional requirements of the external flash device, view the 节7.3.3.1 section.
tCLKPER
SPI_CLK
(Controller output)
tWL
tWH
tP_SU
tP_H
SPI_DIN
(Controller input)
tP_CLQV
SPI_DOUT, SPI_CS(1:0)
(Controller output)
tP_CLQX
图6-9. Flash Interface Timing
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6.15 Other Timing Requirements
MIN
MAX
UNIT
ns
trise, all(1) (2)
20% to 80% reference points
80% to 20% reference points
20% to 80% reference points
80% to 20% reference points
10
10
tfall, all(1) (2)
ns
trise, PARKZ(2)
150
150
ns
tfall, PARKZ(2)
ns
tw, GPIO_08 (normal park) pulse width low(3)
I2C baud rate
200
ms
kHz
100
(1) Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.
(2) This is the recommended signal transition time to avoid input buffer oscillations.
(3) When the controller is turned off by setting PROJ_ON low, PROJ_ON must not be brought high again for at least 200 ms. View 节9.3
for additional requirements.
6.16 DMD Sub-LVDS Interface Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
45%
MIN
TYP
MAX
250
UNIT
ps
(1)
(1)
tR
tF
Differential output rise time
Differential output fall time
DMD HS clock switching rate
DMD HS clock frequency
DMD HS clock output duty cycle
250
ps
tswitch
fclock
1200
600
Mbps
MHz
DCout
50%
55%
(1) Rise and fall times are defined for the differential VOD signal as shown in 图6-2.
6.17 DMD Parking Switching Characteristics
See (2)
PARAMETER
Normal park time(1)
Fast park time(3)
TEST CONDITIONS
TYP
MAX
20
UNIT
ms
tpark
tfast park
32
µs
(1) Normal park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the
normal park request (GPIO_08 goes low).
(2) The oscillator and power supplies must remain active for at least the duration of the park time. The power supplies must additionally be
held on for a time after parking is completed to satisfy DMD requirements. See 节9.2 and the appropriate DMD or PMIC data sheet for
more information.
(3) Fast park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the fast
park request (PARKZ goes low).
6.18 Chipset Component Usage Specification
The DLPC34x6 is a component of a DLP chipset. Reliable function and operation of the DLP chipset requires
that it be used with all components (DMD, PMIC, and controller) of the applicable DLP chipset.
表6-1. DLPC3436 Supported DMDs and PMICs
DLPC3436 DLP Chipset
DMD
PMIC
DLP230NP
DLPA2000
DLPA2005
DLPA3000
DLPA3005
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表6-2. DLPC3426 Supported DMDs and PMICs
DLPC3426 DLP Chipset
DMD
PMIC
DLP230NPSE
DLPA3000
In addition to the required DLP chipset, the XC7Z020-1CLG484I4493 FPGA is required to be used in
conjunction with this particular DLP chipset.
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7 Detailed Description
7.1 Overview
The DLPC3436 and DLPC3426 are the display controllers for the DLP230NP/NPSE .23 1080p digital
micromirror devices (DMD). The DLPC34x6 controller is part of the chipset that contains the DLPC34x6
controller, the DLP230NP/NPSE (.23 1080p ) DMD, and one of the DLPA2000, DLPA2005, DLPA3000, or
DLPA3005 PMIC/LED drivers. All three components of the chipset must be used in conjunction with each other,
along with the XC7Z020-1CLG484I4493 FPGA, for reliable operation of the .23 1080p DMD. The DLPC34x6
display controller provides interfaces and data/image processing functions that are optimized for small form
factor and power-constrained display applications. Applications include smartphones, tablets, laptops, battery-
powered mobile accessories, wearable (near-eye) displays, smart home displays, and smart speakers. An
application processor is needed to interface with the DLP Pico display subsystem.
7.2 Functional Block Diagram
Test
Pattern
Generator
Video Processing
ñ
ñ
ñ
ñ
ñ
Brightness Enhancement
Chroma Interpolation
Color Space Conversion
Color Correction
ñ
ñ
ñ
ñ
ñ
Contrast Adjust
Dynamic Scaling
/
Input
Control
Processing
Parallel Video
Gamma Correction
Image Format Processing
Power Saving Operations
Splash
Screen
CAIC Processing
DLP Subsystem
Display Formatting
eDRAM (Frame Memory)
Arm® Cortex®-M3
Processor
128 KB I/D Memory
JTAG
I2C_0
/
/
/
Real Time
Control System
SPI_0
DMD_HS_CLK
(LVDS)
DMD_HS_DATA(A:H)
/
(LVDS)
DMD Interface
DMD_LS_CLK
SPI_1
I2C_1
LED Control
Other options
Clocks and Reset
Generation
DMD_LS_WDATA
DMD_LS_RDATA
/20
GPIO
DMD_DEN_ARSTZ
Clock (Crystal)
Reset Control
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7.3 Feature Description
7.3.1 Input Source Requirements
7.3.1.1 Input Frame Rates and 3-D Display Operation
表7-1. Supported Input Source Ranges (to FPGA)(1) (2) (3)
SOURCE RESOLUTION RANGE(5)
HORIZONTAL VERTICAL
Landscape Portrait Landscape Portrait
BITS PER
FRAME RATE
RANGE
INTERFACE
IMAGE TYPE
PIXEL (max)(4)
50 ± 2 Hz,
60 ± 2 Hz,
100 ± 2 Hz,
120 ± 2 Hz,
200 ± 2 Hz,
240 ± 2 Hz
Parallel
24
2D - qHD
960
N/A
540
N/A
50 ± 2 Hz,
60 ± 2 Hz
Parallel
Parallel
24
24
2D - 1080p
3D - qHD(6)
1920
960
N/A
N/A
1080
540
N/A
N/A
100 ± 2 Hz,
120 ± 2 Hz
(1) The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line
rate.
(2) The maximum DMD pixel display resolution is 1920 × 1080 while system actuator is enabled.
(3) To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to
determine the latest available frame rate and input resolution support for a given firmware image.
(4) Bits per pixel does not necessarily equal the number of data pins used on the DLPC34xx controller. Fewer pins are used if multiple
clocks are used per pixel transfer.
(5) The DLPC34x6 only supports landscape orientation.
(6) 3D video is formatted as frame sequential.
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The DLPC34x6 supports both 2D and 3D sources on the parallel interface. The frame and sub-frame timing for
2D sources is shown in 图7-1 while the frame timing for 3D sources is shown in 图7-3.
tVSYNC_PRD
IN_VSYNC
IN_3DR
Don‘t Care (3D processing not available when actuator is enabled)
FPGA
Input
Frame 1
( 1920 × 1080 )
IN_DATA
Frame 2
OUT_VSYNC
OUT_3DR
Don‘t Care
FPGA
Output
and
Controller
Input
Frame 1
Subframe A
( 960 × 540 )
Frame 1
Subframe B
( 960 × 540 )
Frame 1
Subframe C
( 960 × 540 )
Frame 1
Subframe D
( 960 × 540 )
Output data
SUB_FRAME_REF
SUB_FRAME_REF
Frame 1
Subframe A
( 960 × 540 )
Frame 1
Subframe B
( 960 × 540 )
Frame 1
Subframe C
( 960 × 540 )
DMD_Data
Controller
Output
ACT_SYNC
Position A
Position B
Position C
Actuator Position
图7-1. 2D Actuator Frame and Signal Timing
7.3.1.1.1 Parallel Interface Data Transfer Format
The data format on the PDATA(23:0) bus between the XC7Z020-1CLG484I4493 FPGA and the DLPC34x6 is
always RGB888, as shown in 图7-2.
23
0
Red / Cr
Green / Y
Blue / Cb
Controller input mapping
7
6
6
5
4
3
2
2
1
1
0
0
7
7
6
6
5
4
3
2
2
1
1
0
0
7
7
6
6
5
5
4
3
2
1
1
0
Controller internal re-mapping
7
5
4
3
5
4
3
4
3
2
0
Red / Cr
Green / Y
Blue / Cb
图7-2. RGB-888 I/O Mapping
It is possible to use image formats outside of RGB888, as well as FPD-Link as an alternative to parallel video
input to the FPGA. When parallel video is used, formatting is preserved from the FPGA to the DLPC34x6
controller. When FPD-Link is used, video data is converted in the FPGA to RGB888 parallel video before being
sent to the DLPC34x6 controller. In cases where parallel formats less than 24 bits are used, each color channel
should have all input bits be MSB-aligned. LSBs will be treated by the FPGA as zeroes and passed through to
the DLPC34x6 controller appropriately. For more information, refer to the DLPC34x6 Board Reference Design
Schematics found on the DLPC3436 product page and the DLPC3426 product page .
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7.3.1.2 3D Display
For 3D sources on the parallel or MIPI DSI interface, images must be frame sequential (L, R, L, ...) when input to
the DLPC34x6 controller. Any processing required to unpack 3D images and to convert them to frame sequential
input must be done by external electronics prior to inputting the images to the controller. Each 3D source frame
input must contain a single eye frame of data, separated by a VSYNC, where an eye frame contains image data
for a single left or right eye. The signal 3DR input to the controller indicates whether the input frame is for the left
eye or right eye.
Each DMD frame is displayed at the same rate as the input interface frame rate. 图 7-3 shows the typical timing
for a 50-Hz or 60-Hz 3D HDMI source frame, the input interface of the DLPC34x6 controller, and the DMD. In
general, video frames sent over the HDMI interface pack both the left and right content into the same video
frame. GPIO_04 is optionally sent to a transmitter on the system PCB for wirelessly transmitting a
synchronization signal to 3D glasses (usually an IR sync signal). The glasses are then in phase with the DMD
images displayed. Alternately, 节7.3.7 shows how DLP link pulses can be used instead.
tVSYNC_PRD
100 Hz or 120 Hz
FPGA IN_VSYNC
FPGA IN_3DR
FPGA
Input
Frame 1, Left Eye
( 960 × 540 )
FPGA IN_DATA
Frame 2, Right Eye
Frame 3, Left Eye
FPGA OUT_VSYNC
FPGA OUT_3DR
FPGA
Output
&
ASIC
Input
Frame 1, Left Eye
( 960 × 540 )
FPGA OUTPUT DATA
Frame 2, Right Eye
Frame 3, Left Eye
Frame 1, Left Eye
( 960 × 540 )
FPGA
P_DATA_L_(0:23)
Frame 2, Right Eye
ASIC
Output
ACT_SYNC
Don‘t Care
Actuator Position
Don‘t Care
(1) Left = 1, Right = 0
(2) 3DR must toggle at least 1 ms before VSYNC
图7-3. 3D Frame and Signal Timing
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7.3.2 Device Startup
• The HOST_IRQ signal is provided to indicate when the system has completed auto-initialization.
• While reset is applied, HOST_IRQ is tristated (an external pullup resistor pulls the line high).
• HOST_IRQ remains tristated (pulled high externally) until the boot process completes. While the signal is
pulled high, this indicates that the controller is performing boot-up and auto-initialization.
• As soon as possible after the controller boots-up, the controller drives HOST_IRQ to a logic high state to
indicate that the controller is continuing to perform auto-initialization (no real state changes occur on the
external signal).
• The software sets HOST_IRQ to a logic low state at the completion of the auto-initialization process. At the
falling edge of the signal, the initialization is complete.
• The DLPC34x6 controller is ready to receive commands through I2C or accept video over the parallel
interface only after auto-initialization is complete.
• The controller initialization typically completes (HOST_IRQ goes low) within 2.94 s of RESETZ being
asserted. However, this time may vary (typically up to 0.3 s) depending on the software version and the
contents of the user configurable auto initialization file.
RESETZ
auto-initialization
HOST_IRQ
(with external pullup)
(INIT_BUSY)
t0
t1
t0: rising edge of RESETZ; auto-initialization begins
t1: falling edge of HOST_IRQ; auto-initialization is complete
图7-4. HOST_IRQ Timing
7.3.3 SPI Flash
7.3.3.1 SPI Flash Interface
The DLPC34x6 controller requires an external SPI serial flash memory device to store the firmware. Follow the
below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing
Requirements section.
The controller supports a maximum flash size of 128 Mb (16 MB). See 表 7-5 for example compatible flash
options. The minimum required flash size depends on the size of the utilized firmware. The firmware size
depends upon a variety of factors including the number of sequences, lookup tables, and splash images.
The DLPC34x6 controller uses a single SPI interface that complies to industry standard SPI flash protocol. The
device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate.
The flash device must support these rates.
The controller has two independent SPI chip select (CS) control lines. Ensure the flash device's chip select pin is
connected to SPI0_CSZ0 as the controller's boot routine is executed from the device connected to chip select
zero. The boot routine uploads program code from flash memory to program memory then transfers control to an
auto-initialization routine within program memory.
The DLPC34x6 is designed to support any flash device that is compatible with the modes of operation, features,
and performance as defined in 表7-2, 表7-3, and 表7-4.
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表7-2. Additional DLPC34x6 SPI Flash Requirements
FEATURE
DLPC34x6 REQUIREMENT
SPI interface width
SPI polarity and phase settings
Fast READ addressing
Programming mode
Page size
Single
SPI mode 0
Auto-incrementing
Page mode
256 B
Sector size
4-KB sector
Any
Block size
Block protection bits
Status register bit(0)
Status register bit(1)
Status register bits(6:2)
Status register bit(7)
0 = Disabled
Write in progress (WIP), also called flash busy
Write enable latch (WEN)
A value of 0 disables programming protection
Status register write protect (SRWP)
Because the DLPC34x6 controller supports only single-byte status register R/W command
execution, it may not be compatible with flash devices that contain an expansion status byte.
However, as long as the expansion status byte is considered optional in the byte 3 position and any
write protection control in this expansion status byte defaults to unprotected, then the flash device is
likely compatible with the DLPC34x6 .
Status register bits(15:8)
(that is expansion status byte)
The DLPC34x6 controller is intended to support flash devices with program protection defaults of either enabled
or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as
part of the boot process.
The DLPC34x6 issues these commands during the boot process:
• A write enable (WREN) instruction to request write enable, followed by
• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8
bits (this disables all programming protection)
Prior to each program or erase instruction, the DLPC34x6 controller issues similar commands:
• A write enable (WREN) instruction to request write enable, followed by
• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
• After the write enable latch (WEL) bit is set, the program or erase instruction
Note that the flash device automatically clears the write enable status after each program and erase instruction.
表 7-3, and 表 7-4 list the specific instruction OpCode and timing compatibility requirements. The DLPC34x6
controller does not adapt protocol or clock rate based on the flash type connected.
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表7-3. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements
BYTE 1
(OPCODE)
SPI FLASH COMMAND
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Fast READ (1 output)
Read status
0x0B
0x05
0x01
0x06
0x02
0x20
0xC7
ADDRS(0)
N/A
ADDRS(1)
N/A
ADDRS(2)
STATUS(0)
dummy
DATA(0)(1)
Write status
STATUS(0)
See (2)
Write enable
Page program
Sector erase (4 KB)
Chip erase
ADDRS(0)
ADDRS(0)
ADDRS(1)
ADDRS(1)
ADDRS(2)
ADDRS(2)
DATA(0)(1)
(1) Shows the first data byte only. Data continues.
(2) Access to a second (expansion) write status byte not supported by the DLPC34x6 controller.
表 7-4 and the Flash Interface Timing Requirements section list the specific timing compatibility requirements for
a DLPC34x6 compatible flash device.
表7-4. SPI Flash Key Timing Parameter Compatibility Requirements
SPI FLASH TIMING PARAMETER (1) (2)
SYMBOL
ALTERNATE SYMBOL
MIN
MAX
UNIT
Access frequency (all commands)
FR
fC
MHz
≤1.4
≥30.1
Chip select high time (also called chip select
deselect time)
tSHSL
tCSH
ns
≤200
≥0
Output hold time
tCLQX
tCLQV
tDVCH
tCHDX
tHO
tV
tDSU
tDH
ns
ns
ns
ns
Clock low to output valid time
Data in set-up time
Data in hold time
≤11
≤5
≤5
In order for the DLPC34x6 controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin
must be supplied with the corresponding voltage. 表 7-5 contains a list of validated 1.8-V, 2.5-V, or 3.3-V
compatible SPI serial flash devices supported by the DLPC34x6 controller.
表7-5. DLPC34x6 Compatible SPI Flash Device Options (3.3-V Compatible Devices)(1)
DVT(2)
Yes
DENSITY (Mb)
VENDOR
Winbond
Winbond
PART NUMBER
W25Q32FVSSIG
W25Q64FVSSIG
PACKAGE SIZE
32 Mb
5.2 mm × 7.9 mm, 8-pin SOIC
5.2 mm × 7.9 mm, 8-pin SOIC
Yes
64 Mb
(1) The flash supply voltage must match VCC_FLSH on the DLPC34x6 . Special attention needs to be paid when ordering devices to be
sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.
(2) All of the flash devices shown are compatible with the DLPC34x6 , but only those marked with yes in the DVT column have been
validated during TI validation testing using a TI reference design. Those marked with no can be used at the ODM’s own risk. Other
parts than those shown can be used if the timing conditions are met.
7.3.3.2 SPI Flash Programming
The SPI pins of the flash can directly be driven for flash programming while the DLPC34xx controller I/Os are tri-
stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state
while power is applied to the controller. The logic state of the SPI0_CSZ1 pin is not affected by this action.
Alternatively, the DLPC34xx controller can program the SPI flash itself when commanded via I2C if a valid
firmware image has already been loaded and the controller is operational.
7.3.4 I2C Interface
Both of the DLPC34xx I2C interface ports support a 100-kHz baud rate. Because I2C interface transactions
operate at the speed of the slowest device on the bus, there is no requirement to match the speed of all devices
in the system.
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7.3.5 Content Adaptive Illumination Control (CAIC)
Content Adaptive Illumination control (CAIC) is part of the IntelliBright® suite of advanced image processing
algorithms that adaptively enhances brightness and reduces power. In common, real-world image content, most
pixels in the images are well below fullscale for the for the R (red), G (green), and B (blue) digital channels input
to the DLPC34xx. As a result of this, the average picture level (APL) for the overall image is also well below full
scale, and the dynamic range for the collective set of pixel values is not fully used. CAIC takes advantage of the
headroom between the source image APL and the top of the available dynamic range of the display system.
CAIC evaluates images on a frame-by-frame basis and derives three unique digital gains, one for each of the R,
G, and B color channel. During image processing, CAIC applies each gain to all pixels in the associated color
channel. The calculated gain is applied to all pixels in that channel so that the pixels as a group collectively shift
upward and as close to full scale as possible. To prevent any image quality degradation, the gains are set at the
point where just a few pixels in each color channel are clipped. The Source Pixels for a Color Channel and
Pixels for a Color Channel After CAIC Processing figures below show an example of the application of CAIC for
one color channel.
Single-pixel
Headroom
255
255
APL Headroom
Clipped
to 255
166
110
Time
Time
(1) APL = 110
.
(1) APL = 166
(2) Channel gain = 166/110 = 1.51
图7-5. Source Pixels for a Color Channel
图7-6. Pixels for a Color Channel After CAIC
Processing
Above, 图 7-6 shows the gain that is applied to a color processing channel inside the DLPC34xx. Additionally,
CAIC adjusts the power for the R, G, and B LED by commanding different LED currents. For each color channel
of an individual frame, CAIC intelligently determines the optimal combination of digital gain and LED power. The
user configurable CAIC settings heavily influence the amount of digital gain that is applied to a color channel and
the LED power for that color.
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0.33
0.22
0.18
(1)
CAIC Disabled
= 1 W
CAIC Enabled
P = 0.73 W
TOTAL
P
TOTAL
(1) With CAIC enabled, if red and blue LEDs require less than nominal power for a given input image, the red and blue LED power will
reduce.
图7-7. CAIC Power Reduction Mode (for Constant Brightness)
As CAIC applies a digital gain to each color channel and adjusts the power to each LED, CAIC ensures the
resulting color balance in the final image matches the target color balance for the projector system. Thus, the
effective displayed white point of images is held constant by CAIC from frame to frame.
CAIC can be used to increase the overall image brightness while holding the total power for all LEDs constant,
or CAIC can be used to hold the overall image brightness constant while decreasing LED power. In summary,
CAIC has two primary modes of operation:
• Power reduction mode holds overall image brightness constant while reducing LED power
• Enhanced brightness mode holds overall LED power constant while enhancing image brightness
In power reduction mode, since the R, G, and B channels can be gained up by CAIC inside the DLPC34xx, the
LED power can be reduced for any color channel until the brightness of the color on the screen is unchanged.
Thus, CAIC can achieve an overall LED power reduction while maintaining the same overall image brightness as
if CAIC was not used. 图 7-7 shows an example of LED power reduction by CAIC for an image where the red
and blue LEDs can consume less power.
In enhanced brightness mode the R, G, and B channels can be gained up by CAIC with LED power generally
being held constant. This results in an enhanced brightness with no power savings.
While there are two primary modes of operation described, the DLPC34xx actually operates within the extremes
of pure power reduction mode and enhanced brightness mode. The user can configure which operating mode
the DLPC34xx will more closely follow by adjusting the CAIC gain setting as described in the software
programmer's guide.
In addition to the above functionality, CAIC also can be used as a tool with which FOFO (full-on full-off) contrast
on a projection system can be improved. While operating in power reduction mode, the DLPC34xx reduces LED
power as the intensity of the image content for each color channel decreases. This will result in the LEDs
operating at nominal settings with full-on content (a white screen) and reducing power output until the dimmest
possible content (a black screen) is reached. In this latter case, the LEDs will be operating at minimum power
output capacity and thus producing the minimum possible amount of off-state light. This optimization provided by
CAIC will thereby improve FOFO contrast ratio. The given contrast ratio will further increase as nominal LED
current (full-on state) is increased.
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7.3.6 Local Area Brightness Boost (LABB)
Local area brightness boost (LABB), part of the IntelliBright™ suite of advanced image processing algorithms,
adaptively gains up regions of an image that are dim relative to the average picture level. The controller applies
significant gain to some regions of the image, and applies little or no gain to other regions. The LABB algorithm
evaluates images frame-by-frame and calculates the local area gains to be used for each image. Since many
images have a net overall boost in gain, even if the controller applies no gain to some parts of the image, the
controller boosts the overall perceived brightness of the image.
图7-8 shows a split screen example of the impact of the LABB algorithm for an image that includes dark areas.
图7-8. LABB Enabled (Left Side) and LABB Disabled (Right Side)
The LABB algorithm operates most effectively when ambient light conditions are used to help determine the
decision about the strength of gains utilized. For this reason, it may be useful to include an ambient light sensor
in the system design that is used to measure the display screen's reflected ambient light. This sensor can assist
in dynamically controlling the LABB strength. Set the LABB gain higher for bright rooms to help overcome
washed out images. Set the LABB gain lower in dark rooms to prevent overdriven pixel intensities in images.
7.3.7 3D Glasses Operation
When using 3D glasses (with 3D video input and appropriate software support), the controller outputs sync
information to align the left eye and right eye shuttering in the glasses with the displayed DMD image frames. 3D
glasses typically use either Infrared (IR) transmission or DLP Link™ technology to achieve this synchronization.
One glasses type uses an IR transmitter on the system PCB to send an IR sync signal to an IR receiver in the
glasses. In this case, the DLPC34xx controller output signal GPIO_04 can be used to cause the IR transmitter to
send an IR sync signal to the glasses. 图7-9 shows the timing sequence for the GPIO_04 signal.
The second type of glasses relies on sync information that is encoded into the light that is output from the
projection lens. This approach uses the DLP Link feature for 3D video. Many 3D glasses from different suppliers
are built using this method. The advantage of using the DLP Link feature is that it takes advantage of existing
projector hardware to transmit the sync information to the glasses. This method may give an advantage in cost,
size, and power savings in the projector.
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When using DLP Link technology, one light pulse per DMD frame is output from the projection lens while the
glasses have both shutters closed. To achieve this, the DLPC34xx tells the DLPAxxxx when to turn on the
illumination source (typically LEDs or lasers) so that an encoded light pulse is output once per DMD frame.
Because the shutters in the glasses are both off when the pulse is sent, the projector illumination source is also
off except when the light is sent to create the pulse. The pulses may use any color; however, due to the
transmission property of the eye-glass LCD shutter lenses and the sensitivity of the white-light sensor used on
the eye-glasses, it is highly recommended that blue is not used for pulses. Red pulses are the recommended
color to use. 图 7-9 shows 3D timing information. 图 7-10 and 表 7-6 show the timing for the light pulses when
using the DLP Link feature.
50 Hz or 60 Hz
(HDMI)
L
R
L
R
L
R
L
R
L
R
L
R
100 Hz or 120 Hz
(34xx Input)
L
R
L
R
L
R
L
R
L
R
L
R
3DR (1)(2)
(3D L/R input)
100 Hz or 120 Hz
(on DMD)
R
L
R
L
R
L
R
L
R
L
R
L
GPIO_04 (1)
(3D L/R output)
0 µs (min)
5 µs (max)
GPIO_04
LED_SEL_0, LED_SEL_1
Video
Video
On DMD
Dark time
t1
t2
(1) Left = 1, Right = 0
(2) 3DR must toggle 1 ms before VSYNC.
t1: both shutters turned off.
t2: next shutter turned on.
图7-9. 3D Display Left and Right Frame and Signal Timing
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video data on subframe n
video data on subframe n+1
3D glasses shutter
E
A
C
B
D
A
Video
Video
t1
t2
The time offset of DLP Link pulses at the end of a subframe alternates between B and B+D where D is the delta offset.
图7-10. 3D DLP Link Pulse Timing
表7-6. 3D DLP Link Timing
HDMI SOURCE FRAME
RATE (Hz)(1)
DLPC34xx INPUT
FRAME RATE (Hz)
A
B
C
D
E
(µs)
(µs)
(µs)
(µs)
(µs)
20 –32
128 –163
49.0
50.0
51.0
59.0
60.0
61.0
98
> 500
> 500
> 500
> 500
> 500
> 500
> 622
> 658
> 655
> 634
> 632
> 630
> 2000
> 2000
> 2000
> 2000
> 2000
> 2000
(31.8 nominal)
(161.6 nominal)
20 –32
128 –163
100
102
118
120
122
(31.2 nominal)
(158.4 nominal)
20 –32
128 –163
(30.6 nominal)
(155.3 nominal)
20 –32
128 –163
(26.4 nominal)
(134.2 nominal)
20 –32
128 –163
(26.0 nominal)
(132.0 nominal)
20 –32
128 –163
(25.6 nominal)
(129.8 nominal)
(1) Timing parameter C is always the sum of B+D.
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7.3.8 Test Point Support
The DLPC34xx test point output port, TSTPT_(7:0), provides selected system calibration and controller debug
support. These test points are inputs when reset is applied. These test points are outputs when reset is released.
The controller samples the signal state upon the release of system reset and then uses the captured value to
configure the test mode until the next time reset is applied. Because each test point includes an internal
pulldown resistor, external pullups must be used to modify the default test configuration.
The default configuration (b000) corresponds to the TSTPT_(2:0) outputs remaining tri-stated to reduce
switching activity during normal operation. For maximum flexibility, a jumper to external pullup resistors is
recommended for TSTPT_(2:0). The pullup resistors on TSTPT_(2:0) can be used to configure the controller for
a specific mode or option. TI does not recommend adding pullup resistors to TSTPT_(7:3) due to potentially
adverse effects on normal operation. For normal use TSTPT_(7:3) should be left unconnected. The test points
are sampled only during a 0-to-1 transition on the RESETZ input, so changing the configuration after reset is
released does not have any effect until the next time reset asserts and releases. 表 7-7 describes the test mode
selections for one programmable scenario defined by TSTPT_(2:0).
表7-7. Test Mode Selection Scenario Defined by TSTPT_(2:0)
NO SWITCHING ACTIVITY
CLOCK DEBUG OUTPUT
TSTPT OUTPUT VALUE(1)
TSTPT_(2:0) = 0b000
TSTPT_(2:0) = 0b010
60 MHz
TSTPT_0
TSTPT_1
TSTPT_2
TSTPT_3
TSTPT_4
TSTPT_5
TSTPT_6
TSTPT_7
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
30 MHz
0.7 to 22.5 MHz
HIGH
LOW
HIGH
HIGH
7.5 MHz
(1) These are default output selections. Software can reprogram the selection at any time.
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7.3.9 DMD Interface
The DLPC34x6 controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface
and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz.
7.3.9.1 Sub-LVDS (HS) Interface
The DLP230NP/NPSE (.23 Full HD) DMD does not require all of the available output data lanes of the controller.
Internal software selection allows the controller to support multiple DMD interface swap configurations. These
options can improve board layout by remapping specific combinations of DMD interface lines to other DMD
interface lines as needed. 表 7-8 shows the two options available for the DLP230NP (.23 Full HD) DMD
specifically.
表7-8. DLP230NP/NPSE (.23 Full HD) DMD –Controller to 8-Lane DMD Pin Mapping Options
DLPC34x6 Controller 8 LANE DMD ROUTING OPTIONS
DMD PINS
OPTION 1
OPTION 2
HS_WDATA_D_P
HS_WDATA_D_N
HS_WDATA_E_P
HS_WDATA_E_N
Input DATA_p_0
Input DATA_n_0
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_F_P
HS_WDATA_F_N
Input DATA_p_1
Input DATA_n_1
HS_WDATA_B_P
HS_WDATA_B_N
HS_WDATA_G_P
HS_WDATA_G_N
Input DATA_p_2
Input DATA_n_2
HS_WDATA_A_P
HS_WDATA_A_N
HS_WDATA_H_P
HS_WDATA_H_N
Input DATA_p_3
Input DATA_n_3
HS_WDATA_H_P
HS_WDATA_H_N
HS_WDATA_A_P
HS_WDATA_A_N
Input DATA_p_4
Input DATA_n_4
HS_WDATA_G_P
HS_WDATA_G_N
HS_WDATA_B_P
HS_WDATA_B_N
Input DATA_p_5
Input DATA_n_5
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_C_P
HS_WDATA_C_N
Input DATA_p_6
Input DATA_n_6
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_D_P
HS_WDATA_D_N
Input DATA_p_7
Input DATA_n_7
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High Speed sub-LVDS DDR Interface
DLPC34xx
DMD_HS_WDATA_A_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_B_P
(Example DMD)
DLP230xx
960 x 540 display
DMD_HS_WDATA_C_N
DMD_HS_WDATA_C_P
Sub-LVDS-DMD
DMD_HS_WDATA_D_N
DMD_HS_WDATA_D_P
DMD_HS_CLK_N
DMD_HS_CLK_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_H_N
DMD_HS_WDATA_H_P
DMD_LS_CLK
DMD_LS_WDATA
DMD_DEN_ARSTZ
DMD_LS_RDATA
Low Speed SDR Interface (120 MHz)
图7-11. DLP230NP/NPSE (.23 Full HD) DMD Interface Example
The sub-LVDS high-speed interface waveform quality and timing on the DLPC34x6 controller depends on the
total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,
and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires
attention to many factors.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and
Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both
waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).
Variation from these recommendations may also work, but should be confirmed with PCB signal integrity
analysis or lab measurements.
7.4 Device Functional Modes
The DLPC34xx controller has two functional modes (ON and OFF) controlled by a single pin, PROJ_ON
(GPIO_08).
• When the PROJ_ON pin is set high, the controller powers up and can be programmed to send data to the
DMD.
• When the PROJ_ON pin is set low, the controller powers down and consumes minimal power.
7.5 Programming
The DLPC34xx controller contains an Arm® Cortex®-M3 processor with additional functional blocks to enable
video processing and control. TI provides software as a firmware image. The customer is required to flash this
firmware image onto the SPI flash memory. The DLPC34xx controller loads this firmware during startup and
regular operation. The controller and its accompanying DLP chipset requires this proprietary software to operate.
The available controller functions depend on the firmware version installed. Different firmware is required for
different chipset combinations (such as when using different PMIC devices). See Documentation Support at the
end of this document or contact TI to view or download the latest published software.
Users can modify software behavior through I2C interface commands. For a list of commands, view the software
user's guide accessible through the Documentation Support page.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The DLPC34x6 controller is used with the DLP230NP/NPSE (.23 Full HD) DMD to provide a reliable display
solution for many data and video display applications. The DMDs are spatial light modulators which reflect
incoming light from an illumination source to one of two directions, with the primary direction being into a
projection or collection optic. Each application is derived primarily from the optical architecture of the system and
the format of the data coming into the controller.
Click these links to find more information about typical applications:
Mobile projector, Smart display, Smartphone, Tablet (multimedia), Augmented reality glasses, Smart home
display, or Pico projector.
8.2 Typical Application
A typical application when using a DLPC34x6 controller with a DLP230NP/NPSE (.23 Full HD) and a DLPA200x
or DLPA300x PMIC/LED driver is to create a Pico projector embedded in a handheld product. For example, a
Pico projector may be embedded in a smartphone, tablet, camera, or camcorder. The controller in the Pico
projector embedded module typically receives images from a host processor within the product.
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图8-1. Typical Application Diagram (using DLPA200x)
DMD/
DLPC
Bucks
1.1 V
1.8 V
2.5 V
3.3 V
AUX
LDOs
+ Battery
–
SYSPWR
V
LED
DC
Supplies
Charger
DLPA300x
Fan(s)
Sensors
SPI(4)
INTZ
R
LIM
SPI1
RESETZ
PARKZ
Thermistor
CMP_OUT
Illumination
optics
PROJ_ON
GPIO_8
1.1 V
VDD
DLPC3436
I2C
HOST_IRQ
HDMI
GPIO_10
Parallel (28)
SUB_FRAME
ACT_SYNC
Parallel (28)
Front-End
Chip
RC_CHARGE
VCC, V
,
BIAS
Flash,
SDRAM
FPD-Link
V
, V
OFFSET RESET
DLP230NP
FPGA
RESETZ
I2C
FPGA RSTZ
1.8 V
CTRL, DATA
(XC7Z020-
1CLG484I4493)
Frame
Memory
Keypad
SPI0
SPI (4)
Flash
ꢀꢁOSD
ꢀꢁAutolock
ꢀꢁScaler
ꢀꢁDeinterlacer
ꢀꢁMicro-controller
VCC_18
SD Card
Reader,
Video
Flash
TI Device
VCC_INTF
VCC_FLSH
Non-TI Device
Decoder
DAC_DATA,
DAC_CLK
Actuator
Driver
Actuator
图8-2. Typical Application Diagram (using DLPA300x)
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8.2.1 Design Requirements
A Pico projector is comprised of a DLP230NP/NPSE (.23 Full HD) DMD, a DLPC34x6 controller, a
XC7Z020-1CLG484I4493 FPGA, and a DLPAxxxx PMIC/LED driver. The controller does the digital image
processing, the DLPAxxxx provides the needed analog functions for the projector, and DMD is the display device
for producing the projected image.
In addition to the three DLP chips in the chipset, other chips may be needed. At a minimum a flash part is
needed to store the software and firmware to control the controller. In addition, a flash part is needed to store the
FPGA program.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the Pico projector.
The entire Pico projector can be turned on and off by using a single signal called PROJ_ON. When PROJ_ON is
high, the projector turns on and begins displaying images. When PROJ_ON is set low, the projector turns off and
draws just microamps of current on SYSPWR. When PROJ_ON is set low, the projector chipset turns off and
draws just microamps of current on SYSPWR. If 1.8 V is supplied separately from the PMIC (as is the case with
the DLPA200x), when PROJ_ON is set low, the 1.8-V supply can continue to be left at 1.8 V and used by other
non-projector sections of the product.
8.2.2 Detailed Design Procedure
For connecting together the DLP230NP/NPSE (.23 Full HD) DMD, DLPC34x6 controller,
XC7Z020-1CLG484I4493 FPGA, and DLPAxxxx PMIC/LED Driver, see the reference design schematic and
board layout on the DLPC3436 and DLPC3426 product page. When a circuit board layout is created from this
schematic, a small circuit board is possible. Follow the layout guidelines to design a reliable projector.
It is typical for an optical engine manufacturer to supply the optical engine that includes the LED packages and a
mounted DMD. These manufacturers specialize in designing optics for DLP projectors. There exists production-
ready optical modules, optical module manufacturers, and design houses.
8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is shown in 图 8-3. For the LED currents shown, it is assumed that
the same current amplitude is applied to the red, green, and blue LEDs. The shape of the curve depends on the
LED devices used as well as the LED system-level heat sink implementation.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
100
200
300 400
Current (mA)
500
600
700
D001
图8-3. Luminance vs Current
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9 Power Supply Recommendations
9.1 PLL Design Considerations
It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.
However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.
9.2 System Power-Up and Power-Down Sequence
Although the DLPC34x6 requires an array of power supply voltages, (for example, VDD, VDDLP12,
VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), because VDDLP12 is tied to the 1.1-V VDD supply, then there
are no restrictions regarding the relative order of power supply sequencing to avoid damaging the controller
(This is true for both power-up and power-down scenarios). Similarly, there is no minimum time between
powering-up or powering-down the different supplies if VDDLP12 is tied to the 1.1-V VDD supply.
Although there is no risk of damaging the controller if the above power sequencing rules are followed, the
following additional power sequencing recommendations must be considered to ensure proper system
operation.
• To ensure that DLPC34x6 output signal states behave as expected, all controller I/O supplies should remain
applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is
applied, then the output signal state associated with the inactive I/O supply goes to a high impedance state.
• Additional power sequencing rules may exist for devices that share the supplies with the controller, and thus
these devices may force additional system power sequencing requirements.
Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be
drawn. This added leakage does not affect normal controller operation or reliability.
图 9-1, 图 9-2, and 图 9-3 show the controller power-up and power-down sequence for both the normal PARK
and fast PARK operations of the DLPC34x6 controller.
备注
During a Normal Park it is recommended to maintain SYSPWR within specification for at least 50 ms
after PROJ_ON goes low. This is to allow the DMD to be parked and the power supply rails to safely
power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended
that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least
50 ms after PROJ_ON goes low.
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Signals
from PMIC (DLPA3000)
from other source
Pre-Initialization
Initialization
Regular operation
PWR On
PWR Off
VIN On
Chipset State
SYSPWR
PROJ_ON
VDD (1.1V)
VCC18 (1.8V)
VCC_INTF (1.8V)
VCC_FLSH (1.8V)
FPGA RESETZ
PARKZ
FPGA PWR
(a)
PLL_REFCLK
RESETZ
(b)
FPGA_RDY
(c)
(d)
HOST_IRQ
I2C
(e)
t1
t2
t3
t4
t1:
t2:
SYSPWR (VIN) applied to the PMIC. All other voltage rails are derived from SYSPWR.
All supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a different
external supply.
t3:
Point where RESETZ is deasserted (goes high). This indicates the beginning of the controller auto-initialization routine.
HOST_IRQ goes low to indicate initialization is complete. I2C is now ready to accept commands.
t4:
(a):
The typical delay between the PLL reference clock becoming active and RESETZ being deasserted (going high) is less than 1
ms. PLL_REFCLK must be stable within 5 ms of all power being applied, and may be active before power is applied.
(b):
(c):
(d):
(e):
There is a typical delay of 1.5 s between being FPGA RESETZ being deasserted and FPGA_RDY being asserted (going high).
This duration is due to FPGA boot logic.
There is a typical controller boot time of 100 ms. PARKZ must be high before RESETZ releases to support auto-initialization.
RESETZ must also be held low for at least 5 ms after the power supplies are in specification.
There is a typical FPGA setup time of 2.75 ms before the system completes boot process. During this period, the DLPC34x6
controller writes startup values to the FPGA registers.
After FPGA setup is complete, I2C now accepts commands.
图9-1. DLPC34x6 Power-Up Timing
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Signals
from PMIC (DLPA3000)
from other source
Normal
Park
System State
Regular operation
Power supply shutdown
(b)
SYSPWR
(c)
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
VDDLP12
(if not tied to VDD)
FPGA PWR
VCC18 (1.8 V)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
PARKZ
PLL_REFCLK
HOST_IRQ
RESETZ
(a)
I2C (activity)
t1
t2
t3
t4
t5
t1:
t2:
t3:
(a):
PROJ_ON goes low to begin the power down sequence.
The controller finishes parking the DMD.
Controller power supplies are turned off.
The DMD will be parked within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and
VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON is
deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. It is therefore
recommended to follow note (c).
(b):
(c):
DMD reset voltage regulation stops typically after 12 ms of normal DMD park being completed.
It is recommended that SYSPWR not be turned off for 50 ms after PROJ_ON is deasserted (goes low). This time allows the
DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.
图9-2. DLPC34x6 Normal Power-Down
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Signals
from PMIC (DLPA3000)
from other source
Fast
Park
(a)
System State
Regular operation
Power supplies collapse
SYSPWR
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
VDDLP12
(if not tied to VDD)
FPGA PWR
VCC18 (1.8 V)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
(b)
PARKZ
PLL_REFCLK
HOST_IRQ
RESETZ
I2C (activity)
t1
t3
t4
t2
t1:
t2:
t3:
t4:
A fault is detected and PARKZ is asserted (goes low) to tell the controller to initiate a fast park of the DMD.
The controller finishes the fast park procedure.
Eventually all power supplies that were derived from SYSPWR collapse.
System is completely turned off.
图9-3. DLPC34x6 Fast Power-Down
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9.3 Power-Up Initialization Sequence
An external power monitor is required to hold the DLPC34xx controller in system reset during the power-up
sequence by driving RESETZ to a logic-low state. It shall continue to drive RESETZ low until all controller
voltages reach the minimum specified voltage levels, PARKZ goes high, and the input clocks are stable. The
external power monitoring is automatically done by the DLPAxxxx PMIC.
No signals output by the DLPC34xx controller will be in their active state while RESETZ is asserted. The
following signals are tri-stated while RESETZ is asserted:
• SPI0_CLK
• SPI0_DOUT
• SPI0_CSZ0
• SPI0_CSZ1
• GPIO [19:00]
Add external pullup (or pulldown) resistors to all tri-stated output signals (including bidirectional signals to be
configured as outputs) to avoid floating controller outputs during reset if they are connected to devices on the
PCB that can malfunction. For SPI, at a minimum, include a pullup to any chip selects connected to devices.
Unused bidirectional signals can be configured as outputs in order to avoid floating controller inputs after
RESETZ is set high.
The following signals are forced to a logic low state while RESETZ is asserted and the corresponding I/O power
is applied:
• LED_SEL_0
• LED_SEL_1
• DMD_DEN_ARSTZ
After power is stable and the PLL_REFCLK_I clock input to the DLPC34xx controller is stable, then RESETZ
should be deactivated (set to a logic high). The DLPC34xx controller then performs a power-up initialization
routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of
RESETZ, all DLPC34xx I/Os will become active. Immediately following the release of RESETZ, the HOST_IRQ
signal will be driven high to indicate that the auto initialization routine is in progress. However, since a pullup
resistor is connected to signal HOST_IRQ, this signal will have already gone high before the controller actively
drives it high. Upon completion of the auto-initialization routine, the DLPC34xx controller will drive HOST_IRQ
low to indicate the initialization done state of the controller has been reached.
To ensure reliable operation, during the power-up initialization sequence, GPIO_08 (PROJ_ON) must not be
deasserted. In other words, once the startup routine has begun (by asserting PROJ_ON), the startup routine
must complete (indicated by HOST_IRQ going low) before the controller can be commanded off (by deasserting
PROJ_ON).
备注
No I2C or DSI (if applicable) activity is permitted until HOST_IRQ goes low.
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9.4 DMD Fast Park Control (PARKZ)
PARKZ is an input early warning signal that must alert the controller at least 32 µs before DC supply voltages
drop below specifications. Typically, the PARKZ signal is provided by the DLPAxxxx interrupt output signal.
PARKZ must be deasserted (set high) prior to releasing RESETZ (that is, prior to the low-to-high transition on
the RESETZ input) for normal operation. When PARKZ is asserted (set low) the controller performs a Fast Park
operation on the DMD which assists in maintaining the lifetime of the DMD. The reference clock must continue
running and RESETZ must remain deactivated for at least 32 µs after PARKZ has been asserted (set low) to
allow the park operation to complete.
Fast Park operation is only intended for use when loss of power is imminent and beyond the control of the host
processor (for example, when the external power source has been disconnected or the battery has dropped
below a minimum level). The longest lifetime of the DMD may not be achieved with Fast Park operation. The
longest lifetime is achieved with a Normal Park operation (initiated through GPIO_08). Hence, PARKZ is typically
only used instead of a Normal Park request if there is not enough time for a Normal Park. A Normal Park
operation takes much longer than 32 µs to park the mirrors. During a Normal Park operation, the DLPAxxxx
keeps on all power supplies, and keeps RESETZ high, until the longer mirror parking has completed.
Additionally, the DLPAxxxx may hold the supplies on for a period of time after the parking has been completed.
View the relevant DLPAxxxx datasheet for more information. The longer mirror parking time ensures the longest
DMD lifetime and reliability. DMD Parking Switching Characteristics specifies the park timings.
9.5 Hot Plug I/O Usage
The DLPC34xx controller provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF).
This allows these inputs to externally be driven even when no I/O power is applied. Under this condition, the
controller does not load the input signal nor draw excessive current that could degrade controller reliability. For
example, the I2C bus from the host to other components is not affected by powering off VCC_INTF to the
DLPC34xx controller. The allows additional devices on the I2C bus to be utilized even if the controller is not
powered on. TI recommends weak pullup or pulldown resistors to avoid floating inputs for signals that feed back
to the host.
If the I/O supply (VCC_INTF) powers off, but the core supply (VDD) remains on, then the corresponding input
buffer may experience added leakage current; however, the added leakage current does not damage the
DLPC34xx controller.
However, if VCC_INTF is powered and VDD is not powered, the controller may drives the IIC0_xx pins low which
prevents communication on this I2C bus. Do not power up the VCC_INTF pin before powering up the VDD pin
for any system that has additional target devices on this bus.
9.6 Maximum Signal Transition Time
Unless otherwise noted, 10 ns is the maximum recommended 20% to 80% rise or fall time to avoid input buffer
oscillation. This applies to all DLPC34x6 input signals. However, the PARKZ input signal includes an additional
small digital filter that ignores any input buffer transitions caused by a slower rise or fall time for up to 150 ns.
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10 Layout
10.1 Layout Guidelines
For a summary of the PCB design requirements for the DLPC34xx controller see PCB Design Requirements for
TI DLP Pico TRP Digital Micromirror Devices. Some applications (such as high frame rate video) may require the
use of 1-oz (or greater) copper planes to manage the controller package heat.
10.1.1 PLL Power Layout
Follow these recommended guidelines to achieve acceptable controller performance for the internal PLL. The
DLPC34xx controller contains two internal PLLs which have dedicated analog supplies (VDD_PLLM,
VSS_PLLM, VDD_PLLD, and VSS_PLLD). At a minimum, isolate the VDD_PLLx power and VSS_PLLx ground
pins using a simple passive filter consisting of two series ferrite beads and two shunt capacitors (to widen the
spectrum of noise absorption). It is recommended that one capacitor be 0.1 µF and one be 0.01 µF. Place all
four components as close to the controller as possible. It is especially important to keep the leads of the high
frequency capacitors as short as possible. Connect both capacitors from VDD_PLLM to VSS_PLLM and
VDD_PLLD to VSS_PLLD on the controller side of the ferrite beads.
Select ferrite beads with these characteristics:
• DC resistance less than 0.40 Ω
• Impedance at 10 MHz equal to or greater than 180 Ω
• Impedance at 100 MHz equal to or greater than 600 Ω
The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog
signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC34xx controller to both
capacitors and then through the series ferrites to the power source. Make the power and ground traces as short
as possible, parallel to each other, and as close as possible to each other.
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signal via
via to common analog digital board power plane
via to common analog digital board ground plane
PCB pad
Controller pad
1
2
3
4
5
A
Signal
Signal
VSS
Signal
F
VSS_
PLLM
G
Signal
VSS
VSS
Signal
Local
decoupling
for the PLL
digital
GND
FB
FB
supply
PLL_
REF
CLK_I
VDD_
PLLM
VSS_
PLLD
H
1.1-V
Power
PLL_
REF
CLK_O
Crystal
Circuit
VDD_
PLLD
J
VSS
VDD
图10-1. PLL Filter Layout
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10.1.2 Reference Clock Layout
The DLPC34xx controller requires an external reference clock to feed the internal PLL. Use either a crystal or
oscillator to supply this reference. The DLPC34xx reference clock must not exceed a frequency variation of ±200
ppm (including aging, temperature, and trim component variation).
图10-2 shows the required discrete components when using a crystal.
PLL_REFCLK_I
PLL_REFCLK_O
RFB
RS
Crystal
CL1
CL2
CL = Crystal load capacitance (farads)
CL1 = 2 × (CL –Cstray_pll_refclk_i)
CL2 = 2 × (CL –Cstray_pll_refclk_o)
where:
•
•
Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_i.
Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_o.
图10-2. Required Discrete Components
10.1.2.1 Recommended Crystal Oscillator Configuration
表10-1. Crystal Port Characteristics
PARAMETER
NOM
UNIT
pF
PLL_REFCLK_I TO GND capacitance
PLL_REFCLK_O TO GND capacitance
1.5
1.5
pF
表10-2. Recommended Crystal Configuration
PARAMETER(1) (2)
RECOMMENDED
UNIT
Crystal circuit configuration
Crystal type
Parallel resonant
Fundamental (first harmonic)
24
Crystal nominal frequency
MHz
PPM
ms
Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200
Maximum startup time
1.0
Crystal equivalent series resistance (ESR)
Crystal load
120 (max)
Ω
6
pF
RS drive resistor (nominal)
RFB feedback resistor (nominal)
100
1
Ω
MΩ
See equation in Reference Clock
Layout notes.
CL1 external crystal load capacitor
CL2 external crystal load capacitor
pF
pF
See equation in Reference Clock
Layout notes.
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表10-2. Recommended Crystal Configuration (continued)
PARAMETER(1) (2)
RECOMMENDED
UNIT
A ground isolation ring around the
crystal is recommended.
PCB layout
(1) Temperature range of –30°C to 85°C.
(2) The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).
If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC34xx
controller, and the PLL_REFCLK_O pin must be left unconnected.
表10-3. Recommended Crystal Parts
TEMPERATURE
AND AGING
(ppm)
LOAD
CAPACITANCE
(pF)
PACKAGE
DIMENSIONS
(mm)
MAXIMUM
MANUFACTURER
SPEED
(MHz)
PART NUMBER
(1) (2)
ESR (Ω)
KDS
DSX211G-24.000M-8pF-50-50
XRCGB24M000F0L11R0
24
24
±50
120
120
8
6
2.0 × 1.6
2.0 × 1.6
Murata
±100
NX2016SA 24M
NDK
24
±145
120
6
2.0 × 1.6
EXS00A-CS05733
(1) The crystal devices in this table have been validated to work with the DLPC34xx controller. Other devices may also be compatible but
have not necessarily been validated by TI.
(2) Operating temperature range: –30°C to 85°C for all crystals.
10.1.3 Unused Pins
To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends tying unused
controller input pins through a pullup resistor to its associated power supply or a pulldown resistor to ground. For
controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown
unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be
expected to drive an external device. The DLPC34xx controller implements very few internal resistors and are
listed in the tables found in the Pin Configuration and Functions section. When external pullup or pulldown
resistors are needed for pins that have weak pullup or pulldown resistors, choose a maximum resistance of 8
kΩ.
Never tie unused output-only pins directly to power or ground. Leave them open.
When possible, TI recommends that unused bidirectional I/O pins are configured to their output state such that
the pin can remain open. If this control is not available and the pins may become an input, then include an
appropriate pullup (or pulldown) resistor.
10.1.4 DMD Control and Sub-LVDS Signals
表10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations
SIGNAL INTERCONNECT TOPOLOGY
DMD BUS SIGNAL(1) (2)
UNIT
SINGLE-BOARD SIGNAL
ROUTING LENGTH
MULTI-BOARD SIGNAL
ROUTING LENGTH
DMD_HS_CLK_P
6.0
in
See (3)
DMD_HS_CLK_N
(152.4)
(mm)
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表10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations (continued)
SIGNAL INTERCONNECT TOPOLOGY
DMD BUS SIGNAL(1) (2)
SINGLE-BOARD SIGNAL
MULTI-BOARD SIGNAL
ROUTING LENGTH
ROUTING LENGTH
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
6.0
in
See (3)
(152.4)
(mm)
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
6.5
in
DMD_LS_CLK
See (3)
See (3)
See (3)
See (3)
(165.1)
(mm)
6.5
in
DMD_LS_WDATA
DMD_LS_RDATA
(165.1)
(mm)
6.5
in
(165.1)
(mm)
7.0
in
DMD_DEN_ARSTZ
(177.8)
(mm)
(1) Maximum signal routing length includes escape routing.
(2) Multi-board DMD routing length is more restricted due to the impact of the connector.
(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS
model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.
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INTERFACE
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表10-5. High Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING(1) (2) (3)
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH(4)
UNIT
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_CLK_P
DMD_HS_CLK_N
±1.0
in
DMD(5)
(±25.4)
(mm)
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
±0.025
in
DMD
DMD
DMD
DMD
DMD_HS_WDATA_x_P
DMD_HS_CLK_P
DMD_HS_WDATA_x_N
DMD_HS_CLK_N
DMD_LS_CLK
N/A
(±0.635)
(mm)
±0.025
in
(±0.635)
(mm)
DMD_LS_WDATA
DMD_LS_RDATA
±0.2
in
(±5.08)
(mm)
in
DMD_DEN_ARSTZ
N/A
(mm)
(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx
controller or the DMD require no additional consideration.
(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data
lines.
(3) DMD LS signals are single ended.
(4) Mismatch variance for a signal group is always with respect to the reference signal.
(5) DMD HS data lines are differential, thus these specifications are pair-to-pair.
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表10-6. Signal Requirements
PARAMETER
REFERENCE
REQUIREMENT
DMD_LS_WDATA
Required
DMD_LS_CLK
Required
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
DMD_LS_WDATA
DMD_LS_CLK
Acceptable
Source series termination
Required
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
68 Ω±10%
68 Ω±10%
68 Ω±10%
68 Ω±10%
100 Ω±10%
100 Ω±10%
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
DMD_LS_WDATA
DMD_LS_CLK
Endpoint termination
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
DMD_LS_WDATA
DMD_LS_CLK
PCB impedance
SDR (single data rate) referenced to DMD_LS_DCLK
SDR referenced to DMD_LS_DCLK
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
SDR
Signal type
SDR referenced to DMD_LS_DLCK
sub-LVDS
sub-LVDS
10.1.5 Layer Changes
• Single-ended signals: Minimize the number of layer changes.
• Differential signals: Individual differential pairs can be routed on different layers. Ideally ensure that the
signals of a given pair do not change layers.
10.1.6 Stubs
• Avoid using stubs.
10.1.7 Terminations
• DMD_HS differential signals require no external termination resistors.
• Make sure the DMD_LS_CLK and DMD_LS_WDATA signal paths include a 43-Ωseries termination resistor
located as close as possible to the corresponding controller pins.
• Make sure the DMD_LS_RDATA signal path includes a 43-Ωseries termination resistor located as close as
possible to the corresponding DMD pin.
• The DMD_DEN_ARSTZ pin requires no series resistor.
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10.1.8 Routing Vias
• The number of vias on DMD_HS signals must be minimized and ideally not exceed two.
• Any and all vias on DMD_HS signals must be located as close to the controller as possible.
• The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be minimized and ideally not
exceed two.
• Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be located as close to the
controller as possible.
10.1.9 Thermal Considerations
The underlying thermal limitation for the DLPC34xx controller is that the maximum operating junction
temperature (TJ) not be exceeded (this is defined in Recommended Operating Conditions).
Some factors that influence TJ are as follows:
• operating ambient temperature
• airflow
• PCB design (including the component layout density and the amount of copper used)
• power dissipation of the DLPC34xx controller
• power dissipation of surrounding components
The controller package is designed to primarily extract heat through the power and ground planes of the PCB.
Thus, copper content and airflow over the PCB are important factors.
The recommends maximum operating ambient temperature (TA) is provided primarily as a design target and is
based on maximum DLPC34xx controller power dissipation and RθJA at 0 m/s of forced airflow, where RθJA is
the thermal resistance of the package as measured using a JEDEC defined standard test PCB with two, 1-oz
power planes. This JEDEC test PCB is not necessarily representative of the DLPC34xx controller PCB, so the
reported thermal resistance may not be accurate in the actual product application. Although the actual thermal
resistance may be different, it is the best information available during the design phase to estimate thermal
performance. TI highly recommended that thermal performance be measured and validated after the PCB is
designed and the application is built.
To evaluate the thermal performance, measure the top center case temperature under the worse case product
scenario (maximum power dissipation, maximum voltage, maximum ambient temperature), and validate the
controller does not exceed the maximum recommended case temperature (TC). This specification is based on
the measured φJT for the DLPC34xx controller package and provides a relatively accurate correlation to junction
temperature.
Take care when measuring this case temperature to prevent accidental cooling of the package surface. TI
recommends a small (approximately 40 gauge) thermocouple. Place the bead and thermocouple wire so that
they contact the top of the package. Cover the bead and thermocouple wire with a minimal amount of thermally
conductive epoxy. Route the wires closely along the package and the board surface to avoid cooling the bead
through the wires.
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10.2 Layout Example
图10-3. Layout Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Device Nomenclature
11.1.2.1 Device Markings DLPC343x
1
DLPC343x
SC
2
DLPC343xRXX
3
4
XXXXXXXXXX-TT
LLLLLL.ZZZ
AA YYWW
5
Pin (terminal) A1 corner identifier
Marking Definitions:
Line 1:
DLP Device Name: DLPC343x = x indicates a 6 device name ID.
SC: Solder ball composition
e1: Indicates lead-free solder balls consisting of SnAgCu
G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content
less than or equal to 1.5% and that the mold compound meets TI's definition of green.
Line 2:
TI Part Number
DLP Device Name: DLPC343x = x indicates a 6 device name ID.
R: corresponds to the TI device revision letter for example A, B, or C.
XX: corresponds to the device package designator.
Line 3:
Line 4:
XXXXXXXXXX-TT: Manufacturer Part Number
LLLLLLLL.ZZZ: Foundry lot code for semiconductor wafers and lead-free solder ball marking
LLLLLLLL: Fab lot number
ZZZ: Lot split number
Line 5:
AA YYWW: Package assembly information
AA: corresponds to the manufacturing site
YYWW: Date code (YY = Year :: WW = Week)
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备注
1. Engineering prototype samples are marked with an X suffix appended to the TI part number. For
example, 2512737-0001X.
2. See 表7-1, for DLPC34xx controller supported input resolutions.
11.1.2.2 Device Markings DLPC342x
1
DLPC342xZVB
2
YMZLLLS SC
Pin (terminal) A1 corner identifier
Marking Definitions:
Line 1:
Line 2:
DLP Device Name: DLPC342x where x is a 6 for this device
YMZLLLS SC: Foundry lot code for semiconductor wafers and lead-free solder ball marking
YM: Year Month
Z, S: Assembly site
LLL: Assembly lot traceability
SC: Solder ball composition
e1: Indicates lead-free solder balls consisting of SnAgCu
G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content
less than or equal to 1.5% and that the mold compound meets TI's definition of green
备注
1. Engineering prototype samples are marked with an X suffix appended to the TI part number. For
example, 2512737-0001X.
2. See Supported Resolution and Frame Rates for DLPC342x resolutions on the DMD supported per
part number.
11.1.2.3 Video Timing Parameter Definitions
See 图11-1 for a visual description.
Active Lines Per Frame Defines the number of lines in a frame containing displayable data. ALPF is a
(ALPF)
Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data. APPL is a
(APPL) subset of the TPPL.
subset of the TLPF.
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Horizontal Back Porch Defines the number of blank pixel clocks after the active edge of horizontal sync but
(HBP) Blanking before the first active pixel.
Horizontal Front Porch Defines the number of blank pixel clocks after the last active pixel but before
(HFP) Blanking horizontal sync.
Horizontal Sync (HS or Timing reference point that defines the start of each horizontal interval (line). The
Hsync)
active edge of the HS signal defines the absolute reference point. The active edge
(either rising or falling edge as defined by the source) is the reference from which all
horizontal blanking parameters are measured.
Total Lines Per Frame Total number of active and inactive lines per frame; defines the vertical period (or
(TLPF) frame time).
Total Pixel Per Line Total number of active and inactive pixel clocks per line; defines the horizontal line
(TPPL) period in pixel clocks.
Vertical Sync (VS or Timing reference point that defines the start of the vertical interval (frame). The
Vsync)
absolute reference point is defined by the active edge of the VS signal. The active
edge (either rising or falling edge as defined by the source) is the reference from
which all vertical blanking parameters are measured.
Vertical
Back
Porch Defines the number of blank lines after the active edge of vertical sync but before
(VBP) Blanking
the first active line.
Vertical Front Porch Defines the number of blank lines after the last active line but before the active edge
(VFP) Blanking
of vertical sync.
TPPL
Vertical Back Porch (VBP)
APPL
Horizontal
Back
Porch
Horizontal
Front
Porch
TLPF
ALPF
(HBP)
(HFP)
Vertical Front Porch (VFP)
图11-1. Parameter Definitions
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11.2 Documentation Support
11.2.1 Related Documentation
The following table lists quick access links for associated parts of the DLP chipset.
表11-1. Chipset Documentation
TECHNICAL
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TOOLS & SOFTWARE
DOCUMENTS
Click here
Click here
Click here
Click here
Click here
DLPA2000
DLPA2005
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
DLPA3000
DLPA3005
DLP230NP/NPSE
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表11-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
DLPC34x6
Click here
Click here
Click here
Click here
Click here
11.4 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.6 Trademarks
IntelliBright™ and Link™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
IntelliBright® is a registered trademark of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
所有商标均为其各自所有者的财产。
11.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
12.1.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Orderable Device
Status(1)
Pins
Eco Plan(2) Lead/Ball Finish
MSL Peak Temp(3)
Op Temp (°C)
Device Marking(4) (5)
DLPC3436 CZVB
DLPC3426 CZVB
ACTIVE
ACTIVE
NFBGA
NFBGA
ZVB
ZVB
176
176
160
160
Call TI
Call TI
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
DLPC343x
DLPC343x
–30 to 85
–30 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a
new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all
6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high
temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)
as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS156
64
Submit Document Feedback
Product Folder Links: DLPC3436
DLPC3436
www.ti.com.cn
ZHCSJN9E –JANUARY 2019 –REVISED APRIL 2023
12.1.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Orderable Device
Status(1)
Pins
Eco Plan(2) Lead/Ball Finish
MSL Peak Temp(3)
Op Temp (°C)
Device Marking(4) (5)
DLPC3436 CZVB
DLPC3426 CZVB
ACTIVE
ACTIVE
NFBGA
NFBGA
ZVB
ZVB
176
176
160
160
Call TI
Call TI
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
DLPC343x
DLPC343x
–30 to 85
–30 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a
new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all
6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high
temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)
as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: DLPC3436
English Data Sheet: DLPS156
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLPC3426ZVB
ACTIVE
ACTIVE
NFBGA
NFBGA
ZVB
ZVB
176
176
260
260
RoHS & Green
RoHS & Green
SNAGCU
Level-3-260C-168Hrs
Level-3-260C-168Hrs
-30 to 85
-30 to 85
DLPC3426ZVB
Samples
Samples
DLPC3436CZVB
SNAGCU
(DLPC3436 G8, DLP
C3436 G8)
DLPC3436CZVB
P292547C-8G
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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