DM383AAAR21F_技术文档

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DM383 DaVinci™ Digital Media Processor

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1 High-Performance System-on-Chip (SoC)

1.1 Features

123

– Hardware Face Detection for up to 35 Faces

Per Frame

• High-Performance DaVinci Digital Media

Processors

• Programmable High-Definition Video Image

Coprocessing (HDVICP v2) Engine

– Up to 1000-MHz ARM® Cortex™-A8 RISC

Processor

– Encode, Decode, Transcode Operations

– H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4

SP/ASP, JPEG/MJPEG

– Up to 2000 ARM Cortex-A8 MIPS

• ARM Cortex-A8 Core

– ARMv7 Architecture

• Media Controller

– Controls the HDVPSS, HDVICP2, and ISS

• Endianness

– ARM Instructions and Data – Little Endian

• HD Video Processing Subsystem (HDVPSS)

– Two 165-MHz HD Video Capture Inputs

•

In-Order, Dual-Issue, Superscalar

Processor Core

•

NEON™ Multimedia Architecture

Supports Integer and Floating Point

Jazelle® RCT Execution Environment

• ARM Cortex-A8 Memory Architecture

– 32KB of Instruction and Data Caches

– 256KB of L2 Cache with ECC

– 64KB of RAM, 48KB of Boot ROM

• 256KB of On-Chip Memory Controller (OCMC)

RAM

•

One 16- or 24-Bit Input, Splittable Into

Dual 8-Bit SD Capture Ports

•

One 8-, 16-, or 24-Bit HD Input and 8-Bit

SD Input Capture Port

– Two 165-MHz HD Video Display Outputs

•

One 16-, 24-, or 30-Bit and One 16- or 24-

Bit Output

• Imaging Subsystem (ISS)

– Camera Sensor Connection

– Component HD Analog Output

– Composite Analog Output

– Digital HDMI 1.3 Transmitter with Integrated

PHY

– Advanced Video Processing Features Such

as Scan, Format, and Rate Conversion

– Three Graphics Layers and Compositors

•

Parallel Connection for Raw (up to 16-Bit)

and BT.656/BT.1120 (8- or 16-Bit)

•

CSI2 Serial Connection

– Image Sensor Interface (ISIF) for Handling

Image and Video Data From the Camera

Sensor

– Image Pipe Interface (IPIPEIF) for Image and

Video Data Connection Between Camera

Sensor, ISIF, IPIPE, and DRAM

• 32-Bit DDR2, DDR3, and DDR3L SDRAM

Interface

– Supports up to 400 MHz for DDR2, 533 MHz

for DDR3, and 533 MHz for DDR3L

– Image Pipe (IPIPE) for Real-Time Image and

Video Processing

– Up to Two x 16 Devices, 2GB of Total

Address Space

– Dynamic Memory Manager (DMM)

– Resizer

•

Resizing Image and Video From 1/16x to

8x

Generating Two Different Resizing

Outputs Concurrently

Hardware 3A Engine (H3A) for Generating

Key Statistics for 3A (AE, AWB, and AF)

Control

•

Programmable Multi-Zone Memory

Mapping

•

Enables Efficient 2D Block Accesses

Supports Tiled Objects in 0°, 90°, 180°, or

270° Orientation and Mirroring

• Face Detect (FD) Engine

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Device/BIOS, XDS are trademarks of Texas Instruments.

2

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

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• General-Purpose Memory Controller (GPMC)

• Dual Controller Area Network (DCAN) Module

– 8- or 16-Bit Multiplexed Address and Data

Bus

– 512MB of Total Address Space Divided

Among up to 8 Chip Selects

– Glueless Interface to NOR Flash, NAND

Flash (BCH/Hamming Error Code Detection),

SRAM and Pseudo-SRAM

– Error Locator Module (ELM) Outside of

GPMC to Provide up to 16-Bit or 512-Byte

Hardware ECC for NAND

– CAN Version 2 Part A, B

• Four Inter-Integrated Circuit (I²C Bus™) Ports

• Two Multichannel Audio Serial Ports (McASP)

– Six Serializer Transmit and Receive Ports

– Two Serializer Transmit and Receive Ports

– DIT-Capable For S/PDIF (All Ports)

• Serial ATA (SATA) 3.0 Gbps Controller with

Integrated PHY

– Direct Interface to 1 Hard Disk Drive

– Hardware-Assisted Native Command

Queuing (NCQ) from up to 32 Entries

– Supports Port Multiplier and Command-

Based Switching

– Flexible Asynchronous Protocol Control for

Interface to FPGA, CPLD, ASICs, and More

• Enhanced Direct Memory Access (EDMA)

Controller

• Real-Time Clock (RTC)

– One-Time or Periodic Interrupt Generation

• Up to 125 General-Purpose I/O (GPIO) Pins

• One Spin Lock Module with up to 128 Hardware

Semaphores

• One Mailbox Module with 12 Mailboxes

• On-Chip ARM ROM Bootloader (RBL)

• Power, Reset, and Clock Management

– SmartReflex™ Technology (Level 2b)

– Multiple Independent Core Power Domains

– Multiple Independent Core Voltage Domains

– Four Transfer Controllers

– 64 Independent DMA Channels

– 8 QDMA Channels

• Dual USB 2.0 Ports with Integrated PHYs

– USB2.0 High- and Full-Speed Clients

– USB2.0 High-, Full-, and Low-Speed Hosts

– Supports End Points 0-15

• Eight 32-Bit General-Purpose Timers

(Timer1–8)

• One System Watchdog Timer (WDT0)

• Three Configurable UART/IrDA/CIR Modules

– UART0 with Modem Control Signals

– Supports up to 3.6864 Mbps

– SIR, MIR, FIR (4.0 MBAUD), and CIR

• Four Serial Peripheral Interfaces (SPIs) (up to

48 MHz)

– Each with Four Chip Selects

• Three MMC/SD/SDIO Serial Interfaces (up to

48 MHz)

– Support for Multiple Operating Points per

Voltage Domain

– Clock Enable and Disable Control for

Subsystems and Peripherals

• 32KB of Embedded Trace Buffer™ (ETB™) and

5-pin Trace Interface for Debug

• IEEE 1149.1 (JTAG) Compatible

• 609-Pin Pb-Free BGA Package (AAR Suffix),

0.8-mm Effective Pitch with Via Channel

Technology to Reduce PCB Cost (0.5-mm Ball

Spacing)

– Supporting up to 1-, 4-, or 8-Bit Modes

• 45-nm CMOS Technology

• 1.8- and 3.3-V Dual Voltage Buffers for General

I/O

2

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1.2 Applications

•

Car Black Box Digital Video Recorder

Portable Digital Video Recorder

Intrusion Control Panels with Video

Access Control Panels with Video

High-Performance System-on-Chip (SoC)

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1.3 Description

DM383 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable

platform that leverages TI’s DaVinci processor technology to meet the processing needs of Car Black Box

Digital Video Recorders, Portable Digital Video Recorders, and similar devices in SD and HD resolutions.

The Programmable High-Definition Video Image Processor of the device supports 1080p60 of real time

H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality

video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a

minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-

4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best

video quality. The low power consumption and high performance of the device makes it particularly

suitable for portable and automotive applications.

The device enables original-design manufacturers (ODMs) and after-market manufacturers to quickly bring

to market devices featuring robust operating systems support, rich user interfaces, and high processing

performance through the maximum flexibility of a fully integrated mixed processor solution. The device

also combines programmable video and audio processing with a highly integrated peripheral set.

The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load

many video and imaging processing tasks for common video and imaging algorithms. Programmability is

provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging

coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on

coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC

processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache;

256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each peripheral, see the related sections in this document and the

associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem;

two USB ports with integrated 2.0 PHY; two serializer McASP audio serial ports (with DIT mode); three

UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three

MMC/SD/SDIO serial interfaces; four I²C master and slave interfaces; a parallel camera interface (CAM);

up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer;

DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; two

Controller Area Network (DCAN) modules; Serial ATA (SATA) 3.0 Gbps controller with integrated PHY; a

Spin Lock; and Mailbox.

Additionally, TI provides a complete set of development tools for the ARM which include C compilers and

a Microsoft® Windows® debugger interface for visibility into source code execution.

4

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

Video Processing

Subsystem

Imaging

Subsystem

ARM Subsystem

Cortex^TM-A8

CPU

NEON

FPU

Video Capture

Parallel Cam Input

CSI2 Serial Input

IPIPE

32 KB

I-Cache

32 KB

D-Cache

Display Processing

HD OSD

SD OSD

256 KB L2 Cache

with ECC

HD VENC

HDMI Xmt

SD VENC

Resizer

Boot ROM

48 KB

RAM

64 KB

SD DAC

H3A

ICE Crusher

HD DAC (3)

System Interconnect

Peripherals

System Control

Real-Time

Clock

Program/Data Storage

Connectivity

Miscellaneous

Serial Interfaces

PRCM

GPMC

McASP

(2)

DDR2/3

+

GPIO (4)

32-bit

ELM

GP Timer (8)

JTAG

USB 2.0

Ctrl/PHY

(2)

SATA

3 Gbp/s

2

SPI (4)

I

C (4)

Watchdog

Timer

MMC/SD/

SDIO

(3)

DCAN (2)

UART (3)

Spinlock

Mailbox

Figure 1-1. Functional Block Diagram

High-Performance System-on-Chip (SoC)

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7.1

Power, Reset and Clock Management (PRCM)

Module ............................................ 125

1

High-Performance System-on-Chip (SoC) ......... 1

1.1 Features ............................................. 1

1.2 Applications .......................................... 3

1.3 Description ........................................... 4

1.4 Functional Block Diagram ........................... 5

7.2 Power .............................................. 125

7.3 Reset .............................................. 133

7.4 Clocking ........................................... 140

7.5 Interrupts .......................................... 154

Peripheral Information and Timings ............. 157

8.1 Parameter Information ............................ 157

Revision History .............................................. 7

2

8

Device Overview ........................................ 8

2.1 Device Comparison .................................. 8

2.2 Device Characteristics ............................... 8

2.3 Device Compatibility ................................ 10

8.2

Recommended Clock and Control Signal Transition

Behavior ........................................... 158

Controller Area Network Interface (DCAN) ....... 159

8.3

2.4

ARM® Cortex™-A8 Microprocessor Unit

8.4 EDMA ............................................. 161

(Processor) Subsystem Overview .................. 10

8.5 Emulation Features and Capability ............... 164

2.5 Media Controller Overview ......................... 12

2.6 HDVICP2 Overview ................................ 12

2.7 Face Detect (FD) Overview ........................ 12

2.8 Spinlock Module Overview ......................... 13

2.9 Mailbox Module Overview .......................... 14

2.10 Memory Map Summary ............................. 15

Device Pins ............................................. 22

3.1 Pin Maps ........................................... 22

3.2 Pin Assignments .................................... 33

3.3 Terminal Functions ................................. 61

Device Configurations .............................. 105

4.1 Control Module Registers ......................... 105

4.2 Boot Modes ....................................... 105

4.3 Pin Multiplexing Control ........................... 110

4.4 Handling Unused Pins ............................ 113

4.5 DeBugging Considerations ........................ 113

System Interconnect ................................ 115

Device Operating Conditions ...................... 119

6.1 Absolute Maximum Ratings ....................... 119

6.2 Recommended Operating Conditions ............. 120

6.3 Reliability Data .................................... 122

8.6

General-Purpose Input/Output (GPIO) ............ 168

General-Purpose Memory Controller (GPMC) and

8.7

Error Location Module (ELM) ..................... 170

8.8

8.9

High-Definition Multimedia Interface (HDMI) ...... 185

High-Definition Video Processing Subsystem

(HDVPSS) ......................................... 188

3

4

8.10 Inter-Integrated Circuit (I2C) ...................... 196

8.11 Imaging Subsystem (ISS) ......................... 199

8.12 DDR2/DDR3/DDR3L Memory Controller .......... 204

8.13 Multichannel Audio Serial Port (McASP) .......... 238

8.14 MultiMedia Card/Secure Digital/Secure Digital Input

Output (MMC/SD/SDIO) ........................... 243

8.15 Serial ATA Controller (SATA) ..................... 245

8.16 Serial Peripheral Interface (SPI) .................. 248

8.17 Timers ............................................. 254

8.18 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 256

8.19 Universal Serial Bus (USB2.0) .................... 258

Device and Documentation Support ............. 260

9.1 Device Support .................................... 260

9.2 Documentation Support ........................... 262

9.3 Community Resources ............................ 262

5

6

9

6.4

Electrical Characteristics Over Recommended

Ranges of Supply Voltage and Operating

10 Mechanical ............................................ 263

10.1 Thermal Data for the AAR ........................ 263

10.2 Packaging Information ............................ 263

Temperature (Unless Otherwise Noted) .......... 123

Power, Reset, Clocking, and Interrupts ......... 125

7

6

Contents

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Revision History

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Global

Added support for OPP100 to:

•

Section 6.2, Recommended Operating Conditions

Section 6.3, Reliability Data

Table 7-3, Device Operating Points (OPPs)

Table 7-4, Supported OPP Combinations

Power, Reset,

Clocking, and

Interrupts

Changed OPP100 speed from 500 to 600 MHz for ARM Cortex-A8 in Table 7-3, Device Operating Points

(OPPs).

Removed requirement that the maximum voltage difference between CVDD and any other CVDD_x voltage

domain must be < 150 mV.

•

Table 7-4, Supported OPP Combinations

Contents

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2 Device Overview

2.1 Device Comparison

2.2 Device Characteristics

Table 2-1 provides an overview of the DM383 DaVinci™ Digital Media Processors,, which includes

significant features of the device, including the capacity of on-chip RAM, peripherals, and the package

type with pin count.

Table 2-1. Characteristics of the Processor

HARDWARE FEATURES

DM383

1 16-/24-bit HD Capture Port or

2 8-bit SD Capture Ports

and

1 8/16/24-bit HD Input Port

and

1 8-bit SD Input Port

and

HD Video Processing Subsystem (HDVPSS)

1 16-/24-/30-bit HD Display Port

or 1 HDMI 1.3 Transmitter

and

1 16-/24-bit HD Display Port

and

1 SD Video DAC

and

3 HD Video DACs

1 Parallel Camera Input for Raw (up to 16-

bit)

Imaging Subsystem (ISS)

and BT.656/BT.1120 (8/16-bit)

and 1 CSI2 Serial Input

DDR2/3 Memory Controller

GPMC + ELM

16-/32-bit Bus Width

Asynchronous (8-/16-bit bus width)

RAM, NOR, NAND

64 Independent Channels

8 QDMA Channels

EDMA

2 (Supports High- and Full-Speed as a

Device and

Peripherals

USB 2.0

High-, Full-, and Low-Speed as a Host)

Not all peripherals

pins are available at

the same time (for

more details, see the

Device Configurations

section).

8 (32-bit General purpose)

and

1 (System Watchdog)

Timers

3 (with SIR, MIR, FIR, CIR support and

RTS/CTS flow control)

(UART0 Supports Modem Interface)

UART

SPI

4 (Each supporting up to 4 slave devices)

1 (1-bit or 4-bit or 8-bit modes)

and

MMC/SD/SDIO

1 (8-bit mode) or

2 (1-bit or 4-bit modes)

I2C

4 Master or Slave

Media Controller

Controls HDVPSS, HDVICP2, and ISS

2 (6/2 Serializers, each with

Transmit/Receive and DIT capability)

McASP

Controller Area Network (DCAN)

2

Serial ATA (SATA) 3.0 Gbps

1 (Supports 1 Hard Disk Drive)

RTC

1

GPIO

Up to 125 pins

8

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Table 2-1. Characteristics of the Processor (continued)

HARDWARE FEATURES

Spinlock Module

DM383

1 (up to 128 H/W Semaphores)

1 (with 12 Mailboxes)

Mailbox Module

Size (Bytes)

640KB RAM, 48KB ROM

ARM

32KB I-cache

32KB D-cache

256KB L2 Cache with ECC

64KB RAM

On-Chip Memory

JTAG BSDL ID

Organization

48KB Boot ROM

ADDITIONAL SHARED MEMORY

256KB On-chip RAM

see Section 8.5.3.1, JTAG ID (JTAGID)

Register Description

DEVICE_ID Register (address location: 0x4814 0600)

CPU Frequency

Cycle Time

MHz

ns

ARM® Cortex™-A8 up to 1000 MHz

ARM® Cortex™ -A8 1.0 ns

DEEP SLEEP,

Core Logic (V)

OPP100, OPP120,

Turbo, Nitro

0.83 V – 1.35 V

Voltage

I/O (V)

16 x 16 mm

μm

1.35 V, 1.5 V, 1.8 V, 3.3 V

609-Pin BGA (AAR) [with Via Channel™

Technology]

Package

Process Technology

0.045 μm

Product Preview (PP),

Advance Information (AI),

or Production Data (PD)

Product Status

PD

Device Overview

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2.3 Device Compatibility

2.4 ARM® Cortex™-A8 Microprocessor Unit (Processor) Subsystem Overview

The ARM® Cortex™-A8 Subsystem is designed to allow the ARM Cortex-A8 master control of the device.

In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystems,

peripherals, and external memories.

The ARM Cortex-A8 Subsystem includes the following features:

•

ARM Cortex-A8 RISC processor:

–

ARMv7 ISA plus Thumb2™, JazelleX™, and Media Extensions

NEON™ Floating-Point Unit

Enhanced Memory Management Unit (MMU)

Little Endian

32KB L1 Instruction Cache

32KB L1 Data Cache

256KB L2 Cache with Error Correction Code (ECC)

•

CoreSight Embedded Trace Module (ETM)

ARM Cortex-A8 Interrupt Controller (AINTC)

Embedded PLL Controller (PLL_ARM)

64KB Internal RAM

48KB Internal Public ROM

Figure 2-1 shows the ARM Cortex-A8 Subsystem for the device.

System Events

128

L3

DMM

DEVOSC

PLL_ARM

128

128 128

128

32

128

ARM Cortex-A8

Interrupt Controller

(AINTC)

ARM Cortex-A8

32

64

32KB L1I$ 32KB L1D$

256KB L2$

48KB ROM

64KB RAM

Arbiter

ETM

NEON

Trace

64

Debug

ICECrusher

Figure 2-1. ARM Cortex-A8 Subsystem

2.4.1 ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose microprocessors.

This processor is targeted at multi-tasking applications where full memory management, high

performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the

ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM

Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem,

including:

•

ARM Cortex-A8 Integer Core

Superscalar ARMv7 Instruction Set

Thumb-2 Instruction Set

Jazelle RCT Acceleration

CP14 Debug Coprocessor

10

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•

CP15 System Control Coprocessor

NEON 64-/128-bit Hybrid SIMD Engine for Multimedia

Enhanced VFPv3 Floating-Point Coprocessor

Enhanced Memory Management Unit (MMU)

Separate Level-1 Instruction and Data Caches

Integrated Level-2 Cache with ECC Support

128-bit Interconnect with Level 3 Fast (L3) System Memories and Peripherals

Embedded Trace Module (ETM).

2.4.2 Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an

embedded trace module (ETM). The ETM consists of two parts:

•

The Trace port which provides real-time trace capability for the ARM Cortex-A8.

Triggering facilities that provide trigger resources, which include address and data comparators,

counter, and sequencers.

The ARM Cortex-A8 trace port is not pinned out and is, instead, only connected to the system-level

Embedded Trace Buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are

required to read/interpret the captured trace data.

2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests

from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor.

2.4.4 ARM Cortex-A8 PLL (PLL_ARM)

The ARM Cortex-A8 subsystem contains an embedded PLL Controller (PLL_ARM) for generating the

subsystem’s clocks from the device Clock input.

2.4.5 ARM Processor Interconnect

The ARM Cortex-A8 processor is connected through the arbiter to the L3 interconnect port. The L3

interconnect port is 128-bits wide and provides access to the other device modules.

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2.5 Media Controller Overview

The Media Controller has the responsibility of managing the HDVPSS, HDVICP2, and ISS modules.

2.6 HDVICP2 Overview

The HDVICP2 is a Video Encoder/Decoder hardware accelerator supporting a range of encode, decode,

and transcode operations for most major video codec standards. The main video Codec standards

supported in hardware are MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP, RV9/10, AVS-1.0,

and ON2 VP6.2/VP7.

The HDVICP2 hardware accelerator is composed of the following elements:

•

Motion estimation acceleration engine

Loop filter acceleration engine

Sequencer, including its memories and an interrupt controller

Intra-prediction estimation engine

Calculation engine

Motion compensation engine

Entropy coder/decoder

Video Direct Memory Access (DMA)

Synchronization boxes

Shared L2 controller

Local interconnect

2.7 Face Detect (FD) Overview

The device Face Detection (FD) module performs face detection and tracking within a picture stored in

memory. This module is typically used for video encoding, face-based priority auto-focusing, or red-eye

removal. The FD module supports QVGA resolution inputs stored in DRR memory in 8-bit Luma format. In

addition, it uses 51.25KB of DDR for its working memory.

The FD module supports the following features:

•

Input image:

–

QVGA Input Image Size (H x V = 320 x 240)

8-bit Gray Scale Data (0x00 = Black and 0xFF = White)

12

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•

Detection Capabilities:

–

Face Inclination of ±45°

Face Direction:

•

Up/Down: ±30°

Left/Right: ±60°

–

Supported Detection Directions:

•

0° Faces are Vertical

+90° Faces are Rotated Right by 90°

-90° Faces are Rotated Left by 90°

Supported Minimum Face Sizes of 20, 25, 32 or 40 Pixels

–

Supported Detection Start Positions:

•

X = 0 to 160

Y = 0 to 120

Supported Detection Area Sizes:

•

X = 160 to 320

Y = 120 to 240

Provides Size, Position, Angle, and Confidence Level for Each Face

2.8 Spinlock Module Overview

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple

processors in the device:

•

ARM Cortex-A8 processor

Media Controller

The Spinlock module implements 128 spinlocks (or hardware semaphores) that provide an efficient way to

perform a lock operation of a device resource using a single read-access, avoiding the need for a read-

modify-write bus transfer of which the programmable cores are not capable.

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2.9 Mailbox Module Overview

The device Mailbox module facilitates communication between the ARM Cortex-A8 and the Media

Controller. It consists of twelve mailboxes, each supporting a 1-way communication between two of the

above processors. The sender sends information to the receiver by writing a message to the mailbox

registers. Interrupt signaling is used to notify the receiver that a message has been queued or to notify the

sender about an overflow situation.

The Mailbox module supports the following features (see Figure 2-2):

•

12 mailboxes

Flexible mailbox-to-processor assignment scheme

Four-message FIFO depth for each message queue

32-bit message width

Message reception and queue-not-full notification using interrupts

Three interrupts (one to ARM Cortex-A8 and two to Media Controller)

Mailbox Module

Mailbox

L4

Interconnect

Interrupt

ARM Cortex-A8

Media Controller

Figure 2-2. Mailbox Module Block Diagram

14

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2.10 Memory Map Summary

The device has multiple on-chip memories associated with its processor and subsystems. To help simplify

software development a unified memory map is used where possible to maintain a consistent view of

device resources across all bus masters.

2.10.1 L3 Memory Map

Table 2-2 shows the L3 memory map for all system masters (including Cortex-A8).

For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see

Section 5.

Table 2-2. L3 Memory Map

START ADDRESS

(HEX)

END ADDRESS

(HEX)

SIZE

DESCRIPTION

Reserved (BOOTROM)

0x0000_0000

0x1000_0000

0x00FF_FFFF

0x1FFF_FFFF

16MB

496MB

General Purpose Memory Controller (GPMC)

External Memory Space

0x2000_0000

0x3000_0000

0x4000_0000

0x2FFF_FFFF

0x3FFF_FFFF

0x4001_FFFF

256MB

128KB

Reserved

ARM Cortex-A8 ROM

(Accessible by ARM Cortex-A8 only)

0x4002_0000

0x4002_BFFF

48KB

0x4002_C000

0x402F_0000

0x402E_FFFF

0x402F_03FF

2832KB

1KB

Reserved

ARM Cortex-A8 RAM

(Accessible by ARM Cortex-A8 only)

0x402F_0400

0x402F_FFFF

64KB - 1KB

0x4030_0000

0x4034_0000

0x4080_0000

0x4084_0000

0x40E0_0000

0x40E0_8000

0x40F0_0000

0x40F0_8000

0x4100_0000

0x4200_0000

0x4400_0000

0x4440_0000

0x4480_0000

0x44C0_0000

0x4600_0000

0x4640_0000

0x4680_0000

0x46C0_0000

0x4700_0000

0x4740_0000

0x4780_0000

0x4781_0000

0x4781_2000

0x47C0_0000

0x4033_FFFF

0x407F_FFFF

0x4083_FFFF

0x40DF_FFFF

0x40E0_7FFF

0x40EF_FFFF

0x40F0_7FFF

0x40FF_FFFF

0x41FF_FFFF

0x43FF_FFFF

0x443F_FFFF

0x447F_FFFF

0x44BF_FFFF

0x45FF_FFFF

0x463F_FFFF

0x467F_FFFF

0x46BF_FFFF

0x46FF_FFFF

0x473F_FFFF

0x477F_FFFF

0x4780_FFFF

0x4781_1FFF

0x47BF_FFFF

0x47FF FFFF

0x47C0_BFFF

256KB

4864KB

256KB

5888KB

32KB

992KB

32KB

992KB

16MB

32MB

4MB

OCMC SRAM

Reserved

L3 Fast configuration registers

4MB

L3 Mid configuration registers

4MB

L3 Slow configuration registers

20MB

4MB

Reserved

McASP0 Data Peripheral Registers

4MB

McASP1 Data Peripheral Registers

4MB

Reserved

4MB

HDMI

4MB

Reserved

4MB

USB

64KB

8KB

Reserved

MMC/SD/SDIO2 Peripheral Registers

4MB - 72KB

4MB

Reserved

48KB

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Table 2-2. L3 Memory Map (continued)

START ADDRESS

(HEX)

END ADDRESS

(HEX)

SIZE

DESCRIPTION

0x47C0_C000

0x47C0_C400

0x47C0_C800

0x47C0_CC00

0x47C0_D000

0x4800_0000

0x47C0_C3FF

0x47C0_C7FF

0x47C0_CBFF

0x47C0_CFFF

0x47FF FFFF

0x48FF_FFFF

1KB

Reserved

DDR PHY Registers

Reserved

1KB

Reserved

4052KB

16MB

Reserved

L4 Slow Peripheral Domain

(see Table 2-4)

0x4900_0000

0x4910_0000

0x4980_0000

0x4990_0000

0x49A0_0000

0x49B0_0000

0x49C0_0000

0x4A00_0000

0x490F_FFFF

0x497F_FFFF

0x498F_FFFF

0x499F_FFFF

0x49AF_FFFF

0x49BF_FFFF

0x49FF_FFFF

0x4AFF_FFFF

1MB

7MB

1MB

4MB

16MB

EDMA TPCC Registers

Reserved

EDMA TPTC0 Registers

EDMA TPTC1 Registers

EDMA TPTC2 Registers

EDMA TPTC3 Registers

Reserved

L4 Fast Peripheral Domain

(see Table 2-3)

0x4B00_0000

0x4C00_0000

0x4D00_0000

0x4E00_0000

0x5000_0000

0x5100_0000

0x5200_0000

0x5500_0000

0x5600_0000

0x5700_0000

0x5800_0000

0x5900_0000

0x5A00_0000

0x5C00_0000

0x5E00_0000

0x6000_0000

0x8000_0000

0x1 0000 0000

0x4BFF_FFFF

0x4CFF_FFFF

0x4DFF_FFFF

0x4FFF_FFFF

0x50FF_FFFF

0x51FF_FFFF

0x54FF_FFFF

0x55FF_FFFF

0x56FF_FFFF

0x57FF_FFFF

0x58FF_FFFF

0x59FF_FFFF

0x5BFF_FFFF

0x5DFF_FFFF

0x5FFF_FFFF

0x7FFF_FFFF

0xFFFF_FFFF

0x1 FFFF FFFF

16MB

32MB

16MB

48MB

16MB

32MB

512MB

2GB

Emulation Subsystem

DDR Registers

Reserved

DDR DMM Registers

GPMC Registers

Reserved

Media Controller

Reserved

HDVICP2 Configuration

HDVICP2 SL2

Reserved

ISS

Reserved

DDR DMM Tiler Window (see Table 2-5)

DDR

4GB

DDR DMM Tiler Extended Address Map

(ISS and HDVPSS only) [see Table 2-5]

16

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2.10.2 L4 Memory Map

The L4 Fast Peripheral Domain and L4 Slow Peripheral Domain regions of the memory maps above are

broken out into Table 2-3 and Table 2-4.

For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see ,

System Interconnect.

2.10.2.1 L4 Fast Peripheral Memory Map

Table 2-3. L4 Fast Peripheral Memory Map

Cortex-A8 and L3 Masters

SIZE

DEVICE NAME

START ADDRESS

(HEX)

END ADDRESS

(HEX)

0x4A00_0000

0x4A00_0800

0x4A00_1000

0x4A00_1400

0x4A00_1800

0x4A00_2000

0x4A08_0000

0x4A0A_0000

0x4A0A_E000

0x4A10_0000

0x4A10_8000

0x4A14_0000

0x4A15_0000

0x4A15_1000

0x4A18_0000

0x4A1A_2000

0x4A1A_4000

0x4A1A_5000

0x4A1A_6000

0x4A1A_7000

0x4A1A_8000

0x4A1A_A000

0x4A1A_B000

0x4A1A_C000

0x4A1A_D000

0x4A1A_E000

0x4A1B_0000

0x4A1B_1000

0x4A1B_2000

0x4A1B_6000

0x4A1B_4000

0x4A00_07FF

0x4A00_0FFF

0x4A00_13FF

0x4A00_17FF

0x4A00_1FFF

0x4A07_FFFF

0x4A09_FFFF

0x4A0A_0FFF

0x4A0F_FFFF

0x4A10_7FFF

0x4A10_8FFF

0x4A14_FFFF

0x4A15_0FFF

0x4A17_FFFF

0x4A1A_1FFF

0x4A1A_3FFF

0x4A1A_4FFF

0x4A1A_5FFF

0x4A1A_6FFF

0x4A1A_7FFF

0x4A1A_9FFF

0x4A1A_AFFF

0x4A1A_BFFF

0x4A1A_CFFF

0x4A1A_DFFF

0x4A1A_FFFF

0x4A1B_0FFF

0x4A1B_1FFF

0x4A1B_2FFF

0x4A1B_6FFF

0x4AFF_FFFF

2KB

L4 Fast Configuration - Address/Protection (AP)

L4 Fast Configuration - Link Agent (LA)

1KB

L4 Fast Configuration - Initiator Port (IP0)

1KB

L4 Fast Configuration - Initiator Port (IP1)

Reserved

2KB

504KB

128KB

4KB

Reserved

380KB

32KB

4KB

Reserved

64KB

4KB

SATA0 Peripheral Registers

SATA0 Interconnect Registers

Reserved

188KB

136KB

8KB

Reserved

4KB

Reserved

4KB

Reserved

4KB

Reserved

4KB

Reserved

8KB

Reserved

4KB

Reserved

4KB

Reserved

4KB

Reserved

4KB

Reserved

8KB

Reserved

4KB

Reserved

4KB

Reserved

4KB

Reserved

4KB

Reserved

14632KB

Reserved

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2.10.2.2 L4 Slow Peripheral Memory Map

Table 2-4. L4 Slow Peripheral Memory Map

Cortex-A8 and L3 Masters

SIZE

DEVICE NAME

START ADDRESS

END ADDRESS

(HEX)

0x4800_0000

0x4800_0800

0x4800_1000

0x4800_1400

0x4800_1800

0x4800_2000

0x4800_8000

0x4801_0000

0x4801_1000

0x4801_2000

0x4802_0000

0x4802_1000

0x4802_2000

0x4802_3000

0x4802_4000

0x4802_5000

0x4802_6000

0x4802_8000

0x4802_9000

0x4802_A000

0x4802_B000

0x4802_C000

0x4802_E000

0x4802_F000

0x4803_0000

0x4803_1000

0x4803_2000

0x4803_3000

0x4803_4000

0x4803_8000

0x4803_A000

0x4803_B000

0x4803_C000

0x4803_E000

0x4803_F000

0x4804_0000

0x4804_1000

0x4804_2000

0x4804_3000

0x4804_4000

0x4804_5000

0x4804_6000

0x4804_7000

0x4800_07FF

0x4800_0FFF

0x4800_13FF

0x4800_17FF

0x4800_1FFF

0x4800_7FFF

0x4800_8FFF

0x4801_0FFF

0x4801_1FFF

0x4801_FFFF

0x4802_0FFF

0x4802_1FFF

0x4802_2FFF

0x4802_3FFF

0x4802_4FFF

0x4802_5FFF

0x4802_7FFF

0x4802_8FFF

0x4802_9FFF

0x4802_AFFF

0x4802_BFFF

0x4802_DFFF

0x4802_EFFF

0x4802_FFFF

0x4803_0FFF

0x4803_1FFF

0x4803_2FFF

0x4803_3FFF

0x4803_7FFF

0x4803_9FFF

0x4803_AFFF

0x4803_BFFF

0x4803_DFFF

0x4803_EFFF

0x4803_FFFF

0x4804_0FFF

0x4804_1FFF

0x4804_2FFF

0x4804_3FFF

0x4804_4FFF

0x4804_5FFF

0x4804_6FFF

0x4804_7FFF

2KB

1KB

2KB

24KB

32KB

4KB

56KB

4KB

8KB

4KB

8KB

4KB

16KB

8KB

4KB

8KB

4KB

L4 Slow Configuration – Address/Protection (AP)

L4 Slow Configuration – Link Agent (LA)

L4 Slow Configuration – Initiator Port (IP0)

L4 Slow Configuration – Initiator Port (IP1)

Reserved

UART0 Peripheral Registers

UART0 Interconnect Registers

UART1 Peripheral Registers

UART1 Interconnect Registers

UART2 Peripheral Registers

UART2 Interconnect Registers

Reserved

I2C0 Peripheral Registers

I2C0 Interconnect Registers

I2C1 Peripheral Registers

I2C1 Interconnect Registers

Reserved

TIMER1 Peripheral Registers

TIMER1 Interconnect Registers

SPI0 Peripheral Registers

SPI0 Interconnect Registers

GPIO0 Peripheral Registers

GPIO0 Interconnect Registers

Reserved

McASP0 CFG Peripheral Registers

McASP0 CFG Interconnect Registers

Reserved

McASP1 CFG Peripheral Registers

McASP1 CFG Interconnect Registers

Reserved

TIMER2 Peripheral Registers

TIMER2 Interconnect Registers

TIMER3 Peripheral Registers

TIMER3 Interconnect Registers

TIMER4 Peripheral Registers

TIMER4 Interconnect Registers

TIMER5 Peripheral Registers

TIMER5 Interconnect Registers

18

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Table 2-4. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters

SIZE

DEVICE NAME

START ADDRESS

END ADDRESS

(HEX)

0x4804_8000

0x4804_9000

0x4804_A000

0x4804_B000

0x4804_C000

0x4804_D000

0x4804_E000

0x4805_0000

0x4805_2000

0x4805_3000

0x4806_0000

0x4807_0000

0x4807_1000

0x4808_0000

0x4809_0000

0x4809_1000

0x480A_0000

0x480B_0000

0x480B_1000

0x480C_0000

0x480C_1000

0x480C_2000

0x480C_4000

0x480C_8000

0x480C_9000

0x480C_A000

0x480C_B000

0x480C_C000

0x4810_0000

0x4812_0000

0x4812_1000

0x4812_2000

0x4812_3000

0x4812_4000

0x4814_0000

0x4816_0000

0x4816_1000

0x4818_0000

0x4818_3000

0x4818_4000

0x4818_8000

0x4818_9000

0x4818_A000

0x4818_B000

0x4818_C000

0x4818_D000

0x4804_8FFF

0x4804_9FFF

0x4804_AFFF

0x4804_BFFF

0x4804_CFFF

0x4804_DFFF

0x4804_FFFF

0x4805_1FFF

0x4805_2FFF

0x4805_FFFF

0x4806_FFFF

0x4807_0FFF

0x4807_FFFF

0x4808_FFFF

0x4809_0FFF

0x4809_FFFF

0x480A_FFFF

0x480B_0FFF

0x480B_FFFF

0x480C_0FFF

0x480C_1FFF

0x480C_3FFF

0x480C_7FFF

0x480C_8FFF

0x480C_9FFF

0x480C_AFFF

0x480C_BFFF

0x480F_FFFF

0x4811_FFFF

0x4812_0FFF

0x4812_1FFF

0x4812_2FFF

0x4812_3FFF

0x4813_FFFF

0x4815_FFFF

0x4816_0FFF

0x4817_FFFF

0x4818_2FFF

0x4818_3FFF

0x4818_7FFF

0x4818_8FFF

0x4818_9FFF

0x4818_AFFF

0x4818_BFFF

0x4818_CFFF

0x4818_DFFF

4KB

TIMER6 Peripheral Registers

TIMER6 Interconnect Registers

TIMER7 Peripheral Registers

TIMER7 Interconnect Registers

GPIO1 Peripheral Registers

GPIO1 Interconnect Registers

Reserved

4KB

8KB

Reserved

4KB

Reserved

52KB

64KB

4KB

Reserved

MMC/SD/SDIO0 Peripheral Registers

MMC/SD/SDIO0 Interconnect Registers

Reserved

60KB

64KB

4KB

ELM Peripheral Registers

ELM Interconnect Registers

Reserved

60KB

64KB

4KB

Reserved

60KB

4KB

Reserved

RTC Peripheral Registers

RTC Interconnect Registers

Reserved

4KB

8KB

16KB

4KB

Reserved

Mailbox Peripheral Registers

Mailbox Interconnect Registers

Spinlock Peripheral Registers

Spinlock Interconnect Registers

Reserved

4KB

208KB

128KB

4KB

HDVPSS Peripheral Registers

HDVPSS Interconnect Registers

Reserved

4KB

HDMI Peripheral Registers

HDMI Interconnect Registers

Reserved

4KB

112KB

128KB

4KB

Control Module Peripheral Registers

Control Module Interconnect Registers

Reserved

124KB

12KB

4KB

PRCM Peripheral Registers

PRCM Interconnect Registers

Reserved

16KB

4KB

SmartReflex0 Peripheral Registers

SmartReflex0 Interconnect Registers

SmartReflex1 Peripheral Registers

SmartReflex1 Interconnect Registers

OCP Watchpoint Peripheral Registers

OCP Watchpoint Interconnect Registers

4KB

Device Overview

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Table 2-4. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters

SIZE

DEVICE NAME

START ADDRESS

END ADDRESS

(HEX)

0x4818_E000

0x4818_F000

0x4819_0000

0x4819_4000

0x4819_C000

0x4819_D000

0x4819_E000

0x4819_F000

0x481A_0000

0x481A_1000

0x481A_2000

0x481A_3000

0x481A_4000

0x481A_5000

0x481A_6000

0x481A_7000

0x481A_8000

0x481A_9000

0x481A_A000

0x481A_B000

0x481A_C000

0x481A_D000

0x481A_E000

0x481A_F000

0x481B_0000

0x481C_0000

0x481C_1000

0x481C_2000

0x481C_3000

0x481C_4000

0x481C_5000

0x481C_6000

0x481C_7000

0x481C_8000

0x481C_9000

0x481C_A000

0x481C_C000

0x481C_E000

0x481D_0000

0x481D_2000

0x481D_4000

0x481D_6000

0x481D_7000

0x481D_8000

0x481E_8000

0x4818_EFFF

0x4818_FFFF

0x4819_3FFF

0x4819_BFFF

0x481F_FFFF

0x4819_CFFF

0x4819_DFFF

0x4819_EFFF

0x4819_FFFF

0x481A_0FFF

0x481A_1FFF

0x481A_2FFF

0x481A_3FFF

0x481A_4FFF

0x481A_5FFF

0x481A_6FFF

0x481A_7FFF

0x481A_8FFF

0x481A_9FFF

0x481A_AFFF

0x481A_BFFF

0x481A_CFFF

0x481A_DFFF

0x481A_EFFF

0x481A_FFFF

0x481B_FFFF

0x481C_0FFF

0x481C_1FFF

0x481C_2FFF

0x481C_3FFF

0x481C_4FFF

0x481C_5FFF

0x481C_6FFF

0x481C_7FFF

0x481C_8FFF

0x481C_9FFF

0x481C_BFFF

0x481C_DFFF

0x481C_FFFF

0x481D_1FFF

0x481D_3FFF

0x481D_5FFF

0x481D_6FFF

0x481D_7FFF

0x481E_7FFF

0x481E_8FFF

4KB

16KB

32KB

400KB

4KB

64KB

4KB

8KB

4KB

64KB

4KB

Reserved

I2C2 Peripheral Registers

I2C2 Interconnect Registers

I2C3 Peripheral Registers

I2C3 Interconnect Registers

SPI1 Peripheral Registers

SPI1 Interconnect Registers

SPI2 Peripheral Registers

SPI2 Interconnect Registers

SPI3 Peripheral Registers

SPI3 Interconnect Registers

Reserved

GPIO2 Peripheral Registers

GPIO2 Interconnect Registers

GPIO3 Peripheral Registers

GPIO3 Interconnect Registers

Reserved

TIMER8 Peripheral Registers

TIMER8 Interconnect Registers

SYNCTIMER32K Peripheral Registers

SYNCTIMER32K Interconnect Registers

PLLSS Peripheral Registers

PLLSS Interconnect Registers

WDT0 Peripheral Registers

WDT0 Interconnect Registers

Reserved

DCAN0 Peripheral Registers

DCAN0 Interconnect Registers

DCAN1 Peripheral Registers

DCAN1 Interconnect Registers

Reserved

MMC/SD/SDIO1 Peripheral Registers

MMC/SD/SDIO1 Interconnect Registers

20

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Table 2-4. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters

SIZE

DEVICE NAME

START ADDRESS

END ADDRESS

(HEX)

0x481E_9000

0x4820_0000

0x4820_1000

0x4824_0000

0x4824_1000

0x4828_0000

0x4828_1000

0x4830_0000

0x481F_FFFF

0x4820_0FFF

0x4823_FFFF

0x4824_0FFF

0x4827_FFFF

0x4828_0FFF

0x482F_FFFF

0x48FF_FFFF

52KB

4KB

Reserved

Interrupt controller⁽¹⁾

Reserved⁽¹⁾

MPUSS config register⁽¹⁾

Reserved⁽¹⁾

SSM⁽¹⁾

Reserved⁽¹⁾

252KB

4KB

252KB

4KB

508KB

13MB

Reserved

(1) These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only

for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.

2.10.3 DDR DMM TILER Extended Addressing Map

The Tiler includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access

the frame buffer in rotated and mirrored views. shows the details of the Tiler Extended Address Mapping.

This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems. However,

other masters can access any one single view through the 512-MB Tiler region in the base 4GByte

address memory map.

Table 2-5. DDR DMM TILER Extended Address Mapping

START ADDRESS

(HEX)

END ADDRESS

(HEX)

BLOCK NAME

SIZE

DESCRIPTION

Tiler View 0

Tiler View 1

0x1 0000_0000

0x1 2000_0000

0x1 1FFF_FFFF

0x1 3FFF_FFFF

512MB

Natural 0° View

0° with Vertical Mirror

View

Tiler View 2

0x1 4000_0000

0x1 5FFF_FFFF

512MB

0° with Horizontal Mirror

View

Tiler View 3

Tiler View 4

0x1 6000_0000

0x1 8000_0000

0x1 7FFF_FFFF

0x1 9FFF_FFFF

512MB

180° View

90° with Vertical Mirror

View

Tiler View 5

Tiler View 6

Tiler View 7

0x1 A000_0000

0x1 C000_0000

0x1 E000_0000

0x1 BFFF_FFFF

0x1 DFFF_FFFF

0x1 FFFF_FFFF

512MB

270° View

90° View

90° with Horizontal Mirror

View

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3 Device Pins

3.1 Pin Maps

The following tables show the top view of the package pin assignments in eight pin maps.

22

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Table 3-1. AAR Ball Map [Section Top_Left - Top View]

A

VSS

B

C

D

UART0_RTS

UART0_CTS

No Ball

E

UART0_DCD

UART0_DTR

UART0_DSR

UART0_TXD

No Ball

F

No Ball

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VOUT[0]_R_CR[9]

VOUT[0]_R_CR[7]

VOUT[0]_R_CR[4]

VOUT[0]_R_CR[3]

VOUT[0]_G_Y_YC[8]

VOUT[0]_G_Y_YC[5]

VOUT[0]_G_Y_YC[7]

USB1_VBUSIN

USB1_DM

No Ball

VOUT[0]_R_CR[8]

VOUT[0]_R_CR[5]

No Ball

VOUT[0]_R_CR[6]

No Ball

DEVOSC_MXI

No Ball

VOUT[0]_R_CR[2]

No Ball

VOUT[0]_G_Y_YC[9]

VOUT[0]_G_Y_YC[6]

No Ball

VOUT[0]_G_Y_YC[3]

VOUT[0]_G_Y_YC[2]

VOUT[0]_B_CB_C[9]

No Ball

VOUT[0]_G_Y_YC[4]

VSS

No Ball

VSS

USB1_ID

VOUT[0]_B_CB_C[8]

No Ball

VOUT[0]_B_CB_C[7]

No Ball

VOUT[0]_B_CB_C[2]

No Ball

USB1_DP

No Ball

USB0_VBUSIN

USB0_DM

No Ball

USB0_DP

USB0_ID

USB1_CE

VOUT[0]_B_CB_C[3]

VSSA_USB

No Ball

VSS

VOUT[0]_HSYNC

VSS

USB0_CE

VOUT[0]_AVID

No Ball

VOUT[0]_VSYNC

No Ball

EMU1

No Ball

EMU0

VIN[0]A_D[0]

No Ball

VIN[0]A_D[1]

No Ball

VIN[0]A_D[2]

VIN[0]A_D[3]

VIN[0]A_D[9]_BD[1]

VIN[0]A_D[4]

DVDD

VIN[0]A_D[5]

DVDD

VIN[0]A_D[8]_BD[0]

VIN[0]A_D[10]_BD[2]

Ball Map Position

1

6

2

7

3

8

4

9

5

10

Device Pins

23

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Table 3-2. AAR Ball Map [Section Top_Left_Middle - Top View]

G

DEVOSC_MXO

VSSA_DEVOSC

SPI[0]_SCS[0]

SPI[0]_SCS[1]

VSS

H

SERDES_CLKN

SERDES_CLKP

RSV40

J

No Ball

K

RSV26

L

RSV36

M

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

No Ball

SATA0_RXP0

SPI[1]_SCLK

RSV54

RSV24

RSV25

SATA0_RXN0

No Ball

SPI[1]_SCS[0]

SPI[0]_D[0]

SPI[0]_D[1]

UART0_RXD

RSV0

No Ball

RSV3

No Ball

RSV1

No Ball

SPI[1]_D[1]

RSV53

VSS

No Ball

VSS

RSV39

No Ball

VDDA_1P8

LDOCAP_SERDESCLK

No Ball

VSS

RSV2

VOUT[0]_B_CB_C[6]

VOUT[0]_B_CB_C[4]

No Ball

VSS

VOUT[0]_B_CB_C[5]

No Ball

USB0_DRVVBUS

VOUT[0]_CLK

No Ball

UART2_RXD

No Ball

UART2_TXD

VDDA_USB_3P3

No Ball

VSS

VIN[0]A_D[7]

No Ball

LDOCAP_ARMRAM

VDDA_USB0_1P8

No Ball

VIN[0]A_D[6]

VDDA_ARMPLL_1P8

CVDD_ARM

VSS

No Ball

LDOCAP_ARM

No Ball

RSV4

VIN[0]A_D[11]_BD[3]

VIN[0]A_D[13]_BD[5]

VDDA_USB1_1P8

VIN[0]A_D[12]_BD[4]

CVDD_ARM

VDDA_HDDAC_1P1

CVDD_ARM

VSS

RSV5

Ball Map Position

1

6

2

7

3

8

4

9

5

10

24

Device Pins

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

Table 3-3. AAR Ball Map [Section Top_Middle_Middle - Top View]

N

SATA0_TXP0

SATA0_TXN0

RTCK

P

RSV31

R

T

TMS

U

AUXOSC_MXO

VSSA_AUXOSC

SD1_DAT[2]_SDRW

DEVOSC_WAKE

DVDD

V

No Ball

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

No Ball

RSV32

No Ball

VSS

RSV43

RSV33

AUXOSC_MXI

No Ball

TCLK

TDI

No Ball

DVDD

No Ball

VDDA_SATA0_1P8

UART0_RIN

VDDA_1P8

SPI[0]_SCLK

SPI[1]_D[0]

VDDA_1P8

No Ball

I2C[0]_SCL

DVDD

No Ball

TDO

No Ball

DVDD_SD

I2C[0]_SDA

VDDA_HDVICPPLL_1P8

LDOCAP_RAM1

VSS

DVDD_SD

TRST

No Ball

VDDA_1P8

No Ball

VSS

No Ball

VDDS_OSC0_1P8

VDDS_OSC1_1P8

No Ball

CVDD_HDVICP

No Ball

CVDD_HDVICP

No Ball

VSSA_USB

No Ball

VSS

No Ball

VSS

CVDD

VSS

CVDD

No Ball

CVDD

VSS

No Ball

VSS

No Ball

Ball Map Position

1

6

2

7

3

8

4

9

5

10

Device Pins

25

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Table 3-4. AAR Ball Map [Section Top_Right_Middle - Top View]

W

SD1_DAT[0]

SD1_CLK

No Ball

Y

SD0_DAT[2]_SDRW

SD0_DAT[3]

SD1_CMD

VSS

AA

No Ball

AB

SD0_DAT[6]

SD0_CLK

No Ball

AC

AD

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

MCA[0]_AXR[3]

SD0_DAT[7]

No Ball

MCA[0]_ACLKR

MCA[1]_ACLKR

MCA[0]_ACLKX

MCA[0]_AXR[5]

MCA[0]_AXR[4]

VSS

SD1_DAT[1]_SDIRQ

SD0_CMD

SD0_DAT[0]

VSS

No Ball

SD1_DAT[3]

VSS

No Ball

SD0_DAT[1]_SDIRQ

No Ball

VSS

No Ball

VSS

No Ball

LDOCAP_HDVICPRAM

No Ball

MCA[1]_AFSR

MCA[1]_ACLKX

DDR[0]_A[1]

No Ball

VSS

LDOCAP_HDVICP

CVDD_HDVICP

No Ball

DDR[0]_A[10]

No Ball

MCA[1]_AXR[0]

MCA[1]_AXR[1]

CVDD

No Ball

MCA[1]_AFSX

DDR[0]_CS[0]

No Ball

CVDD

DDR[0]_RST

VDDA_DDRPLL_1P8

VSS

No Ball

DDR[0]_CKE

DDR[0]_D[28]

No Ball

CVDD

No Ball

DDR[0]_D[29]

DVDD_DDR[0]

DDR[0]_D[23]

No Ball

DVDD_DDR[0]

No Ball

VSS

No Ball

VSS

DDR[0]_D[22]

Ball Map Position

1

6

2

7

3

8

4

9

5

10

26

Device Pins

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

Table 3-5. AAR Ball Map [Section Top_Right - Top View]

AE

AF

AUD_CLKIN0

MCA[0]_AFSR

MCA[0]_AXR[0]

No Ball

AG

No Ball

AH

NMI

AJ

CLKIN32

AK

AL

VSS

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

MCA[0]_AXR[1]

MCA[0]_AXR[2]

MCA[0]_AFSX

VSS

No Ball

AUD_CLKIN2

No Ball

POR

RSTOUT_WD_OUT

No Ball

DDR[0]_A[6]

DDR[0]_A[9]

DDR[0]_A[4]

DDR[0]_CLK

DDR[0]_BA[0]

DDR[0]_CAS

DDR[0]_A[11]

DDR[0]_A[13]

DDR[0]_A[15]

RSV42

DDR[0]_VTP

DDR[0]_A[8]

No Ball

RESET

No Ball

VSS

AUD_CLKIN1

No Ball

DDR[0]_A[5]

No Ball

DDR[0]_A[3]

No Ball

DDR[0]_CLK

DDR[0]_WE

No Ball

VSS

No Ball

VSS

DDR[0]_BA[2]

RSV34

DDR[0]_RAS

RSV35

VSS

DDR[0]_A[0]

DDR[0]_A[14]

No Ball

VSS

DDR[0]_BA[1]

No Ball

DDR[0]_A[7]

No Ball

DDR[0]_A[12]

No Ball

DDR[0]_A[2]

No Ball

VSS

No Ball

DDR[0]_ODT[0]

DDR[0]_DQS[3]

No Ball

VSS

DDR[0]_D[31]

VSS

DDR[0]_D[30]

DDR[0]_D[25]

No Ball

DDR[0]_DQS[3]

DDR[0]_D[24]

DDR[0]_DQM[3]

DDR[0]_DQS[2]

DDR[0]_D[19]

VSS

DDR[0]_D[27]

No Ball

DDR[0]_D[26]

No Ball

DVDD_DDR[0]

No Ball

VREFSSTL_DDR[0]

DDR[0]_DQS[2]

No Ball

DVDD_DDR[0]

DDR[0]_D[21]

DVDD_DDR[0]

DDR[0]_D[20]

Ball Map Position

1

6

2

7

3

8

4

9

5

10

Device Pins

27

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Table 3-6. AAR Ball Map [Section Bottom_Left - Top View]

A

HDMI_CLKP

HDMI_DN0

No Ball

B

HDMI_CLKN

HDMI_DP0

HDMI_DN1

HDMI_DP1

TV_RSET

C

D

No Ball

E

No Ball

F

15

14

13

12

11

10

9

No Ball

VIN[0]A_VSYNC

VIN[0]A_DE

No Ball

VIN[0]A_HSYNC

DVDD_C

VIN[0]A_D[17]

No Ball

VIN[0]A_D[14]_BD[6]

DVDD_C

HDMI_DN2

HDMI_DP2

No Ball

TV_VFB0

No Ball

HDDAC_A

HDDAC_B

No Ball

TV_OUT0

VIN[0]A_CLK

VSSA_VDAC

VIN[0]A_D[21]

No Ball

HDDAC_VSYNC

VSS

HDDAC_HSYNC

VSS

VIN[0]A_D[20]

VSS

8

HDDAC_C

7

HDDAC_VREF

HDDAC_IREF

VIN[0]A_DE

VIN[0]A_FLD

VOUT[0]_FLD

VOUT[1]_G_Y_YC[0]

No Ball

VIN[0]A_D[19]

No Ball

VSS

6

VIN[0]A_D[22]

VIN[0]A_D[23]

No Ball

5

VIN[0]B_DE

No Ball

VOUT[1]_B_CB_C[1]

No Ball

VOUT[1]_VSYNC

No Ball

4

No Ball

3

VIN[0]B_FLD

VOUT[1]_G_Y_YC[1]

VSS

No Ball

VOUT[1]_CLK

I2C[1]_SCL

I2C[1]_SDA

No Ball

VOUT[1]_B_CB_C[4]

VOUT[1]_B_CB_C[3]

VOUT[1]_AVID

2

VOUT[1]_R_CR[0]

VOUT[1]_R_CR[1]

VOUT[1]_HSYNC

No Ball

1

Ball Map Position

1

6

2

7

3

8

4

9

5

10

28

Device Pins

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

Table 3-7. AAR Ball Map [Section Bottom_Left_Middle - Top View]

G

No Ball

H

J

No Ball

K

No Ball

L

VDDA_HDDACREF_1P8

VDDA_HDDAC_1P8

VDDA_VIDPLL_1P8

VOUT[1]_R_CR[6]

No Ball

M

No Ball

15

14

13

12

11

10

9

No Ball

VDDA_VDAC_1P8

VIN[0]A_FLD

No Ball

VDDA_HDMI_1P8

No Ball

CVDD_ARM

No Ball

DVDD_C

No Ball

VIN[0]A_D[15]_BD[7]

VIN[0]B_CLK

No Ball

VIN[0]A_D[16]

VIN[0]A_D[18]

No Ball

VOUT[1]_R_CR[5]

VOUT[1]_R_CR[7]

No Ball

VOUT[1]_FLD

VOUT[1]_G_Y_YC[7]

VOUT[1]_G_Y_YC[4]

VSS

No Ball

VSSA_HDMI

VSS

VOUT[1]_B_CB_C[0]

VSSA_HDMI

VSS

No Ball

8

No Ball

VOUT[1]_B_CB_C[2]

DVDD

7

VSS

No Ball

6

VSS

VOUT[1]_G_Y_YC[3]

VOUT[1]_B_CB_C[9]

VOUT[1]_G_Y_YC[6]

VOUT[1]_B_CB_C[7]

VOUT[1]_R_CR[4]

No Ball

VOUT[1]_R_CR[2]

DVDD

5

VSS

No Ball

GPMC_A[19]

DVDD

4

VSS

No Ball

VOUT[1]_R_CR[3]

VOUT[1]_G_Y_YC[8]

VOUT[1]_G_Y_YC[2]

No Ball

3

VOUT[1]_B_CB_C[8]

VOUT[1]_B_CB_C[6]

VOUT[1]_B_CB_C[5]

No Ball

GPMC_A[18]

GPMC_A[17]

GPMC_A[16]

2

VOUT[1]_R_CR[8]

VOUT[1]_G_Y_YC[5]

VOUT[1]_R_CR[9]

VOUT[1]_G_Y_YC[9]

1

Ball Map Position

1

6

2

7

3

8

4

9

5

10

Device Pins

29

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Table 3-8. AAR Ball Map [Section Bottom_Middle_Middle - Top View]

N

No Ball

VSS

P

CVDD

R

T

U

CVDD

V

15

14

13

12

11

10

9

CVDD

VSS

CVDD

VSSA_CSI2

No Ball

VSS

No Ball

VSS

No Ball

CVDD

No Ball

CVDD

No Ball

DVDD

VSS

CVDD

VSS

CVDD

DVDD

No Ball

GPMC_D[15]

No Ball

VDDA_1P8

GPMC_D[9]

DVDD_GPMC

GPMC_D[5]

DVDD_GPMC

GPMC_D[6]

GPMC_D[7]

GPMC_D[8]

No Ball

LDOCAP_RAM0

No Ball

GPMC_D[3]

No Ball

GPMC_A[20]

No Ball

GPMC_A[22]

GPMC_A[21]

VDDA_1P8

GPMC_A[23]

DVDD_GPMC

GPMC_D[10]

DVDD_GPMC

GPMC_D[11]

GPMC_D[12]

GPMC_D[13]

GPMC_D[14]

VDDA_AUDIOPLL_1P8

No Ball

8

7

No Ball

6

No Ball

5

No Ball

4

No Ball

3

No Ball

2

CSI2_DY[4]

CSI2_DX[4]

1

Ball Map Position

1

6

2

7

3

8

4

9

5

10

30

Device Pins

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

Table 3-9. AAR Ball Map [Section Bottom_Right_Middle - Top View]

W

Y

No Ball

AA

VSS

AB

DVDD_DDR[0]

No Ball

AC

DVDD_DDR[0]

No Ball

AD

DDR[0]_D[18]

No Ball

15

14

13

12

11

10

9

No Ball

CVDD

VSS

CVDD

VSS

DDR[0]_D[13]

No Ball

GPMC_CS[1]

No Ball

DDR[0]_D[11]

No Ball

DDR[0]_D[10]

No Ball

VDDA_L3L4_1P8

VDDA_CSI2_1P8

GPMC_D[4]

GPMC_WAIT[0]

DVDD_RGMII

GPMC_D[0]

DVDD_RGMII

GPMC_D[1]

GPMC_D[2]

CSI2_DX[3]

CSI2_DY[3]

GPMC_BE[1]

No Ball

GPMC_ ADV _ALE

No Ball

LDOCAP_RAM2

GPMC_CLK

No Ball

GPMC_CS[0]

SD2_DAT[2]_SDRW

VSSA_CSI2

SD2_SCLK

SD2_DAT[1]_SDIRQ

SD2_DAT[0]

GPMC_CS[2]

CSI2_DY[0]

No Ball

DDR[0]_D[5]

RSV41

8

GPMC_OE_RE

DVDD_RGMII

GPMC_WE

DVDD_RGMII

GPMC_ BE[0] _CLE

CSI2_DY[2]

No Ball

7

No Ball

VSS

6

No Ball

VSS

5

No Ball

VSS

4

No Ball

VSS

3

No Ball

VSS

2

CSI2_DX[2]

CSI2_DX[1]

CSI2_DX[0]

CSI2_DY[1]

SD2_DAT[4]

SD2_DAT[3]

1

Ball Map Position

1

6

2

7

3

8

4

9

5

10

Device Pins

31

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Table 3-10. AAR Ball Map [Section Bottom_Right - Top View]

AE

DVDD_DDR[0]

No Ball

AF

DDR[0]_D[17]

No Ball

AG

DVDD_DDR[0]

No Ball

AH

DDR[0]_D[16]

No Ball

AJ

DDR[0]_DQM[2]

No Ball

AK

AL

15

14

13

12

11

10

9

DDR[0]_DQS[1]

DDR[0]_D[15]

DDR[0]_D[12]

DDR[0]_DQM[1]

DDR[0]_DQS[0]

DDR[0]_D[2]

DDR[0]_D[1]

GPMC_A[11]

GPMC_A[9]

DDR[0]_DQS[1]

DDR[0]_D[14]

No Ball

VSS

DDR[0]_D[9]

VSS

DDR[0]_D[8]

DDR[0]_D[3]

No Ball

DDR[0]_D[7]

DDR[0]_DQS[0]

No Ball

DDR[0]_D[6]

No Ball

DDR[0]_D[4]

No Ball

VSS

No Ball

DDR[0]_D[0]

DDR[0]_DQM[0]

No Ball

8

VSS

GPMC_A[15]

VSS

GPMC_A[14]

VSS

GPMC_A[13]

VSS

GPMC_A[12]

GPMC_A[8]

GPMC_A[5]

No Ball

7

VSS

6

VSS

No Ball

GPMC_CS[4]

No Ball

GPMC_A[7]

GPMC_A[6]

GPMC_A[3]

No Ball

5

VSS

No Ball

GPMC_A[4]

4

GPMC_A[10]

SD2_DAT[7]

SD2_DAT[6]

SD2_DAT[5]

No Ball

VIN[1]B_D[0]

GP1[12]

No Ball

GPMC_A[2]

No Ball

GPMC_A[1]

3

No Ball

GPMC_A[27]

VIN[1]B_D[5]

VIN[1]B_D[4]

VIN[1]B_D[7]

VIN[1]B_D[6]

VSS

2

GPMC_CS[3]

No Ball

GP1[11]

VIN[1]B_D[2]

VIN[1]B_D[1]

VIN[1]B_D[3]

No Ball

1

TIM2_IO

Ball Map Position

1

6

2

7

3

8

4

9

5

10

32

Device Pins

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.2 Pin Assignments

The following table provides a summary of the device signal ball assignments and characteristics.

1. BALL NUMBER: Package ball number(s) associated with each signal(s).

2. BALL NAME: The name of the package ball or terminal.

Note: The table does not take into account subsystem terminal multiplexing options.

3. SIGNAL NAME: The signal name for that ball in the mode being used.

4. PINCNTL REGISTER NAME AND ADDRESS: The name and address of the register that controls the

pin’s internal pull-up/down resistors and multiplexing options.

5. PINCNTL DEFAULT VALUE: The default value of the PINCNTL after reset.

6. MODE: The setting of the MUXMODE[10:0] bits in the associated PINCNTL register that selects this

multiplexed signal option.

7. TYPE: Signal direction

–

I = Input

O = Output

I/O = Input/Output

D = Open drain

DS = Differential

A = Analog

PWR = Power

GND = Ground

8. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0",

logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx

registers.

–

0: Logic 0 driven on the peripheral's input signal port.

1: Logic 1 driven on the peripheral's input signal port.

PIN: The value on the pin is driven to the peripheral's input signal port.

9. BALL RESET STATE: The state of the ball during device reset.

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor

Z: High-impedance.

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

10. BALL RESET REL. STATE: The state of the ball following the device coming out of reset.

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor

Z: High-impedance.

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

11. POWER: The voltage supply that powers the terminal’s I/O buffers.

12. HYS: Indicates if the input buffer is with hysteresis.

13. BUFFER TYPE: Drive strength of the associated output buffer.

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.2 CSI2 Interface (I/F) Signals

Table 3-13. CSI2 I/F Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

AB2

CSI2_DX[0]

CSI2_DX[1]

CSI2_DX[2]

CSI2_DX[3]

CSI2_DX[4]

CSI2_DY[0]

CSI2_DY[1]

CSI2_DY[2]

CSI2_DY[3]

CSI2_DY[4]

CSI2 Camera lane 0 differential pair input. When CSI2 is

not used these pins can be left unconnected.

I

CSI2 Camera lane 1 differential pair input. When CSI2 is

not used these pins can be left unconnected.

I

AA1

AA2

W2

V1

CSI2 Camera lane 2 differential pair input. When CSI2 is

not used these pins can be left unconnected.

CSI2 Camera lane 3 differential pair input. When CSI2 is

not used these pins can be left unconnected.

CSI2 Camera lane 4 differential pair input. When CSI2 is

not used these pins can be left unconnected.

CSI2 Camera lane 0 differential pair input. When CSI2 is

not used these pins can be left unconnected.

AC2

AB1

Y2

CSI2 Camera lane 1 differential pair input. When CSI2 is

not used these pins can be left unconnected.

CSI2 Camera lane 2 differential pair input. When CSI2 is

not used these pins can be left unconnected.

CSI2 Camera lane 3 differential pair input. When CSI2 is

not used these pins can be left unconnected.

W1

V2

CSI2 Camera lane 4 differential pair input. When CSI2 is

not used these pins can be left unconnected.

Device Pins

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3.3.3 Camera Interface (I/F)

Table 3-14. Camera I/F Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

CAM_D[0]

CAM_D[1]

CAM_D[2]

CAM_D[3]

CAM_D[4]

CAM_D[5]

CAM_D[6]

CAM_D[7]

CAM_D[8]

CAM_D[9]

CAM_D[10]

CAM_D[11]

CAM_D[12]

CAM_D[13]

CAM_D[14]

CAM_D[15]

CAM_FLD

CAM_HS

Camera data input

I

C2

C1

B2

A2

A3

B4

C5

B5

I

K11

E12

K10

D7

I

F9

I

C7

I

A6

I

A5

Camera Field Identification input

Camera Horizontal Synchronization

Camera Pixel Clock

I/O

I

J10

D5

CAM_PCLK

B3

CAM_RESET

CAM_SHUTTER

CAM_STROBE

CAM_VS

Camera Reset. Used for Strobe Synchronization

Camera Mechanical Shutter Control Signal

Camera Flash Strobe Control Signal

Camera Vertical Synchronization

Camera Write Enable

I/O

O

I/O

I

H16

H13

F13

H9

CAM_WE

H17, J10

66

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3.3.4 Controller Area Network (DCAN) Modules (DCAN0, DCAN1)

Table 3-15. DCAN Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

DCAN0 receive data pin

TYPE [3]

I/O

AAR BALL [4]

L22

DCAN0_RX

DCAN0_TX

DCAN1_RX

DCAN1_TX

DCAN0 transmit data pin

DCAN1 receive data pin

DCAN1 transmit data pin

I/O

M21

D31

D30

I/O

Device Pins

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3.3.5 DDR2/DDR3/DDR3L Memory Controller

Table 3-16. DDR2/DDR3/DDR3L Memory Controller 0 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

DDR[0] Address Bus

TYPE [3]

O

AAR BALL [4]

AL24

DDR[0]_A[0]

DDR[0]_A[1]

DDR[0]_A[2]

DDR[0]_A[3]

DDR[0]_A[4]

DDR[0]_A[5]

DDR[0]_A[6]

DDR[0]_A[7]

DDR[0]_A[8]

DDR[0]_A[9]

DDR[0] Address Bus

DDR[0] Bank Address outputs

DDR[0] Column Address Strobe output

DDR[0] Clock Enable

DDR[0] Negative Clock

DDR[0] Clock

O

AC22

AJ23

AJ27

AK28

AH27

AK30

AG23

AL29

AK29

AD23

AK24

AH23

AK23

AL23

AK22

AK26

AF23

AH25

AK25

AD20

AK27

AL27

AB21

AL9

O

DDR[0]_A[10]

DDR[0]_A[11]

DDR[0]_A[12]

DDR[0]_A[13]

DDR[0]_A[14]

DDR[0]_A[15]

DDR[0]_BA[0]

DDR[0]_BA[1]

DDR[0]_BA[2]

DDR[0]_CAS

DDR[0]_CKE

DDR[0]_CLK

DDR[0]_CS[0]

DDR[0]_D[0]

DDR[0]_D[1]

DDR[0]_D[2]

DDR[0]_D[3]

DDR[0]_D[4]

DDR[0]_D[5]

DDR[0]_D[6]

DDR[0]_D[7]

DDR[0]_D[8]

DDR[0]_D[9]

DDR[0]_D[10]

DDR[0]_D[11]

DDR[0]_D[12]

DDR[0]_D[13]

DDR[0]_D[14]

DDR[0]_D[15]

DDR[0]_D[16]

DDR[0]_D[17]

DDR[0]_D[18]

DDR[0]_D[19]

DDR[0]_D[20]

O

DDR[0] Chip Select

DDR[0] Data Bus

O

I/O

DDR[0] Data Bus

AK9

DDR[0] Data Bus

AK10

AJ11

AH11

AD9

DDR[0] Data Bus

AF11

AL12

AJ12

AG12

AD12

AB12

AK13

AC13

AL14

AK14

AH15

AF15

AD15

AK16

AJ16

DDR[0] Data Bus

68

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Table 3-16. DDR2/DDR3/DDR3L Memory Controller 0 Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

O

AAR BALL [4]

AG16

DDR[0]_D[21]

DDR[0]_D[22]

DDR[0]_D[23]

DDR[0]_D[24]

DDR[0]_D[25]

DDR[0]_D[26]

DDR[0]_D[27]

DDR[0]_D[28]

DDR[0]_D[29]

DDR[0]_D[30]

DDR[0]_D[31]

DDR[0]_DQM[0]

DDR[0]_DQM[1]

DDR[0]_DQM[2]

DDR[0]_DQM[3]

DDR[0]_DQS[0]

DDR[0] Data Bus

AD16

AC16

AK19

AJ19

AH19

AF19

AD19

AC19

AJ20

AG20

AL8

Data Mask for lower byte data bus DDR[0]_D[7:0]

Data Mask for DDR[0]_D[15:8]

O

AK12

AJ15

AK18

AL11

AK11

Data Mask for DDR[0]_D[23:16]

O

Data Mask for upper byte data bus DDR[0]_D[31:24]

Data Strobe for lower byte data bus DDR[0]_D[7:0]

O

I/O

Complimentary data strobe for lower byte data bus

DDR[0]_D[7:0]

DDR[0]_DQS[1]

DDR[0]_DQS[2]

DDR[0]_DQS[3]

Complimentary data strobe for DDR[0]_D[15:8]

Data Strobe for DDR[0]_D[15:8]

I/O

AK15

AL15

AL17

AK17

AK20

Data Strobe for DDR[0]_D[23:16]

Complimentary data strobe for DDR[0]_D[23:16]

Complimentary data strobe for upper byte data bus

DDR[0]_D[31:24]

DDR[0]_DQS[3]

DDR[0]_ODT[0]

DDR[0]_RAS

DDR[0]_RST

DDR[0]_VTP

DDR[0]_WE

Data Strobe for upper byte data bus DDR[0]_D[31:24]

DDR[0] On-Die Termination for Chip Select 0

DDR[0] Row Address Strobe output

DDR[0] Reset output

I/O

O

I

AL20

AL21

AJ25

AA20

AL30

AL26

DDR VTP Compensation Resistor Connection

DDR[0] Write Enable

O

Device Pins

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3.3.6 EDMA

Table 3-17. EDMA Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

External EDMA Event 0

TYPE [3]

AAR BALL [4]

AD2, W8

EDMA_EVT0

EDMA_EVT1

EDMA_EVT2

EDMA_EVT3

I

External EDMA Event 1

External EDMA Event 2

External EDMA Event 3

I

G28, Y11

AG30, Y3

AB9, AF27

70

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3.3.7 GPMC

Table 3-18. GPMC Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

AK3, M8

GPMC_A[0]

GPMC_A[1]

GPMC_A[2]

GPMC_A[3]

GPMC_A[4]

GPMC_A[5]

GPMC_A[6]

GPMC_A[7]

GPMC_A[8]

GPMC_A[9]

GPMC_A[10]

GPMC_A[11]

GPMC_A[12]

GPMC_A[13]

GPMC_A[14]

GPMC_A[15]

GPMC_A[16]

GPMC_A[17]

GPMC_A[18]

GPMC_A[19]

GPMC_A[20]

GPMC_A[21]

GPMC_A[22]

GPMC_A[23]

GPMC_A[24]

GPMC_A[25]

GPMC_A[26]

GPMC_A[27]

GPMC_ADV_ALE

GPMC Address 0

GPMC Address 1

GPMC Address 2

GPMC Address 3

GPMC Address 4

GPMC Address 5

GPMC Address 6

GPMC Address 7

GPMC Address 8

GPMC Address 9

GPMC Address 10

GPMC Address 11

GPMC Address 12

GPMC Address 13

GPMC Address 14

GPMC Address 15

GPMC Address 16

GPMC Address 17

GPMC Address 18

GPMC Address 19

GPMC Address 20

GPMC Address 21

GPMC Address 22

GPMC Address 23

GPMC Address 24

GPMC Address 25

GPMC Address 26

GPMC Address 27

O

AD1, AK4

AC8, AJ4

AC5, AL5

AC4, AK5

A2, AJ6

AL6, B2

AK6, C1

AJ7, C2

AK7, D5

AE4, H9

AK8, J10

AJ8, B3

AH8, L2

AG8, L4

AF8, L6

M1

M2

M3

M5

AE3, N9

AE2, N1

AE1, N2

AD2, R8

AC3, AE3, Y11

AA12, AE2, Y3

AE1, AK3, W8

AD2, AK3

AA10

GPMC Address Valid output or Address Latch Enable

output

GPMC_BE[1]

GPMC Upper Byte Enable output

O

Y11

Y3

GPMC_BE[0]_CLE

GPMC Lower Byte Enable output or Command Latch

Enable output

GPMC_CLK

GPMC_CS[0]

GPMC_CS[1]

GPMC_CS[2]

GPMC_CS[3]

GPMC_CS[4]

GPMC_CS[5]

GPMC_CS[6]

GPMC_CS[7]

GPMC_D[0]

GPMC_D[1]

GPMC_D[2]

GPMC_D[3]

GPMC Clock output

O

AB9

AC9

AA12

AC3

AF2

AG6

AB9

AA10

AD2

W6

GPMC Chip Select 0

O

GPMC Chip Select 1

O

GPMC Chip Select 2

O

GPMC Chip Select 3

O

GPMC Chip Select 4

O

GPMC Chip Select 5

O

GPMC Chip Select 6

O

GPMC Chip Select 7

O

GPMC Multiplexed Data/Address I/O

I/O

W4

W3

U2

Device Pins

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Table 3-18. GPMC Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

GPMC Multiplexed Data/Address I/O

GPMC Output Enable output

TYPE [3]

I/O

O

AAR BALL [4]

GPMC_D[4]

GPMC_D[5]

GPMC_D[6]

GPMC_D[7]

GPMC_D[8]

GPMC_D[9]

GPMC_D[10]

GPMC_D[11]

GPMC_D[12]

GPMC_D[13]

GPMC_D[14]

GPMC_D[15]

W9

T5

T3

T2

T1

T8

R6

R4

R3

R2

R1

P2

Y8

W8

GPMC_OE_RE

GPMC_WAIT[0]

GPMC_WAIT[1]

GPMC_WE

GPMC Wait input 0

I

GPMC Wait input 1

I

AB9

Y5

GPMC Write Enable output

O

72

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3.3.8 General-Purpose Input/Outputs (GPIOs)

3.3.8.1 GP0

Table 3-19. GP0 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

Y29

GP0[0]

Interrupt-Capable General-Purpose Input/Output (I/O)

GP0[1]

AB30

AA29

AA28

AA26

Y31

Y30

K23

AF27

AG30

K11

E12

AB31, K10

AC30, D7

F9

GP0[2]

GP0[3]

GP0[4]

GP0[5]

GP0[6]

GP0[7]

GP0[8]

GP0[9]

GP0[10]

GP0[11]

GP0[12]

GP0[13]

GP0[14]

GP0[15]

GP0[16]

GP0[17]

GP0[18]

GP0[19]

GP0[20]

GP0[21]

GP0[22]

GP0[23]

GP0[24]

GP0[25]

GP0[26]

GP0[27]

GP0[28]

C7

A6

A5

B5

C5

B4

A3

A2

B2

C1

C2

D5

H9

J10

3.3.8.2 GP1

Table 3-20. GP1 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

GP1[0]

GP1[1]

GP1[2]

GP1[3]

GP1[4]

GP1[5]

GP1[6]

GP1[7]

GP1[8]

GP1[9]

Interrupt-Capable General-Purpose Input/Output (I/O)

M21

L22

E31

E29

E30

N26

G28

U28

AG6

H12

I/O

Device Pins

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Table 3-20. GP1 Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

AG1

GP1[10]

GP1[11]

GP1[12]

GP1[13]

GP1[14]

GP1[15]

GP1[16]

GP1[17]

GP1[18]

GP1[19]

GP1[20]

GP1[21]

GP1[22]

GP1[23]

GP1[24]

GP1[25]

GP1[26]

GP1[27]

GP1[28]

GP1[29]

GP1[30]

GP1[31]

Interrupt-Capable General-Purpose Input/Output (I/O)

AG2, B18

A17, AG3

AC5, M3

AC4, M5

AC6, N9

J29, N1

M29, N2

M27, R8

AE3

AE2

AE1

AD2

AC9

AA12

AC3

AF2, N23

AB9

AA10

Y3

Y11

W8

3.3.8.3 GP2

Table 3-21. GP2 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

GP2[0]

GP2[1]

GP2[2]

GP2[02]

GP2[3]

GP2[4]

GP2[5]

GP2[6]

GP2[7]

GP2[8]

GP2[9]

GP2[10]

GP2[11]

GP2[12]

GP2[13]

GP2[14]

GP2[15]

GP2[16]

GP2[17]

GP2[18]

Interrupt-Capable General-Purpose Input/Output (I/O)

C12

J13

I/O

C9

I/O

B3

I/O

D13

C13

AD1, M1

AC8, M2

B17

C17

D17

F17

I/O

L20

I/O

H20

B16

C16

E16

H17

J16

I/O

H16

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Table 3-21. GP2 Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

F13

GP2[19]

GP2[20]

GP2[21]

GP2[22]

GP2[23]

GP2[24]

GP2[25]

GP2[26]

GP2[27]

GP2[28]

GP2[29]

GP2[30]

GP2[31]

Interrupt-Capable General-Purpose Input/Output (I/O)

I/O

H13

C20

F24

D21

C25

C26

C28

B28

D3

I/O

E2

I/O

F5

I/O

F1

3.3.8.4 GP3

Table 3-22. GP3 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

GP3[0]

Interrupt-Capable General-Purpose Input/Output (I/O)

F2

GP3[1]

F3

GP3[2]

G1

G2

H3

GP3[3]

GP3[4]

GP3[5]

G3

H5

GP3[6]

GP3[7]

H6

GP3[8]

J8

GP3[9]

J1

GP3[10]

GP3[11]

GP3[12]

GP3[13]

GP3[14]

GP3[15]

GP3[16]

GP3[17]

GP3[18]

GP3[19]

GP3[20]

GP3[21]

GP3[22]

GP3[23]

GP3[24]

GP3[25]

GP3[26]

GP3[27]

GP3[28]

H4

J9

L3

K1

H2

M11

L12

M10

J2

K2

L2

L4

L6

AG4

AH1

AH2

AJ2

AK1

AK2

Device Pins

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Table 3-22. GP3 Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

AL2

GP3[29]

GP3[30]

GP3[31]

Interrupt-Capable General-Purpose Input/Output (I/O)

I/O

AL3, M8

AJ31

I/O

76

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3.3.9 Ground Pins (VSS)

Table 3-23. Ground Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

VSS

Ground (GND)

GND

A1, A31, AA13, AA14,

AA15, AA16, AA17,

AA18, AA27, AC25,

AD24, AD25, AD3,

AD4, AD5, AD6, AD7,

AE12, AE19, AE20,

AE23, AE24, AE25,

AE26, AE27, AE28,

AE5, AE6, AE7, AE8,

AE9, AF12, AF20,

AF24, AF25, AF7,

AG11, AG19, AG24,

AG25, AG7, AH12,

AH20, AH7, AL1,

AL31, D25, D8, E21,

E25, E7, E8, F20,

F25, F7, F8, G20,

G23, G24, G25, G26,

G27, G4, G5, G6, G7,

G8, H26, H7, J7, L16,

M16, N13, N14, N16,

N17, P11, P12, P14,

P18, R11, R12, R14,

R18, R20, R21, T11,

T12, T14, T15, T16,

T19, T20, T21, U14,

U18, U23, V18, W16,

W17, Y16, Y17, Y25,

Y26, Y28

VSSA_AUXOSC

VSSA_CSI2

Supply Ground for Auxiliary Oscillator. If internal oscillator GND

is bypassed, this pin should be connected to ground.

U30

Analog GND for CSI2. Connect to ground even if the

CSI2 is not being used.

GND

AC7, V14

G30

VSSA_DEVOSC

VSSA_HDMI

Supply Ground for DEV Oscillator. If the internal oscillator GND

is bypassed, this pin should be connected to ground.

Analog GND for HDMI. For proper device operation, this GND

pin must always be connected to ground, even if HDMI is

not being used.

G9, H8

VSSA_USB

Analog GND for USB0 and USB1. For proper device

operation, this pin must always be connected to ground,

even if USB is not being used.

GND

D20, N19, N20

C8

VSSA_VDAC

Analog GND for VDAC. For proper device operation, this GND

pin must always be connected to ground, even if VDAC is

not being used.

Device Pins

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3.3.10 HDMI

Table 3-24. HDMI Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

M8, N2

HDMI_CEC

HDMI Consumer Electronics Control I/O

I/O

O

HDMI_CLKN

HDMI Clock Output. When the HDMI PHY is powered

down, this pin should be left unconnected.

B15

A15

A14

B13

A12

B14

B12

A11

HDMI_CLKP

HDMI_DN0

HDMI_DN1

HDMI_DN2

HDMI_DP0

HDMI_DP1

HDMI_DP2

HDMI Clock Output. When the HDMI PHY is powered

down, this pin should be left unconnected.

O

HDMI Data 0 output. When the HDMI PHY is powered

down, this pin should be left unconnected.

HDMI Data 1 output. When the HDMI PHY is powered

down, this pin should be left unconnected.

HDMI Data 2 output. When the HDMI PHY is powered

down, this pin should be left unconnected.

HDMI Data 0 output. When the HDMI PHY is powered

down, this pin should be left unconnected.

HDMI Data 1 output. When the HDMI PHY is powered

down, this pin should be left unconnected.

HDMI Data 2 output. When the HDMI PHY is powered

down, this pin should be left unconnected.

HDMI_HPDET

HDMI_SCL

HDMI Hot Plug Detect Input

HDMI I2C Serial Clock Output

HDMI I2C Serial Data I/O

I

L6, R8

D2, L2

D1, L4

I/O

HDMI_SDA

78

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3.3.11 I2C

Table 3-25. I2C Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

I2C[0]_SCL

I2C[0]_SDA

I2C[1]_SCL

I2C[1]_SDA

I2C[2]_SCL

I2C[2]_SDA

I2C[3]_SCL

I2C[3]_SDA

I2C[0] Clock I/O. For proper device operation, this pin

must be pulled up via external resistor.

I/O

T27

T24

D2

I2C[0] Data I/O. For proper device operation, this pin

must be pulled up via external resistor.

I/O

I2C[1] Clock I/O. For proper device operation in I2C

mode, this pin must be pulled up via external resistor.

I2C[1] Data I/O. For proper device operation in I2C mode, I/O

this pin must be pulled up via external resistor.

D1

I2C[2] Clock I/O. For proper device operation in I2C

mode, this pin must be pulled up via external resistor.

I/O

E31, J13, K11, L2

AG4, C12, E29, L4

AE31, G3, K10, L22

AE30, D7, H5, M21

I2C[2] Data I/O. For proper device operation in I2C mode, I/O

this pin must be pulled up via external resistor.

I2C[3] Clock I/O. For proper device operation in I2C

mode, this pin must be pulled up via external resistor.

I/O

I2C[3] Data I/O. For proper device operation in I2C mode, I/O

this pin must be pulled up via external resistor.

Device Pins

79

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.12 McASP

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3.3.12.1 McASP0

Table 3-26. McASP0 Terminal Functions

SIGNAL NAME [1]

MCA[0]_ACLKR

DESCRIPTION [2]

McASP0 Receive Bit Clock I/O

TYPE [3]

I/O

AAR BALL [4]

AD30

MCA[0]_ACLKX

MCA[0]_AFSR

MCA[0]_AFSX

MCA[0]_AHCLKX

MCA[0]_AXR[0]

MCA[0]_AXR[1]

MCA[0]_AXR[2]

MCA[0]_AXR[3]

MCA[0]_AXR[4]

MCA[0]_AXR[5]

McASP0 Transmit Bit Clock I/O

I/O

AD28

AF30

AE29

AF31

AF29

AE31

AE30

AC31

AD26

AD27

McASP0 Receive Frame Sync I/O

McASP0 Transmit Frame Sync I/O

McASP0 Transmit High-Frequency Master Clock I/O

McASP0 Transmit/Receive Data I/O

I/O

3.3.12.2 McASP1

Table 3-27. McASP1 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

McASP1 Receive Bit Clock I/O

TYPE [3]

I/O

AAR BALL [4]

MCA[1]_ACLKR

MCA[1]_ACLKX

MCA[1]_AFSR

MCA[1]_AFSX

MCA[1]_AHCLKX

MCA[1]_AXR[0]

MCA[1]_AXR[1]

AD29

AC23

AC24

AB22

AF27

Y22

McASP1 Transmit Bit Clock I/O

I/O

McASP1 Receive Frame Sync I/O

McASP1 Transmit Frame Sync I/O

McASP1 Transmit High-Frequency Master Clock I/O

McASP1 Transmit/Receive Data I/O

I/O

Y21

80

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.13 Oscillator/PLL, Audio Reference Clocks, and Clock Generator

3.3.13.1 Audio Reference Clocks

Table 3-28. Audio Reference Clocks Terminal Functions

SIGNAL NAME [1]

AUD_CLKIN0

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

AF31

Audio Reference Clock 0 for Audio Peripherals

Audio Reference Clock 1 for Audio Peripherals

Audio Reference Clock 2 for Audio Peripherals

I

AUD_CLKIN1

AUD_CLKIN2

I

AF27

AG30

3.3.13.2 CLOCK GENERATOR

Table 3-29. Clock Generator Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

CLKOUT0

CLKOUT1

Device Clock output 0. Can be used as a system clock

for other devices.

O

AJ31, H12

Device Clock output 1. Can be used as a system clock

for other devices.

O

AB9, J16

3.3.13.3 OSCILLATOR/PLL

Table 3-30. Oscillator/PLL Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

AUXOSC_MXI

Auxiliary Crystal input [Optional Audio/Video Reference

Crystal Input]. Crystal connection to internal oscillator for

auxiliary clock. Functions as AUX_CLKIN clock input

when an external oscillator is used. If neither a crystal or

external clock is used, this pin should be connected to

ground.

I

V30

AUXOSC_MXO

Auxiliary Crystal output [Optional Audio/Video Reference

Crystal Output]. When auxiliary oscillator is BYPASSED,

leave this pin unconnected.

O

U31

CLKIN32

RTC Clock input. Optional 32.768 KHz clock for RTC

reference.

I

AJ31

F30

DEVOSC_MXI

Device Crystal input. Crystal connection to internal

oscillator for system clock. Functions as DEV_CLKIN

clock input when an external oscillator is used.

DEVOSC_MXO

Device Crystal output. Crystal connection to internal

oscillator for system clock. When device oscillator is

BYPASSED, leave this pin unconnected.

O

G31

DEVOSC_WAKE

DEV_CLKIN

Oscillator Wake-up input

I

U28

F30

Clock input when an external oscillator is used

Device Pins

81

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3.3.14 Reserved Pins

Table 3-31. Reserved Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

RSV0

Reserved. Leave unconnected, do not connect to power

or ground.

J25

RSV1

Reserved. Leave unconnected, do not connect to power

or ground.

H27

H24

J30

RSV2

Reserved. Leave unconnected, do not connect to power

or ground.

RSV24

RSV25

RSV26

RSV3

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

K30

K31

H28

P31

R30

T30

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

RSV31

RSV32

RSV33

RSV34

RSV35

RSV36

RSV39

RSV4

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

AH24

AJ24

L31

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

H25

G17

H29

AD8

AK21

P30

G16

M26

M28

Reserved. Leave unconnected, do not connect to power

or ground.

PWR

RSV40

RSV41

RSV42

RSV43

RSV5

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

O

Reserved. Leave unconnected, do not connect to power

or ground.

Reserved. Leave unconnected, do not connect to power

or ground.

PWR

RSV53

RSV54

For proper device operation, this pin must always be

connected to a 1.8-V Power Supply.

For proper device operation, this pin must always be

connected to a 1.8-V Power Supply.

82

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.15 Reset, Interrupts, and JTAG Interface

3.3.15.1 Interupts

Table 3-32. Interrupts Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

Non-Maskable Interrupt input

TYPE [3]

AAR BALL [4]

AH31

NMI

I

3.3.15.2 JTAG

Table 3-33. JTAG Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

Emulator pin 0

TYPE [3]

I/O

AAR BALL [4]

A18

EMU0

EMU1

EMU2

EMU3

EMU4

RTCK

Emulator pin 1

I/O

B19

F24

C25

C28

N29

Emulator pin 2

I/O

Emulator pin 3

I/O

Emulator pin 4

I/O

JTAG return clock output. The internal pullup (IPU) is

enabled for this pin when the device is in reset and the

IPU is disabled (DIS) when reset is released.

O

TCLK

TDI

JTAG test clock input

JTAG test data input

I

T29

N28

U26

T31

I

TDO

TMS

JTAG test port data output

O

I

JTAG test port mode select input. For proper operation,

do not oppose the IPU on this pin.

TRST

JTAG test port reset input

I

U24

3.3.15.3 Reset

Table 3-34. Reset Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

Power-On Reset input

TYPE [3]

AAR BALL [4]

POR

I

AH30

AH29

AJ30

RESET

Device Reset input

I

RSTOUT_WD_OUT

Reset output (RSTOUT) or watchdog out (WD_OUT). If

this pin is unused, it can be left unconnected.

O

Device Pins

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.16 SD Signals (MMC/SD/SDIO)

3.3.16.1 SD0

www.ti.com

Table 3-35. SD0 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

AB30

SD0_CLK

SD0 Clock output

O

SD0_CMD

SD0_DAT[0]

SD0 Command output

O

AA29

AA28

SD0 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD

mode and single data bit for 1-bit SD mode.

I/O

SD0_DAT[3]

SD0_DAT[4]

SD0_DAT[5]

SD0_DAT[6]

SD0_DAT[7]

SD0 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD

mode.

I/O

I

Y30

SD0 Data4 I/O. Functions as data bit 4 for 8-bit SD

mode.

Y22

SD0 Data5 I/O. Functions as data bit 5 for 8-bit SD

mode.

Y21

SD0 Data6 I/O. Functions as data bit 6 for 8-bit SD

mode.

AB31

AC30

AA26

Y31

SD0 Data7 I/O. Functions as data bit 7 for 8-bit SD

mode.

SD0_DAT[1]_SDIRQ

SD0_DAT[2]_SDRW

SD0_SDCD

SD0 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD

mode and as an IRQ input for 1-bit SD mode.

SD0 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD

mode and as a Read Wait input for 1-bit SD mode.

SD0 Card Detect input

D30

3.3.16.2 SD1

Table 3-36. SD1Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

SD1 Clock output

TYPE [3]

AAR BALL [4]

SD1_CLK

O

W30

SD1_CMD

SD1_DAT[0]

SD1 Command output

O

AA29, Y29

W31

SD1 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD

mode and single data bit for 1-bit SD mode.

I/O

SD1_DAT[3]

SD1 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD

mode.

I/O

Y27

SD1_DAT[4]

SD1 Data4 I/O. Functions as data bit 4 for 8-bit SD

mode.

AA28

AA26

Y31

SD1_DAT[5]

SD1 Data5 I/O. Functions as data bit 5 for 8-bit SD

mode.

SD1_DAT[6]

SD1 Data6 I/O. Functions as data bit 6 for 8-bit SD

mode.

SD1_DAT[7]

SD1 Data7 I/O. Functions as data bit 7 for 8-bit SD

mode.

Y30

SD1_DAT[1]_SDIRQ

SD1_DAT[2]_SDRW

SD1 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD

mode and as an IRQ input for 1-bit SD mode.

AA30

U29

SD1 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD

mode and as a Read Wait input for 1-bit SD mode.

SD1_POW

SD1_SDCD

SD1_SDWP

SD1 Card Power Enable output

SD1 Card Detect input

O

I

E31

G28

E29

SD1 Card Write Protect input

I

84

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.16.3 SD2

Table 3-37. SD2Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

AG6

SD2_CMD

SD2 Command output

O

SD2_DAT[0]

SD2 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD

mode and single data bit for 1-bit SD mode.

AC4

AD1

AD2

AE1

AE2

AE3

AC5

AC8

SD2_DAT[3]

SD2 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD

mode.

I/O

SD2_DAT[4]

SD2 Data4 I/O. Functions as data bit 4 for 8-bit SD

mode.

SD2_DAT[5]

SD2 Data5 I/O. Functions as data bit 5 for 8-bit SD

mode.

SD2_DAT[6]

SD2 Data6 I/O. Functions as data bit 6 for 8-bit SD

mode.

SD2_DAT[7]

SD2 Data7 I/O. Functions as data bit 7 for 8-bit SD

mode.

SD2_DAT[1]_SDIRQ

SD2_DAT[2]_SDRW

SD2 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD

mode and as an IRQ input for 1-bit SD mode.

SD2 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD

mode and as a Read Wait input for 1-bit SD mode.

SD2_SCLK

SD2_SDCD

SD2 Clock output

I/O

I

AC6

D31

SD2 Card Detect input

Device Pins

85

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.17 SPI

www.ti.com

3.3.17.1 SPI 0

Table 3-38. SPI 0 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

SPI[0]_D[0]

SPI[0]_D[1]

SPI[0]_SCLK

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

J28

J27

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

SPI Clock I/O

I/O

N24

G29

G28

E29

E31

SPI[0]_SCS[0]

SPI[0]_SCS[1]

SPI[0]_SCS[2]

SPI[0]_SCS[3]

SPI Chip Select I/O

3.3.17.2 SPI 1

Table 3-39. SPI 1 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

SPI[1]_D[0]

SPI[1]_D[1]

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

N23

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

M27

SPI[1]_SCLK

SPI[1]_SCS[0]

SPI[1]_SCS[1]

SPI[1]_SCS[2]

SPI[1]_SCS[3]

SPI Clock I/O

I/O

M29

J29

SPI Chip Select I/O

U28

D31

D30

3.3.17.3 SPI 2

Table 3-40. SPI 2 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

SPI[2]_D[0]

SPI[2]_D[1]

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

AK6, M8, N1

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

AL6, L6, N2

SPI[2]_SCLK

SPI[2]_SCS[0]

SPI[2]_SCS[1]

SPI[2]_SCS[2]

SPI[2]_SCS[3]

SPI Clock I/O

I/O

AJ6, L4, R8

SPI Chip Select I/O

AF2

N9

L2

AK5

3.3.17.4 SPI 3

Table 3-41. SPI 3 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

SPI[3]_D[0]

SPI[3]_D[1]

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

A5, F5, M10

SPI Data I/O. Can be configured as either MISO or

MOSI.

I/O

A6, E2, L12

86

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

Table 3-41. SPI 3 Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

C20, C7, M11

SPI[3]_SCLK

SPI Clock I/O

SPI[3]_SCS[0]

SPI[3]_SCS[1]

SPI[3]_SCS[2]

SPI[3]_SCS[3]

SPI Chip Select I/O

I/O

F9

I/O

H2

I/O

AK1

AG4

I/O

Device Pins

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.18 Serial ATA (SATA) Signals

3.3.18.1 SATA0

www.ti.com

Table 3-42. Serial ATA 0 (SATA0) Terminal Functions

SIGNAL NAME [1]

SATA0_ACT0_LED

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

G28

Serial ATA Disk 0 Activity LED Output

O

I

SATA0_RXN0

SATA0_RXP0

SATA0_TXN0

Serial ATA Data0 Receive. When the SATA SERDES are

powered down, these pins should be left unconnected.

L30

M30

N30

Serial ATA Data0 Receive. When the SATA SERDES are

powered down, these pins should be left unconnected.

I

Serial ATA Data0 Transmit. When the SATA SERDES

are powered down, these pins should be left

unconnected.

O

SATA0_TXP0

Serial ATA Data0 Transmit. When the SATA SERDES

are powered down, these pins should be left

unconnected.

O

I

N31

H31

H30

SERDES_CLKN

SERDES_CLKP

Optional SATA Reference Clock Inputs. When these pins

are not used as optional SATA Reference Clock Inputs,

these pins can be left unconnected.

Optional SATA Reference Clock Inputs. When these pins

are not used as optional SATA Reference Clock Inputs,

these pins can be left unconnected.

I

88

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.19 Supply Voltages

Table 3-43. Supply Voltages Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

CVDD

Variable Voltage Supply for the CORE_L Core Logic

Voltage Domain

PWR

P15, P17, R15, R17,

T13, T17, T18, U11,

U12, U15, U17, V11,

V12, V15, V17, W13,

W14, W19, W20, Y13,

Y14, Y19, Y20

CVDD_ARM

CVDD_HDVICP

DVDD

Variable Voltage Supply for the ARM_L Core Logic

Voltage Domain. For actual voltage supply ranges, see

Recommended Operating Conditions.

PWR

K17, L17, L18, M13,

M14, M17

Variable Voltage Supply for the HDVICP_L Core Logic

Voltage Domain. For actual voltage supply ranges, see

Recommended Operating Conditions.

U20, U21, V20, V21,

W22

3.3 V/1.8 V Power Supply for General I/Os

D16, E17, F16, L5,

M4, M6, M7, N10,

N11, T26, T28, U27

DVDD_C

3.3 V/1.8 V Power Supply for Camera I/F I/Os. For proper PWR

device operation, this pin must always be connected to a

DVDD Power Supply, even if the Camera I/F is not being

used.

D12, E13, F12, G12,

G13

DVDD_DDR[0]

DVDD_GPMC

1.35 V/1.5 V/1.8 V Power Supply for DDR[0] I/Os

PWR

AB14, AB15, AB17,

AB18, AC15, AC17,

AC18, AE15, AE16,

AF16, AG15, AH16

3.3 V/1.8 V Power Supply for GPMC I/Os. For proper

device operation, this pin must always be connected to a

DVDD Power Supply, even if the GPMC is not being

used.

PWR

R5, R7, T4, T6, T7

DVDD_RGMII

DVDD_SD

3.3 V/1.8 V Power Supply for General I/Os. For proper

device operation, this pin must always be connected to a

DVDD Power Supply.

PWR

W5, W7, Y4, Y6, Y7

T25, U25

3.3 V/1.8 V Power Supply for MMC/SD/SDIO I/Os. For

proper device operation, this pin must always be

connected to a DVDD Power Supply, even if the interface

is not being used.

LDOCAP_ARM

ARM Cortex-A8 VBB LDO output. This pin must always

be connected via a 1-uF capacitor to VSS.

A

J19

LDOCAP_ARMRAM

LDOCAP_HDVICP

LDOCAP_HDVICPRAM

LDOCAP_RAM0

LDOCAP_RAM1

LDOCAP_RAM2

LDOCAP_SERDESCLK

VDDA_1P8

ARM Cortex-A8 RAM LDO output. This pin must always

be connected via a 1-uF capacitor to VSS.

A

K20

W23

Y24

U9

HDVICP2 VBB LDO output.This pin must always be

connected via a 1-uF capacitor to VSS.

A

HDVICP2 RAM LDO output. This pin must always be

connected via a 1-uF capacitor to VSS.

A

CORE RAM0 LDO output. This pin must always be

connected via a 1-uF capacitor to VSS.

A

CORE RAM1 LDO output. This pin must always be

connected via a 1-uF capacitor to VSS.

A

T22

AB10

M24

CORE RAM2 LDO output. This pin must always be

connected via a 1-uF capacitor to VSS.

A

SERDES_CLKP/N Pins LDO output. This pin must

always be connected via a 1-uF capacitor to VSS.

A

1.8 V Power Supply for on-chip LDOs and I/O biasing

PWR

M25, N22, N25, P23,

R9, T10, T9

VDDA_ARMPLL_1P8

VDDA_AUDIOPLL_1P8

1.8 V Analog Power Supply for PLL_ARM

PWR

L19

V9

1.8 V Analog Power Supply for PLL_AUDIO and

PLL_HDVPSS. For proper device operation, this pin must

always be connected to a 1.8-V Power Supply.

Device Pins

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Table 3-43. Supply Voltages Terminal Functions (continued)

SIGNAL NAME [1]

VDDA_CSI2_1P8

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

W10

1.8 V Analog Power Supply for CSI2. For proper device

operation, this pin must always be connected to a 1.8-V

Power Supply, even if the CSI2 is not being used.

PWR

VDDA_DDRPLL_1P8

1.8 V Analog Power Supply for PLL_DDR

PWR

AA19

L15

VDDA_HDDACREF_1P8

1.8 V Reference Power Supply for HDDAC. For proper

device operation, this pin must always be connected to a

1.8-V Power Supply, even if the HDDAC is not being

used.

VDDA_HDDAC_1P1

VDDA_HDDAC_1P8

1.1 V Power Supply for HD-DAC Digital Logic. For proper PWR

device operation, this pin must always be connected to a

1.1-V Power Supply, or if the HD-DAC is not being used

it can be connected to a power supply in the range of

0.9–1.35 V (same level as other core voltages).

K16

L14

1.8 V Power Supply for HDDAC Analog Circuit. For

proper device operation, this pin must always be

connected to a 1.8-V Power Supply, even if the HDDAC

is not being used.

PWR

VDDA_HDMI_1P8

1.8 V Analog Power Supply for HDMI. For proper device PWR

operation, this pin must always be connected to a 1.8-V

Power Supply, even if the HDMI is not being used.

K14

T23

VDDA_HDVICPPLL_1P8

1.8 V Analog Power Supply for PLL_HDVICP. For proper PWR

device operation, this pin must always be connected to a

1.8-V Power Supply, even if the HDVICP2 is not being

used.

VDDA_L3L4PLL_1P8

VDDA_SATA0_1P8

1.8 V Analog Power Supply for PLL_L3L4

PWR

W11

N27

1.8 V Analog Power Supply for SATA0. For proper device PWR

operation, this pin must always be connected to a 1.8-V

Power Supply, even if the SATA0 is not being used.

VDDA_USB0_1P8

VDDA_USB1_1P8

VDDA_USB_3P3

1.8 V Analog Power Supply for USB0. For proper device PWR

operation, this pin must always be connected to a 1.8-V

Power Supply, even if the USB0 is not being used.

K19

1.8 V Analog Power Supply for USB1 .For proper device PWR

operation, this pin must always be connected to a 1.8-V

Power Supply, even if the USB1 is not being used.

J17

3.3 V Analog Power Supply for USB0 and USB1. For

proper device operation, this pin must always be

connected to a 3.3-V Power Supply, even if USB0 and

USB1 are not being used.

PWR

M19, M20

VDDA_VDAC_1P8

VDDA_VIDPLL_1P8

1.8 V Reference Power Supply for VDAC. For proper

device operation, this pin must always be connected to a

1.8-V Power Supply, even if the VDAC is not being used.

PWR

J14

L13

1.8 V Analog Power Supply for PLL_VIDEO0 and

PLL_VIDEO1. For proper device operation, this pin must

always be connected to a 1.8-V Power Supply.

VDDS_OSC0_1P8

VDDS_OSC1_1P8

VREFSSTL_DDR[0]

Oscillator0 IO secondary supply and LJCB LDO supply

Oscillator1 IO secondary power supply

Reference Power Supply DDR[0]

PWR

P21

P20

AL18

90

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3.3.20 Timer

Table 3-44. Timer Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

I/O

AAR BALL [4]

AF27, AG1, M3

AG30, AJ31, M5

AB9, G28, N2

AA10, R8, U28

AE1, F1, Y3

TIM2_IO

TIM3_IO

TIM4_IO

TIM5_IO

TIM6_IO

TIM7_IO

Timer 2 capture event input or PWM output

Timer 3 capture event input or PWM output

Timer 4 capture event input or PWM output

Timer 5 capture event input or PWM output

Timer 6 capture event input or PWM output

Timer 7 capture event input or PWM output

I/O

AD2, C20, Y11

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.21 UART

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3.3.21.1 UART0

Table 3-45. UART0 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

D30

UART0_CTS

UART0 Clear to Send Input. Functions as SD transceiver I/O

control output in IrDA and CIR modes.

UART0_DCD

UART0_DSR

UART0_DTR

UART0_RIN

UART0_RTS

UART0 Data Carrier Detect Input

UART0 Data Set Ready Input

UART0 Data Terminal Ready Output

UART0 Ring Indicator Input

I

E31

E29

E30

N26

D31

I

O

I

UART0 Request to Send Output. Indicates module is

ready to receive data. Functions as transmit data output

in IrDA modes.

O

UART0_RXD

UART0_TXD

UART0 Receive Data Input. Functions as IrDA receive

input in IrDA modes and CIR receive input in CIR mode.

I

J26

UART0 Transmit Data Output. Functions as CIR transmit

output in CIR mode.

O

E28

3.3.21.2 UART1

Table 3-46. UART1 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

UART1_CTS

UART1 Clear to Send Input. Functions as SD transceiver I/O

control output in IrDA and CIR modes.

AG8

UART1_RTS

UART1 Request to Send Output. Indicates module is

ready to receive data. Functions as transmit data output

in IrDA modes.

O

AF8

UART1_RXD

UART1_TXD

UART1 Receive Data Input. Functions as IrDA receive

input in IrDA modes and CIR receive input in CIR mode.

(N26:MUX0, AJ8:MUX1)

I

AJ8, N26

AH8, E30

UART1 Transmit Data Output. Functions as CIR transmit

output in CIR mode. (E30:MUX0, AH8:MUX1)

O

3.3.21.3 UART2

Table 3-47. UART2 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

UART2_CTS

UART2 Clear to Send Input. Functions as SD transceiver I/O

control output in IrDA and CIR modes.

J10

B3

UART2_RTS

UART2 Request to Send Output. Indicates module is

ready to receive data. Functions as transmit data output

in IrDA modes.

O

UART2_RXD

UART2_TXD

UART2 Receive Data Input. Functions as IrDA receive

input in IrDA modes and CIR receive input in CIR mode.

(D5:MUX0, L22:MUX1, AE3:MUX3)

I

AE3, D5, L22

AE2, H9, M21

UART2 Transmit Data Output. Functions as CIR transmit

output in CIR mode. (H9:MUX0, M21:MUX1, AE2:MUX3)

O

92

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.22 USB

3.3.22.1 USB0

Table 3-48. USB0 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

B20

USB0_CE

USB0_DM

USB0 charger enable. When the USB0 PHY is powered

down, this pin should be left unconnected.

O

USB0 bidirectional data differential signal pair

[plus/minus]. When the USB0 PHY is powered down, this

pin should be left unconnected.

I/O

O

B21

A21

K23

USB0_DP

USB0 bidirectional data differential signal pair

[plus/minus]. When the USB0 PHY is powered down, this

pin should be left unconnected.

USB0_DRVVBUS

USB0 Contoller VBUS Control ouput. When this pin is

used as USB0_DRVVBUS and the USB0 Controller is

operating as a Host, this signal is used by the USB0

Controller to enable the external VBUS charge pump.

When the USB0 PHY is powered down, this pin should

be left unconnected.

USB0_ID

USB0 identification input. When the USB0 PHY is

powered down, this pin should be left unconnected.

I

A20

B22

USB0_VBUSIN

5-V USB0 VBUS comparator input. This analog input pin

senses the level of the USB VBUS voltage and should

connect directly to the USB VBUS voltage. When the

USB0 PHY is powered down, this pin should be left

unconnected.

3.3.22.2 USB1

Table 3-49. USB1 Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

USB1_CE

USB1_DM

USB1 charger enable. When the USB1 PHY is powered

down, this pin should be left unconnected.

O

C21

USB1 bidirectional data differential signal pair

[plus/minus]. When the USB1 PHY is powered down, this

pin should be left unconnected.

I/O

O

B23

USB1_DP

USB1 bidirectional data differential signal pair

[plus/minus]. When the USB1 PHY is powered down, this

pin should be left unconnected.

A23

USB1_DRVVBUS

USB1 Contoller VBUS Control ouput. When this pin is

used as USB1_DRVVBUS and the USB1 Controller is

operating as a Host, this signal is used by the USB1

Controller to enable the external VBUS charge pump.

When the USB1 PHY is powered down, this pin should

be left unconnected.

AF31

USB1_ID

USB1 identification input. When the USB1 PHY is

powered down, this pin should be left unconnected.

I

A24

B24

USB1_VBUSIN

5-V USB1 VBUS comparator input. This analog input pin

senses the level of the USB VBUS voltage and should

connect directly to the USB VBUS voltage. When the

USB1 PHY is powered down, this pin should be left

unconnected.

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

3.3.23 Video Input (Digital)

3.3.23.1 Video Input 0 (Digital)

www.ti.com

Table 3-50. Video Input 0 (Digital) Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

VIN[0]A_CLK

Video Input 0 Port A Clock input. Input clock for 8-bit, 16-

bit, or 24-bit Port A video capture.

I

C9

VIN[0]A_D[0]

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

I

B18

A17

B17

C17

D17

F17

L20

H20

VIN[0]A_D[1]

VIN[0]A_D[2]

VIN[0]A_D[3]

VIN[0]A_D[4]

VIN[0]A_D[5]

VIN[0]A_D[6]

VIN[0]A_D[7]

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B data

inputs.

VIN[0]A_D[16]

VIN[0]A_D[17]

VIN[0]A_D[18]

VIN[0]A_D[19]

VIN[0]A_D[20]

VIN[0]A_D[21]

VIN[0]A_D[22]

VIN[0]A_D[23]

VIN[0]A_DE

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

I

K11

E12

K10

D7

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

F9

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

C7

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

A6

Video Input 0 Data inputs. For RGB capture, D[23:16] are

R data inputs.

A5

Video Input 0 Port A Data Enable input. Discrete data

valid signal for Port A RGB capture mode or YCbCr

capture without embedded syncs (BT.601 modes).

B5, C12

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

Table 3-50. Video Input 0 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

E16

VIN[0]A_D[10]_BD[2]

VIN[0]A_D[11]_BD[3]

VIN[0]A_D[12]_BD[4]

VIN[0]A_D[13]_BD[5]

VIN[0]A_D[14]_BD[6]

VIN[0]A_D[15]_BD[7]

VIN[0]A_D[8]_BD[0]

VIN[0]A_D[9]_BD[1]

VIN[0]A_FLD

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

I

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

I

H17

J16

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

H16

F13

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

H13

B16

C16

B4, J13

D13

C13

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

Video Input 0 Data inputs. For 16-bit capture, D[15:8] are

Y Port A inputs. For 8-bit capture, D[15:8] are Port B

YCbCr data inputs. For RGB capture, D[15:8] are G data

inputs.

Video Input 0 Port A Field ID input. Discrete field

identification signal for Port A RGB capture mode or

YCbCr capture without embedded syncs (BT.601

modes).

VIN[0]A_HSYNC

Video Input 0 Port A Horizontal Sync0 input. Discrete

horizontal synchronization signal for Port A RGB capture

mode or YCbCr capture without embedded syncs

(BT.601 modes).

VIN[0]A_VSYNC

Video Input 0 Port A Vertical Sync0 input. Discrete

vertical synchronization signal for Port A RGB capture

mode or YCbCr capture without embedded syncs

(BT.601 modes).

VIN[0]B_CLK

VIN[0]B_DE

VIN[0]B_FLD

Video Input 0 Port B Clock input. Input clock for 8-bit Port

B video capture. This signal is not used in 16-bit and 24-

bit capture modes.

I

H12

C5

Video Input 0 Port B Data Enable input. Discrete data

valid signal for Port B RGB capture mode or YCbCr

capture without embedded syncs (BT.601 modes).

Video Input 0 Port B Field ID input. Discrete field

identification signal for Port B 8-bit YCbCr capture without

embedded syncs (BT.601 modes). Not used in RGB or

16-bit YCbCr capture modes.

A3

VIN[0]B_HSYNC

VIN[0]B_VSYNC

Video Input 0 Port B Horizontal Sync input. Discrete

horizontal synchronization signal for Port B 8-bit YCbCr

capture without embedded syncs (BT.601 modes). Not

used in RGB or 16-bit YCbCr capture modes.

I

C12

J13

Video Input 0 Port B Vertical Sync1 input. Discrete

vertical synchronization signal for Port B 8-bit YCbCr

capture without embedded syncs (BT.601 modes). Not

used in RGB or 16-bit YCbCr capture modes.

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3.3.23.2 Video Input 1 (Digital)

Table 3-51. Video Input 1 (Digital) Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

VIN[1]A_CLK

Video Input 1 Port A Clock input. Input clock for 8-bit, 16-

bit, or 24-bit Port A video capture. Input data is sampled

on the CLK0 edge.

I

F1

F2

VIN[1]A_D[0]

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

I

VIN[1]A_D[1]

VIN[1]A_D[2]

VIN[1]A_D[3]

VIN[1]A_D[4]

VIN[1]A_D[5]

VIN[1]A_D[6]

VIN[1]A_D[7]

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

F3

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

G1

G2

H3

G3

H5

M8

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

Video Input 1 Data inputs. For 16-bit capture, D[7:0] are

Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A

YCbCr data inputs. For RGB capture, D[7:0] are B Port A

data inputs.

VIN[1]A_D[8]

VIN[1]A_D[9]

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

I

H6

J8

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

VIN[1]A_D[10]

VIN[1]A_D[11]

VIN[1]A_D[12]

VIN[1]A_D[13]

VIN[1]A_D[14]

VIN[1]A_D[15]

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

J1

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

H4

J9

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

L3

K1

H2

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y

Port A inputs. For RGB capture, D[15:8] are G Port A

data inputs.

96

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SPRS870B –APRIL 2013–REVISED DECEMBER 2013

Table 3-51. Video Input 1 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

M11

VIN[1]A_D[16]

VIN[1]A_D[17]

VIN[1]A_D[18]

VIN[1]A_D[19]

VIN[1]A_D[20]

VIN[1]A_D[21]

VIN[1]A_D[22]

VIN[1]A_D[23]

VIN[1]A_DE

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

I

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

I

L12

M10

J2

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

K2

L2

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

L4

Video Input 1 Data inputs. For RGB capture, D[23:16] are

R Port A data inputs.

L6

Video Input 1 Port A Data Enable input. Discrete data

valid signal for Port A YCbCr capture modes without

embedded syncs (BT.601 modes).

F5

VIN[1]A_FLD

Video Input 1 Port A Field ID input. Discrete field

identification signal for Port A YCbCr capture modes

without embedded syncs (BT.601 modes).

I

F5

D3

VIN[1]A_HSYNC

Video Input 1 Port A Horizontal Sync input. Discrete

horizontal synchronization signal for Port A YCbCr

capture modes without embedded syncs (BT.601

modes).

VIN[1]A_VSYNC

VIN[1]B_CLK

Video Input 1 Port A Vertical Sync input. Discrete vertical

synchronization signal for Port A YCbCr capture modes

without embedded syncs (BT.601 modes).

I

E2

Video Input 1 Port B Clock input. Input clock for 8-bit Port

B video capture. Input data is sampled on the CLK1

edge. This signal is not used in 16-bit and 24-bit capture

modes.

AF2

VIN[1]B_D[0]

VIN[1]B_D[1]

VIN[1]B_D[2]

VIN[1]B_D[3]

VIN[1]B_D[4]

VIN[1]B_D[5]

VIN[1]B_D[6]

VIN[1]B_D[7]

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

I

AG4

AH1

AH2

AJ2

AK1

AK2

AL2

AL3

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

Video Input Port B Data inputs. For 8-bit capture,

B_D[7:0] are Port B YCbCr data inputs.

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3.3.24 Video Output (Analog, TV)

Table 3-52. Video Output (Analog, TV) Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

HDDAC_A

HDDAC_B

HDDAC_C

Analog HD Video DAC (G/Y). This pin should be

connected to ground through a 165-ohm resistor.

O

A9

A8

B8

Analog HD Video DAC (B/Pb). This pin should be

connected to ground through a 165-ohm resistor.

O

Analog HD Video DAC (R/Pr). This pin should be

connected to ground through a 165-ohm resistor.

HDDAC_HSYNC

HDDAC_IREF

Analog HD Video DAC Discrete HSYNC Output

E9

B6

Video DAC reference current. When the video DACs are I/O

used, this pin should be connected to ground through a

2.67K-ohm resistor. When the video DACs are powered

down, this pin should be left unconnected.

HDDAC_VREF

Video DAC reference voltage. When the video DACs are

powered down, this pin should be left unconnected.

I

B7

HDDAC_VSYNC

TV_OUT0

Analog HD Video DAC Discrete VSYNC Output

O

D9

B9

Composite Amplifier Output. In Normal mode (internal

amplifier used), this pin drives the 75-Ohm TV load. An

external resistor (Rout) should be connected between

this pin and the TV_VFB0 pin and be placed as close to

the pins as possible. The nominal value of Rout is 2700

Ohm. In TVOUT Bypass mode (internal amplifier not

used), this pin is not used. When this pin is not used or

the TV output is powered-down, this pin should be left

unconnected.

TV_RSET

TV Input Reference Current Setting. An external resistor

(Rset) should be connected between this pin and

VSSA_VDAC to set the reference current of the video

DAC. The value of the resistor depends on the mode of

operation. In Normal mode (internal amplifier used), the

nominal value for Rset is 4700 Ohm. In TVOUT Bypass

mode (internal amplifier not used), the nominal value for

Rset is 10000 Ohm. When the TV output is not used, this

pin should be connected to ground (VSS).

A

B11

TV_VFB0

Composite Feedback. In Normal mode (internal amplifier

used), this pin acts as the buffer feedback node. An

external resistor (Rout) should be connected between

this pin and the TV_OUT0 pin. In TVOUT Bypass mode

(internal amplifier not used), this pin acts as the direct

Video DAC output and should be connected to ground

through a load resistor (Rload) and to an external video

amplifier. The nominal value of Rload is 1500 Ohm.

When this pin is not used or the TV output is powered-

down, this pin should be left unconnected.

O

B10

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3.3.25 Video Output (Digital)

3.3.25.1 Video Output 0 (Digital)

Table 3-53. Video Output 0 (Digital) Terminal Functions

SIGNAL NAME [1]

VOUT[0]_AVID

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

C20

Video Output Active Video output. This is the discrete

active video indicator output. This signal is not used for

embedded sync modes.

O

VOUT[0]_B_CB_C[2]

VOUT[0]_B_CB_C[3]

VOUT[0]_B_CB_C[4]

VOUT[0]_B_CB_C[5]

VOUT[0]_B_CB_C[6]

VOUT[0]_B_CB_C[7]

VOUT[0]_B_CB_C[8]

VOUT[0]_B_CB_C[9]

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

O

F24

D21

J23

H23

J24

E24

D24

C24

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

VOUT[0]_CLK

VOUT[0]_FLD

Video Output Clock output

O

K22

Video Output Field ID output. This is the discrete field

identification output. This signal is not used for embedded

sync modes.

B3, C20

VOUT[0]_G_Y_YC[2]

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

O

C25

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Table 3-53. Video Output 0 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

VOUT[0]_G_Y_YC[3]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

C26

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

O

VOUT[0]_G_Y_YC[4]

VOUT[0]_G_Y_YC[5]

VOUT[0]_G_Y_YC[6]

VOUT[0]_G_Y_YC[7]

VOUT[0]_G_Y_YC[8]

VOUT[0]_G_Y_YC[9]

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

O

E26

B26

A26

B25

B27

A27

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

VOUT[0]_HSYNC

VOUT[0]_R_CR[2]

Video Output Horizontal Sync output. This is the discrete

horizontal synchronization output. This signal is not used

for embedded sync modes.

O

F21

C28

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

VOUT[0]_R_CR[3]

VOUT[0]_R_CR[4]

VOUT[0]_R_CR[5]

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

O

B28

B29

A29

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

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Table 3-53. Video Output 0 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

C30

VOUT[0]_R_CR[6]

VOUT[0]_R_CR[7]

VOUT[0]_R_CR[8]

VOUT[0]_R_CR[9]

VOUT[0]_VSYNC

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

O

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

O

B30

A30

B31

E20

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

Video Output Vertical Sync output. This is the discrete

vertical synchronization output. This signal is not used for

embedded sync modes.

3.3.25.2 Video Output 1 (Digital)

Table 3-54. Video Output 1 (Digital) Terminal Functions

SIGNAL NAME [1]

VOUT[1]_AVID

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

Video Output Active Video output. This is the discrete

active video indicator output. This signal is not used for

embedded sync modes.

O

F1

H9

VOUT[1]_B_CB_C[0]

Video Output Data. These signals represent the 2 LSBs

of B/Cb/C video data for 10-bit, 20-bit, and 30-bit video

modes (VOUT[1] only). For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused. These signals

are not used in 16/24-bit modes.

O

VOUT[1]_B_CB_C[1]

Video Output Data. These signals represent the 2 LSBs

of B/Cb/C video data for 10-bit, 20-bit, and 30-bit video

modes (VOUT[1] only). For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused. These signals

are not used in 16/24-bit modes.

O

D5

VOUT[1]_B_CB_C[2]

VOUT[1]_B_CB_C[3]

VOUT[1]_B_CB_C[4]

VOUT[1]_B_CB_C[5]

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

O

M8

F2

F3

G1

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

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Table 3-54. Video Output 1 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

VOUT[1]_B_CB_C[6]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

O

G2

H3

G3

H5

VOUT[1]_B_CB_C[7]

VOUT[1]_B_CB_C[8]

VOUT[1]_B_CB_C[9]

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

O

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

Video Output Data. These signals represent the 8 MSBs

of B/Cb/C video data. For RGB mode they are blue data

bits, for YUV444 mode they are Cb (Chroma) data bits,

for Y/C mode they are multiplexed Cb/Cr (Chroma) data

bits and for BT.656 mode they are unused.

VOUT[1]_CLK

VOUT[1]_FLD

Video Output Clock output

O

D3

Video Output Field ID output. This is the discrete field

identification output. This signal is not used for embedded

sync modes.

J10

VOUT[1]_G_Y_YC[0]

Video Output Data. These signals represent the 2 LSBs

of G/Y/YC video data for 10-bit, 20-bit, and 30-bit video

modes (VOUT[1] only). For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits. These signals are not used in 8/16/24-bit modes.

O

B2

VOUT[1]_G_Y_YC[1]

Video Output Data. These signals represent the 2 LSBs

of G/Y/YC video data for 10-bit, 20-bit, and 30-bit video

modes (VOUT[1] only). For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits. These signals are not used in 8/16/24-bit modes.

O

A2

VOUT[1]_G_Y_YC[2]

VOUT[1]_G_Y_YC[3]

VOUT[1]_G_Y_YC[4]

VOUT[1]_G_Y_YC[5]

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

O

L2

H6

J8

J1

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

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Table 3-54. Video Output 1 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

VOUT[1]_G_Y_YC[6]

VOUT[1]_G_Y_YC[7]

VOUT[1]_G_Y_YC[8]

VOUT[1]_G_Y_YC[9]

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

O

H4

J9

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

O

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

L3

K1

Video Output Data. These signals represent the 8 MSBs

of G/Y/YC video data. For RGB mode they are green

data bits, for YUV444 mode they are Y data bits, for Y/C

mode they are Y (Luma) data bits and for BT.656 mode

they are multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

VOUT[1]_HSYNC

VOUT[1]_R_CR[0]

Video Output Horizontal Sync output. This is the discrete

horizontal synchronization output. This signal is not used

for embedded sync modes.

O

E2

C2

Video Output Data. These signals represent the 2 LSBs

of R/Cr video data for 30-bit video modes. For RGB

mode they are red data bits, for YUV444 mode they are

Cr (Chroma) data bits, for Y/C mode and BT.656 modes

they are unused. These signals are not used in 24-bit

mode.

VOUT[1]_R_CR[1]

Video Output Data. These signals represent the 2 LSBs

of R/Cr video data for 30-bit video modes. For RGB

mode they are red data bits, for YUV444 mode they are

Cr (Chroma) data bits, for Y/C mode and BT.656 modes

they are unused. These signals are not used in 24-bit

mode.

O

C1

VOUT[1]_R_CR[2]

VOUT[1]_R_CR[3]

VOUT[1]_R_CR[4]

VOUT[1]_R_CR[5]

VOUT[1]_R_CR[6]

VOUT[1]_R_CR[7]

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

O

L6

L4

H2

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

M11

L12

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

M10

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Table 3-54. Video Output 1 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

VOUT[1]_R_CR[8]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

O

J2

K2

F5

VOUT[1]_R_CR[9]

VOUT[1]_VSYNC

Video Output Data. These signals represent the 8 MSBs

of R/Cr video data. For RGB mode they are red data bits,

for YUV444 mode they are Cr (Chroma) data bits, for Y/C

mode and BT.656 modes they are unused.

O

Video Output Vertical Sync output. This is the discrete

vertical synchronization output. This signal is not used for

embedded sync modes.

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4 Device Configurations

4.1 Control Module Registers

4.2 Boot Modes

The state of the device after boot is determined by sampling the input states of the BTMODE[15:0] pins

when device reset (POR or RESET) is de-asserted. The sampled values are latched into the

CONTROL_STATUS register, which is part of the Control Module. The BTMODE[15:11] values determine

the following system boot settings:

•

RSTOUT_WD_OUT Control

GPMC CS0 Default Data Bus Width, Wait Enable, and Address/Data Multiplexing

For additional details on BTMODE[15:11] pin functions, see Table 3-12, Boot Configuration Terminal

Functions.

The BTMODE[4:0] values determine the boot mode order according to Table 4-1, Boot Mode Order. The

1st boot mode listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the

primary boot mode fails, the 2nd, 3rd, and 4th boot modes are executed in that order until a successful

boot is completed.

The BTMODE[9:5] pins are RESERVED and should be pulled down as indicated in Table 3-12, Boot

Configuration Terminal Functions.

When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected

(see Table 4-1), the sampled value from BTMODE[10] pin is used to select between GPMC pin muxing

options shown in Table 4-2, XIP (on GPMC) Boot Options [Muxed or Non-Muxed].

For more detailed information on booting the device, including which pins are used for each boot mode,

see the ROM Code Memory and Peripheral Booting chapter in the device-specific Technical Reference

Manual.

Device Configurations

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Table 4-1. Boot Mode Order

BTMODE[4:0]

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

1st

RESERVED

UART

2nd

RESERVED

XIP w/WAIT (MUX0)⁽¹⁾⁽²⁾

SPI

3rd

RESERVED

MMC

4th

RESERVED

SPI

UART

NAND

XIP (MUX0)⁽¹⁾⁽²⁾

NANDI2C

MMC

UART

SPI

RESERVED

Fast XIP (MUX0)⁽¹⁾

XIP (MUX1)⁽¹⁾⁽²⁾

SPI

NAND

NANDI2C

RESERVED

XIP (MUX1)⁽¹⁾⁽²⁾

RESERVED

MMC

RESERVED

MMC

RESERVED

SPI

RESERVED

UART

RESERVED

SPI

UART

XIP w/WAIT (MUX1)⁽¹⁾⁽²⁾

UART

NANDI2C

MMC

NAND

UART

NAND

MMC

UART

NAND

SPI

RESERVED

UART

NANDI2C

RESERVED

UART

SPI

MMC

RESERVED

MMC

SPI

UART

SPI

MMC

RESERVED

SPI

MMC

XIP (MUX0)⁽¹⁾⁽²⁾

XIP w/WAIT (MUX0)⁽¹⁾⁽²⁾

RESERVED

Fast XIP (MUX0)⁽¹⁾

UART

SPI

MMC

RESERVED

UART

RESERVED

(1) GPMC CS0 eXecute In Place (XIP) boot for NOR/OneNAND/ROM. MUX0/1 refers to the multiplexing option for the GPMC_A[12:0] pins.

For more detailed information on booting the device, including which pins are used for each boot mode, see the ROM Code Memory

and Peripheral Booting chapter in the device-specific Technical Reference Manual.

(2) When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected, the sampled value from

BTMODE[10] pin is used to select between GPMC pin configuration options shown in Table 4-2, XIP (on GPMC) Boot Options.

4.2.1 XIP (NOR) Boot Options

Table 4-2 shows the XIP (NOR) boot mode GPMC pin configuration options (Option A: BTMODE[10] = 0

and Option B: BTMODE[10] = 1). For Option B, the pull state on select pins is reconfigured to IPD and

remains IPD after boot until the user software reconfigures it. In Table 4-2, GPMC_A[1:12] are configured

only for Non-Muxed NOR flash. In the case of Muxed NOR Flash, GPMC_D[15:0] act as both address and

data lines so configuration of GPMC_A[1:12] in XIP_Mux0 mode and XIP_Mux1 mode doesn't apply for a

Muxed NOR flash and those pins are not configured by Boot ROM.

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4.2.2 NAND Flash Boot

Table 4-3 lists the device pins that are configured by the ROM for the NAND Flash boot mode.

NOTE: Table 4-3 lists the configuration of the GPMC_CLK pin (pin mux and pull state) in NAND

bootmodes.

The NAND flash memory is not XIP and requires shadowing before the code can be executed.

Table 4-3. Pins Used in NAND FLASH Bootmode

OTHER

CONDITIONS

SIGNAL NAME

PIN NO.

TYPE

GPMC_CS[0]/*

GPMC_ADV_ALE/*

AC9

AA10

Y8

O

I

GPMC_OE_RE

BTMODE[12] = 0b

(8-bit Mode)

BTMODE[12] = 1b

(16-bit Mode)

GPMC_BE[0]_CLE/GPMC_A[25]/*

GPMC_BE[1]/GPMC_A[24]/*

GPMC_WE

Y3

Y11

Y5

BTMODE[14:13] =

00b (GPMC CS0

not muxed)

BTMODE[15] = 0b

(wait disabled)

GPMC_WAIT[0]/GPMC_A[26]/*⁽¹⁾

W8

GPMC_CLK/*

AB9

I/O

P2, R1, R2, R3,

R4, R6, T8, T1, T2,

T3, T5, W9, U2,

W3, W4, W6

GPMC_D[15:0]/*

I/O

(1) GPMC_CLK/* is not configured in BTMODE[10] = 1 [OPTION B]

4.2.3 NAND I2C Boot (I2C EEPROM)

Table 4-4 lists the device pins that are configured by the ROM for the NAND I2C boot mode.

Table 4-4. Pins Used in NAND I2C Bootmode

SIGNAL NAME

I2C[0]_SCL

I2C[0]_SDA

PIN NO.

T27

TYPE

I/O

T24

I/O

4.2.4 MMC/SD Cards Boot

Table 4-5 lists the device pins that are configured by the ROM for the MMC/SD boot mode.

Table 4-5. Pins Used in MMC/SD Bootmode

SIGNAL NAME

SD1_CLK

PIN NO.

W30

Y29

TYPE

I/O

SD1_CMD/GP0[0] [MUX0]

SD1_DAT[0]

I/O

W31

AA30

U29

I/O

SD1_DAT[1]_SDIRQ

SD_DAT[2]_SDRW

SD1_DAT[3]

I/O

Y27

I/O

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4.2.5 SPI Boot

Table 4-6 lists the device pins that are configured by the ROM for the SPI boot mode.

Table 4-6. Pins Used in SPI Bootmode

SIGNAL NAME

SPI[0]_SCS[0]

PIN NO.

G29

TYPE

I/O

SPI[0]_D[0] (MISO)

SPI[0]_D[1] (MOSI)

SPI[0]_SCLK

J28

I/O

J27

I/O

N24

I/O

4.2.6 UART Bootmode

Table 4-7 lists the device pins that are configured by the ROM for the UART boot mode.

Table 4-7. Pins Used in UART Bootmode

SIGNAL NAME

UART0_RXD

PIN NO.

J26

TYPE

I

UART0_TXD

E28

O

4.3 Pin Multiplexing Control

Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1 –

PINCNTL270 registers in the Control Module.

Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output

data values. Table 4-8 shows the peripheral pin functions associated with each MUXMODE setting for all

multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in

which case the pin's I/O buffer is 3-stated.

In most cases, the input from each pin is routed to all of the peripherals that share the pin, regardless of

the MUXMODE setting. However, in some cases a constant "0" or "1" value is routed to the associated

peripheral when its peripheral function is not selected to control any output pin. For more details on the

De-Selected Input State (DSIS), see the columns of each Terminal Functions table (Section 3.3, Terminal

Functions).

Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin

functions are called Multimuxed and may have different Switching Characteristics and Timing

Requirements for each device pin option.

For more detailed information on the Pin Control 1 through Pin Control 270 (PINCNTLx) registers

breakout, see Figure 4-1 and Table 4-8.

Figure 4-1. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Breakout

31

15

24

23

20

19

18

17

16

RESERVED

R - 0000

RSV

RSV PLLTY PLLU

PESE

L

DEN

R - 0000 0000

R/W

8

7

0

RESERVED

MUXMODE[7:0]

R/W - 0000 0000

R - 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 4-8. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions

Bit

Field

Description

Comments

31:20

RESERVED

Reserved. Read only, writes have no effect.

Reserved. This bit must always be written with the

reset (default) value.

19

18

RSV

Reserved. This field must always be written as "1".

Pullup/Pulldown Type Selection bit

For PINCNTLx register reset value

examples, see Table 4-9, PNICNTLx

Register Reset Value Examples.

17

PLLTYPSEL

0 = Pulldown (PD) selected

1 = Pullup (PU) selected

Pullup/Pulldown Enable bit

For the full register reset values of all

PINCNTLx registers.

16

15:8

7:0

PLLUDEN

0 = PU/PD enabled

1 = PU/PD disabled

RESERVED

MUXMODE[7:0]

Reserved. Read only, writes have no effect.

MUXMODE Selection bits

These bits select the multiplexed mode pin function

settings. Values other than those are illegal.

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4.4 Handling Unused Pins

When device signal pins are unused in the system, they can be left unconnected unless otherwise noted

in the Terminal Functions tables (see Section 3.3). For unused input pins, the internal pull resistor should

be enabled, or an external pull resistor should be used, to prevent floating inputs. All supply pins must

always be connected to the correct voltage, even when their associated signal pins are unused.

4.5 DeBugging Considerations

4.5.1 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not

floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and

internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external

pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

•

Boot Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external

pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired

value/state.

•

Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external

pullup/pulldown resistor to pull the signal to the opposite rail.

For the boot configuration pins (listed in Section 3.3, Boot Configuration Terminal Functions), if they are

both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown

resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may

match the desired configuration value, providing external connectivity can help ensure that valid logic

levels are latched on these device boot configuration pins. In addition, applying external pullup/pulldown

resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in

switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

•

Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure

to include the leakage currents of all the devices connected to the net, as well as any internal pullup or

pulldown resistors.

•

Decide a target value for the net. For a pulldown resistor, this should be below the lowest V_ILlevel of

all inputs connected to the net. For a pullup resistor, this should be above the highest V_IHlevel of all

inputs on the net. A reasonable choice would be to target the V_OLor V_OHlevels for the logic family of

the limiting device; which, by definition, have margin to the V_ILand V_IHlevels.

•

Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net

will reach the target pulled value when maximum current from all devices on the net is flowing through

the resistor. The current to be considered includes leakage current plus, any other internal and

external pullup/pulldown resistors on the net.

For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance

value of the external resistor. Verify that the resistance is small enough that the weakest output buffer

can drive the net to the opposite logic level (including margin).

•

Remember to include tolerances when selecting the resistor value.

For pullup resistors, also remember to include tolerances on the DV_DDrail.

For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.

Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration

pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific

application.

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For most systems, a 20-kΩ resistor can also be used as an external PU/PD on the pins that have

IPUs/IPDs disabled and require an external PU/PD resistor while still meeting the above criteria. Users

should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I_I), and the low-/high-level input voltages (V_ILand V_IH) for

the device, see Section 6.4, Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Temperature.

For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal

functions table.

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5 System Interconnect

The device’s various processors, subsystems, and peripherals are interconnected through a switch fabric

architecture. The switch fabric is composed of an L3 and L4 interconnect, a switched central resource

(SCR), and multiple bridges (for an overview, see Figure 5-1). Not all Initiators in the switch fabric are

connected to all Target peripherals. The supported initiator and target connections are designated by a "X"

in Table 5-1, Target/Initiator Connectivity.

EDMATC RD 0/1

EDMATC WR 0/1

L3F

Initiators

EDMATC RD 2/3

EDMATC WR 2/3

HDVICP2

L3F

Initiators

MEDIACTL

L3F

Initiators

FD

SATA0

DAP

L3F

Initiators

JTAG

USB2.0 (2 I/F)

ARM Cortex

A8

HDVPSS (2 I/F)

ISS

64b

128b

64b

128b

32b

1 I/F

8 I/F

4 I/F

1 I/F

4 I/F

3 I/F

L3F/L3Mid

Interconnect

200 MHz (Note 1)

L3S Interconnect

100 MHz (Note 1)

2 I/F

1 I/F

128b

2 I/F

64b

10 I/F

32b

5 I/F

2 I/F

32b

128b

32b

DMM

L3F

Targets

L3F

Targets

L3F

Targets

L3S

Targets

L4F

Interconnect

L4S

Interconnect

ISS

MMCSD 2

HDVICP 2 CFG

EDMATC 0/1/2/3

EDMACC

HDVICP2 SL2

MEDIACTL

OCMC SRAM

MCASP 0/1 Data

GPMC

HDMI

200MHz

100MHz

DDR

(Note 1)

(Note1)

44 I/F

32b

USB

DEBUGSS

2 I/F

32b

L4F Targets

L4S Targets

UART 0/1/2

I2C 0/1/2/3

DMTimer 1/2/3/4/5/6/7/8

SPI 0/1/2/3

GPIO 0/1/2/3

McASP 0/1 CFG

MMCSD 0/1

ELM

SATA0

RTC

WDT 0/1

Mailbox

Spinlock

HDVPSS

HDMIPHY

PLLSS

Control Module

PRCM

SmartReflex 0/1

DCAN0/1

OCPWP

SYNCTIMER32K

Note 1: The frequencies specified are for 100% OPP.

Figure 5-1. System Interconnect

System Interconnect

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Table 5-1. L3 Master/Slave Connectivity

MASTERS

SLAVES

GPMC

SD2

ARM M1 (128-bit)

ARM M2 (64-bit)

HDVICP2 VDMA

HDVPSS Mstr0

HDVPSS Mstr1

SATA0

X

USB2.0 DMA

USB2.0 Queue Mgr

Media Controller

DeBug Access Port (DAP)

EDMA TPTC0 RD

EDMA TPTC0 WR

EDMA TPTC1 RD

EDMA TPTC1 WR

EDMA TPTC2 RD

EDMA TPTC2 WR

EDMA TPTC3 RD

EDMA TPTC3 WR

ISS

X

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The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large

number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to

four initiators and can distribute those communication requests to and collect related responses from up to

63 targets.

The device provides two interfaces with L3 interconnect for high-speed and standard peripherals.

Table 5-2. L4 Peripheral Connectivity⁽¹⁾

MASTERS

L4 PERIPHERALS

ARM Cortex-A8 M2

(64-bit)

EDMA TPTC0

EDMA TPTC1

EDMA TPTC2

EDMA TPTC3

L4 Fast Peripherals Port 0/1

SATA0

Port0

Port1

Port0

Port1

Port0

L4 Slow Peripherals Port 0/1

I2C0

Port0

Port1

Port0

Port1

Port0

I2C1

I2C2

I2C3

SPI0

SPI1

SPI2

SPI3

UART0

UART1

UART2

Timer1

Timer2

Timer3

Timer4

Timer5

Timer6

Timer7

Timer8

GPIO0

GPIO1

MMC/SD0/SDIO

MMC/SD1/SDIO

MMC/SD2/SDIO

WDT0

RTC

SmartReflex0

SmartReflex1

Mailbox

Spinlock

HDVPSS

PLLSS

Port1

Port0

Port1

Port0

Control/Top Regs (Control Module)

PRCM

ELM

HDMIPHY

(1) X, Port0, Port1 = Connection exists.

System Interconnect

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Table 5-2. L4 Peripheral Connectivity⁽¹⁾(continued)

MASTERS

EDMA TPTC1

Port0

L4 PERIPHERALS

ARM Cortex-A8 M2

(64-bit)

EDMA TPTC0

EDMA TPTC2

EDMA TPTC3

DCAN0/1

Port0

Port1

Port0

OCPWP

McASP0 CFG

McASP1 CFG

SYNCTIMER32K

Port1

Port0

Port1

Port0

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6 Device Operating Conditions

(1)(2)

6.1 Absolute Maximum Ratings

Core (CVDD, CVDD_ARM, CVDD_HDVICP)

HD-DAC Digital Logic, 1.1V (VDDA_HDDAC_1P1)

-0.3 V to 1.5 V

-0.5 V to 1.5 V

I/O, 1.8 V (DVDD_DDR[0], VDDA_1P8, VDDA_ARMPLL_1P8,

VDDA_VIDPLL_1P8, VDDA_AUDIOPLL_1P8, VDDA_DDRPLL_1P8,

VDDA_L3L4PLL_1P8, VDDA_SATA0_1P8, VDDA_HDMI_1P8,

VDDA_USB0_1P8, VDDA_USB1_1P8, VDDA_VDAC_1P8,

VDDA_CSI2_1P8, VDDA_HDDACREF_1P8, VDDA_HDDAC_1P8,

VDDA_HDVICPPLL_1P8, VDDS_OSC0_1P8, VDDS_OSC1_1P8)

-0.3 V to 2.1 V

Supply voltage ranges (Steady

State):

I/O 3.3 V (DVDD, DVDD_GPMC, DVDD_RGMII, DVDD_SD, DVDD_C)

DDR Reference Voltage (VREFSSTL_DDR[0])

V I/O, 1.35-V pins (Steady State)

-0.3 V to 4.0 V

-0.3 V to 1.1 V

-0.3 V to DVDD_DDR[0] +

0.3 V

V I/O, 1.35-V pins (Transient Overshoot/Undershoot)

30% of DVDD_DDR[0] for

up to 30% of the signal

period

V I/O, 1.5-V pins (Steady State)

-0.3 V to DVDD_DDR[0] +

0.3 V

V I/O, 1.5-V pins (Transient Overshoot/Undershoot)

30% of DVDD_DDR[0] for

up to 30% of the signal

period

Input and Output voltage ranges:

V I/O, 1.8-V pins (Steady State)

-0.3 V to DVDD + 0.3 V

-0.3 V to DVDD_x + 0.3 V

V I/O, 1.8-V pins (Transient Overshoot/Undershoot)

V I/O, 3.3-V pins (Steady State)

25% of DVDDx for up to

30% of the signal period

-0.3 V to DVDD + 0.3 V

-0.3 V to DVDD_x + 0.3 V

V I/O, 3.3-V pins (Transient Overshoot/Undershoot)

Commercial Temperature

25% of DVDDx for up to

30% of the signal period

Operating junction temperature

range, T_J:

0°C to 95°C

Storage temperature range, T_stg

:

-55°C to 150°C

±1000 V

Component-Level

ESD-HBM (Human Body Model)⁽⁴⁾

ESD-CDM (Charged-Device Model)⁽⁵⁾

Electrostatic Discharge (ESD)

±250 V

Stress Voltage⁽³⁾

Latch-up Performance⁽⁶⁾

Class II (105ºC)

50 mA

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to their associated VSS or VSSA_x.

(3) Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by electrostatic discharges into the device.

(4) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe

manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions

are taken. Pins listed as 1000 V may actually have higher performance.

(5) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe

manufacturing with a standard ESD control process, and manufacturing with less than 250 V CDM is possible if necessary precautions

are taken. Pins listed as 250 V may actually have higher performance.

(6) Based on JEDEC JESD78D [IC Latch-Up Test].

Device Operating Conditions

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6.2 Recommended Operating Conditions

PARAMETER

OPP_Nitro

MIN

NOM

MAX UNIT

1.28

1.35

1.42

Supply voltage, Core (Scalable) OPP_Turbo

DVFS only, No AVS

1.28

1.35

1.42

V

CVDD

120% OPP

100% OPP

OPP_Nitro

OPP_Turbo

1.14

1.05

1.28

1.20

1.10

1.35

1.26

1.16

1.42

Supply voltage, Core ARM

(Scalable)

1.28

1.35

1.42

V

CVDD_ARM

120% OPP

100% OPP

OPP_Nitro

1.14

1.05

1.28

1.20

1.10

1.35

1.26

1.16

1.42

Supply voltage, Core, HDVICP2 OPP_Turbo

CVDD_HDVICP (Scalable)

1.28

1.35

1.42

V

120% OPP

100% OPP

3.3 V

1.14

1.05

3.14

1.71

3.14

1.71

3.14

1.71

3.14

1.71

3.14

1.71

1.43

1.28

1.20

1.10

3.3

1.8

3.3

1.8

3.3

1.8

3.3

1.8

3.3

1.8

1.5

1.35

1.26

1.16

Supply voltage, I/O, standard

3.47

V

pins⁽¹⁾

DVDD

1.8 V

1.89

Supply voltage, I/O, GPMC pin

group

3.3 V

3.47

V

DVDD_GPMC

DVDD_RGMII

DVDD_SD

DVDD_C

1.8 V

1.89

Supply voltage, I/O, RGMII pin

group

3.3 V

3.47

V

1.8 V

1.89

Supply voltage, I/O, SD pin

group

3.3 V

3.47

V

1.8 V

1.89

Supply voltage, I/O, C pin group 3.3 V

1.8 V

3.47

V

1.89

Supply voltage, I/O, DDR[0]

DDR2

DDR3

DDR3L

1.89

DVDD_DDR[0]

1.58

1.42

V

VDDA_USB_3P Supply voltage, I/O, Analog, USB 3.3 V

3

3.14

3.3

1.8

1.1

3.47

1.89

Supply Voltage, I/O, Analog, (VDDA_1P8,

VDDA_ARMPLL_1P8, VDDA_VIDPLL_1P8,

VDDA_AUDIOPLL_1P8, VDDA_DDRPLL_1P8,

VDDA_L3L4PLL_1P8, VDDA_SATA0_1P8,

VDDA_HDMI_1P8, VDDA_USB0_1P8, VDDA_USB1_1P8,

VDDA_VDAC_1P8, VDDA_CSI2_1P8,

VDDA_HDDACREF_1P8, VDDA_HDDAC_1P8,

VDDA_HDVICPPLL_1P8, VDDS_OSC0_1P8,

VDDS_OSC1_1P8)

VDDA_1P8

VDDA_x_1P8

VDDS_x_1P8

1.71

V

Note: HDMI, USB0/1, and VDAC relative to their

respective VSSA.

VDDA_HDDAC Supply voltage, I/O, Analog, HD-DAC 1.1 V

_1P1

1.05

1.15

V

Supply Ground (VSS, VSSA_HDMI, VSSA_USB,

VSS

0

VSSA_VDAC, VSSA_DEVOSC⁽²⁾, VSSA_AUXOSC⁽²⁾

)

IO Reference Voltage, (VREFSSTL_DDR[0])

V_{REFSSTL_DDR[0]}

0.49 *

0.50 *

0.51 *

V

DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0]

USBx_VBUSIN USBx VBUS Comparator Input

4.75 5.25

5

(1) LVCMOS pins are all I/O pins powered by DVDD, DVDD_GPMC, DVDD_RGMII, DVDD_SD, DVDD_C supplies except for I2C[0] and

I2C[1] pins.

(2) When using the internal Oscillators, the oscillator grounds (VSSA_DEVOSC, VSSA_AUXOSC) must be kept separate from other

grounds and connected directly to the crystal load capacitor ground.

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Recommended Operating Conditions (continued)

PARAMETER

MIN

NOM

MAX UNIT

High-level input voltage, LVCMOS (JTAG[TCK] pins), 3.3

V⁽¹⁾

2

V

High-level input voltage, JTAG[TCK], 3.3 V

High-level input voltage, JTAG[TCK], 1.8 V

High-level input voltage, I2C (I2C[0] and I2C[1])

2.15

1.45

V

0.7DVDD

0.65DVDDx

High-level input voltage, LVCMOS⁽¹⁾, 1.8 V

V_IH

High-level input voltage, DDR[0] signals in DDR2 mode

High-level input voltage, DDR[0] signals in DDR3 mode

High-level input voltage, DDR[0] signals in DDR3L mode

V_{REFSSTL_DDR[x]}

+ 0.125

V

V_{REFSSTL_DDR[x]}

+ 0.1

V_{REFSSTL_DDR[x]}

+ 0.09

Low-level input voltage, LVCMOS⁽¹⁾, 3.3 V

Low-level input voltage, JTAG[TCK]

0.8

0.45

V

Low-level input voltage, I2C (I2C[0] and I2C[1])

Low-level input voltage, LVCMOS⁽¹⁾, 1.8 V

0.3DVDDx

0.35DVDDx

Low-level input voltage, DDR[0] signals in DDR2 mode

Low-level input voltage, DDR[0] signals in DDR3 mode

Low-level input voltage, DDR[0] signals in DDR3L mode

V_{REFSSTL_DDR[x]}

- 0.125

V_IL

V

V_{REFSSTL_DDR[x]}

- 0.1

V_{REFSSTL_DDR[x]}

- 0.09

High-level output current

Low-level output current

6 mA I/O buffers

-6 mA

-8 mA

I_OH

DDR[0] buffer @ 50-Ω

impedance setting

6 mA I/O buffers

6

8

mA

V

I_OL

V_ID

t_t

DDR[0] buffer @ 50-Ω

impedance setting

Differential input voltage (SERDES_CLKN/P), [AC coupled]

0.250

2.0

Transition time, 10% - 90%, All inputs (unless otherwise

specified in the Electrical Data/Timing sections of each

peripheral)

0.25P or 10⁽³⁾

95

ns

°C

Operating junction temperature

range⁽⁴⁾

Commercial

Temperature (default)

T_J

0

(3) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve

noise immunity on input signals.

(4) For more detailed information on estimating junction temps within systems, see the IC Package Thermal Metrics Application Report

(Literature Number: SPRA953).

Device Operating Conditions

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6.3 Reliability Data⁽¹⁾

The information in this table is provided solely for convenience and does not extend or modify the warranty provided under

TI's standard terms and conditions for TI semiconductor products.

Operating Condition

CVDD⁽²⁾

CVDD_ARM⁽²⁾

CVDD_HDVICP⁽²⁾

Commercial

Junction Temp.

(T_J)

Lifetime (POH)⁽³⁾

Nitro

1.35 V ± 5%

1.20 V ± 5%

1.10 V ± 5%

1.35 V ± 5%

1.20 V ± 5%

1.10 V ± 5%

1.35 V ± 5%

1.20 V ± 5%

1.10 V ± 5%

95ºC

55K

59K

Turbo

OPP120

OPP100

100K

(1) Logic functions and parameter values are not ensured out of the range specified in the recommended operating conditions. The above

notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and conditions for TI

semiconductor products.

(2) Voltage specification at the device package pin.

(3) Power-on-hours (POH) represent device operation under the specified nominal conditions continuously for the duration of the calculated

lifetime. If actual application results in a system that operates at conditions less than the limits, the resulting POH may increase.

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6.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Temperature (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX UNIT

Low/Full speed: USBx_DM

and USBx_DP

2.8

VDDA_USB_3P

V

mV

V

3

High speed: USBx_DM and

USBx_DP

360

2.4

440

High-level output voltage,

LVCMOS⁽²⁾(3.3-V I/O)

3.3 V, DVDDx = MIN,

I_OH= MAX

High-level output voltage,

LVCMOS⁽²⁾(1.8-V I/O)

1.8 V, DVDDx = MIN,

I_OH= MAX

1.26

V

V_OH

High-level output voltage,

DDR[0] signals in DDR2

mode

1.8 V, I_OL= 6mA, 50

ohm load

DVDD_DDR[0] -

0.4

V

HIgh-level output voltage,

DDR[0] signals in DDR3

mode

1.5 V, I_OL= 6mA, 50

ohm load

DVDD_DDR[0] -

0.4

V

HIgh-level output voltage,

DDR[0] signals in DDR3L

mode

1.35 V, I_OL= 6mA, 50

ohm load

DVDD_DDR[0] -

0.4

Low/Full speed: USBx_DM

and USBx_DP

0.0

-10

0.3

10

V

mV

V

High speed: USBx_DM and

USBx_DP

Low-level output voltage,

LVCMOS⁽²⁾(3.3-V I/O)

3.3 V, DVDDx = MAX,

I_OL= MAX

0.4

Low-level output voltage,

LVCMOS⁽²⁾(1.8-V I/O)

1.8 V, DVDDx = MAX,

I_OL= MAX

V

Low-level output voltage, I2C 1.8/3.3 V, I_OL= 4mA

(I2C[0], I2C[1])

0.4

V

V_OL

Low-level output voltage,

DDR[0] signals in DDR2

mode

1.8 V, I_OL= 6mA, 50

ohm load

Low-level output voltage,

DDR[0] signals in DDR3

mode

1.5 V, I_OL= 6mA, 50

ohm load

0.4

V

Low-level output voltage,

DDR[0] signals in DDR3L

mode

1.35 V, I_OL= 6mA, 50

ohm load

0.4

1.5

V

LDOs (applies to all

LDOCAP_x pins)

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

(2) LVCMOS pins are all I/O pins powered by DVDD, DVDD_GPMC, DVDD_RGMII, DVDD_SD, DVDD_C supplies except for I2C[0] and

I2C[1] pins.

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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature

(Unless Otherwise Noted) (continued)

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX UNIT

Input current, LVCMOS⁽²⁾

3.3 V mode

,

0 < V_I< DVDDx, 3.3 V

pull disabled

-20

20

300

-300

5

µA

0 < V_I< DVDDx, 3.3 V

pulldown enabled⁽⁴⁾

20

-20

-5

100

0 < V_I< DVDDx, 3.3 V

pullup enabled⁽⁴⁾

-100

Input current, LVCMOS⁽²⁾

1.8 V mode

,

0 < V_I< DVDDx, 1.8 V

pull disabled

I_I⁽³⁾

0 < V_I< DVDDx, 1.8 V

pulldown enabled⁽⁴⁾

50

100

200

-200

0 < V_I< DVDDx, 1.8 V

pullup enabled⁽⁴⁾

-50

-100

Input current, I2C (I2C[0],

I2C[1])

3.3 V mode

1.8 V mode

-20

-5

20

5

µA

3.3 V mode, pull

enabled

-300

-20

-200

-5

300

20

µA

3.3 V mode, pull

disabled

(5)

I_OZ

I/O Off-state output current

1.8 V mode, pull

enabled

200

1.8 V mode, pull

disabled

5

µA

pF

Input capacitance

LVCMOS⁽²⁾

12

C_I

Output capacitance

LVCMOS⁽²⁾

12

pF

C_o

(3) I_Iapplies to input-only pins and bi-directional pins. For input-only pins, I_Iindicates the input leakage current. For bi-directional pins, I_I

indicates the input leakage current and off-state (Hi-Z) output leakage current.

(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(5) I_OZapplies to output-only pins, indicating off-state (Hi-Z) output leakage current.

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7 Power, Reset, Clocking, and Interrupts

7.1 Power, Reset and Clock Management (PRCM) Module

The PRCM module is the centralized management module for the power, reset, and clock control signals

of the device. It interfaces with all the components on the device for power, clock, and reset management

through power-control signals. It integrates enhanced features to allow the device to adapt energy

consumption dynamically, according to changing application and performance requirements. The

innovative hardware architecture allows a substantial reduction in leakage current.

The PRCM module is composed of two main entities:

•

Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock

source control (oscillator)

•

Clock manager (CM): Handles the clock generation, distribution, and management.

For more details on the PRCM, see the Power, Reset, and Clock Management (PRCM) Module chapter in

the device-specific Technical Reference Manual.

7.2 Power

7.2.1 Voltage and Power Domains

Every Module within the device belongs to a Core Logic Voltage Domain, Memory Voltage Domain, and a

Power Domain (see Table 7-1).

Table 7-1. Voltage and Power Domains

CORE LOGIC

VOLTAGE DOMAIN

MEMORY VOLTAGE

DOMAIN

POWER

DOMAIN

MODULE(S)

ARM_L

ARM_M

ARM Cortex-A8 Subsystem, SmartReflex Sensor 0

HDMI, DCAN0/1, DMM, EDMA, ELM, DDR, GPIO

Banks 0/1/2/3, GPMC, I2C0/1/2/3, IPC, MCASP0/1,

OCMC SRAM, PRCM, RTC, SATA0, SD/MMC0/1/2,

SPI01/2/3, Timer1/2/3/4/5/6/7/8, UART0/1/2, USB0/1,

WDT0, System Interconnect, JTAG, Media Controller,

ISS, SmartReflex Control Module 0/1, SmartReflex

Sensor 1

ALWAYS ON

CORE_L

CORE_M

HDVPSS

HDVICP

HDVPSS, SD-DAC, HD-DAC

HDVICP_L

HDVICP_M

HDVICP2, SmartReflex Sensor 2

7.2.1.1 Core Logic Voltage Domains

The device contains three Core Logic Voltage Domains. These domains define groups of Modules that

share the same supply voltage for their core logic. Each Core Logic Voltage Domain is powered by a

dedicated supply voltage rail that can be independently scaled using SmartReflex technology to trade off

power versus performance. Table 7-2 shows the mapping between the Core Logic Voltage Domains and

their associated supply pins.

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Table 7-2. Core Logic Voltage Domains and Supply Pin Associations

CORE LOGIC

SUPPLY PIN NAME

VOLTAGE DOMAIN

ARM_L

CORE_L

HDVICP_L

CVDD_ARM

CVDD

CVDD_HDVICP

Note: A regulated supply voltage must be supplied to each Core Logic Voltage Domain at all times,

regardless of the Core Logic Power Domain states.

7.2.1.2 Power Domains

The device contains four Power Domains which supply power to both the Core Logic and SRAM within

their associated modules. Each Power Domain, except for the ALWAYS ON domain, has an internal

power switch that can completely remove power from that domain. All power switches are turned "OFF" by

default after reset, and software can individually turn them "ON/OFF" via Control Module registers.

Note: All Modules within a Power Domain are unavailable when the domain is powered "OFF". For

instructions on powering "ON/OFF" the Power domains, see the Power, Reset, and Clock Management

(PRCM) Module chapter of the device-specific Technical Reference Manual.

7.2.2 SmartReflex™ [Currently Not Supported]

The device contains SmartReflex modules that help to minimize power consumption on the Core Logic

Voltage Domains by using external variable-voltage power supplies. Based on the device process,

temperature, and desired performance, the SmartReflex modules advise the host processor to raise or

lower the supply voltage to each domain for minimal power consumption.

The communication link between the host processor and the external regulators is a system-level decision

and can be accomplished using GPIOs, I2C, SPI, or other methods. The following sections briefly

describe the two major techniques employed by SmartReflex: Dynamic Voltage Frequency Scaling

(DVFS) and Adaptive Voltage Scaling (AVS).

7.2.2.1 Dynamic Voltage Frequency Scaling (DVFS) [Currently Supports Only Discrete OPPs]

Each device Core Logic Voltage Domain can be run independently at one of several Operating

Performance Points (OPPs). An OPP for a specific Core Logic Voltage Domain is defined by: (1)

maximum frequencies of operation for Modules within the Domain and (2) an associated supply voltage

range. Trading off power versus performance, OPPs with lower maximum frequencies also have lower

voltage ranges for power savings.

The OPP for a domain can be changed in real-time without requiring a reset. This feature is called

Dynamic Voltage Frequency Scaling (DVFS) Table 7-3 contains a list of voltage ranges and maximum

module frequencies for the OPPs of each Core Logic Voltage Domain.

NOTE

Not all devices support all OPP frequencies.

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Table 7-3. Device Operating Points (OPPs)

CORE LOGIC VOLTAGE DOMAINS

CORE

ARM

HDVICP2

L3/L4,

Core

(MHz)

Cortex A8

(MHz)

HDVPSS

(MHz)

ISS

(MHz)

Media Ctlr.

(MHz)

DDR

OPP

HDVICP2

(MHz)⁽¹⁾

100%(1.1 V) (AAR0x)

600

720

220

290

200

400

200

400

120% (1.2 V)

(AAR0x)

Turbo (1.35 V)

(AAR1x)

970

410

450

240

260

480

560

240

280

240

533

Nitro (1.35 V)

(AAR2x)

1000

(1) All DDR access must be suspended prior to changing the DDR frequency of operation.

Although the OPP for each Core Logic Voltage Domain is independently selectable, not all combinations

of OPPs are supported. Table 7-4 marks the supported ARM OPPs for a given CORE OPP.

Table 7-4. Supported OPP Combinations⁽¹⁾

ARM

OPP120

HDVICP2

CORE

Nitro

X

Turbo

X

OPP100

Nitro

X

Turbo

OPP120

OPP100

Turbo

X

OPP120

OPP100

X

(1) "X" denotes supported combinations.

7.2.2.2 Adaptive Voltage Scaling [Currently Not Supported]

As mentioned in Section 7.2.2.1, Dynamic Voltage Frequency Scaling (DVFS) above, every OPP has an

associated voltage range. Based on the silicon process, temperature, and chosen OPP, the SmartReflex

modules guide software in adjusting the Core Logic Voltage Domain supply voltage (CVDD) within these

ranges. This technique is called Adaptive Voltage Scaling (AVS). AVS occurs continuously and in real-

time, helping to minimize power consumption in response to changing operating conditions.

7.2.3 Memory Power Management

In order to reduce SRAM leakage, many SRAM blocks can be switched from ACTIVE mode to

SHUTDOWN mode. When SRAM is put in SHUTDOWN mode, the voltage supplied to it is automatically

removed and all data in that SRAM is lost.

All SRAM located in a switchable power domain (all domains except ALWAYS_ON) automatically enters

SHUTDOWN mode whenever its associated power domain goes into the "OFF" state. The SRAM returns

to the ACTIVE state when the corresponding Power Domain returns to the "ON" state.

In addition, the following SRAM within the ALWAYS_ON Power Domain can also be independently put

into SHUTDOWN by programming the x_MEM_PWRDN registers in the Control Module:

•

Media Controller SRAM

OCMC SRAM

7.2.4 SERDES_CLKP/N LDO

The SERDES_CLKP/N input buffers are powered by an internal LDO which is programmed through the

REFCLK_LJCBLDO_CTRL register in the Control Module.

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7.2.5 Dual Voltage I/Os

The device supports dual voltages on some of its I/Os. These I/Os are partitioned into the following

groups, and each group has its own dedicated supply pins: DVDD, DVDD_GPMC, DVDD_C, and

DVDD_SD. The supply voltage for each group can be independently powered with either 1.8 V or 3.3 V.

For the mapping between pins and power groups, see Section 3.3, Terminal Functions of the datasheet.

In addition, the I/O voltage on the DDR interface is independently selectable between 1.35 V, 1.5 V or

1.8 V to support various DDR device types.

7.2.6 I/O Power-Down Modes

On the device, there are power-down modes available for the following PHYs:

•

Video DACs

DDR

USB

HDMI

CSI2

SATA

When a PHY controller is in a power domain that is to be turned "OFF", software must configure the

corresponding PHY into power-down mode, prior to putting the power domain in the "OFF" state.

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7.2.7 Standby and Deep Sleep Modes

The device supports Low-Power Standby and Deep-Sleep Modes as described below.

Standby Mode is defined as a state in which:

•

All switchable power domains are in "OFF" state

The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation

All functional blocks not needed for a given application are clock gated

Deep Sleep Mode is defined to be the same as Standby Mode, with the addition of gating the crystal

oscillator to further eliminate all active power. The device core voltages can be reduced for optimal power

savings.

For detailed instructions on entering and exiting from Standby and Deep Sleep Modes, see the Power,

Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical Reference

Manual.

7.2.8 Supply Sequencing

The device power supplies are organized into five Supply Sequencing Groups:

1. CVDD Core Logic supply (CVDD)

2. All CVDD_x supplies (CVDD_ARM and CVDD_HDVICP)

3. All 1.35-/1.5-/1.8-V DVDD_DDR[0] Supplies (1.35 V for DDR3L, 1.5 V for DDR3, 1.8 V for DDR2)

4. All 1.8-V Supplies (DVDD_x, VDDA_x_1P8, VDDA_1P8)

5. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

To ensure proper device operation, a specific power-up and power-down sequence must be followed.

Some TI power-supply devices include features that facilitate these power sequencing requirements — for

example, TI’s TPS659113 integrated PMIC. For more information on TI power supplies and their features,

visit www.ti.com/processorpower.

7.2.8.1 Power-Up Sequence

For proper device operation, the following power-up sequence in Table 7-5 and Figure 7-1 must be

followed.

Table 7-5. Power-Up Sequence Ramping Values

NO.

1

DESCRIPTION

MIN

0⁽¹⁾

0⁽²⁾

MAX

UNIT

ms

1.8 V supplies to 1.35-/1.5-/1.8-V DVDD_DDR[x] supplies

DVDD_DDR supplies stable to 3.3 V supplies ramp start

2

ms

1.8 V supplies stable to CVDD, CVDD_x variable supplies

ramp start

3

4

0⁽¹⁾

ms

Master

Clocks

All supplies valid to power-on-reset (POR high)

4 096

(1) The 1.8 V supplies must be ≥ 1.35-/1.5-/1.8-V DVDD_DDR[x] and CVDD, CVDD_x variable supplies.

(2) Both 1.8 V and DVDD_DDR[x] supplies must be powered up and stable prior to starting the ramp of the 3.3 V supplies.

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POR

1.8 V Supplies

(DVDD, DVDD_x, VDDA_x_1P8,

VDDA_1P8)

1.35 V/1.5 V/1.8 V DVDD_DDR[0]

3.3 V Supplies

(DVDD, DVDD_x, VDDA_x_3P3)

CVDD

CVDD_x

2

1

3

4

Both 1.8 V and DVDD_DDR[x] supplies must be powered up and stable prior to starting the ramp of the 3.3 V

supplies.

CVDD powered-up coincidently or prior to CVDD_ARM and CVDD_HDVICP supplies.

Figure 7-1. Power-Up Sequence

7.2.8.2 Power-Down Sequence

For proper device operation, the following power-down sequence in Table 7-6, Figure 7-2, Figure 7-3, and

Figure 7-4 must be followed.

Table 7-6. Power-Down Sequence Ramping Values

NO.

5

DESCRIPTION

MIN

MAX

UNIT

ms

CVDD, CVDD_x variable supplies to 1.8 V supplies

1.35-/1.5-/1.8-V DVDD_DDR[x] supplies to 1.8 V supplies

3.3 V supplies to 1.8 V supplies

0

6

0

(1)

ms

(1)

(2)

7

ms

(2)

8

CVDD_x supplies to CVDD supply

ms

(1) The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 7-3).

(2) The CVDD supply must be powered down coincidentally or after CVDD_ARM and CVDD_HDVICP supplies (see Figure 7-4).

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1.8 V Supplies

(DVDD, DVDD_x, VDDA_x_1P8,

VDDA_1P8)

3.3 V Supplies

(DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

1.35 V/1.5 V/1.8 V DVDD_DDR[0]

CVDD, CVDD_x

7

6

5

Figure 7-2. Power-Down Sequence

3.3 V Supplies

V Delta^(A)

1.8 V Supplies

(Excluding DVDD_DDR[x])

A. V Delta Max = 2 V.

Figure 7-3. 3.3 V Supplies Falling After 1.8 V Supplies Delta

CVDD_x

CVDD

8

Figure 7-4. CVDD and CVDD_x Power-Down Sequence

7.2.9 Power-Supply Decoupling

7.2.9.1 Analog and PLL

PLL and Analog supplies benefit from filters or ferrite beads to keep the noise from causing problems. The

minimum recommendation is a ferrite bead along with at least one capacitor on the device side of the

bead. An additional recommendation is to add one capacitor just before the bead to form a Pi filter. The

filter needs to be as close as possible to the device pin, with the device side capacitor being the most

important component to be close to the device pin. PLL pins close together can be combined on the same

supply, but analog pins should all have their own filters. PLL pins farther away from each other may need

their own filtered supply.

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7.2.9.2 Digital

Recommended capacitors for power supply decoupling are all 0.1uF in the smallest body size that can be

used. Capacitors are more effective in the smallest physical size to limit lead inductance. For example,

0201 sized capacitors are better than 0402 sized capacitors, and so on. TI recommends using capacitors

no larger than 0402. Place at least one capacitor for every two power pins. For those power pins that have

only one pin, a capacitor is still required. Place one bulk (10 uF or larger) capacitor for every 10 or so

power pins as closely as possible to the chip. These larger caps do not need to be under the chip

footprint.

Pay special attention not to put so much capacitance on the supply that it slows the start-up voltage ramp

enough to change the power sequencing order. Also be sure to verify that the main chip reset is low until

after all supplies are at their correct voltage and stable.

DDR peripheral related supply capacitor numbers are provided in Section 8.12, DDR2/DDR3/DDR3L

Memory Controller.

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7.3 Reset

7.3.1 System-Level Reset Sources

The device has several types of system-level resets. Table 7-7 lists these reset types, along with the reset

initiator, and the effects of each reset on the device.

Table 7-7. System-Level Reset Types

RESETS ALL

MODULES,

ASSERTS

RSTOUT_WD_OUT

EXCLUDING

EMULATION, PLL

AND CLOCK

CONFIG

RESETS

EMULATION

PLL AND CLOCK

CONFIG

LATCHES

BOOT PINS

TYPE

INITIATOR

Power-on Reset (POR)

External Warm Reset

Emulation Warm Reset

Watchdog Reset

POR pin

RESET pin

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Optional⁽¹⁾⁽²⁾

Optional⁽¹⁾

Yes

On-Chip Emulation Logic

Watchdog Timer

Software

No

Software Global Cold Reset

Software Global Warm Reset

Test Reset

Yes

No

Optional⁽¹⁾

No

Software

TRST pin

Yes

(1) RSTOUT_WD_OUT pin asserted only if BTMODE[11] was latched as "0" when coming out of reset.

(2) While POR and/or RESET is asserted, the RSTOUT_WD_OUT pin is 3-stated and the internal pull resistor is disabled; therefore, an

external pullup/pulldown can be used to set the state of this pin (high/low) while POR and/or RESET is asserted. For more detailed

information on external PUs/PDs, see Section 4.5.1, Pullup/Pulldown Resistors.

7.3.2 Power-on Reset (POR pin)

Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the Test

and Emulation logic. POR is also referred to as a cold reset since it is required to be asserted when the

device goes through a power-up cycle. However, a device power-up cycle is not required to initiate a

Power-on Reset.

The following sequence must be followed during a Power-on Reset:

1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.

2. Wait for the input clock sources DEV_CLKIN, AUX_CLKIN, and SERDES_CLKN/P to be stable (if

used by the system) while keeping the POR pin asserted (low).

3. Once the power supplies and the input clock sources are stable, the POR pin must remain asserted

(low) [see Section 7.3.16, Reset Electrical Data/Timing]. Within the low period of the POR pin, the

following happens:

(a) All pins except Emulation pins enter a Hi-Z mode and the associated pulls, if applicable, will be

enabled.

(b) The PRCM asserts reset to all modules within the device.

(c) The PRCM begins propagating these clocks to the chip with the PLLs in BYPASS mode.

4. The POR pin may now be de-asserted (driven high). When the POR pin is de-asserted (high):

(a) The BTMODE[15:0] pins are latched.

(b) Reset to the ARM Cortex-A8 and Modules without a local processor is de-asserted.

(c) RSTOUT_WD_OUT is briefly asserted if BTMODE[11] was latched as "0".

(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of

the PRCM.

(e) The ARM Cortex-A8 begins executing from the Boot ROM.

7.3.3 External Warm Reset (RESET pin)

An external warm reset is activated by driving the RESET pin active-low. This resets everything in the

device, except for the Test and Emulation logic. An emulator session stays alive during warm reset.

The following sequence must be followed during a warm reset:

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1. Power supplies and input clock sources should already be stable.

2. The RESET pin must be asserted (low)[see Section 7.3.16, Reset Electrical Data/Timing]. Within the

low period of the RESET pin, the following happens:

(a) All pins, except Test and Emulation pins, enter a Hi-Z mode and the associated pulls, if applicable,

will be enabled.

(b) The PRCM asserts reset to all modules within the device, except for the Test and Emulation logic,

PLL, and Clock configuration.

3. The RESET pin may now be de-asserted (driven high). When the RESET pin is de-asserted (high):

(a) The BTMODE[15:0] pins are latched.

(b) Reset to the ARM Cortex-A8 and modules without a local processor is de-asserted, with the

exception of Test and Emulation logic, PLL, and Clock configuration.

(c) RSTOUT_WD_OUT is asserted [see Section 7.3.16, Reset Electrical Data/Timing], if BTMODE[11]

was latched as "0".

(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of

the PRCM.

(e) The ARM Cortex-A8 begins executing from the Boot ROM.

7.3.4 Emulation Warm Reset

An Emulation Warm Reset is activated by the on-chip Emulation Module. It has the same effect and

requirements as an External Warm Reset (RESET), with the following exceptions:

•

BTMODE[15:0] pins are not re-latched

RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the

BTMODE[11] pin.

The emulator initiates an Emulation Warm Reset via the ICEPICK module. To invoke the Emulation Warm

Reset via the ICEPICK module, the user can perform the following from the Code Composer Studio™ IDE

menu: Target -> Reset -> System Reset.

7.3.5 Watchdog Reset

A Watchdog Reset is initiated when the Watchdog Timer counter reaches zero. It has the same effect and

requirements as an External Warm Reset (RESET pin), with the following exceptions:

•

BTMODE[15:0] pins are not re-latched

RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the

BTMODE[11] pin.

In addition, a Watchdog Reset always results in RSTOUT_WD_OUT being asserted, regardless of

whether the BTMODE[11] pin was latched as "0" or "1".

7.3.6 Software Global Cold Reset

A Software Global Cold Reset is initiated under software control. It has the same effect and requirements

as a POR Reset, with the following exceptions:

•

BTMODE[15:0] pins are not re-latched

RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the

BTMODE[11] pin.

Software initiates a Software Global Cold Reset by writing a "1" to the RST_GLOBAL_COLD_SW bit in

the PRM_RSTCTRL register in the PRCM.

For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the

Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical

Reference Manual.

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7.3.7 Software Global Warm Reset

A Software Global Warm Reset is initiated under software control. It has the same effect and requirements

as a External Warm Reset (RESET pin), with the following exceptions:

•

BTMODE[15:0] pins are not re-latched

RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the

BTMODE[11] pin.

Software initiates a Software Global Warm Reset by writing a "1" to the RST_GLOBAL_WARM_SW bit in

the PRM_RSTCTRL register in the PRCM.

For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the

Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical

Reference Manual.

7.3.8 Test Reset (TRST pin)

A Test Reset is activated by the emulator asserting the TRST pin. The only effect a Test Reset has is to

reset the Test and Emulation Logic.

7.3.9 Local Reset

The Local Reset for various Modules within the device is controlled by programming the PRCM and/or the

Peripheral Module’s internal registers. Only the associated Module is reset when a Local Reset is

asserted, leaving the rest of the device unaffected.

For more details on Peripheral Local Resets, see the Reset Management section of the Power, Reset,

and Clock Management (PRCM) Module chapter in the device-specific Technical Reference Manual.

7.3.10 Reset Priority

If any of the above reset sources occur simultaneously, the device only processes the highest-priority

reset request. The reset request priorities, from high-to-low, are as follows:

1. Power-on Reset (POR)

2. Test Reset (TRST)

3. External Warm Reset (RESET pin)

4. Emulation Warm Resets

5. Watchdog Reset

6. Software Global Cold/Warm Resets

7.3.11 Reset Status Register

The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the

system. For more information on this register, see the Power, Reset, and Clock Management (PRCM)

Module chapter in the device-specific Technical Reference Manual.

7.3.12 RSTOUT_WD_OUT Pin

The RSTOUT_WD_OUT pin reflects device reset status and is de-asserted (high) when the device is out

reset. This output will always be asserted when a Watchdog Timer reset (Watchdog Reset) occurs. In

addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR

and/or RESET is asserted; therefore, an external pullup/pulldown can be used to set the state of this pin

(high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see

Section 4.5.1, Pullup/Pulldown Resistors.

If the BTMODE[11] pin is latched as a "0" at the rising edge of POR or RESET, then RSTOUT_WD_OUT

is also asserted when any of the below resets occur:

•

Power-On Reset (asserted after the BTMODE[11] pin is latched)

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•

External Warm Reset (asserted after the BTMODE[11] pin is latched)

Emulation Warm Reset

Software Global Cold/Warm Reset

The RSTOUT_WD_OUT pin remains asserted until the PRCM releases the host ARM Cortex-A8

processor for reset.

7.3.13 Effect of Reset on Emulation & Trace

The device Emulation & Trace Logic will only be reset by the following sources:

•

Power-On Reset

Software Global Cold Reset

Test Reset

Other than these three reset types, none of the other resets will affect the Emulation and Trace Logic.

However, the multiplexing of the EMU[4:2] pins is reset by all system reset types except Test Reset.

7.3.14 Reset During Power Domain Switching

Each Power Domain has a dedicated Warm Reset and Cold Reset. Warm Reset for a Power Domain is

asserted under either of the following two conditions:

1. An External Warm Reset, Emulation Warm Reset, or Software Global Warm Reset occurs

2. When that Power Domain switches from the "ON" state to the "OFF" state

Cold Reset for a Power Domain is asserted under either of the following two conditions:

1. Power-On Reset or Software Global Cold Reset occurs

2. When that Power Domain switches from the "OFF" state to the "ON" state

7.3.15 Pin Behaviors at Reset

When any reset, other than Test Reset, (all described in Section 7.3.1, System-Level Reset Sources) is

asserted, all device I/O pins are reset into a Hi-Z state except for:

•

Emulation Pins. These pins are only put into a Hi-Z state when Test Reset (TRST) is asserted.

RSTOUT_WD_OUT Pin during any reset types except for POR and RESET. For more detailed

information on RSTOUT_WD_OUT pin behavior, see Section 7.3.12, RSTOUT_WD_OUT Pin.

•

DDR[0] Address/Control Pins (CLK, CLK, CKE, WE, CS[0], RAS, CAS, ODT[0], RST, BA[2:0], A[15:0]).

These pins are 3-stated during reset. However, these pins are then driven to the same value as their

internal pull resistor reset value when reset is released.

In addition, the PINCNTL registers, which control pin multiplexing, enabling the IPUs/IPDs, and enabling

the receiver, are reset to their default state.

Internal pull-up/down (IPU/IPD) resistors are enabled during and immediately after reset as described in

Section 3.3, Terminal Functions of this document.

NOTE

The reset pin state is after all the power supplies are ramped up and stable. The state is not

not ensured during power-up sequencing.

Upon coming out of reset, the ARM Cortex-A8 starts executing code from the internal Boot

ROM. The Boot ROM code modifies the PINCNTLx registers to configure the associated

pins for the chosen primary and backup Bootmodes.

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7.3.16 Reset Electrical Data/Timing

NOTE

For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).

Table 7-8. Timing Requirements for Reset (see Figure 7-5 and Figure 7-6)

OPP100

NO.

1

UNIT

MIN

12P⁽¹⁾

2P⁽²⁾

0

MAX

t_w(RESET)

t_su(BOOT)

t_h(BOOT)

Pulse duration, POR low or RESET low

ns

POR

Setup time, BTMODE[15:0] pins valid before POR high or

RESET high

2

RESET

3

Hold time, BTMODE[15:0] pins valid after POR high or RESET high

(1) The device clock source must be stable and at a valid frequency prior to meeting the t_w(RESET)requirement.

(2) P = 1/(DEV Clock) frequency in ns.

Table 7-9. Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 7-6)

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

t_d(RSTL-

IORST)

4

5

Delay time, RESET low or POR low to all I/Os entering their reset state

Delay time, RESET high or POR high to all I/Os exiting their reset state

14 ns

2P ns

t_d(RSTH-

IOFUNC)

RESET assertion t_w(RESET)

0

≥ 30P

t_d(RSTH-

RSTOUTH)

6

Delay time, RESET high to RSTOUT_WD_OUT high⁽¹⁾⁽²⁾

RESET assertion t_w(RESET)

< 30P

32P -

t_w(RESET)

ns

t_d(PORH-

RSTOUTH)

t_d(RSTL-

RSTOUTZ)

t_d(PORH-

RSTOUTL)

t_d(RSTH-

RSTOUTD)

7

8

Delay time, POR high to RSTOUT_WD_OUT high⁽¹⁾⁽²⁾

Delay time, RESET low to RSTOUT_WD_OUT Hi-Z⁽¹⁾⁽²⁾

12500P ns

2P ns

Delay time, POR high to RSTOUT_WD_OUT driven based on latched BTMODE[11]

value⁽¹⁾⁽²⁾

9

2P ns

Delay time, RESET high to RSTOUT_WD_OUT driven based on latched BTMODE[11]

value⁽¹⁾⁽²⁾

10

2P ns

(1) For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 7.3.12, RSTOUT_WD_OUT Pin.

(2) P = 1/(DEV Clock) frequency in ns.

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Figure 7-5 shows the Power-Up Timing. Figure 7-6 shows the Warm Reset (RESET) Timing. Max Reset

Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not re-latched.

Power

Supplies

Ramping

Power Supplies Stable

Clock Source Stable

DEV_CLKIN/

AUX_CLKIN^(A)

1

POR

RESET

7

9

Hi-Z

BTMODE[11]^(B)

RSTOUT_WD_OUT

5

2

3

BTMODE[15:0]

Other I/O Pins^(C)

Config

5

RESET STATE

A. Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of t_w(RESET)

.

B. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.

C. For more detailed information on the RESET STATE of each pin, see Section 7.3.15, Pin Behaviors at Reset. Also

see , Terminal Functions for the IPU/IPD settings during reset.

Figure 7-5. Power-Up Timing

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Power Supplies Stable

DEV_CLKIN/

AUX_CLKIN

POR

1

RESET

8

4

6

10

BTMODE[11]^(A)

Hi-Z

RSTOUT_WD_OUT

5

2

3

BTMODE[15:0]

Other I/O Pins^(B)

Config

5

RESET STATE

A. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.

B. For more detailed information on the RESET STATE of each pin, see Section 7.3.15, Pin Behaviors at Reset. Also

see , Terminal Functions for the IPU/IPD settings during reset.

Figure 7-6. Warm Reset (RESET) Timing

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7.4 Clocking

The device clocks are generated from several reference clocks that are fed to on-chip PLLs and dividers

(both inside and outside of the PRCM Module). Figure 7-7 shows a high-level overview of the device

system clocking structure (Note: to reduce complexity, not all clocking connections are shown). For

detailed information on the device clocks, see the Clock Generation and Management section of the

Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical

Reference Manual.

NOTE

For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).

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PLL_HDVPSS

HDVPSS

PLL_MEDIACTL

ISS, Media Controller

SYSCLK4

SYSCLK6

L3 Fast/Medium, L4 Fast,

EDMA, OCMC

PLL_L3L4

PRCM

L3/L4 Slow, GPMC,

ELM, McASP,

Mailbox, Spinlock

USB0/1

CLKDCO

PLL_USB

SYSCLK10

SYSCLK8

SPI0/1/2/3, I2C0/1/2/3,

UART0/1/2, HDMI CEC

DEVOSC/

DEV_CLKIN

M

U

X

CLKOUT

PRCM

MMC0/1/2

AUXOSC/

AUX_CLKIN

(Note: Separate MUX

exists for each PLL)

PLL_DDR

DDR

/2

DMM

HDVPSS SD VENC

PLL_VIDEO0

PLL_VIDEO2

HDMI

HDVPSS VOUT1

M

U

X

M

U

X

HDMI PHY

PLL_VIDEO1

PLL_AUDIO

HDVPSS HD VENC

HDVPSS VOUT0

M

U

X

SYSCLK20

SYSCLK21

PRCM

M

U

X

MCASP0/1 AUX_CLK

HDMI I2S

From PLL_VIDEO0/1/2

M

U

X

From AUX Clock, AUD_CLK0/1/2

PLL_ARM

(Embedded PLL)

M

U

X

Cortex-A8

RTCDIVIDER

SYSCLK18

RTC, GPIO, SyncTimer,

Cortex-A8 (Optional)

PRCM

From CLKIN32 Pin

M

U

X

TIMER1/2/3/4/5/6/7/8

From DEV/AUX Clock, AUD_CLK0/1/2, TCLKIN

WDT0 (Optional)

DCAN0/1, SmartReflex

M

U

X

SATA0 SERDES

(Embedded PLL)

SERDES_CLK

RCOSC32K

WDT0 (Optional)

Figure 7-7. System Clocking Overview

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7.4.1 Device (DEV) and Auxiliary (AUX) Clock Inputs

The device provides two clock inputs, Device (DEVOSC_MXI/DEV_CLKIN) and Auxiliary

(AUXOSC_MXI/AUX_CLKIN). The Device (DEV) clock is used to generate the majority of the internal

reference clocks, while the Auxiliary (AUX) clock can optionally be used as a source for the Audio and/or

Video PLLs.

The DEV and AUX clocks can be sourced in two ways:

1. Using an external crystal in conjunction with the internal oscillator or

2. Using an external 1.8-V LVCMOS-compatible clock input

Note: The external crystals used with the internal oscillators must operate in fundamental parallel

resonant mode only. There is no overtone support.

The DEV Clock should in most cases be 20 MHz. However, it can optionally range anywhere from 20 - 30

MHz if the following are true:

•

The DEV Clock is not used to source the SATA reference clock

A precise 32768-Hz clock is not needed for Real-Time Clock functionality

If the boot mode is FAST XIP

The AUX Clock is optional and can range from 20-30 MHz. It can be used to source the Audio and/or

Video PLLs when a very precise audio or video frequency is required.

7.4.1.1 Using the Internal Oscillators

When the internal oscillators are used to generate the DEV and AUX clocks, external crystals are required

to be connected across the DEVOSC or AUXOSC oscillator MXI and MXO pins, along with two load

capacitors (see Figure 7-8 and Figure 7-9). The external crystal load capacitors should also be connected

to the associated oscillator ground pin (VSSA_DEVOSC or VSSA_AUXOSC). The capacitors should not

be connected to board ground (VSS).

Figure 7-8. Device Oscillator

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AUXOSC_MXI/

AUX_CLKIN

AUXOSC_MXO

Rd

VSSA_AUXOSC

Crystal

(Optional)

C1

C2

Figure 7-9. Auxiliary Oscillator

The load capacitors, C1 and C2 in the above pictures, should be chosen such that the below equation is

satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components

used to implement the oscillator circuit should be placed as close as possible to the associated oscillator

MXI, MXO, and VSS pins.

C C

1

2

C

=

+ Cshunt

L

C

+ C

2

(

)

1

Table 7-10. Input Requirements for Crystal Circuit on the Device Oscillator (DEVOSC)

PARAMETER

MIN

TYP

MAX

4

UNIT

ms

Start-up time (from power up until oscillating at stable frequency)

Crystal Oscillation frequency⁽¹⁾

Parallel Load Capacitance (C1 and C2)

Crystal ESR

20

12

20

30

24

50

MHz

pF

Ω

Crystal Shunt Capacitance (Cshunt)

Crystal Oscillation Mode

5

pF

Fundamental Only

n/a

ppm

Crystal Frequency stability

±50

(1) 20-MHz DEV clock is required for all bootmodes other than Fast XIP. For more detailed information on boot modes, see the ROM Code

Memory and Peripheral Booting chapter in the device-specific Technical Reference Manual.

Table 7-11. Input Requirements for Crystal Circuit on the Auxiliary Oscillator (AUXOSC)

PARAMETER

Start-up time (from power up until oscillating at stable frequency)

Crystal Oscillation frequency

MIN

TYP

MAX

4

UNIT

ms

20

12

30

24

50

MHz

pF

Parallel Load Capacitance (C1 and C2)

Crystal ESR

Ω

Crystal Shunt Capacitance (Cshunt)

Crystal Oscillation Mode

Crystal Frequency stability⁽¹⁾

5

pF

Fundamental Only

n/a

ppm

±50

(1) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC

7.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input

A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillators as the DEV and

AUX clock inputs to the system. The external connections to support this are shown in Figure 7-10 and

Figure 7-11. The DEV_CLKIN and AUX_CLKIN pins are connected to the 1.8-V LVCMOS-Compatible

clock sources. The DEV_MXO and AUX_MXO pins are left unconnected. The VSSA_DEVOSC and

VSSA_AUXOSC pins are connected to board ground (VSS).

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DEVOSC_MXI/

DEV_CLKIN

DEVOSC_MXO

VSSA_DEVOSC

NC

Figure 7-10. 1.8-V LVCMOS-Compatible Clock Input (DEV_OSC)

AUXOSC_MXI/

AUX_CLKIN

AUXOSC_MXO

VSSA_AUXOSC

NC

Figure 7-11. 1.8-V LVCMOS-Compatible Clock Input (AUX_OSC)

The clock source must meet the DEVOSC_MXI/DEV_CLKIN timing requirements shown in Table 7-14,

Timing Requirements for DEVOSC_MXI/DEV_CLKIN.

The clock source must meet the AUXOSC_MXI/AUX_CLKIN timing requirements shown in Table 7-15,

Timing Requirements for AUXOSC_MXI/AUX_CLKIN.

7.4.2 SERDES_CLKN/P Input Clock

A high-quality, low-jitter differential clock source is required for the SERDES and is an optional clock

source for the SATA PHY. The clock is required to be AC coupled to the device's SERDES_CLKP and

SERDES_CLKN pins according to the specifications in Table 7-12. Both the clock source and the coupling

capacitors should be placed physically as close to the processor as possible. In addition, make sure to

follow any PCB routing and termination recommendations that the clock source manufacturer

recommends.

Table 7-12. SERDES_CLKN/P AC Coupling Capacitors Recommendations

PARAMETER

MIN

TYP

0.27

0402

MAX

4.0

UNIT

nF

SERDES_CLKN/P AC coupling capacitor value

SERDES_CLKN/P AC coupling capacitor package size⁽¹⁾⁽²⁾

0.25

0603

EIA

(1) L x W, 10 Mil units, that is, a 0402 is a 40 x 20 Mil surface mount capacitor.

(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side-by-side.

The value of this capacitor depends on several factors including differential input clock swing. For a

100MHz differential clock with an approximate 1V voltage swing, the recommended typical value for the

SerDes Clock AC Coupling Capacitors is 270pF.

Deviating from this recommendation can result in the reduction of clock signal amplitude or lowering the

noise rejection characteristics.

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In addition, LVDS clock sources that are compliant to the above specification, but with the following

exceptions, are also acceptable:

Table 7-13. Acceptable Exceptions to the REFCLK AC Specifications for LVDS Clock Sources

PARAMETER

Differential High-Level Input Voltage

Differential Low-Level Input Voltage

MIN

125

MAX

1000

-125

UNIT

mV

V_IH

V_IL

-1000

mV

7.4.3 CLKIN32 Input Clock

An external 32768-Hz clock input can optionally be provided at the CLKIN32 pin to serve as a reference

clock in place of the RTCDIVIDER clock for the following Modules:

•

RTC

GPIO0/1/2/3

TIMER1/2/3/4/5/6/7

ARM Cortex-A8

SYNCTIMER

The CLKIN32 source must meet the timing requirements shown in Table 7-16.

7.4.4 Output Clocks Select Logic

The device includes two selectable general-purpose clock outputs (CLKOUT0 and CLKOUT1). The source

for these output clocks is controlled by the CLKOUT_MUX register in the Control Module (see Figure 7-

12).

CLKOUT_MUX

RESERVED

1011-1111

RCOSC32K Output

1010

PLL_AUDIO

1001

ARM Cortex-A8 Functional Clock / 16

1000

AUX Clock

0111

CLKOUT0

DEV Clock

0110

CLKOUT1

PLL_L3L4 Output

0101

PLL_MEDIACTL Output / 2

0100

PLL_HDVPSS Output / 2

0011

RESERVED

0010

SATA0 SERDES Observation Clock

0001

CLKIN32

PLL_VIDEO0

PLL_HDVICP

PLL_HDVPSS

11

10

01

00

PRCM SYSCLK Output

0000

Figure 7-12. CLKOUTx Source Selection Logic

For detailed information on the CLKOUTx switching characteristics, see Table 7-17.

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7.4.5 Input/Output Clocks Electrical Data/Timing

Note: If an external clock oscillator is used, a single clean power supply should be used to power both the

device and the external clock oscillator circuit.

Table 7-14. Timing Requirements for DEVOSC_MXI/DEV_CLKIN^{(1) (2) (3)}(see Figure 7-13)

OPP100

UNIT

NO.

MIN

33.33

0.45C

NOM

MAX

50

1

2

3

4

5

t_c(DMXI)

t_w(DMXIH)

t_w(DMXIL)

t_t(DMXI)

Cycle time, DEVOSC_MXI/DEV_CLKIN

Pulse duration, DEVOSC_MXI/DEV_CLKIN high

Pulse duration, DEVOSC_MXI/DEV_CLKIN low

Transition time, DEVOSC_MXI/DEV_CLKIN

Period jitter, DEVOSC_MXI/DEV_CLKIN

Frequency Stability

50

ns

0.55C

7

ns

t_J(DMXI)

0.02C

±50

ns

ppm

(1) The DEVOSC_MXI/DEV_CLKIN frequency and PLL settings should be chosen such that the resulting SYSCLKs and Module Clocks are

within the specific ranges shown in the Section 7.4.7, SYSCLKs and Section 7.4.8, Module Clocks.

(2) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(3) C = DEV_CLKIN cycle time in ns. For example, when DEVOSC_MXI/DEV_CLKIN frequency is 20 MHz, use C = 50 ns.

5

1

4

1

2

DEVOSC_MXI/

DEV_CLKIN

3

4

Figure 7-13. DEV_MXI/DEV_CLKIN Timing

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Table 7-15. Timing Requirements for AUX_MXI/AUX_CLKIN ^{(1) (2)}(see Figure 7-14)

OPP100

NOM

50

NO.

UNIT

MIN

33.3

MAX

50 ns

1

2

3

4

5

6

t_c(AMXI)

Cycle time, AUXOSC_MXI/AUX_CLKIN

t_w(AMXIH)

t_w(AMXIL)

t_t(AMXI)

t_J(AMXI)

S_f

Pulse duration, AUXOSC_MXI/AUX_CLKIN high

Pulse duration, AUXOSC_MXI/AUX_CLKIN low

Transition time, AUXOSC_MXI/AUX_CLKIN

Period jitter, AUXOSC_MXI/AUX_CLKIN

0.45C

0.55C ns

7

ns

0.02C ns

± 50 ppm

Frequency stability, AUXOSC_MXI/AUX_CLKIN⁽³⁾

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) C = AUX_CLKIN cycle time in ns. For example, when AUXOSC_MXI/AUX_CLKIN frequency is 20 MHz, use C = 50 ns.

(3) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC.

5

1

4

1

2

AUXOSC_MXI/

AUX_CLKIN

3

4

Figure 7-14. AUX_MXI/AUX_CLKIN Timing

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UNIT

Table 7-16. Timing Requirements for CLKIN32 ⁽¹⁾⁽²⁾(see Figure 7-15)

OPP100

NOM

NO.

MIN

1/32768

0.45C

MAX

1

2

3

4

5

t_c(CLKIN32)

t_w(CLKIN32H)

t_w(CKIN32L)

t_t(CLKIN32)

t_J(CLKIN32)

Cycle time, CLKIN32

s

Pulse duration, CLKIN32 high

Pulse duration, CLKIN32 low

Transition time, CLKIN32

Period jitter, CLKIN32

0.55C

7

ns

0.45C

0.02C

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) C = CLKIN32 cycle time in ns. For example, when CLKIN32 frequency is 32768 Hz, use C = 1/32768 s.

5

1

4

1

2

CLKIN32

3

4

Figure 7-15. CLKIN32 Timing

Table 7-17. Switching Characteristics Over Recommended Operating Conditions for CLKOUTx (CLKOUT0

and CLKOUT1)^{(1) (2)}

(see Figure 7-16)

OPP100

NO.

PARAMETER

UNIT

MIN

5

MAX

1

2

3

4

t_c(CLKOUTx)

t_w(CLKOUTxH)

t_w(CLKOUTxL)

t_t(CLKOUTx)

Cycle time, CLKOUTx

ns

Pulse duration, CLKOUTx high

Pulse duration, CLKOUTx low

Transition time, CLKOUTx

0.45P

0.55P

0.05P

(1) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(2) P = 1/CLKOUTx clock frequency in nanoseconds (ns). For example, when CLKOUTx frequency is 200 MHz, use P = 5 ns.

2

4

1

CLKOUTx

(Divide-by-1)

3

4

Figure 7-16. CLKOUTx Timing

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7.4.6 PLLs

The device contains 10 top-level PLLs, and embedded PLLs (within the ARM Cortex-A8, SATA, and CSI)

that provide clocks to different parts of the system. Figure 7-17 and Figure 7-18 show simplified block

diagrams of the Top-Level PLL and PLL_ARM. In addition, see the System Clocking Overview (Figure 7-

7) for a high-level view of the device clock architecture including the PLL reference clock sources and

connections.

DEV/AUX

Clock

REFCLK

CLKDCO

1

xM

Multiplier

(N +1)

M2

CLKOUT

1

(N2 +1)

Figure 7-17. Top-Level PLL Simplified Block Diagram

DEV Clock

REFCLK

DCOCLK

1

2

x2M

Multiplier

(N +1)

M2

CLKOUT

1

(N2 +1)

Figure 7-18. PLL_ARM Simplified Block Diagram

The reference clock for most of the PLLs comes from the DEV input clock, with select PLLs also having

the option to use the AUX input clock as a reference. Also, each PLL supports a Bypass mode in which

the reference clock can be directly passed to the PLL CLKOUT through a divider. All device PLL’s will

come-up in Bypass mode after reset.

For details on programming the device PLLs, see the Control Module chapter in the device-specific

Technical Reference Manual.

7.4.6.1 PLL Power Supply Filtering

The device PLLs are supplied externally via the VDDA_xPLL_1P8 power-supply pins (where "x"

represents ARM, VID0, VID1, AUDIO, DDR, and/or L3). External filtering must be added on the PLL

supply pins to ensure that the requirements in Table 7-18 are met.

Table 7-18. PLL Power Supply Requirements

PARAMETER

MIN

MAX

UNIT

Dynamic noise at VDDA_xPLL_1P8 pins

50

mV p-p

7.4.6.2 PLL Multipliers and Dividers

The Top-Level and PLL_ARM PLLs support the internal multiplier and divider values shown in Table 7-19,

Top-Level PLL Multiplier and Divider Limits and Table 7-20, PLL_ARM Multiplier and Divider Limits. The

PLLs must be programmed to conform to the various REFCLK, CLKDCO, DCOCLK, and CLKOUT limits

described in Section 7.4.6.3, PLL Frequency Limits.

Table 7-19. Top-Level PLL Multiplier and Divider Limits

PARAMETER

MIN

MAX

N Pre-Divider

0

255

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Table 7-19. Top-Level PLL Multiplier and Divider Limits (continued)

PARAMETER

MIN

2

MAX

4095⁽¹⁾

127

PLL Multiplier (M)

M2 Post Divider

N2 Bypass Divider

1

0

15

(1) The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is > 4093.

Table 7-20. PLL_ARM Multiplier and Divider Limits

PARAMETER

MIN

0

MAX

127

N Pre-Divider

PLL Multiplier (M)⁽¹⁾

2

2047⁽²⁾

M2 Post Divider

1

31

N2 Bypass Divider

0

15

(1) This parameter describes the limits on the programmable multiplier value M. The multiplication factor for the PLL_ARM is equal to 2 * M

(also see Figure 7-18).

(2) The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is < 20 OR > 2045.

7.4.6.3 PLL Frequency Limits

Each PLL supports a minimum and maximum operating frequency for its REFCLK, CKLDCO, and

CLKOUT values. The PLLs must be configured not to exceed any of the constraints placed on these

values shown in Table 7-21 through Table 7-23. Care must be taken to stay within these limits when

selecting external clock input frequencies, internal divider values, and PLL multiply ratios. In addition,

limits shown in these tables may be further restricted by the clock frequency limitations of the device

modules using these clocks. For more detailed information on the SYSCLK and Module Clock frequency

limits, see Section 7.4.7, SYSCLKs and Section 7.4.8, Module Clocks.

Table 7-21. Top-Level PLL Frequency Ranges (ALL OPPs)

CLOCK

REFCLK

CLKDCO (HS1)⁽¹⁾

CLKDCO (HS2)⁽²⁾

CLKOUT

MIN

0.5

MAX

2.5

UNIT

MHz

1000

2000

500

1000

see Table 7-23

(1) The PLL has two modes of operation: HS1 and HS2. The mode of operation should be set, according to the desired CLKDCO

frequency, by programming the SELFREQDCO field of the ADPLLLJx_CLKCTRL registers in the Control Module.

(2) CLKDCO of the PLL_USB is used undivided by the USB modules; therefore, CLKDCO for the PLL_USB PLL must be programmed to

960 MHz for proper operation.

Table 7-22. ARM Cortex-A8 Embedded PLL (PLL_ARM) Frequency Ranges (ALL OPPs)

CLOCK

REFCLK

DCOCLK

CLKOUT

MIN

0.032

MAX

52

UNIT

MHz

20

2000

see Table 7-23

Table 7-23. PLL CLKOUT Frequency Ranges

OPP100

PLL

UNIT

MIN

10

MAX

600

266

200

PLL_ARM

PLL_HDVICP

PLL_L3L4

MHz

10

150

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Table 7-23. PLL CLKOUT Frequency Ranges (continued)

OPP100

PLL

UNIT

MIN

10

MAX

400

200

400

960

200

PLL_DDR

PLL_HDVPSS

PLL_AUDIO

PLL_MEDIACTL

PLL_USB

MHz

10

10⁽¹⁾

PLL_VIDEO0

PLL_VIDEO1

PLL_VIDEO2

10

(1) When the USB is used, PLL_USB must be fixed at 960 MHz.

7.4.6.4 PLL Register Description(s)

The PLL Control Registers reside in the Control Module and are listed in Section 4.1, Control Module of

this datasheet.

7.4.7 SYSCLKs

In some cases, the system clock inputs and PLL outputs are sent to the PRCM Module for division and

multiplexing before being routed to the various device Modules. These clock outputs from the PRCM

Module are called SYSCLKs. Table Table 7-24 lists the device SYSCLKs along with their maximum

supported clock frequencies. In addition, limits shown in these tables may be further restricted by the clock

frequency limitations of the device modules using these clocks. For more details on Module Clock

frequency limits, see Section 7.4.8 Module Clocks.

NOTE

For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).

Table 7-24. Maximum SYSCLK Clock Frequencies

MAX CLOCK FREQUENCY

SYSCLK

OPP100 (MHz)

SYSCLK1

SYSCLK2

SYSCLK3

SYSCLK4

SYSCLK5

SYSCLK6

SYSCLK7

SYSCLK8

SYSCLK9

SYSCLK10

SYSCLK11

SYSCLK12

SYSCLK13

SYSCLK14

SYSCLK15

SYSCLK16

SYSCLK17

RSV

266

220

RSV

110

RSV

192

RSV

48

RSV

27

RSV

27

RSV

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Table 7-24. Maximum SYSCLK Clock Frequencies (continued)

MAX CLOCK FREQUENCY

OPP100 (MHz)

SYSCLK

SYSCLK18

SYSCLK19

SYSCLK20

SYSCLK21

SYSCLK22

SYSCLK23

0.032768

192

RSV

7.4.8 Module Clocks

Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from

a PRCM SYSCLK output. Table 7-25 lists the clock source options for each Module on this device, along

with the maximum frequency that Module can accept. To ensure proper Module functionality, the device

PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.

Table 7-25. Maximum Module Clock Frequencies

MAX FREQUENCY

OPP100 (MHz)

MODULE

CLOCK SOURCE(S)

PLL_ARM

SYSCLK18

Cortex-A8

600

DCAN0/1

DDR0

DEV Clock

PLL_DDR

PLL_DDR/2

SYSCLK4

SYSCLK6

SYSCLK18

SYSCLK6

PLL_VIDEO2

SYSCLK10

30

400

DMM

200

EDMA

220

Face Detect

GPIO

220

110

GPIO Debounce

GPMC

Fixed 0.032768

110

HDMI

186

HDMI CEC

Fixed 48

SYSCLK20

SYSCLK21

AUD_CLK0/1/2

AUX Clock

HDMI I2S

50

HDVICP2

HDVPSS

SYSCLK3

266

200

PLL_HDVPSS

PLL_VIDEO2

HDMI PHY

HDVPSS VOUT1

186

PLL_VIDEO1

PLL_VIDEO2

HDVPSS VOUT0

165

HDVPSS SD VENC

PLL_VIDEO0

Fixed 54

PLL_VIDEO0

PLL_VIDEO1

HDMI

HDVPSS HD VENC

Fixed 148.5

I2C0/1/2/3

ISS

SYSCLK10

PLL_ MEDIACTL

SYSCLK4

48

400

220

110

220

110

L3 Fast

L3 Medium

L3 Slow

L4 Fast

L4 Slow

SYSCLK4

SYSCLK6

SYSCLK4

SYSCLK6

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Table 7-25. Maximum Module Clock Frequencies (continued)

MAX FREQUENCY

OPP100 (MHz)

MODULE

CLOCK SOURCE(S)

Mailbox

McASP

SYSCLK6

110

SYSCLK20

SYSCLK21

McASP0/1 AUX_CLK

192

Media Controller

MMCSD0/1/2

OCMC RAM

PLL_MEDIACTL

SYSCLK8

400

192

220

SYSCLK4

DEV Clock

SERDES_CLKx Pins

SATA0 SERDES

20 or 100

SmartReflex

SPI0/1/2/3

Spinlock

DEV Clock

SYSCLK10

SYSCLK6

SYSCLK18

30

48

110

Sync Timer

Fixed 0.032768

SYSCLK18

DEV Clock

AUX Clock

AUD_CLK0/1/2

TCLKIN

TIMER1/2/3/4/5/6/7/8

30

UART0/1/2

USB

SYSCLK10

48

PLL_USB CLKDCO

Fixed 960

RTCDIVIDER

RCOSC32K

WDT0

Fixed 0.032768

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7.5 Interrupts

The device has a large number of interrupts to service the needs of its many peripherals and subsystems.

The ARM Cortex-A8 and Media Controller are capable of servicing these interrupts. The following sections

list the device interrupt mapping and multiplexing schemes.

7.5.1 ARM Cortex-A8 Interrupts

The ARM Cortex-A8 Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the

System peripherals and generating either IRQs or FIQs to the Cortex-A8. The AINTC has the capability to

handle up to 128 requests, and the priority of the interrupt inputs are programmable. Table 7-26 lists the

interrupt sources for the AINTC.

For more details on ARM Cortex-A8 interrupt control, see the Interrupt Controller section of the Chip Level

Resources chapter in the device-specific Technical Reference Manual.

Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources

Cortex-A8

INTERRUPT NUMBER

ACRONYM

SOURCE

0

1

EMUINT

COMMTX

COMMRX

BENCH

Cortex-A8 Emulation

ELM

2

3

4

ELM_IRQ

–

5

Reserved

6

–

Reserved

7

NMI

NMIn Pin

8

–

Reserved

9

L3DEBUG

L3APPINT

TINT8

L3 Interconnect

TIMER8

10

11

12

13

14

15

16

17

18

19

20-27

28

29

30

31

32

33

34

35

36

37

38

39

EDMACOMPINT

EDMAMPERR

EDMAERRINT

WDTINT0

SATAINT0

USBSSINT

USBINT0

USBINT1

–

EDMA CC Completion

EDMA Memory Protection Error

EDMA CC Error

Watchdog Timer 0

SATA0

USB Subsystem

USB0

USB1

Reserved

SDINT1

SDINT2

I2CINT2

I2CINT3

GPIOINT2A

GPIOINT2B

USBWAKEUP

–

MMC/SD1

MMC/SD2

I2C2

I2C3

GPIO2 A

GPIO2 B

USB Subsystem Wakeup

Reserved

DSSINT

–

HDVPSS

Reserved

HDMIINT

ISS_IRQ_5

HDMI

ISS

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Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)

Cortex-A8

INTERRUPT NUMBER

ACRONYM

SOURCE

40-52

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

–

DCAN0_INT0

DCAN0_INT1

DCAN0_PARITY

DCAN1_INT0

DCAN1_INT1

DCAN1_PARITY

–

Reserved

DCAN0

DCAN0 Parity

DCAN1

DCAN1 Parity

Reserved

GPIO3

-

–

GPIOINT3A

GPIOINT3B

SDINT0

SPIINT0

-

GPIO3

MMC/SD0

SPI0

Reserved

TIMER1

TINT1

TINT2

TIMER2

TINT3

TIMER3

I2CINT0

I2CINT1

UARTINT0

UARTINT1

UARTINT2

RTCINT

RTCALARMINT

MBINT

I2C0

I2C1

UART0

UART1

UART2

RTC

RTC Alarm

Mailbox

–

Reserved

PLL Recalculation Interrupt

McASP0 Transmit

McASP0 Receive

McASP1 Transmit

McASP1 Receive

Reserved

SmartReflex HDVICP Domain

Reserved

TIMER4

PLLINT

MCATXINT0

MCARXINT0

MCATXINT1

MCARXINT1

–

SMRFLX_HDVICP

–

TINT4

TINT5

TIMER5

TINT6

TIMER6

TINT7

TIMER7

GPIOINT0A

GPIOINT0B

GPIO0

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Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)

Cortex-A8

INTERRUPT NUMBER

ACRONYM

SOURCE

98

99

GPIOINT1A

GPIO1

GPIOINT1B

GPIO1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116-119

120

121

122

123

124

125

126

127

GPMCINT

GPMC

DDRERR

DDR

–

Reserved

HDVICPCONT1SYNC

HDVICP2

HDVICPCONT2SYNC

HDVICP2

–

Reserved

–

IVA0MBOXINT

–

Reserved

HDVICP2 Mailbox

Reserved

–

Reserved

–

Reserved

–

Reserved

TCERRINT0

TCERRINT1

TCERRINT2

TCERRINT3

–

EDMA TC 0 Error

EDMA TC 1 Error

EDMA TC 2 Error

EDMA TC 3 Error

Reserved

SMRFLX_ARM

SMRFLX_CORE

–

SmartReflex ARM Domain

SmartReflex CORE Domain

Reserved

MCMMUINT

DMMINT

SPIINT1

SPIINT2

SPIINT3

Media Controller

DMM

SPI1

SPI2

SPI3

156

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8 Peripheral Information and Timings

8.1 Parameter Information

Tester Pin Electronics

Data Sheet Timing Reference Point

42 Ω

3.5 nH

Output

Under

Test

Transmission Line

Z0 = 50 Ω

(see Note)

Device Pin

(see Note)

4.0 pF

1.85 pF

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be

taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is

intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 8-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

8.1.1 1.8-V and 3.3-V Signal Transition Levels

All input and output timing parameters are referenced to V_reffor both "0" and "1" logic levels. For 3.3-V I/O,

V_ref= 1.5 V. For 1.8-V I/O, V_ref= 0.9 V.

V_ref

Figure 8-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_ILMAX and V_IHMIN for input clocks, V_OL

MAX and V_OHMIN for output clocks.

V_ref= V_IHMIN (or V_OHMIN)

V_ref= V_ILMAX (or V_OLMAX)

Figure 8-3. Rise and Fall Transition Time Voltage Reference Levels

8.1.2 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

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8.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external

logic hardware such as buffers may be used to compensate any timing differences.

8.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IHand V_IL(or between V_ILand V_IH) in a monotonic

manner.

NOTE

For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).

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8.3 Controller Area Network Interface (DCAN)

The device provides two DCAN interfaces for supporting distributed realtime control with a high level of

security. The DCAN interfaces implement the following features:

•

Supports CAN protocol version 2.0 part A, B

Bit rates up to 1 MBit/s

64 message objects

Individual identifier mask for each message object

Programmable FIFO mode for message objects

Programmable loop-back modes for self-test operation

Suspend mode for debug support

Software module reset

Automatic bus on after Bus-Off state by a programmable 32-bit timer

Message RAM parity check mechanism

Direct access to Message RAM during test mode

CAN Rx/Tx pins are configurable as general-purpose IO pins

Two interrupt lines (plus additional parity-error interrupts line)

RAM initialization

DMA support

For more detailed information on the DCAN peripheral, see the DCAN Controller Area Network chapter in

the device-specific Technical Reference Manual.

8.3.1 DCAN Peripheral Register Descriptions

The DCAN peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

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8.3.2 DCAN Electrical Data/Timing

Table 8-1. Timing Requirements for DCANx Receive⁽¹⁾(see Figure 8-4)

OPP100/OPP120/Turbo/Nitro

NO.

UNIT

MIN

NOM

MAX

1

f(baud)

Maximum programmable baud rate

Mbps

ns

1

t_w(DCANRX)

Pulse duration, receive data bit (DCANx_RX)

H - 2

H + 2

(1) H = period of baud rate, 1/programmed baud rate.

Table 8-2. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit

⁽¹⁾(see Figure 8-4)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

UNIT

MIN

MAX

1

f(baud)

Maximum programmable baud rate

Mbps

ns

2

t_w(DCANTX)

Pulse duration, transmit data bit (DCANx_TX)

H - 2

H + 2

(1) H = period of baud rate, 1/programmed baud rate.

1

2

DCANx_RX

DCANx_TX

Figure 8-4. DCANx Timings

160

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8.4 EDMA

The EDMA controller handles all data transfers between memories and the device slave peripherals on

the device. These data transfers include cache servicing, non-cacheable memory accesses, user-

programmed data transfers, and host accesses.

8.4.1 EDMA Channel Synchronization Events

The EDMA channel controller supports up to 64 channels which service peripherals and memory. Each

EDMA channel is mapped to a default EDMA synchronization event as shown in Table 8-3. In addition,

each EDMA channel can alternatively be mapped to one of the 31 multiplexed EDMA synchronization

events shown in Table 8-4. The EVT_MUX_x registers in the Control Module are used to select between

the default event and the multiplexed events for each channel.

For more detailed information on the EDMA module and how EDMA events are enabled, captured,

processed, linked, chained, cleared, and more, see the Enhanced Direct Memory Access Controller

chapter in the device-specific Technical Reference Manual.

Table 8-3. EDMA Default Synchronization Events

EVENT

NUMBER

DEFAULT

EVENT NAME

DEFAULT EVENT DESCRIPTION

0-1

2

–

Reserved

SDTXEVT1

SDRXEVT1

–

SD1 Transmit

SD1 Receive

3

4-7

8

Reserved

AXEVT0

AREVT0

AXEVT1

AREVT1

–

McASP0 Transmit

McASP0 Receive

McASP1 Transmit

McASP1 Receive

Reserved

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

42

43

44

45

–

Reserved

–

Reserved

–

Reserved

SPI0XEVT0

SPI0REVT0

SPI0XEVT1

SPI0REVT1

SPI0XEVT2

SPI0REVT2

SPI0XEVT3

SPI0REVT3

SDTXEVT0

SDRXEVT0

UTXEVT0

URXEVT0

UTXEVT1

URXEVT1

UTXEVT2

URXEVT2

SPI1XEVT0

SPI1REVT0

SPI1XEVT1

SPI1REVT1

SPI0 Transmit 0

SPI0 Receive 0

SPI0 Transmit 1

SPI0 Receive 1

SPI0 Transmit 2

SPI0 Receive 2

SPI0 Transmit 3

SPI0 Receive 3

SD0 Transmit

SD0 Receive

UART0 Transmit

UART0 Receive

UART1 Transmit

UART1 Receive

UART2 Transmit

UART2 Receive

SPI1 Transmit 0

SPI1 Receive 0

SPI1 Transmit 1

SPI1 Receive 1

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Table 8-3. EDMA Default Synchronization Events (continued)

EVENT

NUMBER

DEFAULT

EVENT NAME

DEFAULT EVENT DESCRIPTION

46

48

49

50

51

52

58

59

60

61

62

63

–

Reserved

TIMER4

TIMER5

TIMER6

TIMER7

GPMC

TINT4

TINT5

TINT6

TINT7

GPMCEVT

I2CTXEVT0

I2CRXEVT0

I2CTXEVT1

I2CRXEVT1

–

I2C0 Transmit

I2C0 Receive

I2C1 Transmit

I2C1 Receive

Reserved

–

Reserved

Table 8-4. EDMA Multiplexed Synchronization Events

EVT_MUX_x

VALUE

MULTIPLEXED

EVENT NAME

MULTIPLEXED EVENT DESCRIPTION

0

-

Default Event

SD2 Transmit

SD2 Receive

I2C2 Transmit

I2C2 Receive

I2C3 Transmit

I2C3 Receive

Reserved

1

SDTXEVT2

SDRXEVT2

I2CTXEVT2

I2CRXEVT2

I2CTXEVT3

I2CRXEVT3

–

2

3

4

5

6

7

8

–

Reserved

9

–

Reserved

10

11

12

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

–

Reserved

–

Reserved

–

Reserved

SPI2XEVT0

SPI2REVT0

SPI2XEVT1

SPI2REVT1

SPI3XEVT0

SPI3REVT0

–

SPI2 Transmit 0

SPI2 Receive 0

SPI2 Transmit 1

SPI2 Receive 1

SPI3 Transmit 0

SPI3 Receive 0

Reserved

TINT1

TIMER1

TINT2

TIMER2

TINT3

TIMER3

–

Reserved

–

Reserved

EDMAEVT0

EDMAEVT1

EDMAEVT2

EDMAEVT3

EDMA_EVT0 Pin

EDMA_EVT1 Pin

EDMA_EVT2 Pin

EDMA_EVT3 Pin

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8.4.2 EDMA Peripheral Register Description

The EDMA peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

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8.5 Emulation Features and Capability

8.5.1 Advanced Event Triggering (AET)

The device supports Advanced Event Triggering (AET). This capability can be used to debug complex

problems as well as understand performance characteristics of user applications. AET provides the

following capabilities:

•

Hardware Program Breakpoints: specify addresses or address ranges that can generate events such

as halting the processor or triggering the trace capture.

•

Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate

events such as halting the processor or triggering the trace capture.

•

Counters: count the occurrence of an event or cycles for performance monitoring.

State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to

precisely generate events for complex sequences.

For more information on AET, see the following documents:

•

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report

(Literature Number: SPRA753).

•

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded

Microprocessor Systems application report (Literature Number: SPRA387).

8.5.2 Trace

The device supports Trace at the Cortex™-A8 and System levels. Trace is a debug technology that

provides a detailed, historical account of application code execution, timing, and data accesses. Trace

collects, compresses, and exports debug information for analysis. The debug information can be exported

to the Embedded Trace Buffer (ETB), or to the 5-pin Trace Interface (system trace only). Trace works in

real-time and does not impact the execution of the system.

For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and

Trace Headers Technical Reference Manual (Literature Number: SPRU655).

8.5.3 IEEE 1149.1 JTAG

The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)

interface is used for BSDL testing and emulation of the device. The TRST pin only needs to be released

when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan

functionality. For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to

ensure that TRST is always asserted upon power up and the device's internal emulation logic is always

properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some

third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally

drive TRST high before attempting any emulation or boundary-scan operations.

The main JTAG features include:

•

32KB embedded trace buffer (ETB)

5-pin system trace interface for debug

Supports Advanced Event Triggering (AET)

All processors can be emulated via JTAG ports

All functions on EMU pins of the device:

–

EMU[1:0] - cross-triggering, boot mode (WIR), STM trace

EMU[4:2] - STM trace only (single direction)

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8.5.3.1 JTAG ID (JTAGID) Register Description

Table 8-5. JTAG ID Register⁽¹⁾

HEX ADDRESS

ACRONYM

REGISTER NAME

JTAG Identification Register⁽²⁾

0x4814 0600

JTAGID

(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

(2) Read-only. Provides the device 32-bit JTAG ID.

The JTAG ID register is a read-only register that identifies to the customer the JTAG/device ID. For this

device, the JTAG ID register resides at address location 0x4814 0600. For the actual register bit names

and their associated bit field descriptions, see Figure 8-5 and Table 8-6.

31

28 27

12 11

1

0

VARIANT (4-

PART NUMBER (16-bit)

R-1011 1001 0110 1011

MANUFACTURER (11-bit)

R-0000 0010 111

LSB

R-1

bit)

R-xxxx

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 8-5. JTAG ID Register Description - Device Register Value: 0x0B8F 202F

Table 8-6. JTAG ID Register Selection Bit Descriptions

Bit

Field

Description

31:28

VARIANT

Variant (4-bit) value. Device value: xxxx. This value reflects the device silicon revision [For example, 0x0

(0000) for initial silicon (1.0)]. For more detailed information on the current device silicon revision, see the

device-specific Silicon Errata.

27:12

11:1

0

PART NUMBER

Part Number (16-bit) value. Device value: 0xB96B (1011 1001 0110 1011)

MANUFACTURER Manufacturer (11-bit) value. Device value: 0x017 (0000 0010 111)

LSB LSB. This bit is read as a ""1 for this device.

8.5.3.2 JTAG Electrical Data/Timing

Table 8-7. Timing Requirements for IEEE 1149.1 JTAG

(see Figure 8-6)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

59

MAX

1

t_c(TCK)

1a t_w(TCKH)

1b t_w(TCKL)

Cycle time, TCK

ns

Pulse duration, TCK high (40% of t_c)

23.6

5.9

Pulse duration, TCK low (40% of t_c)

3

t_su(TDI-TCK)

Input setup time, TDI valid to TCK high (20% of (t_c* 0.5))

Input setup time, TMS valid to TCK high (20% of (t_c* 0.5))

Input hold time, TDI valid from TCK high

Input hold time, TMS valid from TCK high

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

5.9

29.5

4

Table 8-8. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

(see Figure 8-6)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

UNIT

MIN

MAX

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

23.575⁽¹⁾

ns

(1) (0.5 * t_c) - 2

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1

1a

1b

TCK

2

TDO

3

4

TDI/TMS

Figure 8-6. JTAG Timing

Table 8-9. Timing Requirements for IEEE 1149.1 JTAG With RTCK

(see Figure 8-6)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

1

t_c(TCK)

1a t_w(TCKH)

1b t_w(TCKL)

Cycle time, TCK

59

ns

Pulse duration, TCK high (40% of t_c)

23.6

5.9

Pulse duration, TCK low (40% of t_c)

3

t_su(TDI-TCK)

Input setup time, TDI valid to TCK high (20% of (t_c* 0.5))

Input setup time, TMS valid to TCK high (20% of (t_c* 0.5))

Input hold time, TDI valid from TCK high

Input hold time, TMS valid from TCK high

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

5.9

29.5

4

Table 8-10. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

With RTCK

(see Figure 8-7)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, TCK to RTCK with no selected subpaths (that is,

ICEPick is the only tap selected - when the ARM is in the scan

chain, the delay time is a function of the ARM functional clock.)

5

t_d(TCK-RTCK)

0

24

ns

6

7

8

t_c(RTCK)

Cycle time, RTCK

59

23.6

ns

t_w(RTCKH)

t_w(RTCKL)

Pulse duration, RTCK high (40% of t_c)

Pulse duration, RTCK low (40% of t_c)

5

TCK

6

7

8

RTCK

Figure 8-7. JTAG With RTCK Timing

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Table 8-11. Switching Characteristics Over Recommended Operating Conditions for STM Trace

(see Figure 8-8)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

UNIT

MIN

4⁽¹⁾

3.5

MAX

Pulse duration, EMUx high detected at 50% V_OHwith 60/40 duty

cycle

t_w(EMUH50)

t_w(EMUH90)

t_w(EMUL50)

t_w(EMUL10)

t_sko(EMU)

ns

1

Pulse duration, EMUx high detected at 90% V_OH

Pulse duration, EMUx low detected at 50% V_OHwith 60/40 duty

cycle

4⁽¹⁾

3.5

2

3

Pulse duration, EMUx low detected at 10% V_OH

Output skew time, time delay difference between EMUx pins

configured as trace.

-0.5

0.5

Pulse skew, magnitude of difference between high-to-low (t_PHL

and low-to-high (t_PLH) propagation delays

)

t_skp(EMU)

0.6⁽¹⁾

ns

t_{sldp_o(EMU)}

Output slew rate EMUx

3.3

V/ns

(1) This parameter applies to the maximum trace export frequency operating in a 40/60 duty cycle.

A

Buffer

Inputs

Buffers

EMUx Pins

t_PHL

t_PLH

1

2

B

C

B

C

A

3

Figure 8-8. STM Trace Timing

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8.6 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register controls the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal

register. In addition, the GPIO peripheral can produce CPU interrupts in different interrupt generation

modes. The GPIO peripheral provides generic connections to external devices.

The device contains four GPIO modules and each GPIO module consists of up to 32 identical channels.

The device GPIO peripheral supports the following:

•

Up to 125 1.8-V/3.3-V GPIO pins, GP0[0:28], GP1[0:31], GP2[0:31], and GP3[0:31] (the exact number

available varies as a function of the device configuration). Each channel can be configured to be used

in the following applications:

–

Data input/output

Keyboard interface with a de-bouncing cell

Synchronous interrupt generation (in active mode) upon the detection of external events (signal

transitions and/or signal levels).

•

Synchronous interrupt requests from each channel are processed by four identical interrupt generation

sub-modules to be used independently by the ARM or Media Controller. Interrupts can be triggered by

rising and/or falling edge, specified for each interrupt-capable GPIO signal.

Shared registers can be accessed through "Set & Clear" protocol. Software writes 1 to corresponding

bit positions to set or to clear GPIO signals. This allows multiple software processes to toggle GPIO

output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts,

to prevent context switching to another process during GPIO programming).

•

Separate input/output registers.

Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can

be toggled by direct write to the output registers.

•

Output register, when read, reflects output drive status. This, in addition to the input register reflecting

pin status and open-drain I/O cell, allows wired logic to be implemented.

For more detailed information on GPIOs, see the General-Purpose I/O (GPIO) Interface chapter in the

device-specific Technical Reference Manual.

8.6.1 GPIO Peripheral Register Descriptions

The GPIO peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

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8.6.2 GPIO Electrical Data/Timing

Table 8-12. Timing Requirements for GPIO Inputs

(see Figure 8-9)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

1

2

t_w(GPIH)

t_w(GPIL)

Pulse duration, GPx[31:0] input high

Pulse duration, GPx[31:0] input low

12P⁽¹⁾

ns

(1) P = Module clock.

Table 8-13. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs

(see Figure 8-9)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

UNIT

MIN

36P-8⁽¹⁾

MAX

3

4

t_w(GPOH)

t_w(GPOL)

Pulse duration, GPx[31:0] output high

Pulse duration, GPx[31:0] output low

ns

(1) P = Module clock.

2

1

GPx[31:0]

input

4

3

GPx[31:0]

output

Figure 8-9. GPIO Port Timing

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8.7 General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)

The GPMC is a device memory controller used to provide a glueless interface to external memory devices

such as NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection for 8-bit or 16-bit NAND

Flash), SRAM, and Pseudo-SRAM. It includes flexible asynchronous protocol control for interface to

SRAM-like memories and custom logic (FPGA, CPLD, ASICs, etc.).

Other supported features include:

•

8-/16-bit wide multiplexed address/data bus

512 MBytes maximum addressing capability divided among up to eight chip selects

Non-multiplexed address/data mode

Pre-fetch and write posting engine associated with system DMA to get full performance from NAND

device with minimum impact on NOR/SRAM concurrent access.

The device also contains an Error Locator Module (ELM) which is used to extract error addresses from

syndrome polynomials generated using a BCH algorithm. Each of these polynomials gives a status of the

read operations for a 512 bytes block from a NAND flash and its associated BCH parity bits, plus

optionally spare area information. The ELM has the following features:

•

4-bit, 8-bit and 16-bit per 512byte block error location based on BCH algorithms

Eight simultaneous processing contexts

Page-based and continuous modes

Interrupt generation on error location process completion

–

When the full page has been processed in page mode

For each syndrome polynomial in continuous mode

8.7.1 GPMC and ELM Peripherals Register Descriptions

The GPMC and ELM peripheral registers are described in the device-specific Technical Reference

Manual. Each register is documented as an offset from a base address for the peripheral. The base

addresses for all of the peripherals are in the device memory map (see Section 2.10).

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8.7.2 GPMC Electrical Data/Timing

8.7.2.1 GPMC and NOR Flash Interface Synchronous Mode Timing (Non-Multiplexed and Multiplexed

Modes)

Table 8-14. Timing Requirements for GPMC and NOR Flash Interface - Synchronous Mode

(see Figure 8-10, Figure 8-11, Figure 8-12 for Non-Multiplexed Modes)

(see Figure 8-13, Figure 8-14, Figure 8-15 for Multiplexed Modes)

OPP100/OPP120/Turbo/Nitr

o

NO.

UNIT

MIN

3.2

2.5

3.2

2.5

MAX

13 t_su(DV-CLKH)

14 t_h(CLKH-DV)

22 t_{su(WAITV-CLKH)}

23 t_{h(CLKH-WAITV)}

Setup time, read GPMC_D[15:0] valid before GPMC_CLK high

Hold time, read GPMC_D[15:0] valid after GPMC_CLK high

Setup time, GPMC_WAIT[x] valid before GPMC_CLK high

Hold time, GPMC_WAIT[x] valid after GPMC_CLK high

ns

Table 8-15. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR

Flash Interface - Synchronous Mode

(see Figure 8-10, Figure 8-11, Figure 8-12 for Non-Multiplexed Modes)

(see Figure 8-13, Figure 8-14, Figure 8-15 for Multiplexed Modes)

OPP100/OPP120/Turb

o/Nitro

NO.

PARAMETER

UNIT

MIN

MAX

1

2

t_c(CLK)

Cycle time, output clock GPMC_CLK period

16⁽¹⁾

0.5P⁽²⁾

ns

t_w(CLKH)

Pulse duration, output clock GPMC_CLK high

t_w(CLKL)

Pulse duration, output clock GPMC_CLK low

3

4

5

t_d(CLKH-nCSV)

t_{d(CLKH-nCSIV)}

t_d(ADDV-CLK)

Delay time, GPMC_CLK rising edge to GPMC_CS[x] transition

Delay time, GPMC_CLK rising edge to GPMC_CS[x] invalid

Delay time, GPMC_A[27:0] address bus valid to GPMC_CLK first edge

F - 2.2⁽³⁾F + 4.5⁽³⁾

E - 2.2⁽⁴⁾E + 4.5⁽⁴⁾

B - 4.5⁽⁵⁾B + 2.3⁽⁵⁾

ns

Delay time, GPMC_CLK rising edge to GPMC_A[27:0] GPMC address bus

invalid

6

t_{d(CLKH-ADDIV)}

-2.3

ns

7

8

t_d(nBEV-CLK)

Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CLK first edge

Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE, GPMC_BE1 invalid

B - 1.9⁽⁵⁾B + 2.3⁽⁵⁾

D - 2.3⁽⁶⁾D + 1.9⁽⁶⁾

ns

t_{d(CLKH-nBEIV)}

(1) Sync mode = 62.5 MHz; Async mode = 125 MHz.

(2) P = GPMC_CLK period.

(3) For nCS falling edge (CS activated):

•

For GpmcFCLKDivider = 0:

F = 0.5 * CSExtraDelay * GPMC_FCLK

For GpmcFCLKDivider = 1:

•

F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are

even)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise

•

For GpmcFCLKDivider = 2:

F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)

F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)

(4) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(5) B = ClkActivationTime * GPMC_FCLK

(6) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

Peripheral Information and Timings

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Table 8-15. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR

Flash Interface - Synchronous Mode (continued)

(see Figure 8-10, Figure 8-11, Figure 8-12 for Non-Multiplexed Modes)

(see Figure 8-13, Figure 8-14, Figure 8-15 for Multiplexed Modes)

OPP100/OPP120/Turb

o/Nitro

NO.

PARAMETER

UNIT

MIN

MAX

9

t_d(CLKH-nADV)

Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE transition

Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE invalid

Delay time, GPMC_CLK rising edge to GPMC_OE_RE transition

Delay time, GPMC_CLK rising edge to GPMC_OE_RE invalid

G - 2.3⁽⁷⁾G + 4.5⁽⁷⁾

D - 2.3⁽⁶⁾D + 4.5⁽⁶⁾

H - 2.3⁽⁸⁾H + 3.5⁽⁸⁾

E - 2.3⁽⁴⁾E + 3.5⁽⁴⁾

ns

10 t_{d(CLKH-nADVIV)}

11 t_d(CLKH-nOE)

12 t_{d(CLKH-nOEIV)}

(7) For ADV falling edge (ADV activated):

•

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

•

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are

even)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

•

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and

ADVRdOffTime are even)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

•

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and

ADVWrOffTime are even)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)

(8) For OE falling edge (OE activated) / IO DIR rising edge (IN direction) :

•

Case GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are

even)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)

For OE rising edge (OE deactivated):

•

Case GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are

even)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)

172

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Table 8-15. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR

Flash Interface - Synchronous Mode (continued)

(see Figure 8-10, Figure 8-11, Figure 8-12 for Non-Multiplexed Modes)

(see Figure 8-13, Figure 8-14, Figure 8-15 for Multiplexed Modes)

OPP100/OPP120/Turb

o/Nitro

MIN

I - 2.3⁽⁹⁾

NO.

PARAMETER

UNIT

MAX

I + 4.5⁽⁹⁾

15 t_d(CLKH-nWE)

16 t_d(CLKH-Data)

Delay time, GPMC_CLK rising edge to GPMC_WE transition

ns

Delay time, GPMC_CLK rising edge to GPMC_D[15:0] data bus transition

J - 2.3⁽¹⁰⁾J + 1.9⁽¹⁰⁾

Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE, GPMC_BE1

transition

18 t_d(CLKH-nBE)

J - 2.3⁽¹⁰⁾J + 1.9⁽¹⁰⁾

ns

19 t_w(nCSV)

20 t_w(nBEV)

21 t_w(nADVV)

Pulse duration, GPMC_CS[x] low

A⁽¹¹⁾

C⁽¹²⁾

K⁽¹³⁾

ns

Pulse duration, GPMC_BE0_CLE, GPMC_BE1 low

Pulse duration, GPMC_ADV_ALE low

(9) For WE falling edge (WE activated):

•

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

•

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are

even)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)

For WE rising edge (WE deactivated):

•

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are

even)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)

(10) J = GPMC_FCLK period.

(11) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n

= page burst access number]

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n

= page burst access number]

(12) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst

access number]

For Burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst

access number]

(13) For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

Peripheral Information and Timings

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2

1

2

GPMC_CLK

3

4

19

GPMC_CS[x]

5

GPMC_A[27:0]

Address

7

8

20

GPMC_BE1

7

20

GPMC_BE0_CLE

9

21

10

12

GPMC_ADV_ALE

GPMC_OE

11

14

13

GPMC_D[15:0]

GPMC_WAIT[x]

D0

22

23

Figure 8-10. GPMC Non-Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)

2

1

2

GPMC_CLK

3

4

19

GPMC_CS[x]

5

GPMC_A[27:0]

GPMC_BE1

Address

20

8

7

Valid

20

Valid

GPMC_BE0_CLE

9

10

12

21

GPMC_ADV_ALE

GPMC_OE

11

14

13

GPMC_D[15:0]

(Non-Multplexed Mode)

D0

22

D1

D2

D3

23

GPMC_WAIT[x]

Figure 8-11. GPMC Non-Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read

(GPMCFCLKDIVIDER = 0)

174

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2

1

GPMC_CLK

3

4

19

GPMC_CS[x]

GPMC_A[27:0]

GPMC_BE1

5

7

Address

18

7

18

GPMC_BE0_CLE

9

10

21

GPMC_ADV_ALE

GPMC_WE

15

16

GPMC_D[15:0]

(Non-Multiplexed Mode)

D0

23

D1

22

D2

D3

GPMC_WAIT[x]

Figure 8-12. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

2

1

2

GPMC_CLK

3

4

19

GPMC_CS[x]

5

7

GPMC_A[27:16]

Address

20

8

GPMC_BE1

7

20

GPMC_BE0_CLE

9

21

10

12

GPMC_ADV_ALE

GPMC_OE

11

5

6

13

14

GPMC_D[15:0]

(Multiplexed Mode)

Address (LSB)

23

D0

22

GPMC_WAIT[x]

Figure 8-13. GPMC Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)

Peripheral Information and Timings

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2

1

2

GPMC_CLK

GPMC_CS[x]

3

4

19

5

GPMC_A[27:16]

Address (MSB)

8

7

20

Valid

GPMC_BE1

8

7

20

Valid

GPMC_BE0_CLE

9

10

12

21

GPMC_ADV_ALE

GPMC_OE

11

14

13

5

6

GPMC_D[15:0]

(Multplexed Mode)

Address (LSB)

D0

22

D1

D2

D3

23

GPMC_WAIT[x]

Figure 8-14. GPMC Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read (GPMCFCLKDIVIDER = 0)

2

1

GPMC_CLK

GPMC_CS[x]

3

4

19

5

7

6

GPMC_A[27:16]

GPMC_BE1

Address (MSB)

18

7

GPMC_BE0_CLE

9

10

21

GPMC_ADV_ALE

GPMC_WE

15

16

6,16

5

16

GPMC_D[15:0]

(Multiplexed Mode)

Address (LSB)

D0

D1

22

D2

D3

23

GPMC_WAIT[x]

Figure 8-15. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

8.7.2.2 GPMC and NOR Flash Interface Asynchronous Mode Timing (Non-Multiplexed and Multiplexed

Modes)

176

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Table 8-16. Timing Requirements for GPMC and NOR Flash Interface - Asynchronous Mode

(see Figure 8-16, Figure 8-17 for Non-Multiplexed Mode )

(see Figure 8-18, Figure 8-20 for Multiplexed Mode)

OPP100/OPP120/Turbo/Nitr

o

NO.

UNIT

MIN

MAX

H⁽¹⁾cycles

6

t_acc(DAT)

Data maximum access time (GPMC_FCLK cycles)

Page mode successive data maximum access time (GPMC_FCLK

cycles)

21 t_{acc1-pgmode(DAT)}

22 t_{acc2-pgmode(DAT)}

P⁽²⁾

H⁽¹⁾

cycles

Page mode first data maximum access time (GPMC_FCLK cycles)

(1) H = AccessTime * (TimeParaGranularity + 1)

(2) P = PageBurstAccessTime * (TimeParaGranularity + 1).

Table 8-17. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR

Flash Interface - Asynchronous Mode

(see Figure 8-16, Figure 8-17, Figure 8-18, Figure 8-19 for Non-Multiplexed Modes)

(see Figure 8-20, Figure 8-21 for Multiplexed Modes)

OPP100/OPP120/Turb

o/Nitro

NO

.

PARAMETER

UNIT

MIN

MAX

N⁽¹⁾

A⁽²⁾

1

2

4

5

t_w(nBEV)

Pulse duration, GPMC_BE0_CLE, GPMC_BE1 valid time

Pulse duration, GPMC_CS[x] low

ns

t_w(nCSV)

t_{d(nCSV-nADVIV)}

t_{d(nCSV-nOEIV)}

Delay time, GPMC_CS[x] valid to GPMC_NADV_ALE invalid

Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (single read)

Delay time, GPMC_A[27:0] address bus valid to GPMC_CS[x] valid

Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CS[x] valid

Delay time, GPMC_CS[x] valid to GPMC_ADV_ALE valid

Delay time, GPMC_CS[x] valid to GPMC_OE_RE valid

B - 0.2⁽³⁾B + 2.0⁽³⁾

C - 0.2⁽⁴⁾C + 2.0⁽⁴⁾

10 t_d(AV-nCSV)

J - 0.2⁽⁵⁾

J + 2.0⁽⁵⁾

11 t_d(nBEV-nCSV)

13 t_{d(nCSV-nADVV)}

14 t_d(nCSV-nOEV)

K - 0.2⁽⁶⁾K + 2.0⁽⁶⁾

L - 0.2⁽⁷⁾

L + 2.0⁽⁷⁾

Pulse duration, GPMC_A[27:0] address bus invalid between 2 successive R/W

accesses

17 t_w(AIV)

G⁽⁸⁾

ns

19 t_{d(nCSV-nOEIV)}

21 t_w(AV)

Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (burst read)

I - 0.2⁽⁹⁾

D⁽¹⁰⁾

I + 2.0⁽⁹⁾

Pulse duration, GPMC_A[27:0] address bus valid: second, third and fourth

accesses

26 t_d(nCSV-nWEV)

Delay time, GPMC_CS[x] valid to GPMC_WE valid

E - 0.2⁽¹¹⁾E + 2.0⁽¹¹⁾

(1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(3) = B - nCS Max Delay + nADV Min Delay

For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK

For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK

(4) = C - nCS Max Delay + nOE Min Delay

C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(5) = J - Address Max Delay + nCS Min Delay

J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK

(6) = K - nCS Max Delay + nADV Min Delay

K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK

(7) = L - nCS Max Delay + nOE Min Delay

L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(8) G = Cycle2CycleDelay * GPMC_FCLK

(9) = I - nCS Max Delay + nOE Min Delay

I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *

GPMC_FCLK

(10) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK

(11) = E - nCS Max Delay + nWE Min Delay

E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK

Peripheral Information and Timings

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Table 8-17. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR

Flash Interface - Asynchronous Mode (continued)

(see Figure 8-16, Figure 8-17, Figure 8-18, Figure 8-19 for Non-Multiplexed Modes)

(see Figure 8-20, Figure 8-21 for Multiplexed Modes)

OPP100/OPP120/Turb

o/Nitro

NO

.

PARAMETER

UNIT

MIN

MAX

28 t_{d(nCSV-nWEIV)}

29 t_d(nWEV-DV)

30 t_d(DV-nCSV)

37 t_d(ADVV-AIV)

Delay time, GPMC_CS[x] valid to GPMC_WE invalid

F - 0.2⁽¹²⁾F + 2.0⁽¹²⁾

ns

Delay time, GPMC_WE valid to GPMC_D[15:0] data bus valid

Delay time, GPMC_D[15:0] data bus valid to GPMC_CS[x] valid

Delay time, GPMC_ADV_ALE valid to GPMC_D[15:0] address invalid

2.0

J - 0.2⁽⁵⁾

J + 2.0⁽⁵⁾

2.0

Delay time, GPMC_OE_RE valid to GPMC_D[15:0] address/data busses phase

end

38 t_d(nOEV-AIV)

39 t_d(AIV-ADVV)

2.0

ns

Delay time, GPMC_D[15:0] address valid to GPMC_ADV_ALE invalid

(12) = F - nCS Max Delay + nWE Min Delay

F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK

GPMC_FCLK

GPMC_CLK

6

2

GPMC_CS[x]

10

GPMC_A[10:1]

GPMC_BE1

Valid Address

1

11

1

GPMC_BE0_CLE

GPMC_ADV_ALE

4

13

5

14

GPMC_OE

GPMC_D[15:0]

Data In 0

GPMC_WAIT[x]

Figure 8-16. GPMC/Non-Multiplexed NOR Flash - Asynchronous Read - Single Word Timing

178

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GPMC_FCLK

GPMC_CLK

6

2

GPMC_CS[x]

17

10

11

10

11

GPMC_A[10:1]

Address 2

1

Address 1

1

GPMC_BE1

GPMC_BE0_CLE

GPMC_ADV_ALE

11

1

4

13

5

14

GPMC_OE

GPMC_D[15:0]

Data Upper

GPMC_WAIT[x]

Figure 8-17. GPMC/Non-Multiplexed NOR Flash - Asynchronous Read - 32-Bit Access Timing

GPMC_FCLK

GPMC_CLK

22

21

2

GPMC_CS[x]

10

11

GPMC_A[10:1]

Add0

Add1

Add2

Add3

Add4

1

GPMC_BE1

11

GPMC_BE0_CLE

GPMC_ADV_ALE

13

19

14

GPMC_OE

GPMC_D[15:0]

D0

D1

D2

D3

GPMC_WAIT[x]

Figure 8-18. GPMC/Non-Multiplexed Only NOR Flash - Asynchronous Read - Page Mode 4x16-Bit Timing

Peripheral Information and Timings

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GPMC_FCLK

GPMC_CLK

2

GPMC_CS[x]

10

GPMC_A[10:1]

Valid Address

1

11

GPMC_BE1

11

1

GPMC_BE0_CLE

4

13

GPMC_ADV_ALE

28

26

GPMC_WE

30

GPMC_D[15:0]

Data OUT

GPMC_WAIT[x]

Figure 8-19. GPMC/Non-Multiplexed NOR Flash - Asynchronous Write - Single Word Timing

GPMC_FCLK

GPMC_CLK

2

6

GPMC_CS[x]

10

11

Address (MSB)

1

GPMC_A[26:17]

GPMC_BE1

11

1

GPMC_BE0_CLE

13

4

GPMC_ADV_ALE

GPMC_OE

5

14

30

38

GPMC_A[16:1]

GPMC_D[15:0]

Address (LSB)

Data IN

GPMC_WAIT[x]

Figure 8-20. GPMC/Multiplexed NOR Flash - Asynchronous Read - Single Word Timing

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GPMC_CLK

GPMC_CS[x]

2

10

11

Address (MSB)

1

GPMC_A[26:17]

GPMC_BE1

11

1

GPMC_BE0_CLE

13

4

GPMC_ADV_ALE

GPMC_WE

28

26

30

Valid Address (LSB)

29

GPMC_A[16:1]

GPMC_D[15:0]

Data OUT

GPMC_WAIT[x]

Figure 8-21. GPMC/Multiplexed NOR Flash - Asynchronous Write - Single Word Timing

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8.7.2.3 GPMC/NAND Flash and ELM Interface Timing

Table 8-18. Timing Requirements for GPMC/NAND Flash Interface

(see Figure 8-24)

NO.

OPP100/OPP120/Turbo/Nitr

o

UNIT

MIN

MAX

13 t_acc(DAT)

Data maximum access time (GPMC_FCLK cycles)

J⁽¹⁾

cycles

(1) J = AccessTime * (TimeParaGranularity + 1)

Table 8-19. Switching Characteristics Over Recommended Operating Conditions for GPMC/NAND Flash

Interface

(see Figure 8-22, Figure 8-23, Figure 8-24, Figure 8-25)

OPP100/OPP120/Turbo/Nitr

o

NO.

PARAMETER

UNIT

MIN

MAX

A⁽¹⁾

1

2

3

4

5

6

7

8

9

t_w(nWEV)

Pulse duration, GPMC_WE valid time

ns

t_d(nCSV-nWEV)

t_d(CLEH-nWEV)

t_d(nWEV-DV)

Delay time, GPMC_CS[X] valid to GPMC_WE valid

Delay time, GPMC_BE0_CLE high to GPMC_WE valid

Delay time, GPMC_D[15:0] valid to GPMC_WE valid

Delay time, GPMC_WE invalid to GPMC_AD[15:0] invalid

Delay time, GPMC_WE invalid to GPMC_BE0_CLE invalid

Delay time, GPMC_WE invalid to GPMC_CS[X] invalid

Delay time, GPMC_ADV_ALE High to GPMC_WE valid

Delay time, GPMC_WE invalid to GPMC_ADV_ALE invalid

Cycle time, write cycle time

B - 0.2⁽²⁾

C - 0.2⁽³⁾

D - 0.2⁽⁴⁾

E - 0.2⁽⁵⁾

F - 0.2⁽⁶⁾

G - 0.2⁽⁷⁾

C - 0.2⁽³⁾

F - 0.2⁽⁶⁾

B + 2.0⁽²⁾

C + 2.0⁽³⁾

D + 2.0⁽⁴⁾

E + 2.0⁽⁵⁾

F + 2.0⁽⁶⁾

G + 2.0⁽⁷⁾

C + 2.0⁽³⁾

F + 2.0⁽⁶⁾

H⁽⁸⁾

I + 2.0⁽⁹⁾

K⁽¹⁰⁾

L⁽¹¹⁾

M + 2.0⁽¹²⁾

t_d(nWEIV-DIV)

t_{d(nWEIV-CLEIV)}

t_{d(nWEIV-nCSIV)}

t_d(ALEH-nWEV)

t_{d(nWEIV-ALEIV)}

10 t_c(nWE)

11 t_d(nCSV-nOEV)

12 t_w(nOEV)

Delay time, GPMC_CS[X] valid to GPMC_OE_RE valid

Pulse duration, GPMC_OE_RE valid time

I - 0.2⁽⁹⁾

13 t_c(nOE)

Cycle time, read cycle time

14 t_{d(nOEIV-nCSIV)}

Delay time, GPMC_OE_RE invalid to GPMC_CS[X] invalid

M - 0.2⁽¹²⁾

(1) A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(2) = B + nWE Min Delay - nCS Max Delay

B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(3) = C + nWE Min Delay - CLE Max Delay

C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK

(4) = D + nWE Min Delay - Data Max Delay

D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK

(5) =E + Data Min Delay - nWE Max Delay

E = ((WrCycleTime - WEOffTime) * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK

(6) = F + CLE Min Delay - nWE Max Delay

F = ((ADVWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay )) * GPMC_FCLK

(7) =G + nCS Min Delay - nWE Max Delay

G = ((CSWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay )) * GPMC_FCLK

(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(9) = I + nOE Min Delay - nCS Max Delay

I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK

(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(12) =M + nCS Min Delay - nOE Max Delay

M = ((CSRdOffTime - OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ))* GPMC_FCLK

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GPMC_FCLK

2

3

7

6

GPMC_CS[x]

GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE

1

GPMC_WE

4

5

GPMC_A[16:1]

GPMC_D[15:0]

Command

Figure 8-22. GPMC/NAND Flash - Command Latch Cycle Timing

GPMC_FCLK

GPMC_CS[x]

2

7

GPMC_BE0_CLE

8

9

GPMC_ADV_ALE

GPMC_OE

10

1

GPMC_WE

5

4

GPMC_A[16:1]

GPMC_D[15:0]

Address

Figure 8-23. GPMC/NAND Flash - Address Latch Cycle Timing

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GPMC_FCLK

13

11

16

GPMC_CS[x]

GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE

15

14

GPMC_A[16:1]

GPMC_D[15:0]

Data

GPMC_WAIT[x]

Figure 8-24. GPMC/NAND Flash - Data Read Cycle Timing

GPMC_FCLK

2

7

GPMC_CS[x]

GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE

10

1

GPMC_WE

4

5

GPMC_A[16:1]

GPMC_D[15:0]

Data

Figure 8-25. GPMC/NAND Flash - Data Write Cycle Timing

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8.8 High-Definition Multimedia Interface (HDMI)

The device includes an HDMI 1.3a-compliant transmitter for digital video and audio data to display

devices. The HDMI interface consists of a digital HDMI transmitter core with TMDS encoder, a core

wrapper with interface logic and control registers, and a transmit PHY, with the following features:

•

Hot-plug detection

Consumer electronics control (CEC) messages

DVI 1.0 compliant (only RGB pixel format)

CEA 861-D and VESA DMT formats

Supports up to 165-MHz pixel clock

–

1920 x 1080p @75 Hz with 8-bit/component color depth

1600 x 1200 @60 Hz with 8-bit/component color depth

•

Support for deep-color mode:

–

10-bit/component color depth up to 1080p @60 Hz (Max pixel clock = 148.5 MHz)

12-bit/component color depth up to 720p/1080i @60 Hz (Max pixel clock = 123.75 MHz)

•

TMDS clock to the HDMI-PHY is up to 185.625 MHz

Maximum supported pixel clock:

–

165 MHz for 8-bit color depth

148.5 MHz for 10-bit color depth

123.75 MHz for 12-bit color depth

•

Uncompressed multichannel (up to eight channels) audio (L-PCM) support

Master I2C interface for display data channel (DDC) connection

Options available to support HDCP encryption engine for transmitting protected audio and video (for

information, contact your local TI sales representative).

For more details on the HDMI, see the High-Definition Multimedia Interface (HDMI) chapter in the device-

specific Technical Reference Manual.

8.8.1 HDMI Design Guidelines

This section provides PCB design and layout guidelines for the HDMI interface. The design rules constrain

PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system

design work has been done to ensure the HDMI interface requirements are met.

8.8.1.1 HDMI Interface Schematic

The HDMI bus is separated into three main sections:

1. Transition Minimized Differential Signaling (TMDS) high-speed digital video interface

2. Display Data Channel (I2C bus for configuration and status exchange between two devices)

3. Consumer Electronics Control (optional) for remote control of connected devices.

The DDC and CEC are low-speed interfaces, so nothing special is required for PCB layout of these

signals. Their connection is shown in Figure 8-26, HDMI Interface High-Level Schematic.

The TMDS channels are high-speed differential pairs and, therefore, require the most care in layout.

Specifications for TMDS layout are below.

Figure 8-26 shows the HDMI interface schematic. The specific pin numbers can be obtained from , HDMI

Terminal Functions.

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DEVICE

HDMI CONNECTOR

TD0

HDMI_DP0

HDMI_DN0

TD0+

Shld

TD0-

TD1

HDMI_DP1

HDMI_DN1

TD1+

Shld

TD1-

TD2

Shld

HDMI_DP2

HDMI_DN2

TPD12S521

or other

TD2+

TD2-

ESD Protection

w/I2C-Level

Translation

HDMI_CLKP

HDMI_CLKN

TCLK

Shld

TCLK+

HDMI_CEC

3.3 V

CEC

DDC

Gnd

Rpullup^(A)

HDMI_SDA

HDMI_SCL

SDA

SCL

HDMI_HPDET

HPDET

A. 5K-10K Ω pullup resistors are required if not integrated in the ESD protection chip.

Figure 8-26. HDMI Interface High-Level Schematic

8.8.1.2 TMDS Routing

The TMDS signals are high-speed differential pairs. Care must be taken in the PCB layout of these signals

to ensure good signal integrity.

The TMDS differential signal traces must be routed to achieve 100 Ω (±10%) differential impedance and

60 Ω (±10%) single-ended impedance. Single-ended impedance control is required because differential

signals are extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes

important.

These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric

material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as

close to 60 Ω impedance traces as possible. For best accuracy, work with your PCB fabricator to ensure

this impedance is met.

In general, closely coupled differential signal traces are not an advantage on PCBs. When differential

signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing

variations affect impedance dramatically, so tight impedance control can be more problematic to maintain

in production.

Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing

make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it

is easier to maintain an accurate impedance over the length of the signal. The wider traces also show

reduced skin effect and, therefore, often result in better signal integrity.

Table 8-20 shows the routing specifications for the TMDS signals.

Table 8-20. TMDS Routing Specifications

PARAMETER

Processor-to-HDMI header trace length

MIN

TYP

MAX

7000

0

UNIT

Mils

Stubs

Ω

Number of stubs allowed on TMDS traces

TX/RX pair differential impedance

TX/RX single ended impedance

90

54

100

60

110

66

Ω

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Table 8-20. TMDS Routing Specifications (continued)

PARAMETER

MIN

TYP

MAX

UNIT

Number of vias on each TMDS trace

2

Vias⁽¹⁾

TMDS differential pair to any other trace spacing

2*DS⁽²⁾

(1) Vias must be used in pairs with their distance minimized.

(2) DS = differential spacing of the HDMI traces.

8.8.1.3 DDC Signals

As shown in Figure 8-26, HDMI Interface High-Level Schematic, the DDC connects just like a standard

I2C bus. As such, resistor pullups must be used to pull up the open drain buffer signals unless they are

integrated into the ESD protection chip used. If used, these pullup resistors should be connected to a 3.3-

V supply.

8.8.1.4 HDMI ESD Protection Device (Required)

Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built

into the processor's outputs. Therefore, this HDMI interface requires the use of an ESD protection chip to

provide adequate ESD protection and to translate I2C voltage levels from the 3.3 V supplied by the device

to the 5 volts required by the HDMI specification.

When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to

minimize signal degradation. In no case should the ESD protection circuit capacitance be more than 5 pF.

TI manufactures devices that provide ESD protection for HDMI signals such as the TPD12S521. For more

information see the www.ti.com website.

8.8.1.5 PCB Stackup Specifications

Table 8-21 shows the stackup and feature sizes required for HDMI.

Table 8-21. HDMI PCB Stackup Specifications

PARAMETER

MIN

TYP

6

MAX

UNIT

Layers

Cuts

PCB routing/plane layers

Signal routing layers

4

2

-

3

Number of ground plane cuts allowed within HDMI routing region

Number of layers between HDMI routing region and reference ground plane

PCB trace width

-

0

-

Layers

Mils

-

4

PCB BGA escape via pad size

-

20

10

0.4

-

Mils

PCB BGA escape via hole size

Processor device BGA pad size⁽¹⁾⁽²⁾

-

Mils

mm

(1) Non-solder mask defined pad.

(2) Per IPC-7351A BGA pad size guideline.

8.8.1.6 Grounding

Each TMDS channel has its own shield pin which should be grounded to provide a return current path for

the TMDS signal.

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8.9 High-Definition Video Processing Subsystem (HDVPSS)

The device High-Definition Video Processing Subsystem (HDVPSS) provides a video input interface for

external imaging peripherals (for example, image sensors, video decoders, and more) and a video output

interface for display devices, such as analog SDTV and HDTV displays, digital HDTV displays, digital LCD

panels, and more. It includes HD and SD video encoders and an HDMI transmitter interface.

The device HDVPSS features include:

•

Two display processing pipelines with de-interlacing, scaling, alpha blending, chroma keying, color

space conversion, flicker filtering, and pixel format conversion.

•

HD/SD compositor features for PIP support.

Format conversions (up to 1080p 60 Hz) include scan format conversion, scan rate conversion, aspect-

ratio conversion, and frame size conversion.

•

Supports additional video processing capabilities by using the subsystem's memory-to-memory feature.

Two parallel video processing pipelines support HD (up to 1080p60) and SD (NTSC/PAL)

simultaneous outputs.

–

HD analog component output with OSD and embedded timing codes (BT.1120)

•

3-channel HD-DAC with 10-bit resolution.

External HSYNC and VSYNC signals.

SD analog output with OSD with embedded timing codes (BT.656)

•

Composite output

1-channel SD-DAC with 10-bit resolution

Options available to support MacroVision and CGMS-A (contact local TI Sales rep for

information).

–

Digital HDMI 1.3a-compliant transmitter (for details, see Section 8.8, High-Definition Multimedia

Interface (HDMI)).

–

One digital video output supporting up to 30-bits @ 165 MHz

One digital video output supporting up to 24-bits @ 165 MHz

Supports clock inversion for VOUT[0] and VOUT[1] clock signals.

•

Two independently configurable external video input capture ports (up to 165 MHz).

–

16/24-bit HD digital video input or dual clock independent 8-bit SD inputs on each capture port.

8/16/24-bit digital video input

8-bit digital video input

Embedded sync and external sync modes are supported for all input configurations (VIN1 Port B

supports embedded sync only).

–

De-multiplexing of both pixel-to-pixel and line-to-line multiplexed streams, effectively supporting up

to 16 simultaneous SD inputs with a glueless interface to an external multiplexer such as the

TVP5158.

Additional features include: programmable color space conversion, scaler and chroma

downsampler, ancillary VANC/VBI data capture (decoded by software).

•

Graphics features:

–

Three independently-generated graphics layers.

Each supports full-screen resolution graphics in HD, SD or both.

Up/down scaler optimized for graphics.

Global and pixel-level alpha blending supported.

For more detailed information on specific features and registers, see the High Definition Video Processing

Subsystem chapter in the device-specific Technical Reference Manual.

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8.9.1 HDVPSS Electrical Data/Timing

Table 8-22. Timing Requirements for HDVPSS Input

(see Figure 8-27 and Figure 8-28)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

VIN[X]A_CLK

1

2

3

7

t_c(CLK)

Cycle time, VIN[x]A_CLK

6.06⁽¹⁾

2.73

ns

t_w(CLKH)

Pulse duration, VIN[x]A_CLK high (45% of t_c)

Pulse duration, VIN[x]A_CLK low (45% of t_c)

Transition time, VIN[x]A_CLK (10%-90%)

t_w(CLKH)

2.73

t_t(CLK)

2.64

t_su(DE-CLK)

t_{su(VSYNC-CLK)}

t_su(FLD-CLK)

t_{su(HSYNC-CLK)}

t_su(D-CLK)

Input setup time, control valid to VIN[x]A_CLK high/low

Input setup time, data valid to VIN[x]A_CLK high/low

Input hold time, control valid from VIN[x]A_CLK high/low

3.11

-0.5

4

5

ns

t_h(CLK-DE)

t_h(CLK-VSYNC)

t_h(CLK-FLD)

t_h(CLK-HSYNC)

t_h(CLK-D)

Input hold time, data valid from VIN[x]A_CLK high/low

VIN[x]B_CLK

1

2

3

7

t_c(CLK)

Cycle time, VIN[x]B_CLK

6.06⁽¹⁾

2.73

ns

t_w(CLKH)

Pulse duration, VIN[x]B_CLK high (45% of t_c)

Pulse duration, VIN[x]B_CLK low (45% of t_c)

Transition time, VIN[x]B_CLK (10%-90%)

t_w(CLKH)

2.73

t_t(CLK)

2.64

t_su(DE-CLK)

t_{su(VSYNC-CLK)}

t_su(FLD-CLK)

t_{su(HSYNC-CLK)}

t_su(D-CLK)

Input setup time, control valid to VIN[x]B_CLK high/low

Input setup time, data valid to VIN[x]B_CLK high/low

Input hold time, control valid from VIN[x]B_CLK high/low

Input hold time, data valid from VIN[x]B_CLK high/low

3.11

-0.5

4

5

ns

t_h(CLK-DE)

t_h(CLK-VSYNC)

t_h(CLK-FLD)

t_h(CLK-HSYNC)

t_h(CLK-D)

(1) For maximum frequency of 165 MHz.

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Table 8-23. Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output

(see Figure 8-27 and Figure 8-29)

OPP100/OPP120/Turbo/

Nitro

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

7

t_c(CLK)

Cycle time, VOUT[x]_CLK

6.06⁽¹⁾

2.73

ns

t_w(CLKH)

Pulse duration, VOUT[x]_CLK high (45% of t_c)

Pulse duration, VOUT[x]_CLK low (45% of t_c)

Transition time, VOUT[x]_CLK (10%-90%)

t_w(CLKL)

2.73

t_t(CLK)

2.64

4.18

t_d(CLK-AVID)

t_d(CLK-FLD)

t_d(CLK-VSYNC)

t_d(CLK-HSYNC)

t_d(CLK-RCR)

t_d(CLK-GYYC)

t_d(CLK-BCBC)

t_d(CLK-YYC)

t_d(CLK-C)

Delay time, VOUT[x]_CLK low (falling) to control valid, positive

clock edge

1.64

ns

Delay time, VOUT[0]_CLK low (falling) to data valid, positive clock

edge

4.18

Delay time, VOUT[1]_CLK low (falling) to data valid, positive clock

edge

6

t_d(CLK-AVID)

t_d(CLK-FLD)

t_d(CLK-VSYNC)

t_d(CLK-HSYNC)

t_d(CLK-RCR)

t_d(CLK-GYYC)

t_d(CLK-BCBC)

t_d(CLK-YYC)

t_d(CLK-C)

Delay time, VOUT[x]_CLK low (falling) to control valid, negative

clock edge

-1.64

Delay time, VOUT[0]_CLK low (falling) to data valid, negative clock

edge

Delay time, VOUT[1]_CLK low (falling) to data valid, negative clock

edge

(1) For maximum frequency of 165 MHz.

3

2

1

VIN[x]A_CLK/

VIN[x]B_CLK/

VOUT[x]_CLK

7

1

7

Figure 8-27. HDVPSS Clock Timing

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VIN[x]A_CLK/

VIN[x]B_CLK

(positive-edge clocking)

VIN[x]A_CLK/

VIN[x]B_CLK

(negative-edge clocking)

5

4

VIN[x]A/

VIN[x]B

Figure 8-28. HDVPSS Input Timing

VOUT[x]_CLK

VOUT[x]

6

Figure 8-29. HDVPSS Output Timing

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8.9.2 Video SD-DAC Guidelines and Electrical Data/Timing

The device's analog video SD-DAC output can be operated in one of two modes: Normal mode and

TVOUT Bypass mode. In Normal mode, the device’s internal video amplifier is used. In TVOUT Bypass

mode, the internal video amplifier is bypassed and an external amplifier is required.

Figure 8-30 shows a typical circuit that permits connecting the analog video output from the device to

standard 75-Ω impedance video systems in Normal mode. Figure 8-31 shows a typical circuit that permits

connecting the analog video output from the device to standard 75-Ω impedance video systems in TVOUT

Bypass mode.

Reconstruction

Filter^(A)

~9.5 MHz

TV_OUTx

(B)

C_AC

R_OUT

TV_VFBx

A. Reconstruction Filter (optional)

B. AC coupling capacitor (optional)

Figure 8-30. TV Output (Normal Mode)

75 Ω

Reconstruction

Filter^(A)

~9.5 MHz

Amplifier

3.7 V/V

TV_VFBx

(B)

C_AC

R_LOAD

A. Reconstruction Filter (optional). Note: An amplifier with an integrated reconstruction filter can alternatively be used

instead of a discrete reconstruction filter.

B. AC coupling capacitor (optional)

Figure 8-31. TV Output (TVOUT Bypass Mode)

During board design, the onboard traces and parasitics must be matched for the channel. The video SD-

DAC output pin (TV_OUT0/TV_VFB0) are very high-frequency analog signals and must be routed with

extreme care. As a result, the paths of these signals must be as short as possible, and as isolated as

possible from other interfering signals. In TVOUT Bypass mode, the load resistor and amplifier/buffer

should be placed as close as possible to the TV_VFB0 pin. Other layout guidelines include:

•

Take special care to bypass the VDDA_VDAC_1P8 power supply pin with a capacitor. For more

information, see Section 7.2.9, Power-Supply Decoupling.

•

In TVOUT Bypass mode, place the R_LOADresistor as close as possible to the Reconstruction Filter

and Amplifier. In addition, place the 75-Ω resistor as close as possible (< 0.5 ") to the Amplifier/buffer

output pin. To maintain a high-quality video signal, the onboard traces after the 75-Ω resistor should

have a characteristic impedance of 75 Ω (± 20%).

•

In Normal mode, TV_VFB0 is the most sensitive pin in the TV out system. The R_OUTresistor should

be placed as close as possible to the device pin. To maintain a high-quality video signal, the onboard

traces leading to the TV_OUT0 pin should have a characteristic impedance of 75 Ω (± 20%) starting

from the closest possible place to the device pin output.

•

Minimize input trace lengths to the device to reduce parasitic capacitance.

Include solid ground return paths.

For additional Video SD-DAC Design guidelines, see the High Definition Video Processing Subsystem

chapter in the device-specific Technical Reference Manual.

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Table 8-24. Static and Dynamic SD-DAC Specifications

VDAC STATIC SPECIFICATIONS

PARAMETER

Reference Current Setting Resistor Normal Mode

(R_SET

TEST CONDITIONS

MIN

4653

9900

2673

TYP

4700

10000

2700

MAX

4747

10100

2727

UNIT

Ω

)

TVOUT Bypass Mode

Ω

Output resistor between TV_OUT0 Normal Mode

Ω

and TV_VFB0 pins (R_OUT

)

TVOUT Bypass Mode

Normal Mode

N/A

Load Resistor (R_LOAD

)

75-Ω Inside the Display

TVOUT Bypass Mode

Normal Mode

1485

220

1500

1515

Ω

AC-Coupling Capacitor (Optional)

[C_AC

uF

]

TVOUT Bypass Mode

Normal Mode

See External Amplifier Specification

Total Capacitance from TV_OUT0

to VSSA_VDAC_1P8

300

pF

TVOUT Bypass Mode

N/A

Resolution

10

Bits

LSB

V

Integral Non-Linearity (INL), Best

Fit

Normal Mode

-4

-1

4

TVOUT Bypass Mode

Normal Mode

1

Differential Non-Linearity (DNL)

-2.5

-1

2.5

1

TVOUT Bypass Mode

Normal Mode (R_LOAD= 75 Ω)

Full-Scale Output Voltage

1.3

TVOUT Bypass Mode (R_LOAD

1.5 kΩ)

=

0.7

V

Full-Scale Output Current

Normal Mode

N/A

-10

TVOUT Bypass Mode

470

uA

%FS

Ω

Gain Error

Normal Mode (Composite) and

TVOUT Bypass Mode

10

Output Impedance

Looking into TV_OUT0 nodes

75

VDAC DYNAMIC SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

54

6

MAX

UNIT

MHz

Output Update Rate (F_CLK

)

60

Signal Bandwidth

3 dB

Spurious-Free Dynamic Range

(SFDR) within bandwidth

F_CLK= 54 MHz, F_OUT= 1 MHz

50

54

6

dBc

dB

Signal-to-Noise Ration (SNR)

F_CLK= 54 MHz, F_OUT= 1 MHz

Normal Mode, 100 mVpp @ 6

MHz on VDDA_VDAC_1P8

Power Supply Rejection (PSR)

dB

TVOUT Bypass Mode, 100

mVpp @ 6 MHz on

20

VDDA_VDAC_1P8

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8.9.3 Video HD-DAC Guidelines and Electrical Data/Timing

The device's analog video HD-DAC outputs are designed to drive a 165-Ω load. An external video

buffer/amplifier is required to provide additional gain (4.5V/V) and to drive the actual video outputs. 75-Ω

back termination resistors should be connected in series with the video buffer output pins. For component

video applications, a reconstruction filter should precede the video buffer. One solution is to use a video

buffer/amplifier with integrated reconstruction filter, such as the Texas Instruments THS7360, which

provides a complete solution for the typical output circuit, shown in Figure 8-32.

75 W

Amplifier

4.5 V/V

Reconstruction

Filter

HDDAC_x

SD:

ED:

HD:

9.5 MHz

18 MHz

36 MHz

R_LOAD

1080p: 72 MHz

Figure 8-32. Typical Output Circuits for Analog Video from DACs

During board design, the onboard traces and parasitics must be matched for the channel. The video HD-

DAC output pins (HDDAC_x) are very high-frequency analog signals and must be routed with extreme

care. As a result, the path of this signal must be as short as possible, and as isolated as possible from

other interfering signals. Other schematic and layout guidelines include:

•

The correct external video gain (4.5V/V) must always be provided (even when not using the

recommended video buffer). The recommended video buffer is the THS7360.

The load resistor (RLOAD) should be placed as close as possible (< 0.5 in.) to the THS7360 video

buffer input pins.

The 75-Ω series resistors should be placed as close as possible (< 0.5 in.) to the THS7360 video

buffer output pins.

The trace lengths within a video format group should match as close as possible (for example, for

component video outputs, the Y, Pb, and Pr trace lengths should match each other).

The characteristic impedance of the HD-DAC output signal traces should match the HD-DAC load

value (165Ω) as close as possible (±10%). The minimum trace width may limit how closely these

impedances can be matched.

•

The characteristic impedance of the video buffer output signal traces should match the back

termination value (75 Ω) as close as possible (±10%). The minimum trace width may limit how closely

these impedances can be matched.

To provide adequate frequency response on the VGA/YPbPr output, recommend the following:

–

The length of the signal traces from the HD-DAC output pins to the THS7360 video buffer input pins

should be minimized (< 1 in.) to reduce parasitic capacitance (~2 pF per inch).

–

Ensure the THS7360 reconstruction filter is properly programmed for each output format.

Enable 2x up-sampling for 720p/1080i component video outputs.

•

To minimize noise on the VGA/YPbPr output, recommend the following:

–

The HD-DAC power supply pins (VDDA_REF_1P8V, VDDA_HD_1P8V) should be connected to a

low-noise 1.8-V analog supply. Use a dedicated voltage regulator for best noise performance.

The THS7360 power supply pin should be connected to a low-noise 3.3-V analog supply. Use a

dedicated voltage regulator for best noise performance.

Special care should be taken to provide adequate power supply decoupling on all analog supply

pins (for example, ferrite bead and bypass capacitor).

–

Provide a ground guard adjacent to analog video signal traces to minimize noise coupling.

Provide a low impedance path to ground for the shield of the VGA/YPbPr output connector.

Include solid ground return paths.

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•

To provide adequate ESD protection on the VGA/YPbPr output, recommend the following:

–

Provide ESD protection on all output signals (that is, Video, Syncs and DDC I/F).

Minimize the distance from the ESD protection device to the VGA/YPbPr output connector.

Mount all ESD protection devices on the PCB level next to the ground plane to provide the lowest

possible impedance path to ground.

–

Provide a low impedance path to ground for the shield of the VGA/YPbPr output connector.

•

For VGA outputs, recommend the following:

–

3.3 V to 5 V level shifters should be used for the H/V Sync signals.

3.3 V to 5 V bi-directional level shifters should be used for the DDC signals. This is typically

implemented using two N-channel enhancement MOSFETs.

–

Recommend using the TPD7S019 ESD protection device with integrated level shifters for the H/V

Sync and DDC signals.

–

The source impedance of the H/V Sync outputs should be 50 Ω.

The characteristic impedance of the H/V Sync output signal traces should be 50 Ω.

The THS7360 reconstruction filter should be bypassed to provide maximum bandwidth.

The 5-V supply output should be current limited (for example, using a series resistor or resettable

fuse).

For additional video HD-DAC design guidelines, see the High Definition Video Processing Subsystem

chapter in the device-specific Technical Reference Manual.

Table 8-25. HD-DAC Recommended Operating Conditions

MIN

NOM

MAX

5

UNIT

pF

(1)

Output Load Capacitance (C_LOAD

Output Load Resistors (R_LOAD

Full-Scale Current Adjust Resistor (R_{HDDAC_IREF}

)

–1%

–5%

–3%

165

2.67

467

4.5

+1%

+5%

+3%

Ω

)

kΩ

Optional External Voltage Reference (HDDAC_VREF)⁽²⁾

mV

V/V

Required External Amplification (THS7360)

(1) The output load capacitance includes the signal trace parasitic capacitance and the video buffer input capacitance.

(2) An external voltage reference is not required since an internal bandgap reference is provided.

Table 8-26. HD-DAC Specifications

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

10

Bits

DC Accuracy

Integral Non-Linearity (INL), best fit

Differential Non-Linearity (DNL)

2.5

1.0

LSB

Analog Output

Full-Scale Output Current (IFS)

Full-Scale Output Voltage (VFS)

Zero Scale Offset Error (ZSET)

Channel matching

DAC input = 1023

3

494

0.5

mA

mV

LSB

%

–15%

150

+15%

2

Dynamic Specifications

Maximum Output Update Rate (FCLK)

Spurious - Free Dynamic Range (SFDR)

MHz

dB

FCLK = 74.25 MHz,

30-MHz full-scale sine wave

70

60

FCLK = 148.5 MHz,

dB

30-MHz full-scale sine wave

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8.10 Inter-Integrated Circuit (I2C)

The device includes four inter-integrated circuit (I2C) modules which provide an interface to other devices

compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External

components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through

the I2C module. The I2C port does not support CBUS compatible devices.

The I2C port supports the following features:

•

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers)

Noise filter to remove noise 50 ns or less

Seven- and ten-bit device addressing modes

Multimaster transmitter/slave receiver mode

Multimaster receiver/slave transmitter mode

Combined master transmit/receive and receive/transmit modes

Two DMA channels, one interrupt line

Built-in FIFO (32 byte) for buffered read or write.

For more detailed information on the I2C peripheral, see the Inter-Integrated Circuit (I2C) Controller

Module chapter in the device-specific Technical Reference Manual.

8.10.1 I2C Peripheral Register Descriptions

The I2C peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

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8.10.2 I2C Electrical Data/Timing

Table 8-27. Timing Requirements for I2C Input Timings⁽¹⁾

(see Figure 8-33)

OPP100/OPP120/Turbo/Nitro

STANDARD

NO.

FAST MODE

UNIT

MODE

MIN MAX

10

MIN MAX

1

2

t_c(SCL)

Cycle time, SCL

2.5

µs

Setup time, SCL high before SDA low (for a repeated START

condition)

t_{su(SCLH-SDAL)}

4.7

4

0.6

Hold time, SCL low after SDA low (for a START and a

repeated START condition)

3

t_h(SDAL-SCLL)

0.6

µs

4

5

6

7

t_w(SCLL)

Pulse duration, SCL low

4.7

1.3

0.6

100⁽²⁾

µs

ns

µs

t_w(SCLH)

Pulse duration, SCL high

4

t_{su(SDAV-SCLH)}

t_h(SCLL-SDAV)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0⁽³⁾3.45⁽⁴⁾

0⁽³⁾0.9⁽⁴⁾

Pulse duration, SDA high between STOP and START

conditions

8

t_w(SDAH)

4.7

1.3

µs

(5)

9

t_r(SDA)

Rise time, SDA

1000 20 + 0.1C_b

300

ns

µs

ns

pF

(5)

10

11

12

13

14

15

t_r(SCL)

Rise time, SCL

1000 20 + 0.1C_b

t_f(SDA)

Fall time, SDA

300 20 + 0.1C_b

t_f(SCL)

Fall time, SCL

t_{su(SCLH-SDAH)}

t_w(SP)

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

4

0.6

0

50

(5)

C_b

400

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be

met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line t_rmax + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns

(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(4) The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.

(5) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

9

11

I2C[x]_SDA

I2C[x]_SCL

6

8

14

4

13

5

10

1

12

3

7

2

3

Stop

Start

Repeated

Start

Stop

Figure 8-33. I2C Receive Timing

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Table 8-28. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings

(see Figure 8-34)

OPP100/OPP120/Turbo/Nitro

STANDARD

NO.

PARAMETER

FAST MODE

UNIT

MODE

MIN MAX

MIN

MAX

16

17

t_c(SCL)

Cycle time, SCL

10

2.5

µs

Setup time, SCL high before SDA low (for a repeated START

condition)

t_{su(SCLH-SDAL)}

4.7

0.6

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

18

t_h(SDAL-SCLL)

4

µs

19

20

21

22

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

µs

ns

µs

t_w(SCLH)

Pulse duration, SCL high

t_{su(SDAV-SCLH)}

t_h(SCLL-SDAV)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low (for I2C bus devices)

250

0

3.45

0.9

Pulse duration, SDA high between STOP and START

conditions

23

24

25

26

27

t_w(SDAH)

t_r(SDA)

t_r(SCL)

t_f(SDA)

t_f(SCL)

4.7

1.3

µs

ns

20 + 0.1C_b

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

1000

300

(1)

20 + 0.1C_b

(1)

20 + 0.1C_b

(1)

20 + 0.1C_b

300

(1)

28

29

t_{su(SCLH-SDAH)}

C_p

Setup time, SCL high before SDA high (for STOP condition)

Capacitance for each I2C pin

4

0.6

µs

pF

10

(1) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

26

24

I2C[x]_SDA

21

23

19

28

20

25

I2C[x]_SCL

27

16

18

22

17

18

Stop

Start

Repeated

Start

Stop

Figure 8-34. I2C Transmit Timing

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8.11 Imaging Subsystem (ISS)

The device Imaging Subsystem captures and processes pixel data from external image and video inputs.

The inputs can be connected to the Image Processing block through the Parallel Camera Interface (CAM).

In addition, a Timing control module provides flash strobe and mechanical shutter interfaces. The features

of each component of the ISS are described below.

•

Parallel Camera (CAM) interface features:

–

Input format

•

Bayer pattern Raw (up to 16bit) or YCbCr 422 (8-bit or 16-bit) data.

ITU-R BT.656/1120 standard format

–

Generates HD/VD timing signals and field ID to an external timing generator, or can synchronize to

the external timing generator.

Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware

supports for higher number of fields, typically 3-, 4-, and 5-field sensors.

•

CSI2 Serial Connection features:

–

Supports up to 1Gb/s data-rate per lane for 1, 2, and 3 Data-lane configurations, and up to

824Mbps per lane for a 4 Data-lane configuration

–

Supports up to four data configurable links in addition to the clock signaling

Data merger for 2-, 3-, or 4-data lane configurations

1-D and 2-D addressing mode

Supports all primary and secondary MIPI-defined formats (RGB, RAW, YUV, and more)

DPCM decompression

Image cropping and A-Law/DPCM compression

•

Image Sensor Interface (ISIF) features:

–

Support for up to 32K pixels (image size) in both the horizontal and vertical direction

Color space conversion for non-Bayer pattern Raw data

Digital black clamping with Horizontal/Vertical offset drift compensation

Vertical Line defect correction based on a lookup table

Color-dependent gain control and black level offset control

Ability to control output to the DDR2/DDR3/DDR3L via an external write enable signal

Down sampling via programmable culling patterns

A-law/DPCM compression

Generating 16-, 12- or 8-bit output to memory

•

Two independent Resizers

–

Providing two different sizes of outputs simultaneously on one input

Maximum line width is 5376 and 2336, respectively

YUV422 to YUV420 conversion

Data output format: RGB565, ARGB888, YUV422 co sited and YUV4:2:0 planar

Resizer Ratio: x1/4096 ~ x20

Input from memory

Timing control module features:

–

STROBE signal for flash pre-strobe and flash strobe

SHUTTER signal for mechanical shutter control

Global reset control

For more detailed information on the ISS, see the ISS Overview section, the ISS Interfaces section, and

the ISS ISP section of the device-specific Technical Reference Manual.

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8.11.1 ISS Peripheral Register Description

The ISS peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

8.11.2 ISSCAM Electrical Data/Timing

Table 8-29. Timing Requirements for ISSCAM⁽¹⁾(see Figure 8-35)

OPP100/OPP120/Turb

N

O.

o/Nitro

MIN NOM

6.17

UNIT

MAX

1

2

3

4

t_c(PCLK)

t_w(PCLKH)

t_w(PCLKL)

t_t(PCLK)

Cycle time, PCLK

ns

Pulse duration, PCLK high

Pulse duration, PCLK low

Transition time, PCLK

2.78

2.64 ns

t_su(DATA-

PCLK)

3.11

ns

t_su(DE-PCLK)

3.11

ns

5

t_su(VS-PCLK)Input setup time, Data/Control valid before PCLK high/low

t_su(HS-PCLK)

t_su(FLD-

PCLK)

3.11

-0.5

0.0

ns

≤ 148.5 MHz clock rate

t_h(PCLK-

DATA)

Input hold time, Data valid after PCLK high/low

> 148.5 MHz and

≤ 162 MHz clock rate

t_h(PCLK-DE)

-0.5

ns

6

t_h(PCLK-VS)

Input hold time, Control valid after PCLK high/low

t_h(PCLK-HS)

t_h(PCLK-FLD)

(1) H = period of baud rate, 1/programmed baud rate.

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Table 8-30. Switching Characteristics Over Recommended Operating Conditions for ISSCAM (see

Figure 8-35)

OPP100/OPP120/Turbo/Nitr

o

NO.

PARAMETER

UNIT

MIN

1.64

MAX

14.68

15 t_d(PCLK-FLD)

16 t_d(PCLK-VS)

Delay time, PCLK rising/falling clock edge to Control valid

ns

17 t_d(PCLK-HS)

18 t_{d(PCLK-STROBE)}

19 t_{d(PCLK-SHUTTER)}

PCLK

(negative edge clocking)

4

1

3

PCLK

(positive edge clocking)

2

4

Data/Control input

Data/Control output

5

6

7

Figure 8-35. ISSCAM Timings

8.11.3 CSI2 PCB Layout Specifications

The following PCB guidelines for CSI2 working at 1 Gbps (up to 3 data lanes), 824 Mbps (up to 4 data

lanes), and 800 Mbps (up to 4 data lanes) are based on a three-step design and validation methodology.

For the design of the PCB differential lines, PCB designers need to keep in mind the requirements of Step

1 and Step 2: the characteristic impedance must be 50 Ω, the total length must be smaller than 100 mm,

and the length mismatch requirements must be satisfied.

After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D

Maxwell Equation Solver, such as High-Frequency Structure Simulator (HFSS) or equivalent, and

compared to the frequency-domain specification as outlined in Step 3 of the design methodology. If the

PCB lines satisfy the frequency-domain specification, the design is done. Otherwise, the design needs to

be improved.

8.11.3.1 Step 1: General Guidelines

The general guidelines for the PCB differential lines of CSI2 are given as:

•

Single-ended Z0 = 50 Ω

Total conductor length on the board < 100 mm

In this step, the general rule of thumb for the space S = 2 × W is not designated. Although the S = 2 × W

rule is a good rule of thumb, it is not always the best solution. The electrical performance will be checked

with the frequency-domain specification in Step 3. Even if the design does not follow the S = 2 × W rule,

the differential lines are okay if the lines satisfy the frequency-domain specification in Step 3.

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8.11.3.2 Step 2: Length Mismatch Guidelines

8.11.3.2.1 CSI2 at 1.0 Gbps

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The guidelines of the length mismatch for CSI2 at 1.0 Gbps are presented in Table 8-31. The intralane

length mismatch must be less than 0.5 mm, and the interlane length mismatch must be less than 1.5 mm.

Table 8-31. Length Mismatch Guidelines for CSI2 at 1.0 Gbps

PARAMETER

TYPICAL VALUE

UNIT

Mbps

ps

Operating speed

1000

3

UI (bit time)

Intralane skew (UI / 300)

Length between N and P traces

Interlane skew (UI / 100)

Length between pairs

ps

0.5

10

mm

ps

1.5

mm

8.11.3.2.2 CSI2 at 824 Mbps

The guidelines of the length mismatch for CSI2 at 824 Mbps are presented in Table 8-32. The intralane

length mismatch must be less than 0.6 mm, and the interlane length mismatch must be less than 1.8 mm.

Table 8-32. Length Mismatch Guidelines for CSI2 at 824 Mbps

PARAMETER

TYPICAL VALUE

UNIT

Mbps

ps

Operating speed

824

1213

4

UI (bit time)

Intralane skew (UI / 300)

Length between N and P traces

Interlane skew (UI / 100)

Length between pairs

ps

0.6

12

mm

ps

1.8

mm

8.11.3.2.3 CSI2 at 800 Mbps

The guidelines of the length mismatch for CSI2 at 800 Mbps are presented in Table 8-33. The intralane

length mismatch must be less than 0.6 mm, and the interlane length mismatch must be less than 1.8 mm.

Table 8-33. Length Mismatch Guidelines for CSI2 at 800 Mbps

PARAMETER

TYPICAL VALUE

UNIT

Mbps

ps

Operating speed

800

1250

4

UI (bit time)

Intralane skew (UI / 300)

Length between N and P traces

Interlane skew (UI / 100)

Length between pairs

ps

0.6

12

mm

ps

1.8

mm

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8.11.3.3 Step 3: Frequency-Domain Specification Guidelines

The PCB differential lines should be drawn in order to satisfy the Step 1 and Step 2 requirements.

However, although the PCB designer may draw the lines carefully, the lines can have poor electrical

performance due to many reasons.

Vertical connections such as vias and non-uniform line connections can degrade the electrical

performance of the differential lines. The ground design around the lines can also affect the electrical

performance. To ensure that the differential lines are well designed, the frequency-domain behavior must

be compared to the frequency-domain specification.

1. Intralane frequency-domain specification

–

Differential-mode characteristics

Sdd12, Sdd11/Sdd22

Common-mode characteristics

Scc11/Scc22

Mode-conversion characteristics

Scd11, Scd12, Scd21, Scd22, Sdc11, Sdc12, Sdc21, Sdc22

2. Interlane frequency-domain specification

–

Differential-mode characteristics

Sdd11/Sdd22

Common-mode characteristics

Scc11/Scc22

–

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8.12 DDR2/DDR3/DDR3L Memory Controller

The device has a dedicated interface to DDR3L, DDR3 and DDR2 SDRAM. It supports DDR2, DDR3 and

DDR3L SDRAM devices with the following features:

•

16-bit or 32-bit data path to external SDRAM memory

Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb devices

One interface with associated DDR2/DDR3/DDR3L PHY

For details on the DDR2, DDR3 and DDR3L Memory Controller, see the DDR2/DDR3/DDR3L Memory

Controller chapter in the device-specific Technical Reference Manual.

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8.12.1 DDR2/3/3L Memory Controller Register Descriptions

The DDR2/3/3L peripheral registers are described in the device-specific Technical Reference Manual.

Each register is documented as an offset from a base address for the peripheral. The base addresses for

all of the peripherals are in the device memory map (see Section 2.10).

8.12.2 DDR2 Routing Specifications

8.12.2.1 Board Designs

TI only supports board designs that follow the guidelines outlined in this document. The switching

characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-34 and

Figure 8-36.

Table 8-34. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory

Controller

-1G

NO.

PARAMETER

UNIT

MIN

MAX

1

t_{c(DDR_CLK)}

Cycle time, DDR_CLK

2.5

8

ns

1

DDR_CLK

Figure 8-36. DDR2 Memory Controller Clock Timing

8.12.2.2 DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need

for a complex timing closure process. For more information regarding the guidelines for using this DDR2

specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application

Report (Literature Number: SPRAAV0).

8.12.2.2.1 DDR2 Interface Schematic

Figure 8-37 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-38 the x16

DDR2 system schematic is identical except that the high-word DDR2 device is deleted.

When not using a DDR2 interface, the proper method of handling the unused pins is to tie off the DQS

pins by pulling the non-inverted DQS pin to the DVDD_DDR[0] supply via a 1k-Ω resistor and pulling the

inverted DQS pin to ground via a 1k-Ω resistor. This needs to be done for each byte not used. Also,

include the 50-Ω pulldown for DDR[0]_VTP. The DVDD_DDR[0] and VREFSSTL_DDR[0] power supply

pins must be connected to their respective power supplies even if DDR[0] is not used. All other DDR

interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are 32-

bits wide, 16-bits wide, or not used.

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DDR2

DQ0

DDR[0]_D[0]

DDR[0]_D[7]

DQ7

LDM

LDQS

DDR[0]_DQM[0]

DDR[0]_DQS[0]

DDR[0]_D[8]

LDQS

DQ8

DDR[0]_D[15]

DDR[0]_DQM[1]

DDR[0]_DQS[1]

DQ15

UDM

UDQS

DDR[0]_DQS[1]

UDQS

ODT

DDR[0]_ODT[0]

T0

DDR2

ODT

DDR[0]_D[16]

DQ0

DDR[0]_D[23]

DDR[0]_DQM[2]

DDR[0]_DQS[2]

DQ7

LDM

LDQS

DDR[0]_DQS[2]

DDR[0]_D[24]

LDQS

DQ8

DDR[0]_D[31]

DDR[0]_DQM[3]

DDR[0]_DQS[3]

DQ15

UDM

UDQS

DDR[0]_BA[0]

T0

BA0

DDR[0]_BA[2]

DDR[0]_A[0]

T0

BA2

A0

BA2

A0

DDR[0]_A[15]

DDR[0]_CS[0]

T0

A15

CS

A15

CS

Vio 1.8^(A)

DDR[0]_CAS

DDR[0]_RAS

CAS

RAS

T0

CAS

RAS

DDR[0]_WE

DDR[0]_CKE

DDR[0]_CLK

WE

CKE

0.1 µF

1 K Ω 1%

CK

DDR[0]_CLK

VREF VREF

VREFSSTL_DDR[0]

VREF

0.1 µF^(B)

1 K Ω 1%

DDR[0]_RST

DDR[0]_VTP

NC

50 Ω ( 2%)

T0

Termination is required. See terminator comments.

A. Vio1.8 is the power supply for the DDR2 memories and the device DDR2 interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.

Figure 8-37. 32-Bit DDR2 High-Level Schematic

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DDR2

DQ0

DDR[0]_D[0]

DDR[0]_D[7]

DQ7

LDM

LDQS

DDR[0]_DQM[0]

DDR[0]_DQS[0]

DDR[0]_D[8]

LDQS

DQ8

DDR[0]_D[15]

DDR[0]_DQM[1]

DDR[0]_DQS[1]

DQ15

UDM

UDQS

DDR[0]_ODT[0]

DDR[0]_D[16]

T0

NC

ODT

Vio 1.8^(A)

DDR[0]_D[23]

NC

DDR[0]_DQM[2]

1 KΩ

DDR[0]_DQS[2]

NC

DDR[0]_D[24]

Vio 1.8^(A)

DDR[0]_D[31]

DDR[0]_DQM[3]

DDR[0]_DQS[3]

NC

1 KΩ

DDR[0]_BA[0]

T0

BA0

DDR[0]_BA[2]

DDR[0]_A[0]

T0

BA2

A0

DDR[0]_A[15]

DDR[0]_CS[0]

T0

A15

CS

DDR[0]_CAS

DDR[0]_RAS

DDR[0]_WE

DDR[0]_CKE

DDR[0]_CLK

CAS

RAS

T0

Vio 1.8^(A)

WE

CKE

CK

1 K Ω 1%

VREF

0.1 µF

DDR[0]_CLK

VREFSSTL_DDR[0]

VREF VREF

0.1 µF^(B)

1 K Ω 1%

DDR[0]_RST

DDR[0]_VTP

NC

50 Ω ( 2%)

T0

Termination is required. See terminator comments.

A. Vio1.8 is the power supply for the DDR2 memories and the device DDR2 interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.

Figure 8-38. 16-Bit DDR2 High-Level Schematic

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8.12.2.2.2 Compatible DDR2 Devices

Table 8-35 shows the parameters of the DDR2 devices that are compatible with this interface. Generally,

the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.

Table 8-35. Compatible DDR2 Devices (Per Interface)

NO.

1

PARAMETER

MIN

MAX

UNIT

DDR2 device speed grade⁽¹⁾

DDR2 device bit width

DDR2 device count⁽²⁾

DDR2-800

2

x16

1

x16

2

Bits

Devices

Balls

3

4

DDR2 device ball count⁽³⁾

84

92

(1) Higher DDR2 speed grades are supported due to inherent DDR2 backwards compatibility.

(2) One DDR2 device is used for a 16-bit DDR2 memory system. Two DDR2 devices are used for a 32-bit DDR2 memory system.

(3) The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball

DDR2 devices are the same.

8.12.2.2.3 PCB Stackup

The minimum stackup required for routing the device is a six-layer stackup as shown in Table 8-36.

Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the size

of the PCB footprint.

Table 8-36. Minimum PCB Stackup

LAYER

TYPE

Signal

Plane

Signal

Plane

Signal

DESCRIPTION

Top routing mostly horizontal

Ground

1

2

3

4

5

6

Power

Internal routing

Ground

Bottom routing mostly vertical

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Complete stackup specifications are provided in Table 8-37.

Table 8-37. PCB Stackup Specifications

NO.

1

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing/plane layers

Signal routing layers

6

3

2

3

Full ground layers under DDR2 routing region

Number of ground plane cuts allowed within DDR routing region

Number of ground reference planes required for each DDR2 routing layer

Number of layers between DDR2 routing layer and reference ground plane

PCB feature spacing

4

0

5

1

6

7

4

Mils

mm

Ω

8

PCB trace width, w

9

PCB BGA escape via pad size⁽¹⁾

18

10

0.4

20

10 PCB BGA escape via hole size⁽¹⁾

11 Processor BGA pad size

13 Single-ended impedance, Zo

14 Impedance control⁽²⁾

50

75

Z-5

Z

Z+5

Ω

(1) A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the

processor.

(2) Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

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8.12.2.2.4 Placement

Figure 8-39 shows the required placement for the processor as well as the DDR2 devices. The

dimensions for this figure are defined in Table 8-38. The placement does not restrict the side of the PCB

on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace

lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device

is omitted from the placement.

Recommended DDR2 Device

Orientation

X

1

X

A1

1

X

OFFSET OFFSET

Y

Figure 8-39. Device and DDR2 Device Placement

Table 8-38. Placement Specifications

NO.

1

PARAMETER

MIN

MAX

1660

1280

650

UNIT

Mils

X + Y⁽¹⁾⁽²⁾

X^'(1)(2)

X^'Offset^{(1)(2) (3)}

DDR2 keepout region⁽⁴⁾

2

3

4

5

Clearance from non-DDR2 signal to DDR2 keepout region⁽⁵⁾

4

w

(1) For dimension definitions, see Figure 8-37.

(2) Measurements from center of processor to center of DDR2 device.

(3) For 16-bit memory systems, it is recommended that X^'offset be as small as possible.

(4) DDR2 keepout region to encompass entire DDR2 routing area.

(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

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8.12.2.2.5 DDR2 Keepout Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2

keepout region is defined for this purpose and is shown in Figure 8-40. The size of this region varies with

the placement and DDR routing. Additional clearances required for the keepout region are shown in

Table 8-38.

A1

DDR2 Device

A1

Figure 8-40. DDR2 Keepout Region

NOTE

The region shown in should encompass all the DDR2 circuitry and varies depending on

placement. Non-DDR2 signals should not be routed on the DDR signal layers within the

DDR2 keepout region. Non-DDR2 signals may be routed in the region, provided they are

routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be

allowed in the reference ground layers in this region. In addition, the 1.8-V power plane

should cover the entire keepout region. Routes for the DDR interface must be separated by

at least 4x; the more separation, the better.

8.12.2.2.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.

Table 8-39 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk

bypass capacitance may be needed for other circuitry.

Table 8-39. Bulk Bypass Capacitors

No. Parameter

Min

3

Max

Unit

Devices

μF

1

2

3

4

DVDD18 bulk bypass capacitor count⁽¹⁾

DVDD18 bulk bypass total capacitance

DDR bulk bypass capacitor count⁽¹⁾

DDR bulk bypass total capacitance⁽¹⁾

30

1

Devices

μF

10

(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed

(HS) bypass capacitors.

8.12.2.2.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,

and processor/DDR ground connections. Table 8-40 contains the specification for the HS bypass

capacitors as well as for the power connections on the PCB. Due to the number of required bypass

capacitors, it is recommended that the bypass capacitors are placed before routing the board.

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UNIT

Table 8-40. High-Speed Bypass Capacitors

NO.

1

PARAMETER

MIN

MAX

HS bypass capacitor package size⁽¹⁾

0402 10 Mils

2

Distance from HS bypass capacitor to device being bypassed

Number of connection vias for each HS bypass capacitor⁽²⁾

Trace length from bypass capacitor contact to connection via

Number of connection vias for each processor power/ground ball

Trace length from processor power/ground ball to connection via

Number of connection vias for each DDR2 device power/ground ball

Trace length from DDR2 device power/ground ball to connection via

DVDD18 HS bypass capacitor count⁽³⁾

250

Mils

Vias

Mils

3

2

1

4

30

5

Vias

Mils

6

35

7

1

Vias

Mils

8

35

9

20

1.2

8

Devices

μF

10 DVDD18 HS bypass capacitor total capacitance

11 DDR device HS bypass capacitor count⁽⁴⁾⁽⁵⁾

12 DDR device HS bypass capacitor total capacitance⁽⁵⁾

Devices

μF

0.4

(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.

(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

(3) These devices should be placed as close as possible to the device being bypassed.

(4) These devices should be placed as close as possible to the device being bypassed.

(5) Per DDR device.

8.12.2.2.8 Net Classes

Table 8-41 lists the clock net classes for the DDR2 interface. Table 8-42 lists the signal net classes, and

associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-41. Clock Net Class Definitions

CLOCK NET CLASS PROCESSOR PIN NAMES

CK

DDR[0]_CLK/DDR[0]_CLK

DQS0

DDR[0]_DQS[0]/DDR[0]_DQS[0]

DDR[0]_DQS[1]/DDR[0]_DQS[1]

DDR[0]_DQS[2]/DDR[0]_DQS[2]

DDR[0]_DQS[3]/DDR[0]_DQS[3]

DQS1

DQS2⁽¹⁾

DQS3⁽¹⁾

(1) Only used on 32-bit wide DDR2 memory systems.

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Table 8-42. Signal Net Class Definitions

ASSOCIATED CLOCK

CLOCK NET CLASS

PROCESSOR PIN NAMES

NET CLASS

ADDR_CTRL

CK

DDR[0]_BA[2:0], DDR[0]_A[15:0], DDR[0]_CS[x], DDR[0]_CAS,

DDR[0]_RAS, DDR[0]_WE, DDR[0]_CKE, DDR[0]_ODT[0]

DQ0

DQ1

DQ2⁽¹⁾

DQ3⁽¹⁾

DQS0

DQS1

DQS2

DQS3

DDR[0]_D[7:0], DDR[0]_DQM[0]

DDR[0]_D[15:8], DDR[0]_DQM[1]

DDR[0]_D[23:16], DDR[0]_DQM[2]

DDR[0]_D[31:24], DDR[0]_DQM[3]

(1) Only used on 32-bit wide DDR2 memory systems.

8.12.2.2.9 DDR2 Signal Termination

Signal terminators are required in CK and ADDR_CTRL net classes. Serial terminators may be used on

data lines to reduce EMI risk; however, serial terminations are the only type permitted. ODT's are

integrated on the data byte net classes. They should be enabled to ensure signal integrity.Table 8-43

shows the specifications for the series terminators.

Table 8-43. DDR2 Signal Terminations

NO.

1

PARAMETER

MIN

0

TYP

MAX UNIT

CK net class⁽¹⁾⁽²⁾

ADDR_CTRL net class^{(1) (2)(3)(4)}

10

Zo

Ω

2

0

22

3

Data byte net classes (DQS0-DQS3, DQ0-DQ3)⁽⁵⁾

0

(1) Only series termination is permitted, parallel or SST specifically disallowed on board.

(2) Only required for EMI reduction.

(3) Terminator values larger than typical only recommended to address EMI issues.

(4) Termination value should be uniform across net class.

(5) No external terminations allowed for data byte net classes. ODT is to be used.

8.12.2.2.10 VREFSSTL_DDR Routing

VREFSSTL_DDR is used as a reference by the input buffers of the DDR2 memories as well as the

processor. VREF is intended to be half the DDR2 power supply voltage and should be created using a

resistive divider as shown in Figure 8-38. Other methods of creating VREF are not recommended.

Figure 8-41 shows the layout guidelines for VREF.

VREF Nominal Max Trace

width is 20 mils

DDR2 Device

VREF Bypass Capacitor

A1

+

DDR2 Controller

Neck down to minimum in BGA escape

regions is acceptable. Narrowing to

accomodate via congestion for short

distances is also acceptable. Best

performance is obtained if the width

of VREF is maximized.

Figure 8-41. VREF Routing and Topology

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8.12.2.3 DDR2 CK and ADDR_CTRL Routing

Figure 8-42 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a

balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A

(A'+A'') should be maximized.

A1

B

C

A´´

T

A´

A = A´ + A´´

Figure 8-42. CK and ADDR_CTRL Routing and Topology

(1)

Table 8-44. CK and ADDR_CTRL Routing Specification

NO.

1

PARAMETER

MIN

TYP

MAX

2w

25

UNIT

Center-to-center CK-CK spacing

CK/CK skew⁽¹⁾

2

Mils

3

CK A-to-B/A-to-C skew length mismatch⁽²⁾

25

4

CK B-to-C skew length mismatch

25

5

Center-to-center CK to other DDR2 trace spacing⁽³⁾

CK/ADDR_CTRL nominal trace length⁽⁴⁾

4w

6

CACLM-50

CACLM

CACLM+50

100

Mils

7

ADDR_CTRL-to-CK skew length mismatch

8

ADDR_CTRL-to-ADDR_CTRL skew length mismatch

Center-to-center ADDR_CTRL to other DDR2 trace spacing⁽³⁾

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing⁽³⁾

ADDR_CTRL A-to-B/A-to-C skew length mismatch⁽²⁾

ADDR_CTRL B-to-C skew length mismatch

100

9

4w

3w

10

11

12

100

Mils

(1) The length of segment A = A' + A′′ as shown in Figure 8-42.

(2) Series terminator, if used, should be located closest to the device.

(3) Center-to-center spacing is allowed to fall to minimum (2w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

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Figure 8-43 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.

Skew matching across bytes is not needed nor recommended.

T

A1

E2

E3

E0

E1

Figure 8-43. DQS and DQ Routing and Topology

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Table 8-45. DQS and DQ Routing Specification

NO.

1

PARAMETER

Center-to-center DQS-DQSn spacing in E0|E1|E2|E3

DQS-DQSn skew in E0|E1|E2|E3

MIN

TYP

MAX

2w

UNIT

2

25

Mils

3

Center-to-center DQS to other DDR2 trace spacing⁽¹⁾

4w

(2)(3)(4)

4

DQS/DQ nominal trace length

DQLM-50

DQLM

DQLM+50

Mils

Vias

5

DQ-to-DQS skew length mismatch^(2)(3)(4)

DQ-to-DQ skew length mismatch^(2)(3)(4)

DQ-to-DQ/DQS via count mismatch^(2)(3)(4)

Center-to-center DQ to other DDR2 trace spacing⁽¹⁾⁽⁵⁾

Center-to-center DQ to other DQ trace spacing^(1)(6)(7)

100

1

6

7

8

4w

3w

9

10 DQ/DQS E skew length mismatch^(2)(3)(4)

100

Mils

(1) Center-to-center spacing is allowed to fall to minimum (2w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated

DQS (2 DQSs) per DDR EMIF used.

(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS

(4 DQSs) per DDR EMIF used.

(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data

byte 1.

(5) DQs from other DQS domains are considered other DDR2 trace.

(6) DQs from other data bytes are considered other DDR2 trace.

(7) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

8.12.3 DDR3/DDR3L Routing Specifications

8.12.3.1 Board Designs

TI only supports board designs utilizing DDR3/DDR3L memory that follow the guidelines in this document.

The switching characteristics and timing diagram for the DDR3/DDR3L memory controller are shown in

Table 8-46 and Figure 8-44. For the remainder of this section, DDR3 refers to both DDR3 and DDR3L.

Table 8-46. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory

Controller

-1G

NO.

PARAMETER

UNIT

MIN

MAX

1

t_{c(DDR_CLK)}

Cycle time, DDR_CLK

1.876

3.3⁽¹⁾

ns

(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and

operating frequency (see the DDR2/3 Memory Controller chapter in the device-specific Technical Reference Manual).

1

DDR_CLK

Figure 8-44. DDR3 Memory Controller Clock Timing

8.12.3.1.1 DDR3 versus DDR2

This specification only covers device PCB designs that utilize DDR3 memory. Designs using DDR2

memory should use the PCB design specifications for DDR2 memory in Section 8.12.2. While similar, the

two memory systems have different requirements. It is currently not possible to design one PCB that

covers both DDR2 and DDR3.

8.12.3.2 DDR3 Device Combinations

Since there are several possible combinations of device counts and single- or dual-side mounting,

Table 8-47 summarizes the supported device configurations.

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Table 8-47. Supported DDR3 Device Combinations

NUMBER OF DDR3 DEVICES

DDR3 DEVICE WIDTH (BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

1

2

4

16

8

N

Y⁽¹⁾

N

16

32

16

8

Y⁽¹⁾

N

Y⁽²⁾

8

(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

(2) This is two mirrored pairs of DDR3 devices.

8.12.3.3 DDR3 Interface Schematic

8.12.3.3.1 32-Bit DDR3 Interface

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width

of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR

devices look like two 8-bit devices. Figure 8-45 and Figure 8-46 show the schematic connections for 32-bit

interfaces using x16 devices.

8.12.3.3.2 16-Bit DDR3 Interface

Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-45

and Figure 8-46); only the high-word DDR memories are removed and the unused DQS inputs are tied off.

The processor DDR[0]_DQS[2] and DDR[0]_DQS[3] pins should be pulled to the DDR supply via 1-kΩ

resistors. Similarly, the DDR[0]_DQS[2] and DDR[0]_DQS[3] pins should be pulled to ground via 1-kΩ

resistors.

When not using a DDR interface, the proper method of handling the unused pins is to tie off the

DDR[0]_DQS[n] pins to the corresponding DVDD_DDR[0] supply via a 1-kΩ resistor and pulling the

DDR[0]_DQS[n] pins to ground via a 1k-Ω resistor. This needs to be done for each byte not used.

Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide

additional protection against external electrical noise causing activity on the signals.

Also, include the 50-Ω pulldown for DDR[0]_VTP. The DVDD_DDR[0] and VREFSSTL_DDR[0] power

supply pins must be connected to their respective power supplies even if DDR[0] is not used. All other

DDR interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are

32 bits wide, 16 bits wide, or not used.

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32-bit DDR3 EMIF

16-Bit DDR3

Devices

DDR[0]_D[31]

8

DQ15

DDR[0]_D[24]

DQ8

DDR[0]_DQM[3]

DDR[0]_DQS[3]

UDM

UDQS

DDR[0]_D[23]

8

DQ7

DDR[0]_D[16]

D08

DDR[0]_DQM[2]

DDR[0]_DQS[2]

LDM

LDQS

DDR[0]_D[15]

8

DQ15

DQ8

DDR[0]_D[8]

DDR[0]_DQM[1]

DDR[0]_DQS[1]

UDM

UDQS

DDR[0]_D[7]

8

DQ7

DDR[0]_D[0]

DQ0

DDR[0]_DQM[0]

DDR[0]_DQS[0]

LDM

LDQS

0.1 µF

Zo

DDR[0]_CLK

CK

DVDD_DDR[0]

DDR[0]_ODT[0]

DDR[0]_CS[0]

DDR[0]_BA[0]

DDR[0]_BA[1]

DDR[0]_BA[2]

ODT

CS

BA0

BA1

BA2

BA0

BA1

BA2

DDR_VTT

Zo

DDR[0]_A[0]

16

A0

DDR[0]_A[15]

DDR[0]_CAS

A15

CAS

RAS

WE

DDR[0]_RAS

DDR[0]_WE

DDR[0]_CKE

DDR[0]_RST

RAS

WE

CKE

RST

DDR_VREF

RST

ZQ

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFSSTL_DDR[0]

0.1 µF

DDR[0]_VTP

50 Ω ( 2%)

Zo

ZQ

Termination is required. See terminator comments.

Value determined according to the DDR memory device data sheet.

Figure 8-45. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices

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DDR[0]_D[31]

SPRS870B –APRIL 2013–REVISED DECEMBER 2013

8-Bit DDR3

Devices

8-Bit DDR3

Devices

DQ7

8

DDR[0]_D[24]

DQ0

DDR[0]_DQM[3]

DM/TQS

TDQS

DQS

NC

DDR[0]_DQS[3]

DDR[0]_D[23]

DQ7

DQ0

8

DDR[0]_D[16]

DDR[0]_DQM[2]

DM/TQS

TDQS

DQS

NC

DDR[0]_DQS[2]

DQS

DDR[0]_D[15]

DQ7

DQ0

8

DDR[0]_D[8]

DDR[0]_DQM[1]

DM/TQS

TDQS

DQS

NC

DDR[0]_DQS[1]

DQS

DDR[0]_D[7]

DQ7

DQ0

8

DDR[0]_D[0]

DDR[0]_DQM[0]

DM/TQS

TDQS

DQS

NC

DDR[0]_DQS[0]

DQS

0.1 µF

Zo

DDR[0]_CLK

CK

DVDD_DDR[0]

DDR[0]_ODT[0]

DDR[0]_CS[0]

DDR[0]_BA[0]

DDR[0]_BA[1]

DDR[0]_BA[2]

ODT

CS

BA0

BA1

BA2

BA0

BA1

BA2

BA0

BA1

BA2

BA0

BA1

BA2

DDR_VTT

Zo

DDR[0]_A[0]

A0

16

DDR[0]_A[15]

A15

DDR[0]_CAS

DDR[0]_RAS

DDR[0]_WE

DDR[0]_CKE

DDR[0]_RST

CAS

RAS

WE

CAS

RAS

WE

RAS

WE

CKE

RST

CKE

RST

DDR_VREF

ZQ

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFSSTL_DDR[0]

0.1 µF

DDR[0]_VTP

50 Ω ( 2%)

Zo

ZQ

Termination is required. See terminator comments.

Value determined according to the DDR memory device data sheet.

Figure 8-46. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices

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8.12.3.4 Compatible DDR3 Devices

Table 8-48 shows the parameters of the DDR3 devices that are compatible with this interface. Generally,

the interface is compatible with DDR3 devices in the x8 or x16 widths.

Table 8-48. Compatible DDR3 Devices (Per Interface)

NO.

1

PARAMETER

DDR3 device speed grade: ≤ 400 MHz clock rate⁽¹⁾

DDR3 device speed grade: > 400 MHz clock rate⁽¹⁾

DDR3 device bit width

MIN

DDR3-800

DDR3-1600

x8

MAX

UNIT

(2)

2

3

x16

4

Bits

4

DDR3 device count⁽³⁾

2

Devices

(1) DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-800, the clock rate is 400 MHz.

(2) DDR3 devices with higher speed grades are supported; however, max clock rate will still be limited to 533 MHz as stated in Table 8-46

Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller.

(3) For valid DDR3 device configurations and device counts, see Section 8.12.3.3, Figure 8-45, and Figure 8-46.

8.12.3.5 PCB Stackup

The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 8-49.

Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI

performance, or to reduce the size of the PCB footprint. A six-layer stackup is shown in Table 8-50.

Complete stackup specifications are provided in Table 8-51.

Table 8-49. Minimum PCB Stackup

LAYER

TYPE

Signal

Plane

Signal

DESCRIPTION

1

2

3

4

Top routing mostly vertical

Split power plane

Full ground plane

Bottom routing mostly horizontal

Table 8-50. Six-Layer PCB Stackup Suggestion

LAYER

TYPE

Signal

Plane

Signal

DESCRIPTION

1

2

3

4

5

6

Top routing mostly vertical

Ground

Split power plane

Split power plane or Internal routing

Ground

Bottom routing mostly horizontal

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Table 8-51. PCB Stackup Specifications

PARAMETER

MIN

TYP

MAX

UNIT

1

2

3

4

5

6

7

8

9

PCB routing/plane layers

Signal routing layers

4

2

1

6

Full ground reference layers under DDR3 routing region⁽¹⁾

Full 1.35-V/1.5-V power reference layers under the DDR3 routing region⁽¹⁾

Number of reference plane cuts allowed within DDR routing region⁽²⁾

Number of layers between DDR3 routing layer and reference plane⁽³⁾

PCB feature spacing

0

4

Mils

mm

Ω

PCB trace width, w

PCB BGA escape via pad size⁽⁴⁾

18

10

0.4

20

10 PCB BGA escape via hole size

11 Processor BGA pad size

13 Single-ended impedance, Zo

14 Impedance control⁽⁵⁾

50

75

Z-5

Z

Z+5

Ω

(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers.

(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available

for power routing. An 18-mil pad is required for minimum layer count escape.

(5) Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

8.12.3.6 Placement

Figure 8-47 shows the required placement for the processor as well as the DDR3 devices. The

dimensions for this figure are defined in Table 8-52. The placement does not restrict the side of the PCB

on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace

lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3

devices are omitted from the placement.

X1

X2

DDR3

Controller

Y

Figure 8-47. Placement Specifications

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Table 8-52. Placement Specifications

NO.

1

PARAMETER

MIN

MAX

1000

600

UNIT

Mils

X1^(1)(2)(3)

X2⁽¹⁾⁽²⁾

Y Offset^(1)(2)(3)

2

3

1500

4

DDR3 keepout region

5

Clearance from non-DDR3 signal to DDR3 keepout region⁽⁴⁾⁽⁵⁾

4

w

(1) For dimension definitions, see Figure 8-47.

(2) Measurements from center of processor to center of DDR3 device.

(3) Minimizing X1 and Y improves timing margins.

(4) w is defined as the signal trace width.

(5) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.

8.12.3.7 DDR3 Keepout Region

The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout

region is defined for this purpose and is shown in Figure 8-48. The size of this region varies with the

placement and DDR routing. Additional clearances required for the keepout region are shown in Table 8-

52. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.

Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the

DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this

region. In addition, the 1.35-V/1.5-V DDR3L/DDR3 power plane should cover the entire keepout region.

Also note that the DDR3 controller's signals should be separated from each other by the specification in

item 5 (see Table 8-52 for item 5 specification).

DDR3 Controller

DDR[0] Keep Out Region

Encompasses Entire DDR[0] Routing Area

Figure 8-48. DDR3 Keepout Region

8.12.3.8 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.

Table 8-53 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR3 controller and DDR3 devices. Additional bulk

bypass capacitance may be needed for other circuitry.

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Table 8-53. Bulk Bypass Capacitors

PARAMETER

MIN

6

MAX

UNIT

Devices

μF

1

2

DVDD_DDR[0] bulk bypass capacitor count⁽¹⁾

DVDD_DDR[0] bulk bypass total capacitance

140

(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-

speed (HS) bypass capacitors and DDR3 signal routing.

8.12.3.9 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,

and processor/DDR ground connections. Table 8-54 contains the specification for the HS bypass

capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

1. Fit as many HS bypass capacitors as possible. Due to the number of required bypass capacitors, it is

recommended that the bypass capacitors are placed before routing the board.

2. Minimize the distance from the bypass cap to the pins/balls being bypassed.

3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.

4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest

hole size via possible.

5. Minimize via sharing. Note the limits on via sharing shown in Table 8-54.

Table 8-54. High-Speed Bypass Capacitors

NO.

1

PARAMETER

HS bypass capacitor package size⁽¹⁾

MIN

TYP

MAX

UNIT

201

402 10 Mils

2

Distance, HS bypass capacitor to processor being bypassed^(2)(3)(4)

400

Mils

Devices

μF

3

Processor DVDD_DDR[0] HS bypass capacitor count

35

4

Processor DVDD_DDR[0] HS bypass capacitor total capacitance

Number of connection vias for each device power/ground ball⁽⁵⁾

Trace length from device power/ground ball to connection via⁽²⁾

Distance, HS bypass capacitor to DDR device being bypassed⁽⁶⁾

DDR3 device HS bypass capacitor count⁽⁷⁾

2.5

5

Vias

Mils

6

35

70

7

150

Mils

8

12

0.85

2

Devices

μF

9

DDR3 device HS bypass capacitor total capacitance⁽⁷⁾

10 Number of connection vias for each HS capacitor⁽⁸⁾⁽⁹⁾

Vias

Mils

11 Trace length from bypass capacitor connect to connection via⁽²⁾⁽⁹⁾

12 Number of connection vias for each DDR3 device power/ground ball⁽¹⁰⁾

13 Trace length from DDR3 device power/ground ball to connection via⁽²⁾⁽⁸⁾

35

100

60

1

Vias

Mils

(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.

(2) Closer/shorter is better.

(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.

(4) Three of these capacitors should be located underneath the processor, between the cluster of DVDD_DDR[0] balls and ground balls,

between the DDR interfaces on the package.

(5) See the Via Channel™ escape for the processor package.

(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.

(7) Per DDR3 device.

(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of

vias is permitted on the same side of the board.

(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the

connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.

(10) Up to a total of two pairs of DDR power/ground balls may share a via.

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8.12.3.9.1 Return Current Bypass Capacitors

Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals

hopping from one signal layer to another. The bypass capacitor here provides a path for the return current

to hop planes along with the signal. As many of these return current bypass capacitors should be used as

possible. Since these are returns for signal current, the signal via size may be used for these capacitors.

8.12.3.10 Net Classes

Table 8-55 lists the clock net classes for the DDR3 interface. Table 8-56 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-55. Clock Net Class Definitions

CLOCK NET CLASS PROCESSOR PIN NAMES

CK

DDR[0]_CLK/DDR[0]_CLK

DQS0

DDR[0]_DQS[0]/DDR[0]_DQS[0]

DDR[0]_DQS[1]/DDR[0]_DQS[1]

DDR[0]_DQS[2]/DDR[0]_DQS[2]

DDR[0]_DQS[3]/DDR[0]_DQS[3]

DQS1

DQS2⁽¹⁾

DQS3⁽¹⁾

(1) Only used on 32-bit wide DDR3 memory systems.

Table 8-56. Signal Net Class Definitions

ASSOCIATED CLOCK

PROCESSOR PIN NAMES

NET CLASS

CLOCK NET CLASS

ADDR_CTRL

CK

DDR[0]_BA[2:0], DDR[0]_A[15:0], DDR[0]_CS[x], DDR[0]_CAS,

DDR[0]_RAS, DDR[0]_WE, DDR[0]_CKE, DDR[0]_ODT[0]

DQ0

DQ1

DQ2⁽¹⁾

DQ3⁽¹⁾

DQS0

DQS1

DQS2

DQS3

DDR[0]_D[7:0], DDR[0]_DQM[0]

DDR[0]_D[15:8], DDR[0]_DQM[1]

DDR[0]_D[23:16], DDR[0]_DQM[2]

DDR[0]_D[31:24], DDR[0]_DQM[3]

(1) Only used on 32-bit wide DDR3 memory systems.

8.12.3.11 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

8.12.3.12 VREFSSTL_DDR Routing

VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as

the processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with

the DDR3 1.35-V/1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1

µF bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate

routing congestion.

8.12.3.13 VTT

Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is

expected to source and sink current, specifically the termination current for the ADDR_CTRL net class

Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power

sub-plane. VTT should be bypassed near the terminator resistors.

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8.12.3.14 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew

between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.

The following subsections show the topology and routing for various DDR3 configurations for CK and

ADDR_CTRL. The figures in the following subsections define the terms for the routing specification

detailed in Table 8-57.

8.12.3.14.1 Four DDR3 Devices

Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one

bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two

pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.

8.12.3.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices

Figure 8-49 shows the topology of the CK net classes and Figure 8-50 shows the topology for the

corresponding ADDR_CTRL net classes.

DDR Differential CK Input Buffers

–

+

Clock Parallel

Terminator

DVDD_DDR[0]

Rcp

A1

A2

A3

A4

A3

AT

Cac

Processor

Differential Clock

Output Buffer

+

–

0.1 µF

Rcp

Routed as Differential Pair

Figure 8-49. CK Topology for Four x8 DDR3 Devices

DDR Address and Control Input Buffers

Address and Control

Terminator

Rtt

Processor

Address and Control

Output Buffer

A1

A2

A3

A4

A3

AT

Vtt

Figure 8-50. ADDR_CTRL Topology for Four x8 DDR3 Devices

8.12.3.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices

Figure 8-51 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-52

shows the corresponding ADDR_CTRL routing.

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DVDD_DDR[0]

Cac

Rcp

A2

A3

A4

A3

AT

0.1 µF

=

Figure 8-51. CK Routing for Four Single-Side DDR3 Devices

Rtt

A2

A3

A4

A3

AT

Vtt

=

Figure 8-52. ADDR_CTRL Routing for Four Single-Side DDR3 Devices

To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of

increased routing and assembly complexity. Figure 8-53 and Figure 8-54 show the routing for CK and

ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.

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DVDD_DDR[0]

Cac

Rcp

A2

A3

A4

A3

AT

0.1 µF

=

Figure 8-53. CK Routing for Four Mirrored DDR3 Devices

Rtt

A2

A3

A4

A3

AT

Vtt

=

Figure 8-54. ADDR_CTRL Routing for Four Mirrored DDR3 Devices

8.12.3.14.2 Two DDR3 Devices

Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one

bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two

devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at

a cost of increased routing complexity and parts on the backside of the PCB.

8.12.3.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices

Figure 8-55 shows the topology of the CK net classes and Figure 8-56 shows the topology for the

corresponding ADDR_CTRL net classes.

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DDR Differential CK Input Buffers

–

+

Clock Parallel

Terminator

DVDD_DDR[0]

Rcp

A1

A2

A3

AT

Cac

Processor

Differential Clock

Output Buffer

+

–

0.1 µF

Rcp

A1

Routed as Differential Pair

Figure 8-55. CK Topology for Two DDR3 Devices

DDR Address and Control Input Buffers

Address and Control

Terminator

Rtt

Processor

Address and Control

Output Buffer

A1

A2

A3

AT

Vtt

Figure 8-56. ADDR_CTRL Topology for Two DDR3 Devices

8.12.3.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices

Figure 8-57 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-58

shows the corresponding ADDR_CTRL routing.

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DVDD_DDR[0]

Cac

Rcp

A2

A3

AT

0.1 µF

=

Figure 8-57. CK Routing for Two Single-Side DDR3 Devices

Rtt

A2

A3

AT

Vtt

=

Figure 8-58. ADDR_CTRL Routing for Two Single-Side DDR3 Devices

To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased

routing and assembly complexity. Figure 8-59 and Figure 8-60 show the routing for CK and ADDR_CTRL,

respectively, for two DDR3 devices mirrored in a single-pair configuration.

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DVDD_DDR[0]

Cac

Rcp

A2

A3

AT

0.1 µF

=

Figure 8-59. CK Routing for Two Mirrored DDR3 Devices

Rtt

A2

A3

AT

Vtt

=

Figure 8-60. ADDR_CTRL Routing for Two Mirrored DDR3 Devices

8.12.3.14.3 One DDR3 Device

A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as

one bank (CS), 16 bits wide.

8.12.3.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device

Figure 8-61 shows the topology of the CK net classes and Figure 8-62 shows the topology for the

corresponding ADDR_CTRL net classes.

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DDR Differential CK Input Buffer

–

+

Clock Parallel

Terminator

DVDD_DDR[0]

Rcp

A1

A2

AT

Cac

Processor

Differential Clock

Output Buffer

+

–

0.1 µF

Rcp

Routed as Differential Pair

Figure 8-61. CK Topology for One DDR3 Device

DDR Address and Control Input Buffers

Address and Control

Terminator

Rtt

Processor

Address and Control

Output Buffer

A1

A2

AT

Vtt

Figure 8-62. ADDR_CTRL Topology for One DDR3 Device

8.12.3.14.3.2 CK and ADDR/CTRL Routing, One DDR3 Device

Figure 8-63 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-64

shows the corresponding ADDR_CTRL routing.

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DVDD_DDR[0]

Cac

Rcp

A2

AT

0.1 µF

=

Figure 8-63. CK Routing for One DDR3 Device

Rtt

A2

AT

Vtt

=

Figure 8-64. ADDR_CTRL Routing for One DDR3 Device

8.12.3.15 Data Topologies and Routing Definition

No matter the number of DDR3 devices used, the data line topology is always point to point, so its

definition is simple.

8.12.3.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices

DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-65

and Figure 8-66 show these topologies.

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Processor

DQS

DDR

DQSn+

DQSn-

DQS

IO Buffer

Routed Differentially

n = 0, 1, 2, 3

Figure 8-65. DQS Topology

Processor

DQ and DM

IO Buffer

DDR

Dn

DQ and DM

IO Buffer

n = 0, 1, 2, 3

Figure 8-66. DQ/DM Topology

8.12.3.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices

Figure 8-67 and Figure 8-68 show the DQS and DQ/DM routing.

DQS

DQSn+

DQSn-

Routed Differentially

n = 0, 1, 2, 3

Figure 8-67. DQS Routing With Any Number of Allowed DDR3 Devices

DQ and DM

Dn

n = 0, 1, 2, 3

Figure 8-68. DQ/DM Routing With Any Number of Allowed DDR3 Devices

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8.12.3.16 Routing Specification

8.12.3.16.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this

skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter

traces up to the length of the longest net in the net class and its associated clock. A metric to establish

this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the

length between the points when connecting them only with horizontal or vertical segments. A reasonable

trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address

Control Longest Manhattan distance.

Given the clock and address pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 8-69 and Figure 8-70 show

this distance for four loads and two loads, respectively. It is from this distance that the specifications on

the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly

for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net

class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-57.

A8^(A)

CACLMY

CACLMX

A8^(A)

Rtt

A2

A3

A4

A3

AT

Vtt

=

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3

memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that

satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this

length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-69. CACLM for Four Address Loads on One Side of PCB

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A8^(A)

CACLMY

CACLMX

A8^(A)

Rtt

A2

A3

AT

Vtt

=

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3

memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that

satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this

length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-70. CACLM for Two Address Loads on One Side of PCB

Table 8-57. CK and ADDR_CTRL Routing Specification⁽¹⁾⁽²⁾

NO.

1

PARAMETER

MIN

TYP

MAX

2500

25

UNIT

mils

A1+A2 length

A1+A2 skew

A3 length

A3 skew⁽³⁾

A3 skew⁽⁴⁾

A4 length

A4 skew

2

3

660

25

4

5

125

660

25

6

7

8

AS length

AS skew

100

70

9

10 AS+/AS- length

11 AS+/AS- skew

12 AT length⁽⁵⁾

13 AT skew⁽⁶⁾

14 AT skew⁽⁷⁾

15 CK/ADDR_CTRL nominal trace length⁽⁸⁾

5

500

100

5

CACLM-50

CACLM

CACLM+50

(1) The use of vias should be minimized.

(2) Additional bypass capacitors are required when using the DVDD_DDR[0] plane as the reference plane to allow the return current to

jump between the DVDD_DDR[0] plane and the ground plane when the net class switches layers at a via.

(3) Non-mirrored configuration (all DDR3 memories on same side of PCB).

(4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).

(5) While this length can be increased for convenience, its length should be minimized.

(6) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.

(7) CK net class only.

(8) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 8.12.3.16.1,

Figure 8-69, and Figure 8-70.

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UNIT

Table 8-57. CK and ADDR_CTRL Routing Specification⁽¹⁾⁽²⁾(continued)

NO.

PARAMETER

MIN

4w

TYP

MAX

16 Center-to-center CK to other DDR3 trace spacing⁽⁹⁾

17 Center-to-center ADDR_CTRL to other DDR3 trace spacing^(9)(10)

18 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing⁽⁹⁾

19 CK center-to-center spacing⁽¹¹⁾

4w

3w

20 CK spacing to other net⁽⁹⁾

21 Rcp⁽¹²⁾

22 Rtt^(12)(13)

4w

Zo-1

Zo-5

Zo

Zo+

Ω

Zo+5

(9) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.

(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.

(11) CK spacing set to ensure proper differential impedance.

(12) Source termination (series resistor at driver) is specifically not allowed.

(13) Termination values should be uniform across the net class.

8.12.3.16.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew

must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces

up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,

a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as

DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four

DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length

matching is only required within each byte.

Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 8-71 shows this distance for

four loads. It is from this distance that the specifications on the lengths of the transmission lines for the

data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-58.

DQLMX0

DQ[0:7]/DM0/DQS0

DB0

DQ[8:15]/DM1/DQS1

DB1

DQLMX1

DQ[16:23]/DM2/DQS2

DB2

DQLMY0

DQLMX2

DQLMY1

DQLMY3 DQLMY2

DQ[23:31]/DM3/DQS3

DB3

DQLMX3

3

2

1

0

DB0 - DB3 represent data bytes 0 - 3.

There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the

byte; therefore:

DQLM0 = DQLMX0 + DQLMY0

DQLM1 = DQLMX1 + DQLMY1

DQLM2 = DQLMX2 + DQLMY2

DQLM3 = DQLMX3 + DQLMY3

Figure 8-71. DQLM for Any Number of Allowed DDR3 Devices

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Table 8-58. Data Routing Specification⁽¹⁾

PARAMETER

MIN

TYP

MAX

DQLM0

DQLM1

DQLM2

DQLM3

25

UNIT

mils

1

2

3

4

5

6

7

8

9

DB0 nominal length⁽²⁾⁽³⁾

DB1 nominal length⁽²⁾⁽⁴⁾

DB2 nominal length⁽²⁾⁽⁵⁾

DB3 nominal length⁽²⁾⁽⁶⁾

DBn skew⁽⁷⁾

DQSn+ to DQSn- skew

DQSn to DBn skew⁽⁷⁾⁽⁸⁾

Center-to-center DBn to other DDR3 trace spacing^(9)(10)

Center-to-center DBn to other DBn trace spacing^(9)(11)

5

25

4w

3w

10 DQSn center-to-center spacing⁽¹²⁾

11 DQSn center-to-center spacing to other net⁽⁹⁾

4w

(1) External termination disallowed. Data termination should use built-in ODT functionality.

(2) DQLMn is the longest Manhattan distance of a byte. r definition, see Section 8.12.3.16.2 and Figure 8-71.

(3) DQLM0 is the longest Manhattan length for the net classes of Byte 0.

(4) DQLM1 is the longest Manhattan length for the net classes of Byte 1.

(5) DQLM2 is the longest Manhattan length for the net classes of Byte 2.

(6) DQLM3 is the longest Manhattan length for the net classes of Byte 3.

(7) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.

(8) Each DQS pair is length matched to its associated byte.

(9) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.

(10) Other DDR3 trace spacing means other DDR3 net classes not within the byte.

(11) This applies to spacing within the net classes of a byte.

(12) DQS pair spacing is set to ensure proper differential impedance.

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8.13 Multichannel Audio Serial Port (McASP)

The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for

the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)

stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission

(DIT).

8.13.1 McASP Device-Specific Information

The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and

McASP1). The McASP module consists of a transmit and receive section. These sections can operate

completely independently with different data formats, separate master clocks, bit clocks, and frame syncs

or, alternatively, the transmit and receive sections may be synchronized. The McASP module also

includes shift registers that may be configured to operate as either transmit data or receive data.

The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)

synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for

S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports

the TDM synchronous serial format.

The McASP module can support one transmit data format (either a TDM format or DIT format) and one

receive format at a time. All transmit shift registers use the same format and all receive shift registers use

the same format; however, the transmit and receive formats need not be the same. Both the transmit and

receive sections of the McASP also support burst mode, which is useful for non-audio data (for example,

passing control information between two devices).

The McASP peripheral has additional capability for flexible clock generation and error detection/handling,

as well as error management.

The device McASP0 module has up to 6 serial data pins, while McASP1 has 2 serial data pins. The

McASP FIFO size is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used

transparently to better manage DMA, which can be leveraged to manage data flow more efficiently.

For more detailed information on and the functionality of the McASP peripheral, see the Multichannel

Audio Serial Port (McASP) chapter in the device-specific Technical Reference Manual.

8.13.2 McASP0 and McASP1 Peripheral Registers Descriptions

The McASP0 and McASP1 peripheral registers are described in the device-specific Technical Reference

Manual. Each register is documented as an offset from a base address for the peripheral. The base

addresses for all of the peripherals are in the device memory map (see Section 2.10).

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8.13.3 McASP (McASP[1:0]) Electrical Data/Timing

Table 8-59. Timing Requirements for McASP⁽¹⁾

(see Figure 8-72)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

1

2

3

4

t_c(AHCLKRX)

t_w(AHCLKRX)

t_c(ACLKRX)

t_w(ACLKRX)

Cycle time, MCA[x]_AHCLKR/X

20

ns

0.5P -

2.5⁽²⁾

Pulse duration, MCA[x]_AHCLKR/X high or low

Cycle time, MCA[x]_ACLKR/X

20

0.5R -

2.5⁽³⁾

Pulse duration, MCA[x]_ACLKR/X high or low

ACLKR/X int

10.5

4

Setup time, MCA[x]_AFSR/X input valid before

MCA[X]_ACLKR/X

5

6

7

8

t_{su(AFSRX-ACLKRX)}

t_{h(ACLKRX-AFSRX)}

t_{su(AXR-ACLKRX)}

t_{h(ACLKRX-AXR)}

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

ns

4

-1

1

Hold time, MCA[x]_AFSR/X input valid after

MCA[X]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

1

10.5

4

Setup time, MCA[x]_AXR input valid before

MCA[X]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

4

-1

1

Hold time, MCA[x]_AXR input valid after

MCA[X]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

1

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2) P = MCA[x]_AHCLKR/X period in nano seconds (ns).

(3) R = MCA[x]_ACLKR/X period in ns.

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2

1

2

MCA[x]_ACLKR/X (Falling Edge Polarity)

MCA[x]_AHCLKR/X (Rising Edge Polarity)

4

3

MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)^(A)

MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)^(B)

6

5

MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)

8

7

MCA[x]_AXR[x] (Data In/Receive)

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

Figure 8-72. McASP Input Timing

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Table 8-60. Switching Characteristics Over Recommended Operating Conditions for McASP⁽¹⁾

(see Figure 8-73)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

UNIT

MIN

MAX

9

t_c(AHCLKRX)

Cycle time, MCA[X]_AHCLKR/X

20⁽²⁾

ns

0.5P -

2.5⁽³⁾

10 t_w(AHCLKRX)

11 t_c(ACLKRX)

12 t_w(ACLKRX)

Pulse duration, MCA[X]_AHCLKR/X high or low

Cycle time, MCA[X]_ACLKR/X

20

0.5P -

2.5⁽³⁾

Pulse duration, MCA[X]_ACLKR/X high or low

ACLKR/X int

-2

1

5

Delay time, MCA[X]_ACLKR/X transmit edge to

MCA[X]_AFSR/X output valid

ACLKR/X ext in

11.5

13 t_{d(ACLKRX-AFSRX)}

ns

Delay time, MCA[X]_ACLKR/X transmit edge to

MCA[X]_AFSR/X output valid with Pad Loopback

ACLKR/X ext out

1

11.5

ACLKX int

-2

1

5

Delay time, MCA[X]_ACLKX transmit edge to

MCA[X]_AXR output valid

ACLKX ext in

11.5

14 t_d(ACLKX-AXR)

Delay time, MCA[X]_ACLKX transmit edge to

MCA[X]_AXR output valid with Pad Loopback

ACLKX ext out

1

11.5

ACLKX int

-2

1

5

Disable time, MCA[X]_ACLKX transmit edge to

MCA[X]_AXR output high impedance

ACLKX ext in

11.5

15 t_{dis(ACLKX-AXR)}

ns

Disable time, MCA[X]_ACLKX transmit edge to

MCA[X]_AXR output high impedance with Pad

Loopback

ACLKX ext out

1

11.5

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2) 50 MHz

(3) P = AHCLKR/X period.

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10

9

MCA[x]_ACLKR/X (Falling Edge Polarity)

MCA[x]_AHCLKR/X (Rising Edge Polarity)

12

11

12

MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)^(A)

MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)^(B)

13

MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)

13

MCA[x]_AXR[x] (Data Out/Transmit)

14

15

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

Figure 8-73. McASP Output Timing

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8.14 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)

The device includes 3 MMC/SD/SDIO Controllers which are compliant with MMC V4.3, Secure Digital Part

1 Physical Layer Specification V2.00 and Secure Digital Input Output (SDIO) V2.00 specifications.

The device MMC/SD/SDIO Controller has the following features:

•

MultiMedia card (MMC)

Secure Digital (SD) memory card

MMC/SD protocol support

SDIO protocol support

Programmable clock frequency

1024 byte read/write FIFO to lower system overhead

Slave EDMA transfer capability

SD High capacity support

SDXC card support

–

Supports only SDHC clock rates

Booting from SDXC cards is not supported

8.14.1 MMC/SD/SDIO Peripheral Register Descriptions

The MMC/SD/SDIO peripheral registers are described in the device-specific Technical Reference Manual.

Each register is documented as an offset from a base address for the peripheral. The base addresses for

all of the peripherals are in the device memory map (see Section 2.10).

8.14.2 MMC/SD/SDIO Electrical Data/Timing

Table 8-61. Timing Requirements for MMC/SD/SDIO

(see Figure 8-75, Figure 8-77)

OPP100/OPP120/

Turbo/Nitro

NO

.

UNIT

ALL MODES

MIN

4.1

1.9

4.1

1.9

MAX

1

2

3

4

t_{su(CMDV-CLKH)}

t_h(CLKH-CMDV)

t_{su(DATV-CLKH)}

t_h(CLKH-DATV)

Setup time, SD_CMD valid before SD_CLK rising clock edge

Hold time, SD_CMD valid after SD_CLK rising clock edge

Setup time, SD_DATx valid before SD_CLK rising clock edge

Hold time, SD_DATx valid after SD_CLK rising clock edge

ns

Table 8-62. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO

(see Figure 8-74 through Figure 8-77)

OPP100/OPP120/

Turbo/Nitro

MODES

NO.

PARAMETER

UNIT

3.3 V STD

1.8 V SDR12

3.3 V HS

1.8 V SDR25

MIN

MAX

MIN

MAX

f_op(CLK)

t_c(CLK)

Operating frequency, SD_CLK

Operating period: SD_CLK

24

48 MHz

7

41.7

20.8

ns

f_op(CLKID)

t_c(CLKID)

t_w(CLKL)

Identification mode frequency, SD_CLK

Identification mode period: SD_CLK

Pulse duration, SD_CLK low

400

400 kHz

8

9

2500.0

0.5*P⁽¹⁾

2500.0

0.5*P⁽¹⁾

ns

10 t_w(CLKH)

Pulse duration, SD_CLK high

(1) P = SD_CLK period.

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Table 8-62. Switching Characteristics Over Recommended Operating Conditions for

MMC/SD/SDIO (continued)

(see Figure 8-74 through Figure 8-77)

OPP100/OPP120/

Turbo/Nitro

MODES

NO.

PARAMETER

UNIT

3.3 V STD

1.8 V SDR12

3.3 V HS

1.8 V SDR25

MIN

MAX

MIN

MAX

11 t_r(CLK)

12 t_f(CLK)

Rise time, All Signals (10% to 90%)

2.2

ns

Fall time, All Signals (10% to 90%)

Delay time, SD_CLK rising clock edge to SD_CMD

transition

13 t_d(CLKL-CMD)

14 t_d(CLKL-DAT)

-4

4

2.3

14

ns

Delay time, SD_CLK rising clock edge to SD_DATx

transition

10

7

9

SDx_CLK

SDx_CMD

13

Valid

13

START

XMIT

Valid

END

Figure 8-74. MMC/SD/SDIO Host Command Timing

9

10

7

SDx_CLK

SDx_CMD

1

2

Valid

START

XMIT

Valid

END

Figure 8-75. MMC/SD/SDIO Card Response Timing

10

9

7

SDx_CLK

14

Dx

START

D0

D1

END

SDx_DAT[x]

Figure 8-76. MMC/SD/SDIO Host Write Timing

9

10

7

SDx_CLK

4

3

Start

SDx_DAT[x]

D0

D1

Dx

End

Figure 8-77. MMC/SD/SDIO Host Read and Card CRC Status Timing

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8.15 Serial ATA Controller (SATA)

The Serial ATA (SATA) peripheral provides a direct interface to one hard disk drive (SATA) or multiple

hard disk drives using a Port Multiplier and supports the following features:

•

Serial ATA 1.5 Gbps and 3 Gbps speeds

Integrated PHYs

Integrated Rx and Tx data buffers

Supports all SATA power management features

Hardware-assisted native command queuing (NCQ) for up to 32 entries

Supports port multiplier with command-based switching

Activity LED support.

8.15.1 SATA Peripheral Register Descriptions

The SATA peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

8.15.2 SATA Interface Design Guidelines

This section provides PCB design and layout guidelines for the SATA interface. The design rules constrain

PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system

design work has been done to ensure the SATA interface requirements are met.

A standard 100-MHz differential clock source must be used for SATA operation (for details, see

Section 7.4.2, SERDES_CLKN/P Input Clock).

8.15.2.1 SATA Interface Schematic

Figure 8-78 shows the data portion of the SATA interface schematic.

The specific pin numbers can be obtained from Section 3.3.18, Serial ATA (SATA) Signals.

SATA Interface (Processor)

SATA Connector

10 nF

SATA_TXN0

TX-

SATA_TXP0

TX+

10 nF

SATA_RXN0

SATA_RXP0

RX-

RX+

10 nF

Figure 8-78. SATA Interface High-Level Schematic

8.15.2.2 Compatible SATA Components and Modes

Table 8-63 shows the compatible SATA components and supported modes. Note that the only supported

configuration is an internal cable from the processor host to the SATA device.

Table 8-63. SATA Supported Modes

PARAMETER

MIN

MAX

UNIT

SUPPORTED

Transfer Rates

xSATA

1.5

3.0

Gbps

-

No

Backplane

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Table 8-63. SATA Supported Modes (continued)

PARAMETER

MIN

MAX

UNIT

SUPPORTED

Internal Cable (iSATA)

-

Yes

8.15.2.3 PCB Stackup Specifications

Table 8-64 shows the PCB stackup and feature sizes required for SATA.

Table 8-64. SATA PCB Stackup Specifications

PARAMETER

MIN

TYP

MAX

UNIT

Layers

Cuts

PCB routing/plane layers

Signal routing layers

4

2

-

6

3

-

Number of ground plane cuts allowed within SATA routing region

Number of layers between SATA routing region and reference ground plane

PCB trace width, w

-

0

-

Layers

Mils

-

4

PCB BGA escape via pad size

-

20

10

0.4

-

Mils

PCB BGA escape via hole size

Processor BGA pad size⁽¹⁾

-

Mils

mm

(1) NSMD pad, per IPC-7351A BGA pad size guideline.

8.15.2.4 Routing Specifications

The SATA data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω

(±15%) single-ended impedance. The single-ended impedance is required because differential signals are

extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.

60 Ω is chosen for the single-ended impedance to minimize problems caused by too low an impedance.

These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric

material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as

close to 100 Ω differential impedance and 60 Ω single-ended impedance traces as possible. For best

accuracy, work with your PCB fabricator to ensure this impedance is met.

When routing SATA on the top (or any single) layer, the pin assignment will not allow a straight routing for

the SATAx_RXP0 and SATAx_RXN0 signals. There are two ways to overcome this:

1. Swap the SATA pin assignment in the software registers to allow straight, single layer routing.

2. Use the method pictured below in Figure 8-79 and Figure 8-80 to route to the SATA connector. This

method results in lines that are still length matched, and still on just one single layer.

Figure 8-79. SATA Routing

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SATAx_RXP0

SATAx_RXN0

Figure 8-80. Close Up of SATA Routing

Table 8-65 shows the routing specifications for the SATA data signals.

Table 8-65. SATA Routing Specifications

PARAMETER

Processor-to-SATA header trace length

MIN

TYP

MAX

10⁽¹⁾Inches

UNIT

Number of stubs allowed on SATA traces⁽²⁾

0

120

69

Stubs

Ω

TX/RX pair differential impedance

80

51

100

60

TX/RX single ended impedance

Ω

Number of vias on each SATA trace

SATA differential pair to any other trace spacing

3

Vias⁽³⁾

2*DS⁽⁴⁾

(1) Beyond this, signal integrity may suffer.

(2) In-line pads may be used for probing.

(3) Vias must be used in pairs with their distance minimized.

(4) DS = differential spacing of the SATA traces.

8.15.2.5 Coupling Capacitors

AC coupling capacitors are required on the receive data pair. Table 8-66 shows the requirements for these

capacitors.

Table 8-66. SATA AC Coupling Capacitors Requirements

PARAMETER

MIN

TYP

10

MAX

12

UNIT

nF

EIA⁽²⁾

SATA AC coupling capacitor value

SATA AC coupling capacitor package size⁽¹⁾

1

0402

0603

(1) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.

(2) EIA LxW units; that is, a 0402 is a 40 x 20 mil surface-mount capacitor.

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8.16 Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed

length (4 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is

normally used for communication between the device and external peripherals. Typical applications

include an interface-to-external I/O or peripheral expansion via devices such as shift registers, display

drivers, SPI EEPROMs, and Analog-to-Digital Converters (ADCs).

The SPI supports the following features:

•

Master/Slave operation

Four chip selects for interfacing/control to up to four SPI Slave devices and connection to a single

external Master

•

32-bit shift register

Buffered receive/transmit data register per channel (1 word deep), FIFO size is 64 bytes

Programmable SPI configuration per channel (clock definition, enable polarity and word width)

Supports one interrupt request and two DMA requests per channel.

For more detailed information on the SPI, see the Multichannel Serial Port Interface (McSPI) chapter in

the device-specific Technical Reference Manual.

8.16.1 SPI Peripheral Register Descriptions

The SPI peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

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8.16.2 SPI Electrical Data/Timing

Table 8-67. Timing Requirements for SPI - Master Mode

(see Figure 8-81 and Figure 8-82)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0)1 LOAD AT A MAXIMUM OF 5 pF

1

2

3

t_c(SPICLK)

Cycle time, SPI_CLK⁽¹⁾⁽²⁾

Pulse duration, SPI_CLK low⁽¹⁾

Pulse duration, SPI_CLK high⁽¹⁾

20.8⁽³⁾

0.5*P - 1⁽⁴⁾

2.29

ns

t_w(SPICLKL)

t_w(SPICLKH)

SPI0, SPI1

SPI2, SPI3

Setup time, SPI_D[x] valid before SPI_CLK active

edge⁽¹⁾

4

t_{su(MISO-SPICLK)}

ns

4

5

6

7

t_{h(SPICLK-MISO)}

t_{d(SPICLK-MOSI)}

t_d(SCS-MOSI)

Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾

Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾

Delay time, SPI_SCS[x] active edge to SPI_D[x] transition

2.67

ns

3.57

MASTER_PH

B-4.2⁽⁶⁾

A-4.2⁽⁷⁾

B-4.2⁽⁶⁾

ns

A0⁽⁵⁾

Delay time, SPI_SCS[x] active to SPI_CLK first

edge⁽¹⁾

8

9

t_{d(SCS-SPICLK)}

MASTER_PH

A1⁽⁵⁾

MASTER_PH

A0⁽⁵⁾

Delay time, SPI_CLK last edge to SPI_SCS[x]

inactive⁽¹⁾

t_{d(SPICLK-SCS)}

MASTER_PH

A1⁽⁵⁾

MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0) LOAD AT MAX 25pF

MASTER: SPI2 (M1, M2, M3) and SPI3 (M1, M2, M3) 1 to 4 LOAD AT 5 to 25pF

1

2

3

t_c(SPICLK)

Cycle time, SPI_CLK⁽¹⁾⁽²⁾

Pulse duration, SPI_CLK low⁽¹⁾

Pulse duration, SPI_CLK high⁽¹⁾

41.7⁽⁸⁾

0.5*P - 2⁽⁴⁾

ns

t_w(SPICLKL)

t_w(SPICLKH)

SPI0, SPI1

SPI2, SPI3

4

6

Setup time, SPI_D[x] valid before SPI_CLK active

edge⁽¹⁾

4

t_{su(MISO-SPICLK)}

ns

5

6

7

t_{h(SPICLK-MISO)}

t_{d(SPICLK-MOSI)}

t_d(SCS-MOSI)

Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾

Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾

Delay time, SPI_SCS[x] active edge to SPI_D[x] transition

3.8

-5.5

ns

5.5

MASTER_PH

B-3.5⁽⁶⁾

A-3.5⁽⁷⁾

B-3.5⁽⁶⁾

ns

A0⁽⁵⁾

Delay time, SPI_SCS[x] active to SPI_CLK first

edge⁽¹⁾

8

9

t_{d(SCS-SPICLK)}

MASTER_PH

A1⁽⁵⁾

MASTER_PH

A0⁽⁵⁾

Delay time, SPI_CLK last edge to SPI_SCS[x]

inactive⁽¹⁾

t_{d(SPICLK-SCS)}

MASTER_PH

A1⁽⁵⁾

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) Related to the SPI_CLK maximum frequency.

(3) Maximum frequency = 48 MHz

(4) P = SPICLK period.

(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

(6) B = (TCS + 0.5) * TSPICLKREF * F_ratio, where TCS is a bit field of the SPI_CH(i)CONF register and F_ratio= Even ≥2.

(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS

+ 0.5) * F_ratio* TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

(8) Maximum frequency = 24 MHz

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PHA=0

EPOL=1

SPI_SCS[x] (Out)

1

3

2

8

2

3

9

POL=0

SPI_SCLK (Out)

POL=1

SPI_SCLK (Out)

6

7

6

SPI_D[x] (Out)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (Out)

SPI_SCLK (Out)

1

3

2

8

2

3

9

POL=0

POL=1

1

SPI_SCLK (Out)

SPI_D[x] (Out)

6

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-81. SPI Master Mode Transmit Timing

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PHA=0

EPOL=1

SPI_SCS[x] (Out)

1

3

2

8

2

3

9

POL=0

POL=1

SPI_SCLK (Out)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (Out)

SPI_SCLK (Out)

1

2

1

3

2

8

9

POL=0

POL=1

SPI_SCLK (Out)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-82. SPI Master Mode Receive Timing

Table 8-68. Timing Requirements for SPI - Slave Mode

(see Figure 8-83 and Figure 8-84)

OPP100/OPP120/Turbo/Nitr

o

NO.

UNIT

MIN

62.5⁽³⁾

0.5*P - 3⁽⁴⁾

12.92

MAX

1

2

3

4

5

6

t_c(SPICLK)

Cycle time, SPI_CLK⁽¹⁾⁽²⁾

Pulse duration, SPI_CLK low⁽¹⁾

Pulse duration, SPI_CLK high⁽¹⁾

Setup time, SPI_D[x] valid before SPI_CLK active edge⁽¹⁾

Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾

Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾

ns

t_w(SPICLKL)

t_w(SPICLKH)

t_{su(MOSI-SPICLK)}

t_{h(SPICLK-MOSI)}

t_{d(SPICLK-MISO)}

12.92

-4.00

17.1

Delay time, SPI_SCS[x] active edge to SPI_D[x]

transition⁽⁵⁾

7

t_d(SCS-MISO)

ns

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) Related to the input maximum frequency supported by the SPI module.

(3) Maximum frequency = 16 MHz

(4) P = SPICLK period.

(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

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Table 8-68. Timing Requirements for SPI - Slave Mode (continued)

(see Figure 8-83 and Figure 8-84)

OPP100/OPP120/Turbo/Nitr

o

NO.

UNIT

MIN

12.92

MAX

8

9

t_{su(SCS-SPICLK)}

t_{h(SPICLK-SCS)}

Setup time, SPI_SCS[x] valid before SPI_CLK first edge⁽¹⁾

Hold time, SPI_SCS[x] valid after SPI_CLK last edge⁽¹⁾

ns

PHA=0

EPOL=1

SPI_SCS[x] (In)

SPI_SCLK (In)

1

3

8

2

9

POL=0

POL=1

1

3

SPI_SCLK (In)

SPI_D[x] (Out)

6

7

6

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (In)

SPI_SCLK (In)

1

3

2

8

2

3

9

POL=0

POL=1

SPI_SCLK (In)

SPI_D[x] (Out)

6

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-83. SPI Slave Mode Transmit Timing

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PHA=0

EPOL=1

SPI_SCS[x] (In)

1

3

8

2

9

POL=0

POL=1

SPI_SCLK (In)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (In)

SPI_SCLK (In)

1

3

2

8

2

3

9

POL=0

POL=1

1

SPI_SCLK (In)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-84. SPI Slave Mode Receive Timing

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8.17 Timers

The device has eight 32-bit general-purpose (GP) timers (TIMER8 - TIMER1) that have the following

features:

•

TIMER8, TIMER1 are for software use and do not have an external connection

Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)

signal

•

Interrupts generated on overflow, compare, and capture

Free-running 32-bit upward counter

Supported modes:

–

Compare and capture modes

Auto-reload mode

Start-stop mode

•

TIMER[8:1] functional clock is sourced from either the DEVOSC, AUXOSC, AUD_CLK2/1/0, TCLKIN,

or SYSCLK18 27 MHz as selected by the timer clock multiplexers.

•

On-the-fly read/write register (while counting)

Generates interrupts to the ARM and Media Controller.

The device has one system watchdog timer that have the following features:

•

Free-running 32-bit upward counter

On-the-fly read/write register (while counting)

Reset upon occurrence of a timer overflow condition

The system watchdog timer has two possible clock sources:

–

RCOSC32K oscillator

RTCDIVIDER

•

The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault

condition, such as a non-exiting code loop.

For more detailed information on the GP and Watchdog Timers, see the Timers and Watchdog Timer

chapters in the device-specific Technical Reference Manual.

8.17.1 Timer Peripheral Register Descriptions

The Timer peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

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8.17.2 Timer Electrical/Data Timing

Table 8-69. Timing Requirements for Timer

(see Figure 8-85)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

1

2

t_w(EVTIH)

t_w(EVTIL)

Pulse duration, high

Pulse duration, low

4P⁽¹⁾

ns

(1) P = module clock.

Table 8-70. Switching Characteristics Over Recommended Operating Conditions for Timer

(see Figure 8-85)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

Pulse duration, high

UNIT

MIN

4P-3⁽¹⁾

MAX

3

4

t_w(EVTOH)

t_w(EVTOL)

ns

Pulse duration, low

(1) P = module clock.

1

2

TCLKIN

3

4

TIMx_IO

Figure 8-85. Timer Timing

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8.18 Universal Asynchronous Receiver/Transmitter (UART)

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-

to-serial conversion on data received from the CPU. The device provides up to three UART peripheral

interfaces, depending on the selected pin multiplexing.

Each UART has the following features:

•

Selectable UART/IrDA (SIR/MIR)/CIR modes

Dual 64-entry FIFOs for received and transmitted data payload

Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt

generation

•

Baud-rate generation based upon programmable divisors N (N=1…16384)

Two DMA requests and one interrupt request to the system

Can connect to any RS-232 compliant device.

UART functions include:

•

Baud-rate up to 3.6 Mbit/s on UART0, UART1, and UART2

Programmable serial interfaces characteristics

–

5, 6, 7, or 8-bit characters

Even, odd, or no parity-bit generation and detection

1, 1.5, or 2 stop-bit generation

Flow control: hardware (RTS/CTS) or software (XON/XOFF)

•

Additional modem control functions (UART0_DTR, UART0_DSR, UART0_DCD, and UART0_RIN) for

UART0 only; UART1 and UART2 do not support full-flow control signaling.

IR-IrDA functions include:

•

Support of IrDA 1.4 slow infrared (SIR, baud-rate up to 115.2 Kbits/s), medium infrared (MIR, baud-

rate up to 1.152 Mbits/s) and fast infrared (FIR baud-rate up to 4.0 Mbits/s) communications

Supports framing error, cyclic redundancy check (CRC) error, illegal symbol (FIR), and abort pattern

(SIR, MIR) detection

8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors.

IR-CIR functions include:

•

Consumer infrared (CIR) remote control mode with programmable data encoding

Free data format (supports any remote control private standards)

Selectable bit rate and configurable carrier frequency.

For more detailed information on the UART peripheral, see the UART/IrDA/CIR Module chapter in the

device-specific Technical Reference Manual.

8.18.1 UART Peripheral Register Descriptions

The UART peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

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8.18.2 UART Electrical/Data Timing

Table 8-71. Timing Requirements for UART

(see Figure 8-86)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

4

5

t_w(RX)

Pulse width, receive data bit, 15/30/100pF high or low

Pulse width, receive start bit, 15/30/100pF high or low

Delay time, transmit start bit to transmit data

0.96U⁽¹⁾

P⁽²⁾

1.05U⁽¹⁾

ns

t_w(CTS)

t_d(RTS-TX)

t_d(CTS-TX)

Delay time, receive start bit to transmit data

P⁽²⁾

(1) U = UART baud time = 1/programmed baud rate

(2) P = Clock period of the reference clock (FCLK, usually 48 MHz).

Table 8-72. Switching Characteristics Over Recommended Operating Conditions for UART

(see Figure 8-86)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

UNIT

MIN

MAX

15 pF

30 pF

100 pF

5

0.23

f_(baud)

Maximum programmable baud rate

MHz

0.115

2

3

t_w(TX)

Pulse width, transmit data bit, 15/30/100 pF high or low

Pulse width, transmit start bit, 15/30/100 pF high or low

U - 2⁽¹⁾

U + 2⁽¹⁾

ns

t_w(RTS)

(1) U = UART baud time = 1/programmed baud rate

3

2

Start

Bit

UARTx_TXD

Data Bits

5

4

Start

Bit

UARTx_RXD

Data Bits

Figure 8-86. UART Timing

Peripheral Information and Timings

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8.19 Universal Serial Bus (USB2.0)

The device includes two USB2.0 modules which support the Universal Serial Bus Specification Revision

2.0. The following are some of the major USB features that are supported:

•

USB 2.0 peripheral at high speed (HS: 480 Mbps) and full speed (FS: 12 Mbps)

USB 2.0 host at HS, FS, and low speed (LS: 1.5 Mbps)

Each endpoint (other than endpoint 0, control only) can support all transfer modes (control, bulk,

interrupt, and isochronous)

•

Supports high-bandwidth ISO mode

Supports 15 Transmit (TX) and 15 Receive (RX) endpoints including endpoint 0

FIFO RAM

–

32K endpoint

Programmable size

•

Includes two integrated PHYs

RNDIS-like mode for terminating RNDIS-type protocols without using short-packet termination for

support of MSC applications.

•

USB Dual Role Device: Host Negotiation Protocol (HNP)

The USB2.0 peripherals do not support the following features:

•

On-chip charge pump (VBUS Power must be generated external to the device.)

RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes

Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64, –

and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined

•

USB OTG extension: Session Request Protocol (SRP)

For more detailed information on the USB2.0 peripheral, see the Universal Serial Bus (USB) chapter in the

device-specific Technical Reference Manual.

8.19.1 USB2.0 Peripheral Register Descriptions

The USB peripheral registers are described in the device-specific Technical Reference Manual. Each

register is documented as an offset from a base address for the peripheral. The base addresses for all of

the peripherals are in the device memory map (see Section 2.10).

258

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8.19.2 USB2.0 Electrical Data/Timing

Table 8-73. Switching Characteristics Over Recommended Operating Conditions for USB2.0

(see Figure 8-87)

OPP100/OPP120/

Turbo/Nitro

NO.

PARAMETER

LOW SPEED

1.5 Mbps

FULL SPEED

12 Mbps

HIGH SPEED

480 Mbps

UNIT

MIN

75

MAX

MIN

4

MAX

20

111

2

MIN

0.5

–

MAX

1

2

3

4

5

t_r(D)

Rise time, USBx_DP and USBx_DM signals⁽¹⁾

Fall time, USBx_DP and USBx_DM signals⁽¹⁾

Rise/Fall time, matching⁽²⁾

300

125

2

ns

%

t_f(D)

75

4

t_rfM

80

90

1.3

–

V_CRS

Output signal cross-over voltage⁽¹⁾

Source (Host) Driver jitter, next transition

Function Driver jitter, next transition

Source (Host) Driver jitter, paired transition⁽⁴⁾

Function Driver jitter, paired transition

Pulse duration, EOP transmitter

Pulse duration, EOP receiver⁽⁵⁾

Data Rate

1.3

–

(3)

V

t_jr(source)NT

t_jr(FUNC)NT

t_jr(source)PT

t_jr(FUNC)PT

t_w(EOPT)

t_w(EOPR)

t_(DRATE)

2

ns

(3)

25

2

6

1

10

1

7

8

9

1250

670

1500

160

82

175

–

1.5

–

12

49.5

–

480 Mb/s

10 Z_DRV

11 Z_INP

Driver Output Resistance

–

28

40.5

–

49.5

–

Ω

Receiver Input Impedance

300

kΩ

(1) Low Speed: C_L= 200 pF, Full Speed: C_L= 50 pF, High Speed: C_L= 50 pF

(2) t_RFM= (t_r/t_f) x 100. [Excluding the first transaction from the Idle state.]

(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7, Electrical.

(4) t_jr= t_px(1)- t_px(0)

(5) Must accept as valid EOP.

t

per − jr

USBx_DM

V

90% V

OH

CRS

10% V

OL

USBx_DP

t

f

t

r

Figure 8-87. USB2.0 Integrated Transceiver Interface Timing

For more detailed information on USB2.0 board design, routing, and layout guidelines, see the USB 2.0

Board Design and Layout Guidelines Application Report (Literature Number: SPRAAR7).

Peripheral Information and Timings

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

TI offers an extensive line of development tools, including tools to evaluate the performance of the

processors, generate code, develop algorithm implementations, and fully integrate and debug software

and hardware modules. The tool's support documentation is electronically available within the Code

Composer Studio™ Integrated Development Environment (IDE).

The following products support development of DM383 processor applications:

Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):

including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software ( Device/BIOS™), which provides the basic run-time target

software needed to support any DM383 processor application.

Reference Design Kits: Production ready reference kits including hardware collaterals and software, for a

faster time-to-market.

Hardware Development Tools: Extended Development System ( XDS™) Emulator

For a complete listing of development-support tools for the DM383 processor platform, visit the Texas

Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field

sales office or authorized distributor.

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9.1.2 Device and Development Support-Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

MPUs and support tools. Each device has one of three prefixes: X, P, or null (no prefix). Texas

Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS.

These prefixes represent evolutionary stages of product development from engineering prototypes

(TMDX) through fully qualified production devices/tools (TMDS).

Device development evolutionary flow:

X

Pre-production device that is not necessarily representative of the final device's electrical

specifications and may not use production assembly flow.

P

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications.

null

Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS

Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

9.1.3 Device Nomenclature

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, AAR), the temperature range (for example, blank is the default commercial

temperature range), and the device speed range (for example, 01 is the 720 MHz ARM device). Figure 9-1

provides a legend for reading the complete device name for any DM383 device.

For device part numbers and further ordering information of DM383 devices in the AAR package type, see

the TI website (www.ti.com) or contact your TI sales representative.

(

)

(

)

(

)

( )

(

)

DM383

AAR

PREFIX

Face Detect

Blank = Production Device (TMS)

X = Pre-production Device

P = Prototype Device

Blank = Disabled

F = Enabled

DEVICE SPEED RANGE

01 = 720-MHz ARM, 290-MHz HDVICP2

11 = 970-MHz ARM, 410-MHz HDVICP2

21 = 1000-MHz ARM, 450-MHz HDVICP2

DEVICE

DM38x DaVinci™ Digital Media Processors

DM383

TEMPERATURE RANGE

Blank = 0°C to 95°C, Commercial Temperature

SILICON REVISION

Blank = Revision 1.0

A = Revision 1.1

PACKAGE TYPE^(A)

AAR = 609-Pin Plastic BGA, with Pb-Free Die Bump

and Solder Ball

Figure 9-1. Device Nomenclature

Device and Documentation Support

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9.2 Documentation Support

Contact your TI sales representative for support documents.

For additional peripheral information, see the latest version of the DM38x DaVinci™ Digital Media

Processor Technical Reference Manual (Literature Number: SPRUHG1).

9.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and

help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster

innovation and growth of general knowledge about the hardware and software surrounding

these devices.

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10 Mechanical

Table 10-1 shows the thermal resistance characteristics for the PBGA–AAR mechanical package.

The device package has been specially engineered with a new technology called Via Channel™, allowing

0.8 mm PCB design rules to be employed. This allows larger than normal PCB via and trace sizes and

reduced PCB signal layers to be used in a PCB design with this 0.5 mm pitch package, and will

substantially reduce PCB costs. It also allows PCB routing in only two signal layers (four layers total

deleted) due to the increased layer efficiency of the Via Channel™ BGA technology.

10.1 Thermal Data for the AAR

Table 10-1. Thermal Resistance Characteristics (PBGA Package) [AAR]

Air Flow (m/s)⁽¹⁾

still air

ºC/W⁽²⁾

17.79

13.36

12.54

12.04

0.08

Θ_JA/JMA

Junction-to-air/ Junction-to-moving air

Junction-to-package top

Junction-to-board

1.0 m/s

2.0 m/s

3.0 m/s

still air

Psi_JT

1.0 m/s

2.0 m/s

3.0 m/s

still air

0.16

0.20

0.23

4.90

Psi_JB

1.0 m/s

2.0 m/s

3.0 m/s

4.81

4.78

4.76

Θ_JB

Junction-to-board

Junction-to-case

4.86

Θ_{JC (1SOP board)}

3.84

(1) m/s = meters per second.

(2) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [ΘJC] measurement, which

was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information,

see these EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air).

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

JESD51-9, Test Boards for Area Array Surface Mount Packages.

10.2 Packaging Information

The following packaging information and addendum reflect the most current data available for the

designated device(s). This data is subject to change without notice and without revision of this document.

Mechanical

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型号：	DM383AAAR21F
厂家：	TEXAS INSTRUMENTS
描述：	DaVinci 数字媒体处理器 \| AAR \| 609
文件：	总267页 (文件大小：2274K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DM383AAAR21F [TI]

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