SPRS872B – MAY 2013 – REVISED DECEMBER 2013

DMVA3 and DMVA4 DaVinci™ Digital Media Processor

Check for Samples:

1 High-Performance System-on-Chip (SoC)

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Features

• Face Detect (FD) Engine

– Hardware Face Detection for up to 35 Faces

Per Frame

• Programmable High-Definition Video Image

Coprocessing (HDVICP v2) Engine

– Encode, Decode, Transcode Operations

– H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4

SP/ASP, JPEG/MJPEG

– Fourth-Generation Motion-Compensated

Noise Filter

• Media Controller

– Controls the HDVPSS, HDVICP2, Vision

Coprocessor, and ISS

• Endianness

– ARM Instructions and Data – Little Endian

• HD Video Processing Subsystem (HDVPSS)

– Two 165-MHz HD Video Capture Inputs

• One 16- or 24-Bit Input, Splittable Into

Dual 8-Bit SD Capture Ports

• One 8-, 16-, or 24-Bit HD Input and 8-Bit

SD Input Capture Port

– Two 165-MHz HD Video Display Outputs

• One 16-, 24-, or 30-Bit and One 16- or 24-

Bit Output

– Component HD Analog Output

– Composite Analog Output

– Digital HDMI 1.3 Transmitter with Integrated

PHY

– Advanced Video Processing Features Such

as Scan, Format, and Rate Conversion

– Three Graphics Layers and Compositors

• 32-Bit DDR2, DDR3, and DDR3L SDRAM

Interface

– Supports up to 400 MHz for DDR2, 533 MHz

for DDR3, and 533 MHz for DDR3L

– Up to Two x 16 Devices, 2GB of Total

Address Space

– Dynamic Memory Manager (DMM)

• Programmable Multi-Zone Memory

Mapping

• Enables Efficient 2D Block Accesses

• Supports Tiled Objects in 0°, 90°, 180°, or

• High-Performance DaVinci Digital Media

Processors

– Up to 970-MHz ARM® Cortex™-A8 RISC

Processor

– Up to 1940 ARM Cortex-A8 MIPS

• ARM Cortex-A8 Core

– ARMv7 Architecture

• In-Order, Dual-Issue, Superscalar

Processor Core

• NEON™ Multimedia Architecture

• Supports Integer and Floating Point

• Jazelle® RCT Execution Environment

• ARM Cortex-A8 Memory Architecture

– 32KB of Instruction and Data Caches

– 256KB of L2 Cache with ECC

– 64KB of RAM, 48KB of Boot ROM

• 256KB of On-Chip Memory Controller (OCMC)

RAM

• Imaging Subsystem (ISS)

– Camera Sensor Connection

• Parallel Connection for Raw (up to 16-Bit)

and BT.656/BT.1120 (8- or 16-Bit)

• CSI2 Serial Connection

– Image Sensor Interface (ISIF) for Handling

Image and Video Data From the Camera

Sensor

– Image Pipe Interface (IPIPEIF) for Image and

Video Data Connection Between Camera

Sensor, ISIF, IPIPE, and DRAM

– Image Pipe (IPIPE) for Real-Time Image and

Video Processing

– Resizer

• Resizing Image and Video From 1/16x to

8x

• Generating Two Different Resizing

Outputs Concurrently

• Hardware 3A Engine (H3A) for Generating

Key Statistics for 3A (AE, AWB, and AF)

Control

• Vision Coprocessor

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Copyright © 2013, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.